Semiconductor device manufacturing method and semiconductor device

Abstract

This semiconductor device manufacturing method comprises: a step for forming a nanosheet laminate on a semiconductor substrate with a sacrificial sheet layer therebetween, the nanosheet laminate comprising a laminate of a plurality of nanosheet layers made of semiconductor material, and patterning the nanosheet laminate into a line shape; a step for forming a line-shaped dummy gate layer extending in a direction substantially perpendicular to the line-shaped nanosheet laminate and an insulating sidewall covering a sidewall of the dummy gate layer; a step for patterning the nanosheet laminate into an island shape by etching using the dummy gate layer and the insulating sidewall as a mask; a step for forming a source and a drain by epitaxial growth on an exposed surface of the island-shaped nanosheet laminate; a step for replacing the line-shaped dummy gate layer and the sacrificial sheet layer with a gate electrode; and a step for separating the line-shaped gate electrode. The source and drain formed adjacent to each other in an extending direction of the gate electrode are separated in the same step as the step for separating the line-shaped gate electrode.

Description

Method for manufacturing semiconductor device and semiconductor device

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

[0002] Regarding a method for manufacturing a semiconductor device, the following procedure is described in Patent Document 1 below. First, a fin group extending on an STI layer is formed, and a gate is formed on the fin group. Next, gate spacers are formed on each side of the gate, and raised S / D regions are formed by epitaxial growth adjacent to each spacer on each fin of the fin group. Further, a liner is formed on and between the respective raised S / D regions, and the liner is removed from the upper surface of each raised S / D region and between the fin group. Next, an overgrowth region is formed by epitaxial growth on the upper surface of each raised S / D region, and an interlayer insulating film is formed on and between the raised S / D regions. According to the document, this achieves uniform epitaxial growth between a narrow pitch device and an isolated device when forming the overgrowth region, and prevents fusion of epitaxial layers.

[0003] US Patent No. 9236452

[0004] However, in the procedure described in Patent Document 1 mentioned above, it is necessary to perform formation of the liner and partial removal of the liner to prevent fusion of the epitaxial layers, which causes an increase in the number of manufacturing steps.

[0005] Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device and a semiconductor device that can separate two source / drain regions formed by epitaxial growth without increasing the number of manufacturing steps.

[0006] The present invention, for solving the above problems, is a method for manufacturing a semiconductor device comprising the steps of: forming a nanosheet laminate on a semiconductor substrate by stacking a plurality of nanosheet layers made of semiconductor material via a sacrificial sheet layer; patterning the nanosheet laminate in a linear shape; forming a linear dummy gate layer extending substantially perpendicular to the linear nanosheet laminate and an insulating sidewall covering the sidewall of the dummy gate layer; patterning the nanosheet laminate in an island shape by etching using the dummy gate layer and the insulating sidewall as a mask; forming a source / drain on the exposed surface of the island-shaped nanosheet laminate by epitaxial growth; replacing the linear dummy gate layer and the sacrificial sheet layer with gate electrodes; and separating the linear gate electrodes, wherein the method separates the source / drain formed adjacent to the extending direction of the gate electrodes in the same step as separating the linear gate electrodes. The present invention is also a semiconductor device manufactured by this method for manufacturing a semiconductor device.

[0007] The present invention provides a method for manufacturing a semiconductor device and a semiconductor device that can separate two source / drain connections formed by epitaxial growth without increasing the number of manufacturing steps.

[0008] This is a manufacturing process diagram (1) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a manufacturing process diagram (2) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a manufacturing process diagram (3) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a manufacturing process diagram (4) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a manufacturing process diagram (5) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a manufacturing process diagram (6) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a manufacturing process diagram (7) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a manufacturing process diagram (8) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a manufacturing process diagram (9) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a manufacturing process diagram (10) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a manufacturing process diagram (11) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a manufacturing process diagram (12) showing the manufacturing method of the semiconductor device according to the first embodiment. This is a diagram (1) showing a characteristic manufacturing process in the manufacturing method of the semiconductor device according to the second embodiment. This is a diagram (2) showing a characteristic manufacturing process in the manufacturing method of the semiconductor device according to the second embodiment. This is a diagram (part 3) showing a characteristic manufacturing process in the method for manufacturing a semiconductor device according to the second embodiment. This is a diagram (part 1) showing a characteristic manufacturing process in the method for manufacturing a semiconductor device according to the third embodiment. This is a diagram (part 2) showing a characteristic manufacturing process in the method for manufacturing a semiconductor device according to the third embodiment. This is a diagram (part 3) showing a characteristic manufacturing process in the method for manufacturing a semiconductor device according to the third embodiment. This is a diagram (part 1) showing a characteristic manufacturing process in the method for manufacturing a semiconductor device according to the fourth embodiment. This is a diagram (part 2) showing a characteristic manufacturing process in the method for manufacturing a semiconductor device according to the fourth embodiment. This is a diagram (part 3) showing a characteristic manufacturing process in the method for manufacturing a semiconductor device according to the fourth embodiment. This is a diagram (part 4) showing a characteristic manufacturing process in the method for manufacturing a semiconductor device according to the fourth embodiment. This is a diagram (part 5) showing a characteristic manufacturing process in the method for manufacturing a semiconductor device according to the fourth embodiment. This is a diagram (part 6) showing a characteristic manufacturing process in the method for manufacturing a semiconductor device according to the fourth embodiment.

[0009] Hereinafter, embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the embodiments described below, the same reference numerals are used for the same components, and some redundant descriptions will be omitted.

[0010] <First Embodiment> <Method of Manufacturing a Semiconductor Device of the First Embodiment> Figures 1 to 12 are manufacturing process diagrams (1) to (12) showing the method of manufacturing a semiconductor device of the first embodiment. The semiconductor device formed by the manufacturing method shown in these figures has a plurality of all-around gate transistors on a substrate. Hereinafter, the method of manufacturing a semiconductor device of the first embodiment to which the present invention is applied will be described in the order of the manufacturing processes shown in Figures 1 to 12. Figures 1 to 12 show at least one of a plan view, a cross-section of each part in the X direction in the plan view, and a Y-Y cross-section in each manufacturing process.

[0011] First, as shown in Figure 1, a nanosheet laminate 103 is formed by stacking nanosheet layers 102 made of a semiconductor material via a sacrificial sheet layer 101 on one main surface of a semiconductor substrate 100 made of single-crystal silicon. The sacrificial sheet layer 101 is constructed using a material that allows for selective etching of the nanosheet layers 102 made of semiconductor material. For example, when silicon is used as the semiconductor material constituting the nanosheet layers 102, silicon germanium is used as the sacrificial sheet layer 101.

[0012] Next, the nanosheet laminate 103 is patterned in a line extending in one direction (in this case, the Y direction) by etching using a resist pattern (not shown in the illustration) as a mask. Subsequently, using the resist pattern as a mask, one main surface side of the semiconductor substrate 100 is etched back to form a groove, and the groove is filled with an insulating material to form a groove-type element separator 104. The direction in which the groove-type element separator 104 extends (the Y direction) is the gate length direction of the full-circumference gate transistor that is formed later.

[0013] Next, as shown in Figure 2, a dummy gate 105 is formed extending approximately perpendicular to the nanosheet laminate 103 so as to cross the linearly separated nanosheet laminate 103, and an insulating sidewall 106 is formed on the side wall of the dummy gate 105. The dummy gate 105 is formed using, for example, amorphous silicon. Subsequently, the nanosheet laminate 103 is patterned in an island-like manner by etching using the dummy gate 105 and the insulating sidewall 106 as a mask.

[0014] Next, as shown in Figure 3, the sacrificial sheet layer 101 exposed on the side wall of the nanosheet laminate 103 is selectively reduced by isotropic etching.

[0015] Next, as shown in Figure 4, insulating inner spacers 107 are formed on the exposed sidewalls of the sacrificial sheet layer 101 so as to fill the spaces between the silicon nanosheet layers 102. First, a silicon nitride film is deposited by isotropic deposition to fill the spaces between the nanosheet layers 102. Then, the silicon nitride film is etched back by anisotropic etching. This leaves the silicon nitride film only between the nanosheet layers 102, and the silicon nitride film remaining between the nanosheet layers 102 is formed as the inner spacer 107.

[0016] Next, as shown in Figure 5, source / drain 108 is formed on both sides of the exposed surface of the nanosheet laminate 103, that is, on both sides in one direction (here, the Y direction) of the nanosheet laminate 103. At this time, a p-type source / drain 108p containing p-type impurities and an n-type source / drain 108n containing n-type impurities are formed by epitaxial growth from the exposed surface of the nanosheet layer 102 and the semiconductor substrate 100. The formation of the p-type source / drain 108p is carried out with the formation region of the n-type source / drain 108n covered with a resist pattern. Similarly, the formation of the n-type source / drain 108n is carried out with the formation region of the p-type source / drain 108p covered with a resist pattern.

[0017] Next, as shown in Figure 6, the source / drain 108 is embedded between the dummy gates 105 with an insulating film 109. In this case, the source / drain 108 is embedded between the dummy gates 105 via the insulating sidewall 106, and the insulating film 109 is deposited to cover the dummy gates 105 and the insulating sidewall 106. Subsequently, the insulating film 109 is CMP polished until the dummy gates 105 are exposed, leaving the insulating film 109 only between the dummy gates 105 via the insulating sidewall 106.

[0018] Next, as shown in Figure 7, the dummy gate 105 is removed by selective etching, thereby exposing the nanosheet laminate 103 and the groove-shaped element separator 104 next to the nanosheet laminate 103.

[0019] Next, as shown in Figure 8, the sacrificial sheet layer 101 (see Figure 7) between the nanosheet layers 102 of the nanosheet laminate 103 is selectively etched and removed by etching from the exposed surface of the nanosheet laminate 103. This exposes the central part of the silicon nanosheet layer 102 around its entire circumference.

[0020] Next, as shown in Figure 9, a gate electrode 110 is formed via a gate insulating film (not shown here) so as to cover the exposed surface of the nanosheet layer 102, and the entire circumference of the nanosheet layer 102 is surrounded by the gate electrode 110 via the gate insulating film. Furthermore, the spaces between the insulating sidewalls 106 are filled with the gate electrode 110 and the hard mask layer 111 above it. This replaces the line-shaped dummy gate 105 (see Figure 2) and the sacrificial sheet layer (see Figure 7) with the gate electrode 110. The gate electrode 110 formed in this way is line-shaped, extending substantially perpendicularly to the groove-type element separator 104 (see Figure 1), and is formed as a common element for the full-circumference gate transistors formed adjacent to each other in the gate width direction (X direction).

[0021] Next, as shown in Figure 10, multiple isolation grooves T1 are formed to separate all adjacent source / drain 108s and all gate electrodes 110 on an element-by-element basis in the extending direction of the gate electrode 110 (gate width direction, which is the X direction). These isolation grooves T1 have a continuous shape that extends across the formation region of the full-circumference gate transistor and are formed with the groove-type element separator 104 as the bottom surface.

[0022] Such isolation grooves T1 are formed by pattern etching of each layer using a resist pattern (not shown in the illustration) as a mask. In this case, first, the insulating sidewall 106, insulating film 109, and hard mask layer 111 are anisotropically etched using the resist pattern as a mask, and then the source / drain 108 and gate electrode 110 are anisotropically etched until the groove-type element separator 104 is reached. This forms multiple isolation grooves T1 with the groove-type element separator 104 as the bottom surface, and these isolation grooves T1 separate all adjacent source / drain 108 and all gate electrode 110 in a direction other than the one direction mentioned above (in this case, the gate width direction, the X direction). After forming the isolation grooves T1, the resist pattern is removed by ashing. Note that the etching of the source / drain 108 and gate electrode 110 can be performed in the same process by reactive ion etching using chlorine gas or hydrogen bromide as an etchant.

[0023] Next, as shown in Figure 11, a separation insulating film 112 is formed to fill the separation groove T1. In this case, first, an insulating material film, for example, made of silicon oxide, is formed to fill the separation groove T1. Then, the insulating material film is CMP polished using the hard mask layer 111 as a stopper. This forms the insulating material film remaining to fill the separation groove T1 as the separation insulating film 112.

[0024] Next, as shown in Figure 12, a first contact 113 connecting the separated source / drain 108 and a second contact 114 connecting the separated gate electrodes 110 are formed at their respective required locations. In this case, first, a resist pattern (not shown) is formed to create openings for the formation of the first contact 113 and the second contact 114. Then, using the resist pattern as a mask, the insulating film 109, the hard mask layer 111, and the separating insulating film 112 are etched to form openings on the side walls that expose the two source / drain 108 and openings on the side walls that expose the two gate electrodes 110. After that, a metal material film is deposited to fill these openings, and the metal material film is CMP polished using the hard mask layer 111 as a stopper to form the first contact 113 and the second contact 114 with the openings filled with the metal material film.

[0025] In this process, a source-drain contact connected to only one source / drain 108 and a gate contact connected to only one gate electrode 110 may be formed simultaneously.

[0026] The semiconductor device 1 formed as described above has island-shaped nanosheet stacks 103 arranged in a matrix on a semiconductor substrate 100, and has a plurality of all-around gate transistors 10, each of which has a gate electrode 110 arranged around the entire circumference of each nanosheet layer 102 constituting the nanosheet stack 103. The gate electrode 110 of each all-around gate transistor 10 is located on the upper part of each island-shaped nanosheet stack 103. Furthermore, on both sides of each nanosheet stack 103 in the gate length direction (Y direction: one direction), source / drain 108 are provided by epitaxial growth from the semiconductor substrate 100 and the nanosheet layer 102. In particular, this semiconductor device 1 has a configuration in which the source / drain 108 and the gate electrode 110, which are arranged adjacent to each other in the gate width direction (X direction: other direction), are separated by a line-shaped isolation insulating film 112 formed in the same process.

[0027] <Effects of the First Embodiment> The first embodiment described above has a configuration in which adjacent source / drain 108s are separated in the same process as the process of separating the gate electrode 110. Therefore, even if the source / drain 108s are formed by non-uniform epitaxial growth, it is possible to reliably separate the two source / drains. As a result, it is possible to obtain a semiconductor device with stable element performance without increasing the number of manufacturing steps.

[0028] <Second Embodiment> <Method of Manufacturing a Semiconductor Device of the Second Embodiment> Figures 13 to 15 are diagrams (1) to (3) showing characteristic manufacturing processes in the method of manufacturing a semiconductor device of the second embodiment, and are diagrams showing processes that differ from the manufacturing method of the first embodiment. Hereinafter, the method of manufacturing a semiconductor device of the second embodiment to which the present invention is applied will be described using Figures 13 to 15, along with the diagrams used in the description of the first embodiment.

[0029] First, in the first embodiment, the procedure described with reference to Figures 1 to 9 is carried out, until the entire circumference of the nanosheet layer 102 is surrounded by the gate electrode 110 via a gate insulating film, and the space between the insulating sidewalls 106 is filled with the gate electrode 110 and the hard mask layer 111 above it.

[0030] Next, as shown in Figure 13, all source / drain 108 adjacent to the gate electrode 110 in the extending direction (gate width direction) are separated, and further, multiple separation grooves T1 and separation holes H1 are formed in the necessary parts to separate the gate electrode 110 into element units.

[0031] Here, each isolation groove T1 has a continuous shape extending over the entire circumference of the gate transistor formation region, and is formed with the groove-type element separator 104 as its bottom surface, similar to the isolation groove T1 in the first embodiment.

[0032] Furthermore, the separation hole H1 is positioned between the source and drain 108 where the separation groove T1 is not located, with the groove-type element separator 104 as its bottom surface. Such a separation hole H1 is formed with the groove-type element separator 104 as its bottom surface to separate the gate electrode 110 as needed in the portion where the separation groove T1 is not located.

[0033] Furthermore, when a separation hole H1 separating the source / drain 108 and a separation hole H1 separating the gate electrode 110 are arranged adjacent to each other in the extending direction of the groove-type element separator 104, these separation holes H1 are integrated into a single series of separation holes H1. In this case, the insulating sidewall 106 is also separated. Moreover, the separation groove T1 can be described as a continuous integration of the separation hole H1 separating the source / drain 108 and the separation hole H1 separating the gate electrode 110 across the entire circumference of the gate transistor formation region.

[0034] The formation of the separation groove T1 and separation hole H1 described above can be carried out in the same procedure as the separation groove T1 formation procedure described in the first embodiment, by anisotropically etching each component using the resist pattern as a mask.

[0035] Next, as shown in Figure 14, a line-shaped separation insulating film 112 is formed to fill the separation groove T1, and an island-shaped separation insulating film 112' is formed to fill the separation hole H1. The formation of the separation insulating films 112 and 112' may be the same procedure as the formation procedure for the separation insulating film 112 described in the first embodiment.

[0036] Next, as shown in Figure 15, a first contact 113 is formed to connect the source / drain 108 at the necessary locations, using the same procedure as described in the first embodiment. Also, in the same process as forming the first contact 113, a gate contact 114' is formed to connect to the gate electrode 110 at the necessary locations.

[0037] The semiconductor device 2 formed as described above differs from the semiconductor device 1 of the first embodiment in that the source / drain 108s and gate electrode 110s, which are arranged adjacent to each other in the gate width direction (X direction), are separated by a line-shaped isolation insulating film 112 or an island-shaped isolation insulating film 112' formed in the same process, while the other configurations are the same.

[0038] <Effects of the Second Embodiment> The second embodiment described above has a configuration in which the adjacent source / drain 108 is separated in the same process as the process of separating the gate electrode 110. Therefore, as with the first embodiment, even if the source / drain 108 is formed by non-uniform epitaxial growth, it is possible to reliably separate the two source / drains. As a result, it is possible to obtain a semiconductor device 2 with stable element performance without increasing the number of manufacturing steps.

[0039] <Third Embodiment> <Method of Manufacturing a Semiconductor Device of the Third Embodiment> Figures 16 to 18 are diagrams (1) to (3) showing characteristic manufacturing processes in the method of manufacturing a semiconductor device of the third embodiment, and are diagrams showing processes that differ from the manufacturing method of the first embodiment. Hereinafter, the method of manufacturing a semiconductor device of the third embodiment to which the present invention is applied will be described using Figures 16 to 18, along with the diagrams used in the description of the first embodiment.

[0040] First, in the first embodiment, the procedure described with reference to Figures 1 to 9 is carried out, until the entire circumference of the nanosheet layer 102 is surrounded by the gate electrode 110 via a gate insulating film, and the space between the insulating sidewalls 106 is filled with the gate electrode 110 and the hard mask layer 111 above it.

[0041] Next, as shown in Figure 16, separation holes H1 are formed between all adjacent source / drain 108 in the extending direction (gate width direction) of the gate electrode 110, and in areas where it is necessary to separate the gate electrode 110 into individual elements. Each separation hole H1 is formed with a groove-type element separator 104 as its bottom surface.

[0042] The formation of the separation holes H1 described above can be carried out in the same procedure as the formation procedure for the separation groove T1 described in the first embodiment, by anisotropically etching each component using the resist pattern as a mask. Note that when separation holes H1 separating the source / drain 108 and separation holes H1 separating the gate electrode 110 are arranged adjacent to each other in the extending direction of the groove-type element separator 104, these separation holes H1 may be formed unintentionally as a single unit.

[0043] Next, as shown in FIG. 17, an island-shaped separation insulating film 112' is formed so as to fill the inside of the separation hole H1. The formation of the separation insulating film 112' may be performed by the same procedure as the formation procedure of the separation insulating film 112 described in the first embodiment. However, in a case where the separation insulating film 112' that separates between the source / drain 108 and the separation insulating film 112' that separates the gate electrode 110 are disposed adjacent to each other in the extending direction of the trench-type element isolation 104, these separation insulating films 112' may be unintentionally formed integrally with each other.

[0044] Next, as shown in FIG. 18, a first contact 113 that connects source / drain 108 to each other at necessary positions is formed by the same procedure as that described in the first embodiment. Also, in the same step as the formation of the first contact 113, a gate contact 114' connected to the gate electrode 110 at a necessary position is formed.

[0045] The semiconductor device 3 formed as described above differs from the semiconductor device 1 of the first embodiment in that between the source / drain 108 disposed adjacent to each other in the gate width direction (X direction) and between the gate electrodes 110 are separated by the island-shaped separation insulating film 112' formed in the same step, and other configurations are the same.

[0046] <Effects of Third Embodiment> The third embodiment described above has a configuration in which adjacent source / drain 108 are separated from each other in the same step as the step of separating the gate electrode 110. Therefore, similar to the first embodiment and the second embodiment, even when the source / drain 108 are formed by non-uniform epitaxial growth, it is possible to reliably separate the two source / drain from each other. As a result, it becomes possible to obtain the semiconductor device 3 having stable element performance without increasing the number of manufacturing steps.

[0047] <<Fourth Embodiment>> <Method of Manufacturing Semiconductor Device According to Fourth Embodiment> FIGS. 19 to 24 are diagrams (1) to (6) showing characteristic manufacturing steps in the method of manufacturing a semiconductor device according to the fourth embodiment, and illustrate steps different from the manufacturing method according to the first embodiment. Hereinafter, the method of manufacturing a semiconductor device according to the fourth embodiment to which the present invention is applied will be described with reference to FIGS. 19 to 24 together with the drawings used in the description of the first embodiment.

[0048] First, the procedure described with reference to FIGS. 1 to 9 in the first embodiment is performed, the entire circumference of the nanosheet layer 102 is surrounded by the gate electrode 110 via the gate insulating film, and the process is performed until the space between the insulating sidewalls 106 is filled with the gate electrode 110 and the hard mask layer 111 thereover.

[0049] Next, as shown in FIGS. 19 and 20, a plurality of isolation trenches T2 and isolation holes H2 for isolating the gate electrode 110 into element units with respect to all source / drains 108 adjacent in the gate width direction and necessary portions are formed by pattern etching. At the same time, an element isolation trench T3 for isolating elements is formed by pattern etching. Note that FIG. 20 corresponds to a Y-Y cross-sectional view of the plan view of FIG. 19.

[0050] Here, each isolation trench T2 is disposed with the semiconductor substrate 100 as a bottom surface over the formation region of the all-around gate transistor, which is different from the isolation trench T1 in the first embodiment and the second embodiment.

[0051] Here, each isolation trench T2 has a continuous shape extending over the formation region of the all-around gate transistor, which is the same as the isolation trench T1 in the first embodiment and the second embodiment. However, since it is formed simultaneously with the element isolation trench T3, it is formed to a depth approximately equal to that of the element isolation trench T3. Therefore, as illustrated, each isolation trench T2 may penetrate the trench-type element isolation 104 and be formed with the semiconductor substrate 100 as a bottom surface.

[0052] Furthermore, as in the second embodiment, the separation holes H2 are located between the source / drain 108 where the separation groove T2 is not present. However, since they are formed simultaneously with the element separation groove T3, they are formed to a depth similar to that of the element separation groove T3. For this reason, each separation hole H2 may penetrate the groove-type element separator 104 and be formed with the semiconductor substrate 100 as the bottom surface, as shown in the figure. Such separation holes H2 are formed to separate the gate electrode 110 as needed in the portion where the separation groove T2 is not present.

[0053] Furthermore, if the isolation hole H2 separating the source / drain 108 and the isolation hole H2 separating the gate electrode 110 are arranged adjacent to each other in the extending direction of the groove-type element separator 104, these isolation holes H2 are integrated into a single series of isolation holes H2. In this case, the insulating sidewall 106 is also divided. Moreover, the isolation groove T2 can be said to be an integrated structure in which the isolation hole H2 separating the source / drain 108 and the isolation hole H2 separating the gate electrode 110 are combined over the entire circumference of the gate transistor formation region.

[0054] Furthermore, the element isolation groove T3 has a depth that penetrates the island-shaped nanosheet laminate 103 and reaches the surface layer of the semiconductor substrate 100. The depth of the element isolation groove T3 is the depth necessary for element isolation on the surface side of the semiconductor substrate 100. Such an element isolation groove T3 is arranged so as to penetrate the center of a plurality of nanosheet laminates 103 arranged in a direction substantially perpendicular to the extension direction of the groove-type element isolation 104.

[0055] The formation of the separation groove T2, separation hole H2, and element separation groove T3 described above can be carried out in the same procedure as for the formation of the separation groove T1 described in the first embodiment. If necessary, the groove-type element separator 104 can be anisotropically etched down to the bottom surface, and then the surface layer of the exposed semiconductor substrate 100 can be anisotropically etched.

[0056] Next, as shown in Figures 21 and 22, a line-shaped separation insulating film 112a that fills the separation groove T2, an island-shaped separation insulating film 112a' that fills the separation hole H2, and a line-shaped element separation insulating film 112b that fills the element separation groove T3 are formed. The formation of the separation insulating films 112a, 112a', and element separation insulating film 112b may be the same procedure as the formation procedure for the separation insulating film 112 described in the first embodiment. Note that Figure 22 corresponds to the Y-Y cross-sectional view of the plan view in Figure 21.

[0057] Next, as shown in Figures 23 and 24, a first contact 113 connecting the separated source / drain 108 is formed using the same procedure as described in the first embodiment. Also, in the same process as forming the first contact 113, gate contacts 114' that connect to the gate electrode 110 are formed at the necessary locations. Note that Figure 24 corresponds to the Y-Y cross-sectional view of the plan view in Figure 23.

[0058] The semiconductor device 4 formed as described above is a modified version of the semiconductor device 2 of the second embodiment. The difference between this fourth embodiment of the semiconductor device 4 and the semiconductor device 2 of the second embodiment is that it has an element isolation insulating film 112b that penetrates a part of the island-shaped nanosheet laminate 103 and reaches the surface layer of the semiconductor substrate 100. This element isolation insulating film 112b has its bottom embedded in the surface layer of the semiconductor substrate 100 and functions as an SDB (Single Diffusion Break) that separates the full-circumference gate transistors 10 by crushing one full-circumference gate transistor. The difference between this semiconductor device 4 and the semiconductor device 2 of the second embodiment is that the line-shaped isolation insulating film 112a and the island-shaped isolation insulating film 112a' are formed in the same process as the element isolation insulating film 112b described above, and the other configurations are the same. These isolation insulating films 112a and 112a' have a depth similar to that of the element isolation insulating film 112b.

[0059] <Effects of the Fourth Embodiment> The fourth embodiment described above has a configuration in which the adjacent source / drain 108 are separated in the same process as the process of separating the gate electrode 110, and therefore the same effects as the second embodiment can be obtained. Furthermore, the semiconductor device 4 of the fourth embodiment has an element isolation insulating film 112b that functions as an SDB (Single Diffusion Break), which makes it possible to reduce the number of elements that are made inactive for element isolation, thus enabling high integration. The manufacturing method of this fourth embodiment is a method in which the separation of the gate electrode 110 and the separation of adjacent source / drain 108 are formed in the same process as the formation of such element isolation insulating film 112b. For this reason, even in the manufacture of a highly integrated semiconductor device, it is possible to obtain a semiconductor device 4 with stable element performance without increasing the number of manufacturing processes.

[0060] Furthermore, this fourth embodiment can be combined with the first or third embodiment to form a modified version of the first or third embodiment, and the effects of each embodiment can be obtained by combining them.

[0061] 1, 2, 3, 4… Semiconductor device 10… Full-circumference gate transistor 100… Semiconductor substrate 101… Sacrificial sheet layer 102… Nanosheet layer 103… Nanosheet laminate 104… Groove-type element isolation 105… Dummy gate 106… Insulating sidewall 107… Inner spacer 108… Source / drain 108n… n-type source / drain 108p… p-type source / drain 109… Insulating film 110… Gate electrode 111… Hard mask layer 112, 112a… Isolation insulating film (line-shaped) 112', 112a'… Isolation insulating film (island-shaped) 112b… Element isolation insulating film 113… First contact 114… Second contact 114'… Gate contact H1, H2… Isolation hole T1, T2… Isolation groove T3… Element isolation groove

Claims

1. A method for manufacturing a semiconductor device comprising the steps of: forming a nanosheet laminate on a semiconductor substrate by stacking a plurality of nanosheet layers made of semiconductor material via a sacrificial sheet layer; patterning the nanosheet laminate in a linear shape; forming a linear dummy gate layer extending substantially perpendicular to the linear nanosheet laminate and an insulating sidewall covering the sidewall of the dummy gate layer; patterning the nanosheet laminate in an island shape by etching using the dummy gate layer and the insulating sidewall as a mask; forming a source / drain on the exposed surface of the island-shaped nanosheet laminate by epitaxial growth; replacing the linear dummy gate layer and the sacrificial sheet layer with a gate electrode; and separating the linear gate electrode, wherein the method for manufacturing a semiconductor device separates the source / drain formed adjacent to the gate electrode in the extending direction in the same step as separating the linear gate electrode.

2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of separating the gate electrode, the gate electrode and the source / drain are pattern-etched, and the pattern-etched portion is filled with a separation insulating film.

3. The method for manufacturing a semiconductor device according to claim 2, wherein, before forming the dummy gate layer, groove-shaped element isolation is formed on the surface side of the semiconductor substrate exposed from the linear nanosheet laminate, and in the step of separating the gate electrode, the pattern etching is performed until the groove-shaped element isolation is reached.

4. The method for manufacturing a semiconductor device according to claim 2, wherein in the step of separating the gate electrode, the gate electrode and the source / drain are pattern-etched, and at the same time, a portion of the island-shaped nanosheet laminate is pattern-etched until it reaches the surface layer of the semiconductor substrate to isolate the element, and each pattern-etched portion is filled with an isolation insulating film.

5. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of separating the gate electrode, a separation groove is formed extending substantially perpendicular to the extension direction of the gate electrode, and the inside of the separation groove is filled with a separation insulating film.

6. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of separating the gate electrode, separation holes are formed in all of the source / drain spaces adjacent to the extending direction of the gate electrode and in the required portion of the gate electrode, and the separation holes are filled with a separation insulating film.

7. The method for manufacturing a semiconductor device according to claim 6, wherein a separation hole for separating the source / drain and a separation hole for separating gate electrodes adjacent to the gate electrodes in the extending direction of the gate electrodes are integrally formed.

8. The method for manufacturing a semiconductor device according to claim 1, wherein contacts are formed to connect the separated gate electrodes and the separated source / drain.

9. A semiconductor device comprising: island-shaped nanosheet stacks arranged in a matrix on a semiconductor substrate; a gate electrode disposed on the upper part of the nanosheet stacks; source / drains provided on both sides in one direction of each nanosheet stack by epitaxial growth from the nanosheet stacks; and a separation insulating film that separates the gate electrode and the source / drains in the other direction.

10. The semiconductor device according to claim 9, wherein the bottom of the isolation insulating film reaches a groove-type element isolation provided on the surface side of the semiconductor substrate.

11. The semiconductor device according to claim 9, which has an element isolation insulating film that penetrates a portion of the island-shaped nanosheet laminate and reaches the surface layer of the semiconductor substrate, wherein the isolation insulating film that separates the gate electrode and the source / drain has a depth of about the same as the element isolation insulating film.

12. The semiconductor device according to claim 9, wherein the isolation insulating film has a line shape that is continuous in one direction.

13. The semiconductor device according to claim 9, wherein the isolation insulating film is island-shaped.

14. The semiconductor device according to claim 9, having contacts connecting gate electrodes separated by the isolation insulating film and between source and drain terminals.

Images