Semiconductor package and method for producing semiconductor package

Abstract

Provided is a semiconductor package in which a semiconductor chip is connected to a substrate by a wire, wherein warpage of the semiconductor chip is suppressed.　This semiconductor package is provided with a substrate, a first semiconductor chip, a transparent member, and a first resin. In this semiconductor package, a first opening is formed in the substrate. In the semiconductor package, the first semiconductor chip is disposed in the first opening and connected to one of the two surfaces of the substrate by a wire. In the semiconductor package, the first resin seals the wire and bonds the transparent member.

Description

Semiconductor package and method of manufacturing semiconductor package

[0001] The present technology relates to a semiconductor package. More specifically, it relates to a semiconductor package in which a semiconductor chip is connected by wires, and a method of manufacturing the semiconductor package.

[0002] Conventionally, wire bonding has been widely used for electrically connecting a semiconductor chip to a substrate. For example, there has been proposed a semiconductor package in which a semiconductor chip adhered to an upper surface of a substrate is connected to the substrate by wires, and glass is fitted to a plastic thin plate adhered to a light-receiving surface of the semiconductor chip (see, for example, Patent Document 1).

[0003] Japanese Unexamined Patent Application Publication No. 2012-80129

[0004] In the above-described conventional technology, an attempt is made to sufficiently increase the distance between the semiconductor chip and the glass by disposing a plastic thin plate between the semiconductor chip and the glass. However, in the above-described conventional technology, since the semiconductor chip is adhered to the substrate, warpage may occur in the semiconductor chip due to the difference in CTE (Coefficient of Thermal Expansion) between the components.

[0005] The present technology has been developed in view of such circumstances, and an object of the present technology is to suppress warpage of a semiconductor chip in a semiconductor package in which a semiconductor chip is connected to a substrate by wires.

[0006] The present technology has been made to solve the above-described problems, and a first aspect of the present technology is a semiconductor package including: a substrate having a first opening formed therein; a first semiconductor chip disposed in the first opening and connected to one of both surfaces of the substrate by a wire; a transparent member; and a first resin that seals the wire and adheres the transparent member. This provides the effect of suppressing warpage of the chip.

[0007] Further, in the first aspect, the semiconductor package may further include external terminals arranged on the substrate. This provides the effect that the substrate can be mounted.

[0008] Furthermore, in this first aspect, a flexible cable connected to the external terminal may be provided. This results in the wiring being extended to an external device.

[0009] Furthermore, in this first aspect, the external terminals may be arranged on one of the two surfaces of the substrate. This results in the light-receiving side of the substrate being connected.

[0010] Furthermore, in this first aspect, the external terminals may be arranged on the other side of the substrate. This results in the connection between the light-receiving side and the side of the substrate opposite to it.

[0011] Furthermore, in this first aspect, a second resin is provided to bond the side surface of the first semiconductor chip to the substrate, and the elastic modulus of the second resin may be higher than that of the first resin. This has the effect of reducing stress on the transparent member.

[0012] Furthermore, in this first aspect, the substrate may have a recess formed around the first resin. This has the effect of suppressing the spreading of the resin 251.

[0013] Furthermore, in this first aspect, the transparent member may further be provided with a frame to which one of the two surfaces is bonded to the substrate, and the transparent member may be supported by the other surface of the frame. This has the effect of ensuring parallelism between the transparent member and the chip.

[0014] Furthermore, in this first aspect, the substrate may be provided with a predetermined number of fitting holes, and the frame may be provided with projections that fit into each of the fitting holes. This has the effect of preventing misalignment of the frame.

[0015] Furthermore, in this first aspect, the frame may be provided with grooves formed along the inner wall of the frame. This has the effect of preventing the resin from overflowing.

[0016] Furthermore, in this first aspect, the frame may be provided with a predetermined number of first notches formed on one of the two surfaces of the frame. This has the effect of suppressing the generation of voids.

[0017] Furthermore, in this first aspect, the substrate may include a dam formed between the inner wall of the frame and the contact. This has the effect of preventing the resin from overflowing.

[0018] Furthermore, in this first aspect, the frame may be provided with a predetermined number of second notches formed on the other side of the frame. This has the effect of suppressing the generation of voids.

[0019] Furthermore, in this first aspect, the substrate may have a step formed around the first opening, and the transparent member may be supported in the region of one of the surfaces of the substrate that is outside the step. This has the effect of ensuring parallelism between the transparent member and the chip.

[0020] Furthermore, in this first aspect, the first resin may bond the transparent member to the region of the substrate on the outer side of the step. This has the effect of increasing the bonding area of ​​the transparent member.

[0021] Furthermore, this first aspect may further include a second semiconductor chip connected by a wire to one of the two surfaces of the substrate. This results in improved performance.

[0022] Furthermore, in this first aspect, the first and second semiconductor chips may be placed in the first opening. This results in the advantage of requiring only one opening.

[0023] Furthermore, on this first side, a second opening may be formed in the substrate, and the second semiconductor chip may be placed in the second opening. This has the effect of reducing the difficulty of mounting.

[0024] Furthermore, in this first aspect, the first semiconductor chip may be equipped with a Time of Flight (ToF) sensor, and the second semiconductor chip may be equipped with a light-emitting element. This results in the function of measuring distance.

[0025] Furthermore, in this first aspect, the second semiconductor chip may be die-bonded to one of the two surfaces of the substrate, and the first and second semiconductor chips may be directly connected by wires. This has the effect of suppressing heat conduction between the chips.

[0026] Furthermore, in this first aspect, the second semiconductor chip may be bonded to one of the two surfaces of the substrate, and the first and second semiconductor chips may be connected via the substrate. This suppresses heat conduction between the chips, resulting in a reduction in the difficulty of mounting.

[0027] Furthermore, in this first aspect, the substrate may also be further equipped with chip components mounted on it. This results in improved performance.

[0028] Furthermore, in this first aspect, the size of the first semiconductor chip may be larger than the size of the first aperture, and the first semiconductor chip may be die-bonded around the first aperture on one of the surfaces. This improves the stability of wire bonding and simplifies the manufacturing process.

[0029] Furthermore, in this first aspect, the substrate may be a flat substrate. This eliminates the need for substrate processing.

[0030] Furthermore, in this first aspect, the substrate may have a step formed around the first opening. This has the effect of shortening the wire length.

[0031] Furthermore, a second aspect of this technology is a semiconductor package comprising a substrate having a first opening and a step formed around the first opening, a semiconductor chip disposed in the first opening and connected to one of the two surfaces of the substrate by a wire, a transparent member, a first resin for sealing the wire, and a second resin for bonding the transparent member to the region of the substrate outside the step on one of the surfaces. This has the effect of increasing the gap between the transparent member and the chip.

[0032] Furthermore, a third aspect of this technology is a method for manufacturing a semiconductor package, comprising the steps of: placing a first semiconductor chip in a first opening formed in a substrate; connecting the first semiconductor chip and the substrate with a wire; sealing the wire with a first resin; and bonding a transparent member with the first resin. This has the effect of suppressing warping of the chip.

[0033] Furthermore, in this third aspect, the procedure may further include a step of forming protrusions along the outer circumference of the transparent member that protrude from the surface of the transparent member, prior to the bonding procedure. This has the effect of suppressing displacement of the transparent member.

[0034] This is a cross-sectional view showing an example of the configuration of a semiconductor package in the first embodiment of this technology. This is a cross-sectional view and a top view illustrating the procedure for mounting a substrate assembly in the first embodiment of this technology. This is a cross-sectional view and a top view illustrating the procedure for mounting a sensor chip in the first embodiment of this technology. This is a cross-sectional view and a top view illustrating the procedure for wire bonding in the first embodiment of this technology. This is a cross-sectional view and a top view illustrating the procedure for applying resin in the first embodiment of this technology. This is a cross-sectional view and a top view illustrating the procedure for mounting a transparent member in the first embodiment of this technology. This is a cross-sectional view and a top view illustrating the procedure for removing a support in the first embodiment of this technology. This is a cross-sectional view and a top view illustrating the procedure for forming a ball terminal in the first embodiment of this technology. This is a cross-sectional view and a top view illustrating the procedure for dicing in the first embodiment of this technology. This is a diagram showing an example of the simulation results in the first embodiment of this technology. This is a cross-sectional view and a top view showing an example of the configuration of a semiconductor package in a first modified example of the first embodiment of this technology. This is a cross-sectional view showing an example of the configuration of a semiconductor package in a second modified example of the first embodiment of this technology. This is a cross-sectional view and a top view showing an example configuration of a semiconductor package in a third modification of the first embodiment of this technology. This is a cross-sectional view and a top view showing an example configuration of a semiconductor package in a fourth modification of the first embodiment of this technology. This is a diagram for explaining the problems of the first embodiment of this technology. This is a cross-sectional view showing an example configuration of a semiconductor package in the second embodiment of this technology. This is a cross-sectional view and a top view for explaining the procedure for mounting a substrate assembly in the second embodiment of this technology. This is a cross-sectional view and a top view for explaining the procedure for mounting a sensor chip in the second embodiment of this technology. This is a cross-sectional view and a top view for explaining the procedure for wire bonding in the second embodiment of this technology. This is a cross-sectional view and a top view for explaining the procedure for applying adhesive resin in the second embodiment of this technology. This is a cross-sectional view and a top view for explaining the procedure for mounting a frame in the second embodiment of this technology.These are cross-sectional and top views illustrating the procedure for applying resin in the second embodiment of this technology. These are cross-sectional and top views illustrating the procedure for mounting a transparent member in the second embodiment of this technology. These are cross-sectional and top views illustrating the procedure for removing a support in the second embodiment of this technology. These are cross-sectional and top views illustrating the procedure for forming a ball terminal in the second embodiment of this technology. These are cross-sectional and top views illustrating the procedure for dicing in the second embodiment of this technology. These are examples of top, cross-sectional, and bottom views of a frame in the first modified example of the second embodiment of this technology. These are examples of top views of an organic substrate in the first modified example of the second embodiment of this technology. These are cross-sectional views showing an example configuration of a semiconductor package in the first modified example of the second embodiment of this technology. These are examples of plan views of a frame and organic substrate with reduced protrusions and fitting holes in the first modified example of the second embodiment of this technology. These are examples of cross-sectional views of a semiconductor package when the frame is floating in the first modified example of the second embodiment of this technology. These are examples of cross-sectional views of a semiconductor package and a bottom view of a frame in the second modified example of the second embodiment of this technology. This is an example of a cross-sectional view of a semiconductor package and a top view of an organic substrate in a third modified example of the second embodiment of this technology. This is an example of a cross-sectional view of a semiconductor package, a bottom view of a frame, and a perspective view of a notch in a fourth modified example of the second embodiment of this technology. This is an example of a cross-sectional view of a semiconductor package, a top view of a frame, and a perspective view of a notch in a fifth modified example of the second embodiment of this technology. This is a cross-sectional view showing an example of the configuration of a semiconductor package in the third embodiment of this technology. This is a cross-sectional view and a top view for explaining the procedure for mounting a substrate assembly in the third embodiment of this technology. This is a cross-sectional view and a top view for explaining the procedure for mounting a sensor chip in the third embodiment of this technology. This is a cross-sectional view and a top view for explaining the procedure for wire bonding in the third embodiment of this technology. This is a cross-sectional view and a top view for explaining the procedure for applying resin in the third embodiment of this technology.These are cross-sectional and top views illustrating the procedure for mounting a transparent member in the third embodiment of this technology. These are cross-sectional and top views illustrating the procedure for removing a support in the third embodiment of this technology. These are cross-sectional and top views illustrating the procedure for forming a ball terminal in the third embodiment of this technology. These are cross-sectional and top views illustrating the procedure for dicing in the third embodiment of this technology. These are cross-sectional views showing an example of the configuration of a semiconductor package in the first modified example of the third embodiment of this technology. These are cross-sectional views showing an example of the configuration of a semiconductor package in the second modified example of the third embodiment of this technology. These are cross-sectional, top, and bottom views showing an example of the configuration of a semiconductor package in the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for mounting a sensor chip and a companion chip in the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for wire bonding in the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for applying resin in the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for mounting a transparent member and pre-curing in the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for resin coating and curing in the fourth embodiment of this technology. These are cross-sectional, top, and bottom views showing an example configuration of a semiconductor package in the first modified example of the fourth embodiment of this technology. These are cross-sectional, top, and bottom views showing an example configuration of a semiconductor package in the second modified example of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for mounting a sensor chip and a companion chip in the second modified example of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for wire bonding in the second modified example of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for resin coating in the second modified example of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for mounting a transparent member and curing in the second modified example of the fourth embodiment of this technology.These are cross-sectional, top, and bottom views showing an example configuration of a semiconductor package in the third modification of the fourth embodiment of this technology. These are cross-sectional, top, and bottom views showing an example configuration of a semiconductor package in the fourth modification of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for mounting a sensor chip and a companion chip in the fourth modification of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for wire bonding in the fourth modification of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for applying resin in the fourth modification of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for mounting a transparent member and pre-curing in the fourth modification of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for applying resin and main curing in the fourth modification of the fourth embodiment of this technology. These are cross-sectional, top, and bottom views showing an example configuration of a semiconductor package in the fifth modification of the fourth embodiment of this technology. These are cross-sectional, top, and bottom views showing an example configuration of a semiconductor package in the sixth modification of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for mounting chip components in the sixth modification of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for mounting a substrate assembly in the sixth modification of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for mounting a sensor chip in the sixth modification of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for wire bonding in the sixth modification of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for applying resin in the sixth modification of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for mounting a transparent member and pre-curing in the sixth modification of the fourth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for applying resin and main curing in the sixth modification of the fourth embodiment of this technology. These are cross-sectional and plan views illustrating the procedure for forming protrusions on a transparent member in the fifth embodiment of this technology.These are cross-sectional and top views illustrating the procedure for applying resin in the fifth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for mounting a transparent member in the fifth embodiment of this technology. These are cross-sectional and bottom views showing an example configuration of a semiconductor package in the sixth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for applying die bond material in the sixth embodiment of this technology. These are plan views showing an example of a location to apply die bond material in the sixth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for die bonding in the sixth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for wire bonding in the sixth embodiment of this technology. These are cross-sectional and top views illustrating the procedure for applying resin in the sixth embodiment of this technology. These are cross-sectional views illustrating the procedure for mounting a transparent member in the sixth embodiment of this technology. These are cross-sectional views showing examples of application to other embodiments and modifications of the sixth embodiment of this technology. These are cross-sectional and bottom views showing an example configuration of a semiconductor package in a modification of the sixth embodiment of this technology. This is a block diagram showing an example of a schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation location of the external information detection unit and the imaging unit.

[0035] The following describes embodiments for implementing this technology. The description will proceed in the following order: 1. First Embodiment (Example of placing a chip in an opening in a substrate and sealing and bonding with a single resin) 2. Second Embodiment (Example of placing a chip in an opening in a substrate, supporting a transparent member with a frame, and sealing and bonding with a single resin) 3. Third Embodiment (Example of placing a chip in an opening in a substrate, supporting a transparent member outside the step of the substrate, and sealing and bonding with a single resin) 4. Fourth Embodiment (Example of placing multiple chips in an opening in a substrate and sealing and bonding with a single resin) 5. Fifth Embodiment (Example of placing a chip in an opening in a substrate and forming a protrusion on a transparent member) 6. Sixth Embodiment (Example of die-bonding a chip around an opening in a substrate) 7. Application Examples to Mobile Bodies

[0036] <1. First Embodiment> [Example of Semiconductor Package Configuration] Figure 1 is a cross-sectional view showing an example of the configuration of a semiconductor package 200 in the first embodiment of the present technology. As illustrated in figure a, the semiconductor package 200 comprises a transparent member 210, an organic substrate 220, a sensor chip 230, a resin 251, and a predetermined number of ball terminals 242. Glass or the like is used as the transparent member 210.

[0037] Hereinafter, a predetermined axis parallel to the substrate plane of the organic substrate 220 will be referred to as the "X-axis," and an axis perpendicular to that substrate plane will be referred to as the "Z-axis." Furthermore, an axis perpendicular to the X-axis and Z-axis will be referred to as the "Y-axis." In the figure, a and b show cross-sectional views from the Y-axis direction.

[0038] Furthermore, incident light is incident on one of the two sides of the sensor chip 230 through the transparent member 210. Hereinafter, the light-receiving side of the transparent member 210, the organic substrate 220, and the sensor chip 230 will be referred to as the "top surface," and the side opposite to the light-receiving side will be referred to as the "bottom surface" or "back surface."

[0039] An opening 221 is formed in the center of the organic substrate 220. In the figure, at point a, the opening 221 is formed between coordinates X1 and X2. A predetermined number of ball terminals 242 are arranged on the upper surface of the organic substrate 220. The organic substrate 220 is an example of a substrate described in the claims, and the ball terminals 242 are an example of an external terminal described in the claims.

[0040] The size of the sensor chip 230 is smaller than the size of the aperture 221, and the sensor chip 230 is positioned in the aperture 221. For example, an image sensor such as a CIS (CMOS Image Sensor) is used as the sensor chip 230. The upper surface of the sensor chip 230 is electrically connected to the upper surface of the organic substrate 220 by a wire 241. Note that the sensor chip 230 is an example of the first semiconductor chip described in the claims.

[0041] The resin 251 seals the wire 241 and bonds the transparent member 210 and the organic substrate 220 together. The viscosity of the resin 251 is preferably 60 to 120 Pascal-seconds (Pa·s). Further, the thixo ratio of the resin 251 is preferably 1.5 to 2.5. Note that the resin 251 is an example of the first resin recited in the claims.

[0042] b in the figure is an enlarged view of a portion surrounded by the one-dot chain line in a of the figure. As illustrated in b of the figure, contacts 222 are arranged along the periphery of the opening on the upper surface of the organic substrate 220, and one end of the wire 241 is connected to the contact 222.

[0043] Further, a distance dX between a side surface of the sensor chip 230 and a side surface of the organic substrate 220 is preferably 0.3 to 0.7 millimeters (mm).

[0044] As exemplified in a and b of the figure, since the sensor chip 230 is arranged in the opening 221 of the organic substrate 220, the back surface of the sensor chip 230 can be exposed. Since the back surface of the sensor chip 230 is not bonded to the organic substrate 220, warping of the sensor chip 230 caused by a difference in CTE between the sensor chip 230 and the organic substrate 220 can be suppressed.

[0045] Further, a heat dissipation member such as a heat sink can be bonded to the exposed back surface of the sensor chip 230. Accordingly, compared with a case where the back surface of the sensor chip 230 is bonded to the organic substrate 220 and a heat dissipation member is bonded to the lower surface of the organic substrate 220, contact thermal resistance can be reduced and heat dissipation performance can be improved.

[0046] Further, since both the sealing of the wire 241 and the bonding of the transparent member 210 are performed using the resin 251, it is not necessary to separately perform a step of applying a sealing resin and a step of applying a bonding resin.

[0047] [Method of Manufacturing Semiconductor Package] Next, a method of manufacturing the semiconductor package 200 according to the first embodiment will be described with reference to FIGS. 2 to 9.

[0048] First, as exemplified in a and b of FIG. 2, an aggregate substrate including a predetermined number of organic substrates 220 is mounted and bonded to a support 300. As the support 300, for example, a release sheet that can be bonded at room temperature is used. An opening is pre-formed in each of the organic substrates 220.

[0049] a in the figure shows a cross-sectional view as viewed from the Y-axis direction, and b in the figure shows a top view as viewed from the Z-axis direction. Further, the circle in b in the figure indicates a position where a ball terminal is to be formed. The same applies hereinafter.

[0050] Next, as exemplified in a and b of FIG. 3, a sensor chip 230 is disposed in the opening of each organic substrate 220 and bonded to the support 300.

[0051] Next, as exemplified in a and b of FIG. 4, each of the sensor chips 230 is electrically connected to the organic substrate 220 via a wire 241.

[0052] Next, as exemplified in a and b of FIG. 5, a resin 251 is applied along the outer periphery of the sensor chip 230, and the wire 241 is sealed. For example, a thermosetting resin is used as the resin 251.

[0053] Next, as exemplified in a and b of FIG. 6, a transparent member 210 is mounted and bonded to the resin 251. Then, the resin 251 is cured by curing or the like.

[0054] Next, as exemplified in a and b of FIG. 7, the support 300 is removed.

[0055] Next, as exemplified in a and b of FIG. 8, a predetermined number of ball terminals 242 are formed by reflow or the like. The alternate long and short dash line in b of the figure indicates a dicing line.

[0056] Next, as exemplified in a and b of FIG. 9, the aggregate substrate is singulated by dicing.

[0057] Figure 10 shows an example of simulation results in the first embodiment of this technology. A comparative example is a structure in which the back surface of the sensor chip 230 is bonded to the organic substrate 220 and wire bonded. Furthermore, the elastic modulus of the resin 251 in the first embodiment was set to various values, and the change in the warping of the sensor chip 230 at a predetermined temperature rise was determined by simulation.

[0058] As illustrated in the figure, the first embodiment exhibits less change in warping than the comparative example. Furthermore, the lower the elastic modulus of the resin 251, the smaller the change in warping.

[0059] Thus, according to the first embodiment of this technology, since the sensor chip 230 is placed in the opening 221 of the organic substrate 220, warping of the sensor chip 230 caused by differences in CTE can be suppressed.

[0060] [First Modification] In the first embodiment described above, ball terminals 242 were arranged on the upper surface of the organic substrate 220, but the configuration is not limited to this. The semiconductor package 200 in this first modification of the first embodiment differs from the first embodiment in that ball terminals 242 are arranged on the lower surface of the organic substrate 220.

[0061] Figure 11 shows a cross-sectional view and a top view of a semiconductor package 200 in a first modification of the first embodiment of the present technology. In the figure, a shows a cross-sectional view taken from the Y-axis direction, and b shows a top view taken from the Z-axis direction.

[0062] As illustrated in Figure a, the semiconductor package 200 in the first modification of the first embodiment differs from the first embodiment in that ball terminals 242 are arranged on the lower surface of the organic substrate 220. This allows the lower surface of the organic substrate 220 to be connected to a mounting substrate (not shown).

[0063] Thus, according to the first modification of the first embodiment of this technology, since the ball terminals 242 are arranged on the lower surface of the organic substrate 220, the lower surface of the organic substrate 220 can be connected to the mounting substrate.

[0064] [Second Modification] In the first embodiment described above, the resin 251 bonded the transparent member 210 and the organic substrate 220, but it is preferable to reduce the stress on the transparent member 210. The semiconductor package 200 in this first modification of the first embodiment differs from the first embodiment in that the resin has a two-layer structure.

[0065] Figure 12 is a cross-sectional view showing an example configuration of a semiconductor package 200 in a second modification of the first embodiment of the present technology. The semiconductor package 200 in the second modification of the first embodiment differs from the first embodiment in that it further comprises a resin 252.

[0066] The resin 252 is used to bond the side surface of the sensor chip 230 to the organic substrate 220. A resin with a higher elastic modulus than resin 251 is used for this resin 252. Note that resin 252 is an example of the second resin described in the claims. By bonding the side surface of the sensor chip 230 with the highly elastic resin 252 and the transparent member 210 with the low-elasticity resin 251, stress on the transparent member 210 can be reduced, and the occurrence of cracks due to stress can be suppressed.

[0067] Furthermore, the second modification of the first embodiment can be applied to the first modification of the first embodiment.

[0068] Thus, according to the second modification of the first embodiment of this technology, the stress on the transparent member 210 can be reduced by bonding the side surface of the sensor chip 230 with a highly elastic resin 252 and bonding the transparent member 210 with a low-elasticity resin 251.

[0069] [Third Modification] In the first embodiment described above, the resin 251 was used to seal the wire 241 and to bond the transparent member 210, but it is preferable to ensure a sufficient gap between the transparent member 210 and the sensor chip 230. The semiconductor package 200 in this third modification of the first embodiment differs from the first embodiment in that a recess is formed around the resin 251.

[0070] Figure 13 shows a cross-sectional view and a top view of a semiconductor package 200 in a first modification of the first embodiment of the present technology. In the figure, a shows a cross-sectional view taken from the Y-axis direction, and b shows a top view taken from the Z-axis direction.

[0071] As illustrated in Figures a and b, the semiconductor package 200 in the third modification of the first embodiment differs from the first embodiment in that a recess 223 is formed around the resin 251 on the upper surface of the organic substrate 220. This recess 223 suppresses the outward spreading of the resin 251. Furthermore, if the size of the resin 251 in the X-axis and Y-axis directions is defined as "width" and the size of the resin 251 in the Z-axis direction is defined as "height", the height can be made larger relative to the width by suppressing the spreading of the resin 251. As a result, a sufficient gap can be secured between the transparent member 210 and the sensor chip 230.

[0072] Furthermore, the third modification of the first embodiment can be applied to each of the first and second modifications of the first embodiment.

[0073] Thus, according to the third modification of the first embodiment of this technology, since a recess 223 is formed around the resin 251 on the upper surface of the organic substrate 220, the spreading of the resin 251 is suppressed, and the height of the resin 251 can be increased relative to its width.

[0074] [Fourth Modification] In the first embodiment described above, ball terminals 242 were arranged on the upper surface of the organic substrate 220, but this configuration can make it difficult to connect to external devices. The semiconductor package 200 in this fourth modification of the first embodiment differs from the first embodiment in that a flexible cable is connected to the ball terminals 242 of the organic substrate 220.

[0075] Figure 14 shows a cross-sectional view and a top view of a semiconductor package 200 in a fourth modification of the first embodiment of the present technology. In the figure, a shows a cross-sectional view taken from the Y-axis direction, and b shows a top view taken from the Z-axis direction.

[0076] As illustrated in figure a, the semiconductor package 200 in the fourth modification of the first embodiment differs from the first embodiment in that it further includes a flexible cable 261 and a connector 262. Flexible printed circuits (FPC) or the like are used as the flexible cable 261.

[0077] One end of the flexible cable 261 is connected to the ball terminal 242 of the organic substrate 220, and the other end of the flexible cable 261 is connected to a connector 262. Various external devices (not shown) can be connected to this connector 262. The flexible cable 261 allows wiring to be extended to the external devices.

[0078] Furthermore, the fourth modification of the first embodiment can be applied to each of the first, second, and third modifications of the first embodiment.

[0079] Thus, according to the third modification of the first embodiment of this technology, since the flexible cable 261 is connected to the ball terminal 242 of the organic substrate 220, the wiring can be extended to an external device.

[0080] <2. Second Embodiment> In the first embodiment described above, the transparent member 210 was bonded with resin 251. However, in this configuration, the mounting position of the transparent member 210 is determined solely by the resin 251, raising concerns that the gap between the sensor chip 230 and the transparent member 210 may become narrow. In Figure 15, dZ in a indicates the gap.

[0081] If this gap dZ becomes narrower, foreign matter resting on the transparent member 210 or pinholes in the AR (Anti-Reflective) coating film will be more susceptible to the effects of foreign matter and pinholes, worsening the stain. Also, the longer the path to the effective pixels on the sensor chip 230, the weaker the effect on flare. For this reason, it is preferable that the gap dZ be 0.3 millimeters (mm) or more.

[0082] Furthermore, in the first embodiment, since the mounting position of the transparent member 210 is determined solely by the resin 251, there is a concern that the parallelism between the transparent member 210 and the sensor chip 230 cannot be ensured, as illustrated in figure b. The semiconductor package 200 in the second embodiment differs from the first embodiment in that the frame is bonded to the organic substrate 220.

[0083] Figure 16 is a cross-sectional view showing an example configuration of a semiconductor package 200 in a second embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200 in the second embodiment, and b shows an enlarged view of the portion enclosed by the dashed line in a.

[0084] As illustrated in figures a and b, the semiconductor package 200 in the second embodiment differs from the first embodiment in that it further comprises a frame 270.

[0085] The frame 270 is a frame-shaped member, and its lower surface is bonded to the outside of the contact 222 of the organic substrate 220 with adhesive resin 243. The transparent member 210 is supported on the upper surface of the frame 270 and bonded with resin 251. By mounting this frame 270, a sufficient gap (such as 0.3 mm or more) can be secured between the sensor chip 230 and the transparent member 210. In addition, since the transparent member 210 is supported on the upper surface of the frame 270, parallelism between the transparent member 210 and the sensor chip 230 can be ensured.

[0086] Next, with reference to Figures 17 to 26, a method for manufacturing the semiconductor package 200 in the second embodiment will be described.

[0087] First, as illustrated in Figures 17 a and b, the substrate assembly is mounted and bonded to the support 300.

[0088] Next, as illustrated in Figures 18 a and b, the sensor chips 230 are placed in the openings of each organic substrate 220 and bonded to the support 300.

[0089] Next, as illustrated in Figures 19 a and b, each of the sensor chips 230 is electrically connected to the organic substrate 220 by wires 241.

[0090] Next, as illustrated in Figures a and b, adhesive resin 243 is applied around the wire 241.

[0091] Next, the frame 270 is mounted and bonded, as illustrated in Figures 21 a and b.

[0092] Next, as illustrated in Figures a and b, resin 251 is applied along the outer circumference of the sensor chip 230, and the wire 241 is sealed.

[0093] Next, as illustrated in Figures 23 a and b, the transparent member 210 is mounted and bonded to the resin 251. Then, the resin 251 is cured by curing or the like.

[0094] Next, the support 300 is removed, as illustrated in Figures a and b of Figure 24.

[0095] Next, a predetermined number of ball terminals 242 are formed by reflow or the like, as illustrated in Figures a and b of 25. The dashed line in Figure b indicates the dicing line.

[0096] Next, as illustrated in Figures 26 a and b, the assembled substrate is divided into individual pieces by dicing.

[0097] Furthermore, the second embodiment can be applied to each of the first, second, third, and fourth modifications of the first embodiment.

[0098] Thus, according to the second embodiment of this technology, a frame 270 is added and the transparent member 210 is supported on the upper surface of the frame 270, so the gap can be made sufficiently wide and the parallelism between the transparent member 210 and the sensor chip 230 can be ensured.

[0099] [First Modification] In the second embodiment described above, the lower surface of the frame 270 was bonded to the organic substrate 220, but it is preferable to prevent the frame 270 from shifting position. The semiconductor package 200 in the first modification of this second embodiment differs from the second embodiment in that the protrusions of the frame 270 are fitted into the fitting holes of the organic substrate 220.

[0100] Figure 27 shows examples of a top view, cross-sectional view, and bottom view of a frame 270 in a first modification of the second embodiment of the present technology. In the figure, a is an example of a top view of the frame 270, and b is an example of a cross-sectional view of the frame 270. In the figure, c is an example of a bottom view of the frame 270. As illustrated in b and c of the figure, in the first modification of the second embodiment, projections 271 that protrude downward are formed at the four corners of the bottom surface of the frame 270.

[0101] Figure 28 is an example of a top view of an organic substrate 220 in a first modification of the second embodiment of the present technology. As illustrated in Figure a, in the first modification of the second embodiment, four fitting holes 224 are formed around the opening 221 of the organic substrate 220 for fitting with the projection 271 of the frame 270. In Figure a, the shape of each fitting hole 224 is circular.

[0102] Furthermore, as illustrated in figure b, the shape of the two diagonally opposite fitting holes 224 can be made elliptical, and the shape of the remaining two can be made circular, taking into consideration ease of fitting. In this case, the shape of the projection 271 will also be circular or elliptical to match the fitting holes 224.

[0103] Figure 29 is a cross-sectional view showing an example configuration of a semiconductor package 200 in a first modification of the second embodiment of the present technology. As illustrated in the figure, the projection 271 of the frame 270 is fitted into the fitting hole 224 of the organic substrate 220. This allows the frame 270 to be temporarily fixed and prevents misalignment of the frame 270.

[0104] The number of projections 271 and fitting holes 224 is not limited to four.

[0105] For example, as illustrated in Figure 30a, the protrusions 271 of the frame 270 can be two diagonally opposite each other. In this case, as illustrated in Figure 30b, the fitting holes 224 of the organic substrate 220 can also be just two diagonally opposite each other.

[0106] Furthermore, as illustrated in Figure 31, the projection 271 of the frame 270 can be lengthened, causing the entire lower surface of the frame 270 to float and creating a gap between it and the organic substrate 220. By allowing the resin 251 to escape into this gap, it is possible to prevent the resin 251 from overflowing onto the sensor chip 230. In this case, the adhesive resin 243 is not used. Alternatively, the adhesive resin 243 can be used to bond only a portion of the lower surface of the frame 270.

[0107] Furthermore, the first modification of the second embodiment can be applied to each of the first, second, third, and fourth modifications of the first embodiment.

[0108] Thus, according to the first modification of the second embodiment of this technology, the projection 271 of the frame 270 is fitted into the fitting hole 224 of the organic substrate 220, thereby preventing misalignment of the frame 270.

[0109] [Second Modification] In the first modification of the second embodiment described above, the wire 241 was sealed with resin 251, but there is a risk that the resin 251 may protrude onto the image plane of the sensor chip 230. The semiconductor package 200 in this second modification of the second embodiment differs from the first modification of the second embodiment in that a groove is provided on the inner wall of the frame 270.

[0110] Figure 32 is an example of a cross-sectional view of the semiconductor package 200 and a bottom view of the frame 270 in a second modification of the second embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200, and b shows a bottom view of the frame 270.

[0111] As illustrated in figures a and b, in the second modification of the second embodiment, a groove 272 is formed along the lower inner wall of the frame 270. By allowing the resin 251 to escape into this groove 272, it is possible to prevent the resin 251 from overflowing.

[0112] Furthermore, the second modification of the second embodiment can be applied to each of the first, second, third, and fourth modifications of the first embodiment.

[0113] Thus, according to the second modification of the second embodiment of this technology, a groove 272 is formed along the lower inner wall of the frame 270, which prevents the resin 251 from overflowing.

[0114] [Third Modification] In the first modification of the second embodiment described above, the wire 241 was sealed with resin 251, but there is a risk that the resin 251 may protrude onto the image plane of the sensor chip 230. The semiconductor package 200 in this third modification of the second embodiment differs from the first modification of the second embodiment in that a dam is provided on the organic substrate 220.

[0115] Figure 33 is an example of a cross-sectional view of the semiconductor package 200 and a top view of the organic substrate 220 in a third modification of the second embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200, and b shows a top view of the organic substrate 220.

[0116] As illustrated in Figures a and b, in the third modification of the second embodiment, a dam 225 is formed on the upper surface of the organic substrate 220 between the inner wall of the frame 270 and the contact 222. By allowing the resin 251 to escape into the space between the dam 225 and the frame 270, the overflow of the resin 251 can be prevented.

[0117] Furthermore, the third modification of the second embodiment can be applied to each of the first, second, third, and fourth modifications of the first embodiment and the second modification of the second embodiment.

[0118] Thus, according to the third modification of the second embodiment of this technology, a dam 225 is formed between the contact 222 of the organic substrate 220 and the inner wall of the frame 270, thereby preventing the resin 251 from overflowing.

[0119] [Fourth Modification] In the first modification of the second embodiment described above, the wire 241 was sealed with resin 251, but there is a risk of voids forming in the resin 251. The semiconductor package 200 in this fourth modification of the second embodiment differs from the first modification of the second embodiment in that a notch is formed on the lower surface of the frame 270.

[0120] Figure 34 shows an example of a cross-sectional view of the semiconductor package 200, a bottom view of the frame 270, and a perspective view of the notch in a fourth modification of the second embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200, b shows a bottom view of the frame 270, and c shows a perspective view of the notch.

[0121] As illustrated in figures a and b, in the fourth modification of the second embodiment, a predetermined number of notches 273 are formed on the lower surface of the frame 270. By allowing voids to escape through these notches 273, the generation of voids can be suppressed.

[0122] Furthermore, the fourth modification of the second embodiment can be applied to the first, second, third, and fourth modifications of the first embodiment, and to the second and third modifications of the second embodiment, respectively.

[0123] Thus, according to the fourth modification of the second embodiment of this technology, since a notch 273 is formed on the lower surface of the frame 270, the generation of voids can be suppressed.

[0124] [Fifth Modification] In the first modification of the second embodiment described above, the wire 241 was sealed with resin 251, but there is a risk of voids forming in the resin 251. The semiconductor package 200 in this fifth modification of the second embodiment differs from the first modification of the second embodiment in that a notch is formed on the upper surface of the frame 270.

[0125] Figure 35 shows an example of a cross-sectional view of the semiconductor package 200, a bottom view of the frame 270, and a perspective view of the notch in a fifth modification of the second embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200, b shows a top view of the frame 270, and c shows a perspective view of the notch.

[0126] As illustrated in figures a and b, in the fifth modification of the second embodiment, a predetermined number of notches 274 are formed on the upper surface of the frame 270. By allowing voids to escape through these notches 274, the generation of voids can be suppressed.

[0127] Furthermore, the fifth modification of the second embodiment can be applied to each of the first, second, third, and fourth modifications of the first embodiment and the second, third, and fourth modifications of the second embodiment.

[0128] Thus, according to the fifth modification of the second embodiment of this technology, since a notch 274 is formed on the lower surface of the frame 270, the generation of voids can be suppressed.

[0129] <3. Third Embodiment> In the first embodiment described above, the mounting position of the transparent member 210 is determined solely by the resin 251, raising concerns that parallelism between the transparent member 210 and the sensor chip 230 cannot be ensured, as illustrated in figure b. The semiconductor package 200 in the third embodiment differs from the first embodiment in that a step is provided in the organic substrate 220, and the transparent member 210 is supported in the area surrounding the step.

[0130] Figure 36 is a cross-sectional view showing one example of the configuration of a semiconductor package 200 in a third embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200 in the third embodiment, and b shows an enlarged view of the portion enclosed by the dashed line in a.

[0131] As illustrated in Figure b, the semiconductor package 200 in the third embodiment differs from the first embodiment in that a step 226 is formed around the opening 221 on the upper surface of the organic substrate 220. The inside of the step 226 is lower than the outside of the step 226, and the transparent member 210 is supported in the area outside the step 226. In Figure b, the step 226 is formed at coordinate X32. The height from coordinate X32 to coordinate X1 on the outer periphery of the opening 221 is lower than the outside of coordinate X32 (the left side of Figure b). The transparent member 210 is mounted in the area from coordinate X31 to X32. No resin 251 is filled between the transparent member 210 and the organic substrate 220, and the transparent member 210 is placed with its lower surface in contact with the organic substrate 220.

[0132] By supporting the transparent member 210 outside the step 226 of the organic substrate 220, the parallelism between the transparent member 210 and the sensor chip 230 can be ensured. In addition, it is possible to prevent the resin 251 from leaking outside the step 226 and reaching the ball terminal 242.

[0133] Alternatively, a ceramic substrate can be used instead of the organic substrate 220.

[0134] Next, with reference to Figures 37 to 44, the manufacturing method of the semiconductor package 200 in the first embodiment will be described.

[0135] First, as illustrated in Figures 37 a and b, a composite substrate containing a predetermined number of organic substrates 220 is mounted and bonded to the support 300. Each of the organic substrates 220 has a step 226 pre-formed on it.

[0136] Next, as illustrated in Figures 38 a and b, the sensor chips 230 are placed in the openings of each organic substrate 220 and bonded to the support 300.

[0137] Next, as illustrated in Figures 39 a and b, each of the sensor chips 230 is electrically connected to the organic substrate 220 by wires 241.

[0138] Next, as illustrated in Figures 40 a and b, resin 251 is applied along the outer circumference of the sensor chip 230, and the wire 241 is sealed.

[0139] Next, as illustrated in Figures 41 a and b, the transparent member 210 is mounted on the organic substrate 220 and bonded with resin 251. Then, the resin 251 is cured by curing or the like.

[0140] Next, the support 300 is removed, as illustrated in Figures 42 a and b.

[0141] Next, a predetermined number of ball terminals 242 are formed by reflow or the like, as illustrated in Figures a and b of Figure 43. The dashed line in b of the same figure indicates the dicing line.

[0142] Next, as illustrated in Figures 44 a and b, the assembled substrate is divided into individual pieces by dicing.

[0143] Furthermore, the third embodiment can be applied to each of the first, second, third, and fourth modifications of the first embodiment.

[0144] Thus, according to the third embodiment of this technology, a step is provided in the organic substrate 220, and the transparent member 210 is supported in the area surrounding the step, thereby ensuring parallelism between the transparent member 210 and the sensor chip 230.

[0145] [First Modification] In the third embodiment described above, the resin 251 was not filled between the transparent member 210 and the organic substrate 220, but the configuration is not limited to this. The semiconductor package 200 in this first modification of the third embodiment differs from the third embodiment in that the resin 251 is also filled between the transparent member 210 and the organic substrate 220.

[0146] Figure 45 is a cross-sectional view showing one example of the configuration of a semiconductor package 200 in a first modification of the third embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200 in the first modification of the third embodiment, and b shows an enlarged view of the portion enclosed by the dashed line in a.

[0147] As illustrated in Figures a and b, in the first modification of the third embodiment, resin 251 is also filled between the transparent member 210 and the organic substrate 220. As a result, the area outside the step 226 between the transparent member 210 and the organic substrate 220 is bonded with resin 251. This increases the bonding area of ​​the transparent member 210.

[0148] Furthermore, the first modification of the third embodiment can be applied to each of the first, second, third, and fourth modifications of the first embodiment.

[0149] Thus, according to the first modification of the third embodiment of this technology, the transparent member 210 and the area outside the step 226 of the organic substrate 220 are bonded with resin 251, making it possible to increase the bonding area of ​​the transparent member 210.

[0150] [Second Modification] In the third embodiment described above, the resin 251 sealed the wire 241 while bonding the transparent member 210, but the configuration is not limited to this. The semiconductor package 200 in the second modification of this third embodiment differs from the third embodiment in that the resin 251 seals the wire 241 while another resin bonds the transparent member 210.

[0151] Figure 46 is a cross-sectional view showing an example configuration of a semiconductor package 200 in a second modification of the third embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200 in the second modification of the third embodiment, and b shows an enlarged view of the portion enclosed by the dashed line in a.

[0152] As illustrated in Figures a and b, the semiconductor package 200 in the second modification of the third embodiment differs from the third embodiment in that a resin 253 is further used. In addition, the resin 251 seals the wire 241, but the transparent member 210 is not bonded to the resin 251.

[0153] The resin 253 adheres the transparent member 210 to the area of ​​the upper surface of the organic substrate 220 that is outside the step 226. The resin 253 is an example of the second resin described in the claims.

[0154] Since the resin 251 does not need to adhere to the transparent member 210, the gap between the transparent member 210 and the sensor chip 230 can be increased without changing the amount of resin 251 applied.

[0155] Furthermore, the second modification of the third embodiment can be applied to each of the first, second, third, and fourth modifications of the first embodiment.

[0156] Thus, according to the second modification of the third embodiment of this technology, the resin 251 seals the wire 241 and the resin 253 adheres to the transparent member 210, making it possible to increase the gap between the transparent member 210 and the sensor chip 230.

[0157] <4. Fourth Embodiment> In the first embodiment described above, only one semiconductor chip (i.e., sensor chip 230) was provided in the semiconductor package 200, but it is also possible to provide two or more semiconductor chips. The semiconductor package 200 in this fourth embodiment differs from the first embodiment in that it provides two or more semiconductor chips.

[0158] Figure 47 shows a cross-sectional view, a top view, and a bottom view illustrating an example configuration of a semiconductor package 200 in a fourth embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200, b shows a top view of the semiconductor package 200, and c shows a bottom view of the semiconductor package 200.

[0159] As illustrated in figure a, the semiconductor package 200 in the fourth embodiment differs from the first embodiment in that it includes a companion chip 235 in addition to the sensor chip 230.

[0160] The companion chip 235 is connected to the sensor chip 230 and the organic substrate 220 by wires 241. For example, a logic chip that processes signals from the sensor chip 230 can be used as the companion chip 235. The logic chip can perform AI (Artificial Intelligence) processing such as object recognition. The addition of the companion chip 235 can improve the performance of the semiconductor package 200.

[0161] The sensor chip 230 and the companion chip 235 are examples of the first and second semiconductor chips described in the claims.

[0162] Furthermore, although two semiconductor chips are provided, it is also possible to provide three or more semiconductor chips. The same applies to each of the modifications of the fourth embodiment described later.

[0163] As illustrated in figure b, the upper surface of the companion tip 235 is covered with resin 251.

[0164] Furthermore, as illustrated in figure c, the combined size of the sensor chip 230 and the companion chip 235 is smaller than the size of the opening 221, and these chips are positioned within the opening 221. By exposing the back surfaces of these chips, heat dissipation performance can be improved.

[0165] Next, with reference to Figures 48 to 52, a method for manufacturing the semiconductor package 200 in the fourth embodiment will be described.

[0166] First, as illustrated in Figures 48 a and b, a composite substrate containing a predetermined number of organic substrates 220 is mounted and bonded to the support 300. The dashed lines in Figures 48 a and b indicate the dicing lines. Sensor chips 230 and companion chips 235 are placed in the openings of the organic substrates 220 and bonded to the support 300.

[0167] Next, as illustrated in Figures 49 a and b, the sensor chip 230 and the companion chip 235 are electrically connected by wires 241.

[0168] Next, as illustrated in Figures 50 a and b, resin 251 is applied along the outer circumference of the sensor chip 230, and the wire 241 is sealed.

[0169] Next, as illustrated in Figures 51 a and b, the transparent member 210 is mounted and bonded to the resin 251. Then, temporary curing is performed by irradiation with ultraviolet light or the like, and the resin 251 is partially hardened.

[0170] If heat treatment were used instead of UV irradiation, the resin 251 would shrink, potentially impairing the parallelism of the transparent member 210. By pre-curing with UV irradiation, the parallelism of the transparent member 210 can be maintained.

[0171] Furthermore, from the viewpoint of maintaining the parallelism of the transparent member 210, it is preferable to make the chip thickness of the sensor chip 230 and the substrate thickness of the organic substrate 220 the same.

[0172] Next, as illustrated in Figures 52 a and b, resin 251 is applied to the companion tip 235. Then, curing is performed by heat treatment or the like, and the resin 251 is hardened.

[0173] Then, the support 300 is removed, a predetermined number of ball terminals 242 (not shown) are formed, and the assembled substrate is separated into individual pieces.

[0174] Furthermore, the fourth embodiment can be applied to each of the variations of the first embodiment, the second and third embodiments, and each of the variations of the second and third embodiments.

[0175] Thus, according to the fourth embodiment of this technology, since multiple semiconductor chips are provided, the performance of the semiconductor package 200 can be improved compared to the case where there is only one semiconductor chip.

[0176] [First Modification] In the fourth embodiment described above, two semiconductor chips were placed in one opening, but this configuration can make it difficult to connect the chips. The semiconductor package 200 in this first modification of the fourth embodiment differs from the fourth embodiment in that a semiconductor chip is placed in each of the two openings and the chips are connected to each other via an organic substrate 220.

[0177] Figure 53 is a cross-sectional view, a top view, and a bottom view showing an example configuration of a semiconductor package 200 in a first modification of the fourth embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200, b shows a top view of the semiconductor package 200, and c shows a bottom view of the semiconductor package 200.

[0178] As illustrated in figure c, the organic substrate 220 of the fourth embodiment has openings 221-1 and 221-2 formed therein. The size of the sensor chip 230 is smaller than the opening 221-1, and the sensor chip 230 is placed in opening 221-1. The size of the companion chip 235 is smaller than the opening 221-2, and the companion chip 235 is placed in opening 221-2.

[0179] Furthermore, as illustrated in figure a, the sensor chip 230 and the companion chip 235 are connected by a wire 241 to the portion of the organic substrate 220 between openings 221-1 and 221-2. This allows the sensor chip 230 and the companion chip 235 to be connected via the organic substrate 220. In this way, the organic substrate 220 functions as an interposer substrate. This configuration makes mounting easier compared to directly connecting the chips.

[0180] The method for manufacturing the semiconductor package 200 of the first modification of the fourth embodiment is the same as that of the fourth embodiment, except that each chip is connected to the organic substrate 220 in wire bonding.

[0181] Furthermore, the first modified example of the fourth embodiment can be applied to each of the modifications of the first embodiment, the second and third embodiments, and each of the modifications of the second and third embodiments.

[0182] Thus, according to the first modification of the fourth embodiment of this technology, the sensor chip 230 and the companion chip 235 are connected via the organic substrate 220, thereby reducing the difficulty of implementation.

[0183] [Second Modification] In the fourth embodiment described above, a sensor chip 230 (such as a CIS) and a companion chip 235 (such as a logic chip) were arranged, but instead of these, a ToF sensor and a laser chip can also be arranged. The semiconductor package 200 in this second modification of the fourth embodiment differs from the fourth embodiment in that it arranges a ToF sensor and a laser chip.

[0184] Figure 54 shows a cross-sectional view, a top view, and a bottom view of a semiconductor package 200 in a second modification of the fourth embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200, b shows a top view of the semiconductor package 200, and c shows a bottom view of the semiconductor package 200.

[0185] As illustrated in figures a, b, and c, in the second modification of the fourth embodiment, a sensor chip 231 and a laser chip 236 are arranged instead of the sensor chip 230 and the companion chip 235.

[0186] The sensor chip 231 includes, for example, a ToF sensor. This ToF sensor receives reflected light from the light emitted from the laser chip 236 and measures the distance to the object to be measured using the ToF method.

[0187] Furthermore, the laser chip 236 is equipped with a predetermined number of light-emitting elements, such as semiconductor lasers. Only the portion of the upper surface of the laser chip 236 surrounding the light-emitting region where the semiconductor lasers are arranged is sealed with resin 251. In addition, the transparent member 210 covers the upper surfaces of the sensor chip 231 and the laser chip 236, and these chips are sealed within a cavity surrounded by the transparent member 210 and the resin 251.

[0188] The sensor chip 231 and the laser chip 236 are examples of the first and second semiconductor chips described in the claims.

[0189] Next, with reference to Figures 55 to 58, a method for manufacturing the semiconductor package 200 in a second modified example of the fourth embodiment will be described.

[0190] First, as illustrated in Figures a and b of Figure 55, a composite substrate containing a predetermined number of organic substrates 220 is mounted and bonded to the support 300. The dashed lines in Figures a and b indicate the dicing lines. A sensor chip 231 and a laser chip 236 are then placed in the openings 221 of the organic substrates 220 and bonded to the support 300.

[0191] Next, as illustrated in Figures 56 a and b, the sensor chip 231 and the laser chip 236 are electrically connected by wires 241.

[0192] Next, as illustrated in Figures 57 a and b, resin 251 is applied along the outer circumference of the sensor chip 231 and the laser chip 236, respectively, and the wire 241 is sealed. In order to maintain the parallelism of the transparent member 210, the amount of resin around each chip is adjusted as appropriate so that it is equal.

[0193] Next, as illustrated in Figures 58 a and b, the transparent member 210 is mounted and bonded to the resin 251. Then, curing is performed by heat treatment or the like, and the resin 251 hardens.

[0194] Then, the support 300 is removed, a predetermined number of ball terminals 242 (not shown) are formed, and the assembled substrate is separated into individual pieces.

[0195] Furthermore, the second modified example of the fourth embodiment can be applied to each of the modifications of the first embodiment, the second and third embodiments, and each of the modifications of the second and third embodiments.

[0196] Thus, according to the second modification of the fourth embodiment of this technology, since the sensor chip 231 and the laser chip 236 are arranged, distance can be measured by the Time of Flight (ToF) method.

[0197] [Third Modification] In the second modification of the fourth embodiment described above, two semiconductor chips were placed in one opening, but this can make it difficult to connect the chips. The semiconductor package 200 in this third modification of the fourth embodiment differs from the second modification of the fourth embodiment in that a semiconductor chip is placed in each of the two openings and the chips are connected to each other via an organic substrate 220.

[0198] Figure 59 shows a cross-sectional view, a top view, and a bottom view of a semiconductor package 200 in a third modification of the fourth embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200, b shows a top view of the semiconductor package 200, and c shows a bottom view of the semiconductor package 200.

[0199] As illustrated in figure c, the organic substrate 220 of the fourth embodiment has openings 221-1 and 221-2 formed therein. The size of the sensor chip 231 is smaller than the opening 221-1, and the sensor chip 231 is placed in opening 221-1. The size of the laser chip 236 is smaller than the opening 221-2, and the laser chip 236 is placed in opening 221-2.

[0200] The method for manufacturing the semiconductor package 200 in the third modification of the fourth embodiment is the same as the second modification of the fourth embodiment, except that each chip is connected to the organic substrate 220 in wire bonding.

[0201] Furthermore, the third modification of the fourth embodiment can be applied to each of the modifications of the first embodiment, the second and third embodiments, and each of the modifications of the second and third embodiments.

[0202] Thus, according to the third modification of the fourth embodiment of this technology, the sensor chip 231 and the laser chip 236 are connected via the organic substrate 220, thereby reducing the difficulty of implementation.

[0203] [Fourth Modification] In the fourth embodiment described above, both the sensor chip 230 and the companion chip 235 were placed in the opening 221, but there was a risk that heat generated by one of these chips would be conducted to the other. The semiconductor package 200 in this fourth modification of the fourth embodiment differs from the fourth embodiment in that the companion chip 235 is mounted on the upper surface of the organic substrate 220.

[0204] Figure 60 shows a cross-sectional view, a top view, and a bottom view of a semiconductor package 200 in a fourth modification of the fourth embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200, b shows a top view of the semiconductor package 200, and c shows a bottom view of the semiconductor package 200.

[0205] As illustrated in Figure a, in the fourth modification of the fourth embodiment, only the sensor chip 230 is placed in the opening 221. The companion chip 235 is die-bonded to the upper surface of the organic substrate 220 and connected to the sensor chip 230 and the organic substrate 220 by wires 241. By mounting the companion chip 235 on the organic substrate 220 in this way, it is possible to thermally separate it from the sensor chip 230 and suppress the conduction of heat generated in one chip to the other chip.

[0206] Next, with reference to Figures 61 to 65, a method for manufacturing the semiconductor package 200 in a fourth modified example of the fourth embodiment will be described.

[0207] First, as illustrated in Figures 61 a and b, a composite substrate containing a predetermined number of organic substrates 220 is mounted and bonded to the support 300. The dashed lines in Figures 61 a and b indicate the dicing lines. Sensor chips 230 are placed in the openings of the organic substrates 220 and bonded to the support 300. Companion chips 235 are die-bonded to the upper surface of the organic substrates 220.

[0208] Next, as illustrated in Figures 62 a and b, the sensor chip 230 and the companion chip 235 are electrically connected by wires 241.

[0209] Next, as illustrated in Figures 63 a and b, resin 251 is applied along the outer circumference of the sensor chip 230, and the wire 241 is sealed.

[0210] Next, as illustrated in Figures 64 a and b, the transparent member 210 is mounted and bonded to the resin 251. Then, temporary curing is performed by irradiation with ultraviolet light or the like, and the resin 251 is partially hardened.

[0211] Next, as illustrated in Figures 65 a and b, resin 251 is applied to the companion tip 235. Then, curing is performed by heat treatment or the like, and the resin 251 is hardened.

[0212] Then, the support 300 is removed, a predetermined number of ball terminals 242 (not shown) are formed, and the assembled substrate is separated into individual pieces.

[0213] Furthermore, the fourth modification of the fourth embodiment can be applied to each of the modifications of the first embodiment, the second and third embodiments, and each of the modifications of the second and third embodiments.

[0214] Thus, according to the fourth modification of the fourth embodiment of this technology, since the companion chip 235 is mounted on the upper surface of the organic substrate 220, the conduction of heat generated in one chip to the other chip can be suppressed.

[0215] [Fifth Modification] In the fourth modification of the fourth embodiment described above, the sensor chip 230 and the companion chip 235 were directly connected by a wire 241, but in this configuration, it can be difficult to connect the chips. The semiconductor package 200 in this fifth modification of the fourth embodiment differs from the fourth modification of the fourth embodiment in that the chips are connected to each other via an organic substrate 220.

[0216] Figure 66 is a cross-sectional view, a top view, and a bottom view showing an example configuration of a semiconductor package 200 in a fifth modification of the fourth embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200, b shows a top view of the semiconductor package 200, and c shows a bottom view of the semiconductor package 200.

[0217] As illustrated in figure a, in the fifth modification of the fourth embodiment, the sensor chip 230 and the companion chip 235 are connected via the organic substrate 220.

[0218] The method for manufacturing the semiconductor package 200 in the fifth modification of the fourth embodiment is the same as the fourth modification of the fourth embodiment, except that each chip is connected to the organic substrate 220 in wire bonding.

[0219] Furthermore, the fifth modification of the fourth embodiment can be applied to each of the modifications of the first embodiment, the second and third embodiments, and each of the modifications of the second and third embodiments.

[0220] Thus, according to the fifth modification of the fourth embodiment of this technology, the sensor chip 230 and the companion chip 235 are connected via the organic substrate 220, thereby reducing the difficulty of implementation.

[0221] [Sixth Modification] In the fourth embodiment described above, multiple semiconductor chips were arranged within the semiconductor package 200, but it is also possible to mount additional chip components. The semiconductor package 200 in this sixth modification of the fourth embodiment differs from the fourth embodiment in that it has chip components mounted on it.

[0222] Figure 67 shows a cross-sectional view, a top view, and a bottom view of a semiconductor package 200 in a sixth modification of the fourth embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200, b shows a top view of the semiconductor package 200, and c shows a bottom view of the semiconductor package 200.

[0223] As illustrated in figures a and b, in the sixth modification of the fourth embodiment, a predetermined number of chip components 244 (such as resistors and capacitors) are further mounted on the upper surface of the organic substrate 220. This improves the performance of the semiconductor package 200.

[0224] Next, with reference to Figures 68 to 74, a method for manufacturing the semiconductor package 200 in a sixth modified example of the fourth embodiment will be described.

[0225] First, as illustrated in Figures 68 a and b, the chip components 244 are mounted on the upper surface of the organic substrate 220 through various processes such as solder printing, component mounting, reflow soldering, and substrate cleaning.

[0226] Next, as illustrated in Figures 69 a and b, a composite substrate containing a predetermined number of organic substrates 220 is mounted and bonded to the support 300.

[0227] Next, as illustrated in Figures 70 a and b, the sensor chip 230 and the companion chip 235 are placed in the openings of the organic substrate 220 and bonded to the support 300.

[0228] Next, as illustrated in Figures 71 a and b, the sensor chip 230 and the companion chip 235 are electrically connected by wires 241.

[0229] Next, as illustrated in Figures a and b of Figure 72, resin 251 is applied along the outer circumference of the sensor chip 230, and the wire 241 is sealed.

[0230] Next, as illustrated in Figures 73 a and b, the transparent member 210 is mounted and bonded to the resin 251. Then, temporary curing is performed by irradiation with ultraviolet light or the like, and the resin 251 is temporarily hardened. From the viewpoint of maintaining the parallelism of the transparent member 210, it is preferable to make the chip thickness of the sensor chip 230 and the substrate thickness of the organic substrate 220 the same.

[0231] Next, as illustrated in Figures 74 a and b, resin 251 is applied to the companion tip 235. Then, curing is performed by heat treatment or the like, and the resin 251 is hardened.

[0232] Then, the support 300 is removed, a predetermined number of ball terminals 242 (not shown) are formed, and the assembled substrate is separated into individual pieces.

[0233] Furthermore, the sixth modification of the fourth embodiment can be applied to each of the variations of the first embodiment, the second and third embodiments, each of the variations of the second and third embodiments, and the first to fifth variations of the fourth embodiment.

[0234] Thus, according to the sixth modification of the fourth embodiment of this technology, the performance of the semiconductor package 200 can be improved because the chip components 244 are mounted on the organic substrate 220.

[0235] <5. Fifth Embodiment> In the first embodiment described above, the transparent member 210 was mounted on the resin 251 surrounding the sensor chip 230, but misalignment (so-called tilting) of the transparent member 210 may occur during mounting. The manufacturing method of the semiconductor package 200 in this fifth embodiment differs from the first embodiment in that a protrusion is formed along the outer circumference of the transparent member 210 before mounting.

[0236] The method for manufacturing the semiconductor package 200 in the fifth embodiment will be described with reference to Figures 75 to 77.

[0237] As illustrated in Figures 75 a and b, projections 254 protruding from the surface along the outer circumference of the transparent member 210 are formed, for example, from the same resin as the adhesive and sealing resin 251. When the height of the projection 254 is h and its width is w, the aspect ratio h / w is preferably about 0.5. Note that the resin used to form the projection 254 may be a different resin from the resin 251.

[0238] In the figure, 'a' shows a cross-sectional view of the transparent member 210, and 'b' shows a plan view of the transparent member 210.

[0239] A projection 254 is formed on one of the two surfaces of the transparent member 210, on the surface facing the sensor chip 230 (not shown). The projection 254 is formed in a location on the chip layout of the sensor chip 230 where there is no wire 241 (not shown) so as not to interfere with the wire 241. The procedure for forming the projection 254 is performed before mounting the transparent member 210.

[0240] Furthermore, as illustrated in Figures 76 a and b, the aggregate substrate is mounted and bonded to the support 300, and the sensor chips 230 are placed in the openings of each organic substrate 220. Wire bonding is then performed, and resin 251 is applied along the outer circumference of the sensor chip 230.

[0241] Then, as illustrated in Figures 77 a and b, a transparent member 210 with protrusions along its outer circumference is mounted and bonded to the resin 251. These protrusions prevent the transparent member 210 from shifting (moving) in the X-axis and Y-axis directions during mounting.

[0242] Then, the resin 251 is cured by curing or the like, and the support 300 is removed. A predetermined number of ball terminals 242 (not shown) are formed by reflow or the like, and the assembled substrate is divided into individual pieces by dicing.

[0243] Furthermore, the fifth embodiment can be applied to each of the variations of the first embodiment, the second, third, and fourth embodiments, and each of the variations of the second to fourth embodiments.

[0244] Thus, according to the fifth embodiment of this technology, since the projection 254 is formed along the outer circumference of the transparent member 210, it is possible to prevent misalignment of the transparent member 210 when it is mounted.

[0245] <6. Sixth Embodiment> In the first embodiment described above, the size of the sensor chip 230 was made smaller than the opening 221 and placed inside the opening 221. However, this configuration requires bonding and peeling processes for the support 300 during manufacturing. In addition, the stability during wire bonding is reduced. The semiconductor package 200 in this sixth embodiment differs from the first embodiment in that the size of the sensor chip 230 is made larger than the opening 221 and the sensor chip 230 is die-bonded around the opening 221.

[0246] Figure 78 shows a cross-sectional view and a bottom view of a semiconductor package 200 in a sixth embodiment of the present technology. In the figure, a shows a cross-sectional view of the semiconductor package 200, and b shows a bottom view of the semiconductor package 200.

[0247] As illustrated in Figure a, in the sixth embodiment, the size of the sensor chip 230 is larger than the size of the opening 221. The sensor chip 230 is die-bonded to the area around the opening 221 on the upper surface of the flat organic substrate 220 using die-bonding material 245. Also, as illustrated in Figure b, in the sixth embodiment as well, the lower surface of the sensor chip 230 is exposed, which improves heat dissipation performance.

[0248] Next, with reference to Figures 79 to 84, a method for manufacturing the semiconductor package 200 in the sixth embodiment will be described.

[0249] As illustrated in Figures 79 a and b, the die bond material 245 is applied to the area around the opening of the organic substrate 220.

[0250] Figures 80 a, b, and c are plan views showing examples of locations where the die bond material 245 is applied in the sixth embodiment of this technology. The dotted line indicates the outer circumference of the sensor chip 230 (not shown).

[0251] When sealing with resin 251 (not shown), a void may form between the resin 251 and the die bond material 245. If a void is present, voids may form within the resin 251 or die bond material 245, and cracks caused by these voids may occur during heat treatment such as reliability testing. Therefore, as illustrated in a, b, and c in the figure, it is preferable to apply the die bond material 245 to all but a portion of the frame-shaped area along the outer circumference of the opening 221.

[0252] Next, as illustrated in Figures 81 a and b, the sensor chip 230 is die-bonded to the area of ​​the organic substrate 220 coated with die-bonding material 245. This improves the stability during wire bonding. Then, the die-bonding material 245 is cured by curing or the like.

[0253] Next, as illustrated in Figures 82 a and b, each of the sensor chips 230 is electrically connected to the organic substrate 220 by wires 241.

[0254] Next, as illustrated in Figures 83 a and b, resin 251 is applied along the outer circumference of the sensor chip 230, and the wire 241 is sealed.

[0255] Next, as illustrated in Figures 84 a and b, the transparent member 210 is mounted and bonded to the resin 251. Then, the resin 251 is cured by curing or the like.

[0256] Then, a predetermined number of ball terminals 242 (not shown) are formed by reflow or the like, and the assembled substrate is divided into individual pieces by dicing.

[0257] As described above, by die-bonding the sensor chip 230 around the opening 221, the processes of bonding and peeling the support 300 are eliminated, thereby simplifying the manufacturing process.

[0258] Furthermore, as illustrated in Figure 85 a, the sixth embodiment can be applied to the second embodiment, which includes a frame 270, and to each of its modified forms.

[0259] Furthermore, as illustrated in figure b, the sixth embodiment can be applied to the fourth and fifth modifications of the fourth embodiment, in which the companion chip 235 is mounted on the organic substrate 220.

[0260] Furthermore, the sixth embodiment can be applied to the fifth embodiment.

[0261] Thus, according to the sixth embodiment of this technology, since the sensor chip 230 is die-bonded around the opening 221, the manufacturing process can be simplified and the stability during wire bonding can be improved.

[0262] [Modification] In the sixth embodiment described above, a flat organic substrate 220 was used, but in this configuration, the wire length may be longer than in the first embodiment. The semiconductor package 200 in this modification of the sixth embodiment differs from the sixth embodiment in that it uses an organic substrate 220 with steps.

[0263] Figure 86 is a cross-sectional view showing an example configuration of a semiconductor package 200 in a modified version of the sixth embodiment of this technology. In this modified version of the sixth embodiment, a step 226 is formed around the opening 221 of the organic substrate 220. The inside of the step 226 is lower than the outside of the step 226, and a cavity is formed in the inner region. The sensor chip 230 is placed in this cavity. As a result, the wire length can be shortened and the electrical characteristics can be improved compared to the sixth embodiment. Note that a ceramic substrate with a cavity structure can be used instead of the organic substrate 220.

[0264] Furthermore, the modified form of the sixth embodiment can be applied to the second embodiment, each of its modified forms, the fourth and fifth modified forms of the fourth embodiment, and the fifth embodiment.

[0265] Thus, according to the modified sixth embodiment of this technology, since an organic substrate 220 with a stepped cavity structure is used, the wire length can be shortened and the electrical characteristics can be improved.

[0266] <7. Examples of Application to Mobile Devices> The technology disclosed herein (the technology) can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0267] Figure 87 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0268] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 87, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0269] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0270] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0271] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0272] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0273] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0274] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0275] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0276] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0277] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 87, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0278] Figure 88 shows an example of the installation position of the imaging unit 12031.

[0279] In Figure 88, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0280] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0281] Figure 88 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0282] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0283] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0284] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0285] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0286] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to the imaging unit 12031 of the configuration described above. Specifically, the semiconductor package 200 in Figure 1 can be applied to the imaging unit 12031. By applying the technology described herein to the imaging unit 12031, the warping of the sensor chip can be suppressed, making it possible to obtain a clearer image, and thus reducing driver fatigue.

[0287] The embodiments described above are merely examples of how to realize this technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of this technology that bear the same name. However, this technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology.

[0288] The effects described herein are merely illustrative and not limited to those described herein, and other effects may also occur.

[0289] Furthermore, this technology can also take the following configurations: (1) A semiconductor package comprising a substrate having a first opening formed thereon, a first semiconductor chip disposed in the first opening and connected to one of the two surfaces of the substrate by a wire, a transparent member, and a first resin for sealing the wire and bonding the transparent member. (2) The semiconductor package according to (1), further comprising external terminals arranged on the substrate. (3) The semiconductor package according to (2), further comprising a flexible cable connected to the external terminals. (4) The semiconductor package according to (2) or (3), wherein the external terminals are arranged on one of the two surfaces of the substrate. (5) The semiconductor package according to (2) or (3), wherein the external terminals are arranged on the other of the two surfaces of the substrate. (6) The semiconductor package according to any one of (1) to (5), further comprising a second resin for bonding the side surface of the first semiconductor chip to the substrate, wherein the elastic modulus of the second resin is higher than that of the first resin. (7) The semiconductor package according to any one of (1) to (6), wherein the substrate comprises a recess formed around the first resin. (8) The semiconductor package according to any one of (1) to (8), further comprising a frame to which one of the two surfaces is bonded to the substrate, and the transparent member is supported on the other surface of the frame. (9) The semiconductor package according to (8), wherein the substrate comprises a predetermined number of fitting holes, and the frame comprises projections that fit into each of the fitting holes. (10) The semiconductor package according to (8) or (9), wherein the frame comprises a groove formed along the inner wall of the frame. (11) The semiconductor package according to any one of (8) to (10), wherein the substrate comprises a dam formed between the inner wall of the frame and a contact. (12) The semiconductor package according to any one of (8) to (11), wherein the frame comprises a predetermined number of first notches formed on one of the two surfaces of the frame. (13) The semiconductor package according to any one of (8) to (12), wherein the frame comprises a predetermined number of second notches formed on the other side of the frame.(14) The semiconductor package according to claim (1), wherein the substrate has a step formed around the first opening, and the transparent member is supported in the region of the substrate that is outside the step on one of the surfaces of the substrate. (15) The semiconductor package according to claim (14), wherein the first resin bonds the transparent member to the region of the substrate that is outside the step on one of the surfaces of the substrate. (16) The semiconductor package according to claim 1, further comprising a second semiconductor chip connected by a wire to one of the two surfaces of the substrate. (17) The semiconductor package according to claim (16), wherein the first and second semiconductor chips are disposed in the first opening. (18) The semiconductor package according to claim (16), wherein a second opening is further formed in the substrate, and the second semiconductor chip is disposed in the second opening. (19) The semiconductor package according to any one of (16) to (18), wherein the first semiconductor chip comprises a Time of Flight (ToF) sensor, and the second semiconductor chip comprises a light-emitting element. (20) The semiconductor package according to (16), wherein the second semiconductor chip is die-bonded to one of the two surfaces of the substrate, and the first and second semiconductor chips are directly connected by wires. (21) The semiconductor package according to (16), wherein the second semiconductor chip is bonded to one of the two surfaces of the substrate, and the first and second semiconductor chips are connected via the substrate. (22) The semiconductor package according to any one of (16) to (21), further comprising chip components mounted on the substrate. (23) The semiconductor package according to (1), wherein the size of the first semiconductor chip is larger than the size of the first opening, and the first semiconductor chip is die-bonded around the first opening on one of the surfaces. (24) The semiconductor package according to (23), wherein the substrate is a flat substrate. (25) The semiconductor package according to (23), wherein the substrate has a step formed around the first opening.(26) A semiconductor package comprising: a substrate having a first opening and a step formed around the first opening; a semiconductor chip disposed in the first opening and connected to one of the two surfaces of the substrate by a wire; a transparent member; a first resin for sealing the wire; and a second resin for bonding the transparent member to the region of the substrate on the one surface that is outside the step. (27) A method for manufacturing a semiconductor package comprising: a step of placing a first semiconductor chip in a first opening formed in the substrate; a connection step of connecting the first semiconductor chip and the substrate by a wire; a sealing step of sealing the wire with a first resin; and an adhesion step of bonding the transparent member with the first resin. (28) The method for manufacturing a semiconductor package according to (27), further comprising a step of forming a projection protruding from the surface of the transparent member along the outer circumference of the transparent member before the adhesion step.

[0290] 200 Semiconductor package 210 Transparent component 220 Organic substrate 221, 221-1, 221-2 Opening 222 Contact 223 Recess 224 Mating hole 225 Dam 226 Step 230, 231 Sensor chip 235 Companion chip 236 Laser chip 241 Wire 242 Ball terminal 243 Adhesive resin 244 Chip component 245 Die bond material 251, 252, 253 Resin 254, 271 Protrusion 261 Flexible cable 262 Connector 270 Frame 272 Groove 273, 274 Notch 300 Support 12031 Imaging unit

Claims

1. A semiconductor package comprising: a substrate having a first opening formed therein; a first semiconductor chip disposed in the first opening and connected to one of the two surfaces of the substrate by a wire; a transparent member; and a first resin for sealing the wire and bonding the transparent member.

2. The semiconductor package according to claim 1, further comprising external terminals arranged on the substrate.

3. The semiconductor package according to claim 2, further comprising a flexible cable connected to the external terminal.

4. The semiconductor package according to claim 2, wherein the external terminals are arranged on one of the two surfaces of the substrate.

5. The semiconductor package according to claim 2, wherein the external terminals are arranged on the other side of the substrate.

6. The semiconductor package according to claim 1, further comprising a second resin for bonding the side surface of the first semiconductor chip to the substrate, wherein the elastic modulus of the second resin is higher than that of the first resin.

7. The semiconductor package according to claim 1, wherein the substrate comprises a recess formed around the first resin.

8. The semiconductor package according to claim 1, further comprising a frame on which one of its two surfaces is bonded to the substrate, wherein the transparent member is supported on the other surface of the frame.

9. The semiconductor package according to claim 8, wherein the substrate is provided with a predetermined number of mating holes, and the frame is provided with a projection that mates with each of the mating holes.

10. The semiconductor package according to claim 8, wherein the frame comprises grooves formed along the inner wall of the frame.

11. The semiconductor package according to claim 8, wherein the substrate comprises a dam formed between the inner wall of the frame and the contact.

12. The semiconductor package according to claim 8, wherein the frame comprises a predetermined number of first notches formed on one of the two surfaces of the frame.

13. The semiconductor package according to claim 8, wherein the frame comprises a predetermined number of second notches formed on the other side of the frame.

14. The semiconductor package according to claim 1, wherein the substrate has a step formed around the first opening, and the transparent member is supported in the region of one of the surfaces of the substrate that is outside the step.

15. The semiconductor package according to claim 14, wherein the first resin adheres the transparent member to the region of the substrate on the outer side of the step on one of the surfaces of the substrate.

16. The semiconductor package according to claim 1, further comprising a second semiconductor chip connected by a wire to one of the two surfaces of the substrate.

17. The semiconductor package according to claim 16, wherein the first and second semiconductor chips are arranged in the first aperture.

18. The semiconductor package according to claim 16, wherein a second opening is further formed in the substrate, and the second semiconductor chip is disposed in the second opening.

19. The semiconductor package according to claim 16, wherein the first semiconductor chip comprises a Time of Flight (ToF) sensor, and the second semiconductor chip comprises a light-emitting element.

20. The semiconductor package according to claim 16, wherein the second semiconductor chip is die-bonded to one of the two surfaces of the substrate, and the first and second semiconductor chips are directly connected by wires.

21. The semiconductor package according to claim 16, wherein the second semiconductor chip is bonded to one of the two surfaces of the substrate, and the first and second semiconductor chips are connected via the substrate.

22. The semiconductor package according to claim 16, further comprising chip components mounted on the substrate.

23. The semiconductor package according to claim 1, wherein the size of the first semiconductor chip is larger than the size of the first aperture, and the first semiconductor chip is die-bonded around the first aperture on one of the surfaces.

24. The semiconductor package according to claim 23, wherein the substrate is a flat substrate.

25. The semiconductor package according to claim 23, wherein the substrate comprises a step formed around the first opening.

26. A semiconductor package comprising: a substrate having a first opening and a step formed around the first opening; a semiconductor chip disposed in the first opening and connected to one of the two surfaces of the substrate by a wire; a transparent member; a first resin for sealing the wire; and a second resin for bonding the transparent member to the region of the substrate on the outer side of the step.

27. A method for manufacturing a semiconductor package, comprising: a step of placing a first semiconductor chip in a first opening formed in a substrate; a connection step of connecting the first semiconductor chip and the substrate with a wire; a sealing step of sealing the wire with a first resin; and an adhesion step of bonding a transparent member with the first resin.

28. The method for manufacturing a semiconductor package according to claim 27, further comprising a step of forming protrusions that protrude from the surface of the transparent member along the outer circumference of the transparent member, prior to the bonding step.

Images