Display device

Abstract

A display device according to the present disclosure comprises: a plurality of pixels; and a signal processing circuit that writes a video signal to each of the plurality of pixels using a signal of a first scheme, and writes correction signals for correcting deviations in characteristics of the respective pixels by using a signal of a second scheme different from the first scheme.

Description

Display device

[0001] The present disclosure relates to a display device.

[0002] Technologies for correcting variations in emission luminance of display elements have been proposed (see Patent Document 1).

[0003] Japanese Unexamined Patent Publication No. 11-344949

[0004] The technology described in Patent Document 1 is difficult to apply to active matrix display devices. In active matrix display devices, there is a demand for developing technologies capable of correcting variations in pixel characteristics while suppressing circuit scale and power consumption.

[0005] Therefore, it is desirable to provide a display device capable of improving display quality while suppressing circuit scale and power consumption.

[0006] A display device according to an embodiment of the present disclosure includes a plurality of pixels, and a signal processing circuit that, for each of the plurality of pixels, writes a video signal using a signal of a first scheme, and writes a correction signal for correcting variations in characteristics of each pixel using a signal of a second scheme different from the first scheme.

[0007] In the display device according to an embodiment of the present disclosure, for each of the plurality of pixels, a video signal is written using a signal of the first scheme, and a correction signal for correcting variations in characteristics of each pixel is written using a signal of the second scheme different from the first scheme.

[0008] Figure 1 is an explanatory diagram showing an overview of uniformity correction by a display device according to a comparative example. Figure 2 is an explanatory diagram showing an overview of a first method of uniformity correction by a display device according to a comparative example. Figure 3 is an explanatory diagram showing an overview of a second method of uniformity correction by a display device according to a comparative example. Figure 4 is an explanatory diagram showing the problems of the second method of uniformity correction by a display device according to a comparative example. Figure 5 is a block diagram showing an overview of the signal processing circuit in a display device according to comparative example 1. Figure 6 is a block diagram showing an overview of the signal processing circuit in a display device according to comparative example 2. Figure 7 is a block diagram showing an overview of the signal processing circuit in a display device according to one embodiment of the present disclosure. Figure 8 is an explanatory diagram showing an overview of the data capacity and correction dimension required for uniformity correction by a display device according to a comparative example. Figure 9 is an explanatory diagram showing an overview of the data capacity and correction dimension required for uniformity correction by a display device according to one embodiment. Figure 10 is an explanatory diagram showing an example of correction values ​​obtained for uniformity correction during the manufacturing of the display device according to a comparative example and during the manufacturing of an optical system module including the display device according to a comparative example. Figure 11 is an explanatory diagram showing an example of correction values ​​obtained for uniformity correction during the manufacturing of the display device 1 according to one embodiment and during the manufacturing of the optical system module including the display device 1 according to one embodiment. Figure 12 is an explanatory diagram comparing the gradation state after uniformity correction by the uniformity correction method of the display device according to one embodiment with the gradation state after uniformity correction by the uniformity correction method of the display device according to a comparative example. Figure 13 is a circuit diagram showing a first configuration example of the pixel circuit in the display device according to one embodiment. Figure 14 is a timing chart showing an example of operation of the pixel circuit according to the first configuration example. Figure 15 is a timing chart showing an example of operation of the pixel circuit according to the first configuration example. Figure 16 is a circuit diagram showing a second configuration example of the pixel circuit in the display device according to one embodiment. Figure 17 is a timing chart showing an example of operation of the pixel circuit according to the second configuration example. Figure 18 is a timing chart showing an example of operation of the pixel circuit according to the second configuration example. Figure 19 is a circuit diagram showing a third configuration example of the pixel circuit in the display device according to one embodiment. Figure 20 is a timing chart showing an example of operation of the pixel circuit according to the third configuration example. Figure 21 is a timing chart showing an example of the operation of a pixel circuit according to the third configuration example.Figure 22 is a circuit diagram showing a fourth configuration example of a pixel circuit in a display device according to one embodiment. Figure 23 is a timing chart showing an example of operation of the pixel circuit according to the fourth configuration example. Figure 24 is a timing chart showing an example of operation of the pixel circuit according to the fourth configuration example. Figure 25 is a circuit diagram showing a fifth configuration example of a pixel circuit in a display device according to one embodiment. Figure 26 is a timing chart showing an example of operation of the pixel circuit according to the fifth configuration example. Figure 27 is a timing chart showing an example of operation of the pixel circuit according to the fifth configuration example. Figure 28 is a circuit diagram showing a first configuration example of a pixel peripheral circuit in a display device according to one embodiment. Figure 29 is a circuit diagram showing a second configuration example of a pixel peripheral circuit in a display device according to one embodiment. Figure 30 is a circuit diagram showing an example of an amplifier circuit in a display device according to one embodiment. Figure 31 is a timing chart showing an example of PWM driving by a PWM conversion circuit in a display device according to one embodiment. Figure 32 is a schematic configuration diagram showing a first example of storage of a correction value included in the uniformity correction signal Sc in a display device according to one embodiment. Figure 33 is a schematic diagram illustrating an example of the relationship between the pixel value variation (luminance variation) component and the correction amount used to correct the pixel value variation. Figure 34 is a schematic configuration diagram illustrating a second example of storing the correction value included in the uniformity correction signal Sc in a display device according to one embodiment. Figure 35 is a schematic configuration diagram illustrating a third example of storing the correction value included in the uniformity correction signal Sc in a display device according to one embodiment. Figure 36 is an explanatory diagram showing an overview of the third storage example. Figure 37 is a block diagram illustrating an example of the overall configuration of the display device 1 according to one embodiment.

[0009] The embodiments of this disclosure will be described in detail below with reference to the drawings. The description will be in the following order: 0. Comparative Examples 1. One Embodiment 1.1 Overview 1.2 Example of Pixel Circuit 1.3 Example of Pixel Peripheral Circuit 1.4 Example of Correction Value Storage 1.5 Example of Overall Configuration of Display Device 1.6 Effects 2. Other Embodiments

[0010] <0. Comparative Example> Figure 1 is an explanatory diagram showing an overview of uniformity correction by a display device according to the comparative example. Figure 1(A) shows the brightness variation of pixels, Figure 1(B) shows the video signal Sv, and Figure 1(C) shows an example of the brightness spectrum.

[0011] In general, display devices exhibit brightness unevenness due to variations in the characteristics of light-emitting elements, as shown on the left side of Figure 1. In contrast, as shown on the right side of Figure 1, a highly uniform image can be achieved by superimposing a uniformity correction signal Sc onto the video signal Sv and writing it to the pixels. The uniformity correction signal Sc, for example, leaves dark pixels uncorrected and reduces the brightness of bright pixels.

[0012] Figure 2 is an explanatory diagram illustrating the outline of the first method of uniformity correction using a display device according to the comparative example. Figure 3 is an explanatory diagram illustrating the outline of the second method of uniformity correction using a display device according to the comparative example. In Figures 2 and 3, the vertical axis represents the signal level (luminance level), and the horizontal axis represents time.

[0013] As mentioned above, the uniformity correction signal Sc reduces the brightness of bright pixels, for example. Therefore, when the uniformity correction signal Sc is simply superimposed on the video signal Sv as shown in Figure 2, the maximum brightness of the corrected video signal Sv is limited to the minimum brightness value of the uniformity correction signal Sc. In other words, when the uniformity correction signal Sc is simply superimposed on the video signal Sv, the grayscale range of the corrected video signal Sv is reduced. In addition, complex processing is required because the display grayscale differs for each pixel, which increases power consumption.

[0014] In contrast, as a second method of uniformity correction, as shown in Figure 3, the gradation bits of the video signal Sv are expanded by bit (for example, expanding an 8-bit video signal Sv to 9 bits), and then the uniformity correction signal Sc is superimposed, thereby suppressing the decrease in maximum brightness and the reduction in the gradation range. However, in this second method, the circuit size increases and power consumption increases due to the effect of bit expansion. Also, the difference in display gradation between pixels is not eliminated, and the signal range will differ between bright pixels and dark pixels. For this reason, gradation correction according to the gradation difference is required for all pixels. Furthermore, in order to reduce the correction error of gamma correction, further gradation expansion (for example, expanding from 9 bits to 12 bits) is required, which further increases the circuit size and power consumption.

[0015] Figure 4 is an explanatory diagram illustrating the problems of the second method of uniformity correction using a display device according to the comparative example.

[0016] The second method of uniformity correction described above requires gamma correction for each pixel, necessitating a complex calculation circuit (gamma conversion circuit) and a large memory to store different parameters for each pixel. This increases the circuit area and power consumption. Furthermore, it significantly increases the inspection time during manufacturing and drives up production costs.

[0017] Figure 5 is a block diagram showing an overview of the signal processing circuit in the display device 100A according to Comparative Example 1.

[0018] The display device 100A according to Comparative Example 1 includes a bit expansion circuit 21, an adder circuit 22, a grayscale correction circuit 23, and a PWM conversion circuit 130.

[0019] In the display device 100A according to Comparative Example 1, a uniformity correction signal Sc is superimposed on the bit-expanded video signal Sv by the bit expansion circuit 21 using the adder circuit 22. After that, the corrected video signal Sv is grade-corrected by the gradation correction circuit 23, and then the PWM-converted video signal Sv is written to the pixels P by the PWM conversion circuit 130.

[0020] Figure 6 is a block diagram showing an overview of the signal processing circuit in the display device 100B according to Comparative Example 2.

[0021] The display device 100B according to Comparative Example 2 includes a bit expansion circuit 21, an adder circuit 22, a grayscale correction circuit 23, and a PAM conversion circuit 140.

[0022] In the display device 100B according to Comparative Example 2, a uniformity correction signal Sc is superimposed on the bit-expanded video signal Sv by the bit expansion circuit 21 using the adder circuit 22. After that, the corrected video signal Sv is grade-corrected by the gradation correction circuit 23, and then the PAM-converted video signal Sv is written to the pixels P by the PAM conversion circuit 140.

[0023] Hereinafter, the display device 100A according to Comparative Example 1 and the display device 100B according to Comparative Example 2 will be collectively referred to as "display device 100 according to the comparative example."

[0024] As described above, when superimposing a uniformity correction signal Sc according to brightness unevenness in order to display a uniform image, it is common practice to extend the bit depth or voltage range of the video signal Sv in order to avoid compromising gradation. However, this process has the disadvantage of increasing the circuit size and power consumption required, which has been a hindrance, especially in cases where low power consumption is required.

[0025] Therefore, there is a need for the development of technology to realize an active-matrix display device that can display uniform images without compromising gradation, power consumption, and manufacturing costs.

[0026] <1. One Embodiment> [1.1 Overview] Figure 7 is a block diagram showing an overview of the signal processing circuit in a display device 1 according to one embodiment of the present disclosure.

[0027] One embodiment of the display device 1 is an active-matrix type display device having a plurality of pixels P, and includes a signal processing circuit consisting of a PWM conversion circuit 30 (first conversion circuit) and a PAM conversion circuit 40 (second conversion circuit).

[0028] The PWM conversion circuit 30 is a circuit that writes a video signal Sv to each of the multiple pixels P using a signal of the first type. Specifically, the PWM conversion circuit 30 is a circuit that converts the video signal Sv into a PWM signal (a signal of the first type) having a temporal weight (bit-plane) corresponding to the grayscale bit. The PAM conversion circuit 40 is a circuit that writes a uniformity correction signal Sc, which is a correction signal that corrects the variation in the characteristics of each pixel P, using a signal of the second type, which is different from the first type. Specifically, the PAM conversion circuit 40 has a DAC (Digital to Analog Converter) circuit that converts into a PAM signal (a signal of the second type) having a voltage amplitude corresponding to the uniformity correction signal Sc.

[0029] In one embodiment of the display device 1, the video signal Sv converted into a PWM signal by the PWM conversion circuit 30 is written to the pixels P. In addition, the uniformity correction signal Sc converted into a PAM signal by the PAM conversion circuit 40 is written to the pixels P. The video signal Sv converted into a PWM signal and the uniformity correction signal Sc converted into a PAM signal may be written to the pixels P simultaneously in time, or they may be written to the pixels P separately in time. In one embodiment of the display device 1, the PAM signal may be output to each pixel P when the signal value of the PWM signal is either High or Low.

[0030] Figure 8 is an explanatory diagram showing an overview of the data capacity and correction dimensions required for uniformity correction by the display device 100 according to the comparative example. Figure 8 shows an overview of the data capacity and correction dimensions for the number of horizontal pixels × the number of vertical pixels.

[0031] When the number of correction parameters increases by one dimension, the complexity increases by an amount equivalent to multiplying the amount of information required to represent that dimension, thus increasing not only the memory but also the size of the arithmetic circuit and the measurement time. In the uniformity correction method using the display device 100 in the comparative example, the correction parameters include uniformity correction value, gamma correction value, brightness variation, temperature variation, and current density correction (PAM), and the number of dimensions of the correction parameters is, for example, four or five dimensions.

[0032] Figure 9 is an explanatory diagram showing an overview of the data capacity and correction dimensions required for uniformity correction by a display device 1 according to one embodiment. Figure 9 shows an overview of the data capacity and correction dimensions for the number of horizontal pixels × the number of vertical pixels.

[0033] In the uniformity correction method using the display device 1 according to one embodiment, the number of dimensions of the correction parameters can be limited to, for example, three dimensions. In the uniformity correction method using the display device 1 according to one embodiment, the gradation is produced using the PWM method without superimposing the uniformity correction signal Sc on the gradation, so gamma correction can be performed on the entire surface at once (there is no need to perform gamma correction for each pixel P), resulting in a small circuit area and low power consumption.

[0034] Figure 10 is an explanatory diagram showing an example of correction values ​​obtained for uniformity correction during the manufacturing of the comparative example display device 100 and the manufacturing of the optical system module including the comparative example display device 100. The optical system module comprises the comparative example display device 100, a lens 203 for guiding the display image of the display device 100, and a diffraction light guide plate 204.

[0035] During the manufacturing of the comparative example display device 100, the display image of the display device 100 is inspected by an image inspection device 201. Based on the inspection results by the image inspection device 201, a uniformity correction value D based on uniformity caused by the display device is determined. Furthermore, during the manufacturing of the optical system module including the display device 100 according to the comparative example, the display image of the display device 100 guided by the diffraction light guide plate 204 is inspected by an image inspection device 202. Based on the inspection results by the image inspection device 202, a uniformity correction value S is determined. The uniformity correction value S is a uniformity correction value based on uniformity caused by the display device and uniformity caused by the set optical system. Therefore, the uniformity correction value D during the manufacturing of the display device 100 and the uniformity correction value S during the manufacturing of the optical system module are different, making it difficult (or meaningless) to adjust the display device 100, such as gamma correction, during the manufacturing of the display device 100. Furthermore, because the gamma value shifts for each pixel P, it is necessary to acquire images for each gradation and maximum brightness, and perform complex gamma correction using the gamma correction value for each pixel P. This takes time to acquire the uniformity correction value S, resulting in higher manufacturing costs.

[0036] Figure 11 is an explanatory diagram showing an example of correction values ​​obtained for uniformity correction during the manufacturing of the display device 1 according to one embodiment and during the manufacturing of the optical system module including the display device 1 according to one embodiment. The optical system module comprises the display device 1 according to one embodiment, a lens 203 for guiding the display image of the display device 1, and a diffraction light guide plate 204.

[0037] During the manufacturing of the display device 1 according to one embodiment, the display image of the display device 1 is inspected by an image inspection device 201. Based on the inspection results from the image inspection device 201, a global (common to all pixels P) gamma correction value is determined. Furthermore, during the manufacturing of the optical system module including the display device 1 according to one embodiment, the display image of the display device 1 guided by the diffraction light guide plate 204 is inspected by an image inspection device 202. Based on the inspection results from the image inspection device 202, a uniformity correction value S is determined. The uniformity correction value S is a uniformity correction value based on uniformity caused by the display device and uniformity caused by the set optical system. In the display device 1 according to one embodiment, the setting values ​​of the display device 1, such as gamma correction, can be determined during the manufacturing of the display device 1, and only the uniformity correction value S needs to be determined during the manufacturing of the optical system module, thus improving manufacturing efficiency and reducing costs.

[0038] Figure 12 is an explanatory diagram comparing the gradation state after unevenness correction by the unevenness correction method of the display device 1 according to one embodiment (Figure 12(A)) and the gradation state after unevenness correction by the unevenness correction method of the display device 100 according to the comparative example (Figures 12(B) and (C)). Figure 12(B) shows the gradation state in Comparative Example 1, where an unevenness correction signal Sc is superimposed on a bit-expanded video signal Sv, and then the signal that has undergone further gradation correction is written to each pixel P using a PWM drive method. Figure 12(C) shows the gradation state in Comparative Example 2, where an unevenness correction signal Sc is superimposed on a bit-expanded video signal Sv, and then the signal that has undergone further gradation correction is written to each pixel P using a PAM drive method.

[0039] In the display device 1 according to one embodiment, a video signal Sv is written to each pixel P by the PWM method, and a unevenness correction signal Sc is written by the PAM method (as an analog value). Therefore, as shown in FIG. 12A, the gradation is the same for each pixel P (the gradation is the same between a bright pixel P and a dark pixel P).

[0040] In contrast, in the unevenness correction method using the display device 100 according to a comparative example, after superimposing the unevenness correction signal Sc on the video signal Sv, a signal subjected to further gradation correction is written to each pixel P by the PWM driving method or the PAM driving method. Therefore, as shown in FIGS. 12B and 12C, the gradation differs for each pixel P (the gradation differs between a bright pixel P and a dark pixel P).

[0041] [1.2 Example of Pixel Circuit] The display device 1 according to one embodiment includes a pixel circuit as a signal processing circuit. The pixel P includes a light-emitting element 11. The pixel circuit is a circuit that supplies a pixel voltage Vpix to the light-emitting element 11.

[0042] Next, a specific example of the pixel circuit in the display device 1 according to one embodiment will be described. In the pixel circuit of the display device 1 according to one embodiment, there is no need to provide a correction circuit or the like in the pixel, so the number of elements is small and miniaturization is possible.

[0043] (Pixel Circuit Example 1) FIG. 13 is a circuit diagram showing a first configuration example of the pixel circuit in the display device 1 according to one embodiment. FIG. 14 is a timing chart showing an operation example of the pixel circuit according to the first configuration example. FIG. 15 is a timing chart showing another operation example of the pixel circuit according to the first configuration example. FIGS. 13 to 15 show a configuration example and an operation example of the pixel circuit in a case where a PWM signal Sig_PWM corresponding to the video signal Sv and a PAM signal Sig_PAM corresponding to the unevenness correction signal Sc are written to the pixel P at the same time.

[0044] The pixel circuit according to the first configuration example includes a transistor Tn1, a transistor Tn2, and a capacitor C1.

[0045] One end of the transistor Tn1 is connected to the supply lines of the PWM signal Sig_PWM and the PAM signal Sig_PAM, and the other end is connected to the gate of the transistor Tn2 and one end of the capacitor C1. The gate of the transistor Tn1 is connected to the supply lines of the Set signal and the Reset signal. One end of the transistor Tn2 is connected to one end of the light-emitting element 11, and the other end is connected to the other end of the capacitor C1.

[0046] The light-emitting element 11 is formed of a self-luminous element, for example, a micro LED (Light Emitting Diode) or an OLED (Organic Light-Emitting Diode). The transistor Tn1 is a selection transistor. The transistor Tn2 is a driving transistor. The capacitor C1 is a holding capacitor.

[0047] The timing chart of FIG. 14 shows the Set signal, the Reset signal, the signal voltage of a signal on which the PWM signal Sig_PWM and the PAM signal Sig_PAM are superimposed, and the Vpix signal (pixel voltage).

[0048] In the pixel circuit according to the first configuration example, as shown in the timing charts of FIG. 14 and FIG. 15, all pixels P are written to 0 before the completion of writing in one frame period. In the pixel circuit according to the first configuration example, the bit plane of the minimum bit is restricted by the scan time, and as shown in the timing chart of FIG. 15, one reset scan is required after writing the final bit.

[0049] (Pixel Circuit Example 2) FIG. 16 is a circuit diagram showing a second configuration example of a pixel circuit in the display device 1 according to an embodiment. FIG. 17 is a timing chart showing an operation example of the pixel circuit according to the second configuration example. FIG. 18 is a timing chart showing an operation example of the pixel circuit according to the second configuration example. FIGS. 16 to 18 show a configuration example and an operation example of a pixel circuit in a case where the PWM signal Sig_PWM corresponding to the video signal Sv and the PAM signal Sig_PAM corresponding to the unevenness correction signal Sc are simultaneously written to the pixel P.

[0050] The pixel circuit according to the second configuration example includes a transistor Tn1, a transistor Tn2, a transistor Tn3, a capacitor C1, and a light-emitting element 11.

[0051] The gate of transistor Tn1 is connected to the supply line for the Set signal. Transistor Tn3 is a reset transistor. The gate of transistor Tn3 is connected to the supply line for the Reset signal.

[0052] The timing chart in Figure 17 shows the signal voltages of the Set signal, the Reset signal, the signal voltage of the signal in which the PWM signal Sig_PWM and the PAM signal Sig_PAM are superimposed, and the Vpix signal (pixel voltage).

[0053] In the pixel circuit according to the second configuration example, since the Set signal and the Reset signal are input to separate transistors, the bit plane of the smallest bit is not constrained by the scan time, as shown in the timing charts of Figures 17 and 18.

[0054] Other configurations may be substantially the same as those of the pixel circuit in the first configuration example shown in Figure 13 above.

[0055] (Pixel Circuit Example 3) Figure 19 is a circuit diagram showing a third configuration example of a pixel circuit in a display device 1 according to one embodiment. Figure 20 is a timing chart showing an example of operation of the pixel circuit according to the third configuration example. Figure 21 is a timing chart showing an example of operation of the pixel circuit according to the third configuration example. Figures 19 to 21 show an example of the configuration and operation of a pixel circuit when a PWM signal Sig_PWM corresponding to the video signal Sv and a PAM signal Sig_PAM corresponding to the uniformity correction signal Sc are written to the pixel P in a time-separated manner.

[0056] The pixel circuit according to the third configuration example includes a transistor Tn1, a transistor Tn2, a transistor Tn4, a capacitor C1, a capacitor C2, and a light-emitting element 11.

[0057] The gate of transistor Tn1 is connected to the supply line for the Set signal. Transistor Tn4 is an offset transistor. The gate of transistor Tn4 is connected to the supply line for the Offset signal.

[0058] The timing chart in Figure 20 shows the Set signal, the Offset signal, the signal voltages of the PWM signal Sig_PWM or PAM signal Sig_PAM, and the Vpix signal (pixel voltage).

[0059] In the pixel circuit according to the third configuration example, the on / off control of transistor Tn4 based on the Offset signal causes the PWM signal Sig_PWM, which corresponds to the video signal Sv, and the PAM signal Sig_PAM, which corresponds to the uniformity correction signal Sc, to be written in a time-separated manner, as shown in the timing charts of Figures 17 and 18.

[0060] Other configurations may be substantially the same as those of the pixel circuit in the first configuration example shown in Figure 13 above.

[0061] (Pixel Circuit Example 4) Figure 22 is a circuit diagram showing a fourth configuration example of a pixel circuit in a display device 1 according to one embodiment. Figure 23 is a timing chart showing an example of operation of the pixel circuit according to the fourth configuration example. Figure 24 is a timing chart showing an example of operation of the pixel circuit according to the fourth configuration example. Figures 22 to 24 show an example of the configuration and operation of a pixel circuit when a PWM signal Sig_PWM corresponding to the video signal Sv and a PAM signal Sig_PAM corresponding to the uniformity correction signal Sc are written to the pixel P in a time-separated manner.

[0062] The pixel circuit according to the fourth configuration example includes a transistor Tn1, a transistor Tn2, a transistor Tn11, a transistor Tn12, a capacitor C1, a capacitor C11, and a light-emitting element 11.

[0063] The gate of transistor Tn1 is connected to the supply line for the Set signal. One end of transistor Tn11 is connected to the supply lines for the PWM signal Sig_PWM and the PAM signal Sig_PAM, and the other end is connected to the gate of transistor Tn12 and one end of capacitor C11. The gate of transistor Tn11 is connected to the supply line for the Set_PWM signal. One end of transistor Tn12 is connected to one end of the light-emitting element 11 via transistor Tn2, and the other end is connected to the other end of capacitor C11.

[0064] The timing chart in Figure 23 shows the Set signal, the Set_PWM signal, the signal voltages of the PWM signal Sig_PWM or the PAM signal Sig_PAM, and the Vpix signal (pixel voltage).

[0065] In the pixel circuit according to the fourth configuration example, the on / off control of transistor Tn1 based on the Set signal and the on / off control of transistor Tn11 based on the Set_PWM signal cause the PWM signal Sig_PWM, which corresponds to the video signal Sv, and the PAM signal Sig_PAM, which corresponds to the uniformity correction signal Sc, to be written in a time-separated manner, as shown in the timing charts of Figures 23 and 24.

[0066] Other configurations may be substantially the same as those of the pixel circuit in the first configuration example shown in Figure 13 above.

[0067] (Pixel Circuit Example 5) Figure 25 is a circuit diagram showing a fifth configuration example of a pixel circuit in a display device 1 according to one embodiment. Figure 26 is a timing chart showing an example of operation of the pixel circuit according to the fifth configuration example. Figure 27 is a timing chart showing an example of operation of the pixel circuit according to the fifth configuration example. Figures 25 to 27 show an example of the configuration and operation of a pixel circuit when a PWM signal Sig_PWM corresponding to the video signal Sv and a PAM signal Sig_PAM corresponding to the uniformity correction signal Sc are written to the pixel P in a time-separated manner.

[0068] The pixel circuit according to the fifth configuration example includes a transistor Tn1, a transistor Tn2, a transistor Tn11, a transistor Tn12, a capacitor C1, a capacitor C11, and a light-emitting element 11.

[0069] One end of transistor Tn1 is connected to the supply line for the PAM signal Sig_PAM, and its gate is connected to the supply line for the Set signal. One end of transistor Tn11 is connected to the supply line for the PWM signal Sig_PWM, and its other end is connected to the gate of transistor Tn12 and one end of capacitor C11. The gate of transistor Tn11 is connected to the supply line for the Set_PWM signal. One end of transistor Tn12 is connected to one end of the light-emitting element 11 via transistor Tn2, and its other end is connected to the other end of capacitor C11.

[0070] The timing chart in Figure 26 shows the Set signal, the Set_PWM signal, the signal voltage of the PWM signal Sig_PWM, the signal voltage of the PAM signal Sig_PAM, and the Vpix signal (pixel voltage).

[0071] In the pixel circuit according to the fifth configuration example, the on / off control of transistor Tn1 based on the Set signal and the on / off control of transistor Tn11 based on the Set_PWM signal cause the PWM signal Sig_PWM, which corresponds to the video signal Sv, and the PAM signal Sig_PAM, which corresponds to the uniformity correction signal Sc, to be written in a time-separated manner, as shown in the timing charts of Figures 26 and 27.

[0072] Other configurations may be substantially the same as those of the pixel circuit in the first configuration example shown in Figure 13 above.

[0073] [1.3 Example of Pixel Peripheral Circuit] A display device 1 according to one embodiment includes a pixel peripheral circuit as a signal processing circuit.

[0074] (Pixel peripheral circuit example 1) Figure 28 is a circuit diagram showing a first configuration example of a pixel peripheral circuit in a display device 1 according to one embodiment.

[0075] A display device 1 according to one embodiment includes, as a pixel peripheral circuit according to the first configuration example, a PWM conversion circuit 30, a PAM conversion circuit 40, a gamma conversion circuit 51, an adder circuit 52, and a correction value storage memory 70.

[0076] The PWM conversion circuit 30 includes a latch circuit 31 and a PWM signal generation circuit 32. The PAM conversion circuit 40 includes a latch circuit 41 and a DAC 42.

[0077] Furthermore, the display device 1 according to one embodiment further includes an amplifier circuit AMP1, a changeover switch SW1, and a changeover switch SW2 as pixel peripheral circuits according to the first configuration example.

[0078] The video signal Sv is gamma corrected by the gamma conversion circuit 51 and then output to the PWM conversion circuit 30. In the PWM conversion circuit 30, the video signal Sv, which has been latched by the latch circuit 31, is converted to a PWM signal Sig_PWM by the PWM signal generation circuit 32 and output to the amplifier circuit AMP1 via the toggle switch SW1.

[0079] The uniformity correction signal Sc is output to the PAM conversion circuit 40. In the PAM conversion circuit 40, the uniformity correction signal Sc, which has been latched by the latch circuit 41, is converted to a PAM signal Sig_PAM by the DAC 42 and output to the amplifier circuit AMP1.

[0080] Here, the PAM conversion circuit 40 may receive multiple correction signals of different types, including a uniformity correction signal Sc, in a merged (integrated) state. For example, a set of correction signals, in which the Top (maximum) brightness signal, the uniformity correction signal Sc, the defect correction signal, and the voltage drop correction signal are merged, may be stored in the correction value storage memory 70 and read out, or signals stored in separate memories may be read out and merged by the adder circuit 52.

[0081] The amplifier circuit AMP1 is controlled so that when the PWM signal Sig_PWM is 0, the Amp current is cut off and the output drops to 0.

[0082] (Pixel peripheral circuit example 2) Figure 29 is a circuit diagram showing a second example of the configuration of a pixel peripheral circuit in a display device 1 according to one embodiment.

[0083] The display device 1 according to one embodiment further includes a selection circuit 53 in addition to the pixel peripheral circuit according to the first configuration example in Figure 28.

[0084] The selection circuit 53 reads out and outputs a plurality of different types of correction signals, including an unevenness correction signal Sc, based on the video signal Sv. In this case, for example, a set of correction signals in which the Top (maximum) brightness signal, the unevenness correction signal Sc, the defect correction signal, and the voltage drop correction signal are merged may be stored in and read from the correction value storage memory 70, or signals stored in separate memories may be read out and merged by the addition circuit 52.

[0085] Other components may be substantially the same as those of the pixel peripheral circuit in the first configuration example shown in Figure 28 above.

[0086] (Example of amplifier circuit) Figure 30 is a circuit diagram showing one example configuration of an amplifier circuit AMP1 in a display device 1 according to one embodiment.

[0087] The amplifier circuit AMP1 comprises an inverter INV1, a constant current circuit 61, a differential amplifier circuit 62, an output circuit 63, and a switching element SWc.

[0088] The constant current circuit 61 includes transistors T21, T22, T23, and T24.

[0089] The differential amplifier circuit 62 includes transistors T31, T32, T33, T34, and T35.

[0090] The output circuit 63 includes transistor T41 and transistor T42.

[0091] The PAM signal Sig_PAM from the PAM conversion circuit 40 is input to the gate of transistor T31 of the differential amplifier circuit 62. The PWM signal Sig_PWM from the PWM conversion circuit 30 is input to the gate of switching element SWa and the gate of transistor T31. In addition, the PWM signal Sig_PWM is input to the gate of switching element SWb via inverter INV1.

[0092] In amplifier circuit AMP1, when the PWM signal Sig_PWM is 0, the Amp current of amplifier circuit AMP1 is cut off, and the output is controlled to drop to 0. In amplifier circuit AMP1, when the PWM signal Sig_PWM is at a low level, switching elements SWa and SWb are turned ON, node Na becomes the VCC voltage, and node Nb becomes the GND voltage. As a result, the constant current circuit 61, differential amplifier circuit 62, and output circuit 63 stop, and no current flows. At the same time, switching element SWc is turned ON, so the output voltage Sig of amplifier circuit AMP1 is fixed at a low level.

[0093] (PWM Drive Example) Figure 31 is a timing chart showing an example of PWM drive by the PWM conversion circuit 30 of the display device 1 according to one embodiment. Figure 31 shows an example of 10-bit PWM drive. Figure 31 shows a timing chart of the Set signal and Reset signal Rst associated with the bit plane and the pixel voltage. Note that in Figure 31, the correction value (unevenness correction signal Sc) is omitted, and only the signal voltage corresponding to the PWM signal Sig_PWM is shown as the pixel voltage.

[0094] In one embodiment of the display device 1, one frame period is divided into multiple bit planes, and a PWM signal Sig_PWM with a pulse width weighted according to the bit is written to the pixel P as a pixel voltage. In Figure 31, bits 0 to 5 are at the same time interval, but in actual operation, the timing of the Reset signal Rst is adjusted so that a PWM signal Sig_PWM with a pulse width weighted according to the bit is written to the pixel P as a pixel voltage.

[0095] [1.4 Examples of storing correction values] (Example 1 of storing correction values) Figure 32 is a schematic diagram showing a first example of storing correction values ​​included in the unevenness correction signal Sc in a display device 1 according to one embodiment.

[0096] A display device 1 according to one embodiment includes an adder circuit 54, a selection circuit 55, a PAM conversion circuit 40, a correction value storage memory 70, and an address counter 71. The correction value storage memory 70 may have a first memory 70A and a second memory 70B.

[0097] Figure 33 is a schematic diagram illustrating an example of the relationship between the pixel value variation (luminance variation) component and the correction amount used to compensate for the pixel value variation.

[0098] As shown in Figure 33, there is variation in the pixel value of each pixel P due to variations in the characteristics of the light-emitting element 11 of each pixel P. For example, there is a decrease in brightness due to dark spots caused by through-transmission of the light-emitting element 11, and variations in brightness due to the In concentration distribution.

[0099] The correction value storage memory 70 may store the difference from the representative value of the statistical brightness distribution when a uniform image is displayed. For example, the correction value storage memory 70 stores the correction value for each brightness region, or the correction value for each pixel P corresponding to the brightness variation of the pixel P. The correction value for each pixel P corresponding to the brightness variation of the pixel P may only store the difference from the global offset value (such as the mean value of the histogram). The first memory 70A stores, for example, the correction value of the pixel P corresponding to brightness region A in Figure 33. If a large amount of correction is required, for example, if there are a small number of pixels P in brightness region B in Figure 33, the difference from the correction value stored in the first memory 70A is stored in the second memory 70B. At this time, the pixel address is also stored in the second memory 70B. The PAM conversion circuit 40 outputs the correction value for each pixel P stored in the correction value storage memory 70 as a uniformity correction signal Sc via the adder circuit 54 and the selection circuit 55.

[0100] In one embodiment of the display device 1, by storing the correction values ​​in the correction value storage memory 70 as described above, the memory capacity can be reduced, contributing to miniaturization and cost reduction of the display device 1. By applying this method, the memory capacity of the correction value storage memory 70 can be reduced, resulting in a reduction in circuit area and power consumption. However, the method for storing and reading the correction values ​​is not limited to the example described above.

[0101] (Example of storing correction values ​​2) Figure 34 is a schematic diagram showing a second example of storing correction values ​​included in the unevenness correction signal Sc in a display device 1 according to one embodiment.

[0102] A display device 1 according to one embodiment may include an adder circuit 56, an adder circuit 57, a PAM conversion circuit 40, and a correction value storage memory 70. The correction value storage memory 70 may have a first memory 70A, a second memory 70B, and a third memory 70C.

[0103] Multiple correction values ​​for different brightness levels may be expressed as follows. In this case, the first memory 70A stores correction value A as the correction value for the high brightness setting. The second memory 70B stores correction value B, which is the difference between correction value A and the medium brightness setting, as the correction value for the medium brightness setting. The third memory 70C stores correction value C, which is the difference between correction value A + correction value B, as the correction value for the low brightness setting. High brightness setting: Correction value A Medium brightness setting: Correction value A + Correction value B Low brightness setting: Correction value A + Correction value B + Correction value C

[0104] The adder circuit 57 receives the correction value stored in the second memory 70B, the correction value stored in the third memory 70C, and the Top (maximum) brightness signal as input. The adder circuit 56 receives the correction value stored in the first memory 70A, the correction values ​​stored in the second memory 70B and the third memory 70C added by the adder circuit 57, and the Top (maximum) brightness signal as input. The PAM conversion circuit 40 outputs the correction value for each pixel P stored in the correction value storage memory 70 via the adder circuits 56 and 57 as a uniformity correction signal Sc.

[0105] Other configurations may be substantially the same as those in the first storage example shown in Figure 32 above.

[0106] (Example 3 of storing correction values) Figure 35 is a schematic diagram showing a third example of storing correction values ​​included in the unevenness correction signal Sc in a display device 1 according to one embodiment. Figure 36 is an explanatory diagram showing an overview of the third storage example.

[0107] The display device 1 according to one embodiment may include a PAM conversion circuit 40 and a correction value storage memory 70. The correction value storage memory 70 may have a first memory 70A, a second memory 70B, and a third memory 70C.

[0108] The correction value storage memory 70 may store correction values ​​for each RGB color. For example, the correction value storage memory 70 may store correction values ​​for each RGB color area, or correction values ​​for each pixel P corresponding to the brightness variation of the pixel P. The correction value for each pixel P corresponding to the brightness variation of the pixel P may only store the difference from the global offset value (such as the mean value of the histogram).

[0109] The first memory 70A stores correction value A, which is, for example, the correction value for the R color. The second memory 70B stores correction value B, which is, for example, the correction value for the G color. The third memory 70C stores correction value C, which is, for example, the correction value for the B color.

[0110] The memory area can be separated for each color, or a common memory area can be provided for all colors.

[0111] Other configurations may be substantially the same as those in the first storage example shown in Figure 32 above.

[0112] [1.5 Example of Overall Configuration of Display Device] Figure 37 is a block diagram showing an example of the overall configuration of a display device 1 according to one embodiment.

[0113] A display device 1 according to one embodiment includes a pixel array 10, a PWM conversion circuit 30, a PAM conversion circuit 40, a gamma conversion circuit 51, a correction value storage memory 70, an interface circuit 80, a video signal storage memory 81, a timing controller 82, a readout circuit 91, a readout circuit 92, and a vertical drive circuit 110.

[0114] The PWM conversion circuit 30 includes a latch circuit 31 and a PWM signal generation circuit 32 (see Figures 28 and 29). The PAM conversion circuit 40 includes a latch circuit 41 and a DAC 42 (see Figures 32, 34, and 35). The pixel array 10 has a plurality of pixels P arranged in a matrix in two dimensions.

[0115] The correction value storage memory 70 may also be configured as an external memory capable of communicating with the display device 1.

[0116] The display device 1 receives a video signal Sv, an unevenness correction signal Sc, and a synchronization signal CLK via an interface circuit 80. The timing controller 82 controls the timing of signal processing in the PWM conversion circuit 30, the PAM conversion circuit 40, the readout circuit 91, the readout circuit 92, and the vertical drive circuit 110 based on the synchronization signal CLK.

[0117] The video signal Sv is temporarily stored in the video signal storage memory 81, then read out from the readout circuit 91 at a predetermined timing based on the synchronization signal CLK, and output to the gamma conversion circuit 51. After gamma correction processing is performed by the gamma conversion circuit 51, the video signal Sv is output to the PWM conversion circuit 30. The PWM conversion circuit 30 writes the video signal Sv, which has been converted to a PWM signal Sig_PWM, to the pixel P.

[0118] The unevenness correction signal Sc is temporarily stored in the correction value storage memory 70, then read out from the readout circuit 92 at a predetermined timing based on the synchronization signal CLK, and output to the PAM conversion circuit 40. The PAM conversion circuit 40 writes the unevenness correction signal Sc, which has been converted to a PAM signal Sig_PAM, to the pixel P.

[0119] [1.6 Effects] As described above, according to the display device 1 of one embodiment, a video signal Sv is written to each of the multiple pixels P using the PWM signal Sig_PWM, and a uniformity correction signal Sc, which corrects the variation in the characteristics of each pixel, is written using the PAM signal Sig_PAM. This makes it possible to improve display quality while keeping the circuit size and power consumption down.

[0120] Furthermore, according to one embodiment of the display device 1, high image quality is achieved because brightness can be corrected with high precision within the same gradation, and circuit size and power consumption can be reduced. Since only the bit depth necessary for gamma conversion needs to be secured, the number of PWM bits can be minimized, enabling a reduction in circuit size and low power consumption. Since it is no longer necessary to correct gradation shifts for each pixel P, the circuit required for this correction is eliminated, enabling a reduction in circuit size and low power consumption. In addition, complex image inspection and correction are unnecessary, reducing manufacturing costs. The memory size required for uniformity correction can be reduced, and the chip size can be reduced. Uniform correction can be performed even for uniformity that occurs for each maximum brightness setting. Since a simple pixel P with a small number of elements is sufficient, the pixel P can be miniaturized.

[0121] The effects described herein are merely illustrative and not limiting, and other effects may also exist. The same applies to the effects of other embodiments described later.

[0122] <2. Other Embodiments> The technology described herein is not limited to the above-described embodiment and can be implemented in various modified forms.

[0123] For example, this technology can also take the following configuration. According to this configuration, a video signal is written to each of multiple pixels using a first type of signal, and a correction signal that corrects the variations in the characteristics of each pixel is written using a second type of signal different from the first type. This makes it possible to provide a display device that can improve display quality while keeping the circuit size and power consumption down.

[0124] (1) A display device comprising a plurality of pixels and a signal processing circuit that writes a video signal to each of the plurality of pixels using a signal of a first method and writes a correction signal to correct variations in the characteristics of each pixel using a signal of a second method different from the first method. (2) The display device according to (1) above, wherein the first method is a pulse width modulation method and the second method is a pulse amplitude modulation method. (3) The display device according to (1) or (2) above, wherein the signal processing circuit writes the video signal and the correction signal to each of the pixels simultaneously. (4) The display device according to (1) or (2) above, wherein the signal processing circuit writes the video signal and the correction signal to each of the pixels in a temporally separated manner. (5) The display device according to any one of (1) to (4) above, wherein the signal processing circuit comprises a first conversion circuit that converts the video signal into a pulse width modulation signal and a second conversion circuit that converts the correction signal into a pulse amplitude modulation signal. (6) The display device according to (5) above, wherein the signal processing circuit outputs the pulse amplitude modulated signal to each pixel when the signal value of the pulse width modulated signal is either High or Low. (7) The display device according to any one of (1) to (6) above, further comprising a storage memory for storing the correction signal. (8) The display device according to (7) above, wherein the storage memory stores the difference from the representative value of the statistical luminance distribution when a uniform image is displayed. (9) The display device according to (7) or (8) above, wherein the storage memory stores a plurality of correction signals of different types. (10) The display device according to (7) or (9) above, wherein the storage memory stores a plurality of correction signals for each luminance region. (11) The display device according to (7) or (10) above, wherein the storage memory stores a plurality of correction signals for each color.

[0125] This application claims priority based on Japanese Patent Application No. 2025-038972, filed with the Japan Patent Office on 12 March 2025, and all contents of that application are incorporated herein by reference.

[0126] Those skilled in the art will understand that various modifications, combinations, subcombinations, and changes can be conceived depending on design requirements and other factors, and that these fall within the scope of the attached claims and their equivalents.

Claims

1. A display device comprising a plurality of pixels, and a signal processing circuit that writes a video signal to each of the plurality of pixels using a first type of signal, and writes a correction signal to correct variations in the characteristics of each pixel using a second type of signal different from the first type.

2. The display device according to claim 1, wherein the first method is a pulse width modulation method, and the second method is a pulse amplitude modulation method.

3. The display device according to claim 1, wherein the signal processing circuit simultaneously writes the video signal and the correction signal to each of the pixels.

4. The display device according to claim 1, wherein the signal processing circuit temporally separates the video signal and the correction signal and writes them to each pixel.

5. The display device according to claim 1, wherein the signal processing circuit comprises a first conversion circuit that converts the video signal into a pulse width modulation signal, and a second conversion circuit that converts the correction signal into a pulse amplitude modulation signal.

6. The display device according to claim 5, wherein the signal processing circuit outputs the pulse amplitude modulated signal to each pixel when the signal value of the pulse width modulated signal is either High or Low.

7. The display device according to claim 1, further comprising a storage memory for storing the correction signal.

8. The display device according to claim 7, wherein the storage memory stores the difference between the statistical luminance distribution and a representative value when a uniform image is displayed.

9. The display device according to claim 7, wherein the storage memory stores a plurality of correction signals of different types.

10. The display device according to claim 7, wherein the storage memory stores a plurality of correction signals for each brightness region.

11. The display device according to claim 7, wherein the storage memory stores a plurality of correction signals for each color.

Images