Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device comprising a semiconductor substrate, a front-surface-side metal layer provided above the semiconductor substrate, and a protective film provided above the semiconductor substrate. The protective film has: a first end portion having a first taper angle; and a second end portion having a second taper angle different from the first taper angle. Also provided is a method for manufacturing a semiconductor device, the method comprising: a step for providing a front-surface-side metal layer above a semiconductor substrate; and a step for providing, above the semiconductor substrate, a protective film in which a first end portion and a second end portion have different taper angles.

Description

Semiconductor device and method for manufacturing semiconductor device

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Patent Document 1 describes "wiring in which the side surface angles of the wiring are precisely varied in desired portions on one mother glass substrate". [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Unexamined Patent Publication No. 2009-158940 General Disclosure

[0003] According to a first aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; a front surface side metal layer provided above the semiconductor substrate; and a protective film provided above the semiconductor substrate, wherein the protective film has a first end portion having a first taper angle and a second end portion having a second taper angle different from the first taper angle.

[0004] In the above semiconductor device, the first end portion may be an end portion of the protective film closest to an edge of the semiconductor substrate. The second end portion may be an end portion of the protective film above the front surface side metal layer.

[0005] In any one of the above semiconductor devices, the first taper angle may be larger than the second taper angle.

[0006] In any one of the above semiconductor devices, the first taper angle may be not less than 40 degrees and not more than 45 degrees.

[0007] In any one of the above semiconductor devices, the second taper angle may be not less than 25 degrees and not more than 30 degrees.

[0008] In any one of the above semiconductor devices, the front surface side metal layer may include a plurality of front surface side metals including a first front surface side metal and a second front surface side metal having a larger area than the first front surface side metal. The first end portion may be an end portion of the protective film closest to an edge of the semiconductor substrate. The second end portion may be an end portion of the protective film above the first front surface side metal.

[0009] In any of the semiconductor devices described above, the protective film may have a third end having a third taper angle above the second front metal. The third taper angle may be equal to the second taper angle.

[0010] In any of the semiconductor devices described above, the protective film may have a third end having a third taper angle above the second front metal. The third taper angle may be equal to the first taper angle.

[0011] In any of the above-described semiconductor devices, the protective film may be an organic film.

[0012] In any of the above-described semiconductor devices, the protective film may be a polyimide film or a polybenzoxazole film.

[0013] In any of the above-mentioned semiconductor devices, the thickness of the protective film may be 2 μm or more and 30 μm or less.

[0014] A second aspect of the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: providing a front-side metal layer above a semiconductor substrate; and providing a protective film above the semiconductor substrate having a first end and a second end with different taper angles.

[0015] In the above-described method for manufacturing a semiconductor device, the step of providing the protective film may include the steps of providing the protective film with the first end having a first taper angle and providing the protective film with the second end having a second taper angle different from the first taper angle.

[0016] In any of the above methods for manufacturing a semiconductor device, the first end may be the end of the protective film closest to the dicing line of the semiconductor substrate. The second end may be the end of the protective film above the metal layer on the front side.

[0017] In any of the above methods for manufacturing a semiconductor device, the first taper angle may be larger than the second taper angle.

[0018] In any of the above methods for manufacturing a semiconductor device, the step of providing the first end and the step of providing the second end may be different steps.

[0019] In any of the above methods for manufacturing a semiconductor device, the material of the protective film may be a photosensitive material. The step of providing the first end may include a step of exposing the protective film above the dicing line of the semiconductor substrate. The step of providing the second end may include a step of exposing the protective film above the surface metal layer.

[0020] In any of the above methods for manufacturing a semiconductor device, the first distance from the first focus position to the semiconductor substrate in the step of exposing the protective film above the dicing line may be smaller than the second distance from the second focus position to the front-side metal layer in the step of exposing the protective film above the front-side metal layer.

[0021] In any of the above methods for manufacturing a semiconductor device, the first distance may be 1% or more and 45% or less of the second distance.

[0022] In any of the above methods for manufacturing a semiconductor device, the step of providing the second end may be performed after the step of providing the first end.

[0023] In any of the above methods for manufacturing a semiconductor device, the step of providing the second end may be performed before the step of providing the first end.

[0024] In any of the above methods for manufacturing a semiconductor device, the material of the protective film may be a non-photosensitive material. The step of providing the first end may include the steps of providing a resist above the non-photosensitive material, baking the non-photosensitive material and the resist, exposing the resist above the dicing line of the semiconductor substrate, and etching the non-photosensitive material above the dicing line. The step of providing the second end may include the steps of providing a resist above the non-photosensitive material, baking the non-photosensitive material and the resist, exposing the resist above the surface metal layer, and etching the non-photosensitive material above the surface metal layer.

[0025] In any of the above methods for manufacturing a semiconductor device, the thickness of the resist at the step of providing the first end may be 2 μm or more and 3.5 μm or less. The thickness of the resist at the step of providing the second end may be 3 μm or more and 4.5 μm or less.

[0026] In any of the above methods for manufacturing a semiconductor device, the step of providing the second end may be performed after the step of providing the first end.

[0027] In any of the above methods for manufacturing a semiconductor device, the bake temperature in the baking step of providing the second end may be higher than the bake temperature in the baking step of providing the first end.

[0028] In any of the above methods for manufacturing a semiconductor device, the baking time in the baking step of providing the second end may be longer than the baking time in the baking step of providing the first end.

[0029] It should be noted that the above summary of the invention does not enumerate all of its features. Subcombinations of these features may also constitute an invention.

[0030] An example of the upper surface of semiconductor device 100 is shown. An example of region A in Figure 1 is shown. An example of the c-c' cross section in Figure 2A is shown. An example of the a-a' cross section in Figure 1 is shown. An example of the wire bonding process is shown. An example of the wire bonding process according to a comparative example is shown. An example of the region near the dicing line of semiconductor device 100 before dicing is shown. An example of the region near the dicing line of semiconductor device 500 according to a comparative example is shown. An example of the b-b' cross section in Figure 1 is shown. An example of the b-b' cross section in Figure 1 is shown. This is a flowchart showing an example of the manufacturing process of semiconductor device 100. This is a flowchart showing an example of step S110 for providing the protective film 180. This is a flowchart showing an example of step S110 for providing the protective film 180. This is a flowchart showing an example of the manufacturing process of semiconductor device 100. This is a flowchart showing an example of step S110 for providing the protective film 180. This is a flowchart showing an example of the manufacturing process of semiconductor device 100.

[0031] The following embodiments are not intended to limit the claims of the invention. Not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0032] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the upper surface, and the other surface as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0033] In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z axis and the -Z axis.

[0034] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0035] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0036] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0037] In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type.

[0038] Figure 1 shows an example of the upper surface of the semiconductor device 100. In Figure 1, the positions of each component projected onto the upper surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted. The semiconductor device 100 may be a semiconductor chip comprising a transistor section 70 and a diode section 80.

[0039] The transistor portion 70 may include a transistor such as an IGBT (Insulated Gate Bipolar Transistor). The diode portion 80 may include a diode such as a free wheel diode (FWD). The semiconductor device 100 of the present example is a reverse conducting IGBT (RC-IGBT: Reverse Conducting IGBT) that has the transistor portion 70 and the diode portion 80 on the same chip.

[0040] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, may be a silicon carbide substrate, or may be a nitride semiconductor substrate such as gallium nitride or the like.

[0041] The semiconductor substrate 10 has an edge 102 when viewed from above. In the present specification, when simply referred to as a top view, it means viewing from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 of the present example has two pairs of edges 102 facing each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to any one of the edges 102. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10. The semiconductor substrate 10 has an active portion 160 and an edge termination structure portion 170.

[0042] The active portion 160 is a region where a main current flows in the depth direction between the top surface and the bottom surface of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode is provided above the active portion 160, which is omitted in FIG. 1. The emitter electrode is an example of a front surface side metal layer.

[0043] The active portion 160 is provided with at least one of a transistor portion 70 including a transistor element such as an IGBT and a diode portion 80 including a diode element such as a freewheeling diode (FWD). In the example of FIG. 1, the transistor portions 70 and the diode portions 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. In other examples, the active portion 160 may be provided with only one of the transistor portion 70 and the diode portion 80. For example, the semiconductor device 100 may be an IGBT, a MOSFET, a PIN diode, or a Schottky barrier diode.

[0044] In FIG. 1, the symbol "I" is attached to a region where the transistor portion 70 is arranged, and the symbol "F" is attached to a region where the diode portion 80 is arranged. In the present specification, a direction perpendicular to the arrangement direction in a top view may be referred to as a stretching direction (the Y-axis direction in FIG. 1). Each of the transistor portion 70 and the diode portion 80 may have a length in the stretching direction. That is, the length of the transistor portion 70 in the Y-axis direction is larger than the width thereof in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is larger than the width thereof in the X-axis direction. The stretching direction of the transistor portion 70 and the diode portion 80 may be the same as the longitudinal direction of each trench portion described later.

[0045] The diode portion 80 has an N+-type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In the present specification, a region provided with the cathode region is referred to as the diode portion 80. That is, the diode portion 80 is a region overlapping the cathode region in a top view. On the lower surface of the semiconductor substrate 10, a P+-type collector region may be provided in a region other than the cathode region.

[0046] The transistor portion 70 has a P+-type collector region in a region in contact with the lower surface of the semiconductor substrate 10. Further, in the transistor portion 70, gate structures including an N-type emitter region, a P-type base region, a gate conductive portion and a gate insulating film are periodically arranged on the upper surface side of the semiconductor substrate 10.

[0047] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is located near the edge 102. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires. Each pad is an example of a metal layer on the front side.

[0048] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 includes gate wiring 130 that connects the gate pad 112 and the gate trench.

[0049] The gate wiring 130 is electrically connected to the gate conductive part of the transistor section 70 and applies a gate voltage to the transistor section 70. The gate wiring 130 is provided so as to surround the outer circumference of the active section 160 when viewed from above. The gate wiring 130 is electrically connected to the gate pad 112.

[0050] Furthermore, the semiconductor device 100 may also include a temperature sensing unit which is a PN junction diode made of polysilicon or the like, and a current detection unit which simulates the operation of the transistor unit provided in the active unit 160.

[0051] The semiconductor device 100 in this example includes a front-side metal layer provided above the semiconductor substrate 10. As described above, the emitter electrode and gate pad 112 are examples of the front-side metal layer. If the semiconductor device 100 has pads such as an anode pad, cathode pad, and current detection pad, these pads are also examples of the front-side metal layer.

[0052] The front-side metal layer may have multiple front-side metals. The multiple front-side metals may include a first front-side metal and a second front-side metal having a larger area than the first front-side metal. As described above, the emitter electrode is provided above the active portion 160. Therefore, the area of ​​the emitter electrode is larger than the area of ​​the gate pad 112. That is, the gate pad 112 is an example of the first front-side metal, and the emitter electrode is an example of the second front-side metal. If the semiconductor device 100 has pads such as an anode pad, a cathode pad, and a current detection pad, the area of ​​these pads may also be smaller than the area of ​​the emitter electrode, and these pads are also examples of the first front-side metal.

[0053] If the first front-facing metal has a roughly rectangular shape, the length of the shorter side of the first front-facing metal may be 200 μm or less. If the second front-facing metal has a roughly rectangular shape, the length of the shorter side of the second front-facing metal may be longer than 200 μm.

[0054] In this example, the semiconductor device 100 includes an edge termination structure 170 between the active portion 160 and the edge 102 when viewed from above. The edge termination structure 170 in this example is positioned between the gate wiring 130 and the edge 102. The edge termination structure 170 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 170 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 160.

[0055] The semiconductor device 100 in this example includes a protective film 180 provided on top of the semiconductor substrate 10. The protective film 180 prevents solder on one pad from flowing to other pads, etc. In this example, the area where the protective film 180 is provided is indicated by hatching. The protective film 180 is an insulating protective film. The protective film 180 may be an organic film. The protective film 180 may be a polyimide film or a polybenzoxazole film. The material of the protective film 180 may be a photosensitive material or a non-photosensitive material. That is, the protective film 180 may be a photosensitive polyimide film, a non-photosensitive polyimide film, a photosensitive polybenzoxazole film, or a non-photosensitive polybenzoxazole film. However, the material of the protective film 180 is not limited to these.

[0056] The protective film 180 may have a first end 182, a second end 184, and a third end 186. The first end 182 may be the end of the protective film 180 closest to the edge 102 of the semiconductor substrate 10. The second end 184 and the third end 186 may be the ends of the protective film 180 above the front-side metal layer. For example, the second end 184 is the end of the protective film 180 above the first front-side metal (gate pad 112 in this example), and the third end 186 is the end of the protective film 180 above the second front-side metal (emitter electrode in this example). Details of each end of the protective film 180 will be described later.

[0057] Figure 2A shows an example of region A in Figure 1. Region A includes the transistor section 70, the diode section 80, and the gate wiring 130. In this example, the gate wiring 130 includes the gate metal layer 50 and the connection section 25. Note that the protective film 180 is omitted in this figure.

[0058] On the front surface of the semiconductor substrate 10, a boundary region 90 is provided between the transistor portion 70 and the diode portion 80. The front surface 21 of the semiconductor substrate 10 refers to one of the two opposing main surfaces of the semiconductor substrate 10. The front surface 21 will be described later.

[0059] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, a well region 17, an emitter region 12, a base region 14, and a contact region 15 formed inside the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0060] An interlayer insulating film is formed between the emitter electrode 52 and the gate metal layer 50 and the front surface 21 of the semiconductor substrate 10, but the interlayer insulating film is omitted in Figure 2A. In this example, contact holes 54, 55, and 56 are provided through the interlayer insulating film.

[0061] The emitter electrode 52 is electrically connected to the emitter region 12, contact region 15, and base region 14 on the front surface 21 of the semiconductor substrate 10 through a contact hole 54 opened in the interlayer insulating film. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion.

[0062] The gate metal layer 50 contacts the connection portion 25 through the contact hole 55. The connection portion 25 is formed of a semiconductor such as polysilicon doped with impurities. The connection portion 25 is connected to the gate conductive portion in the gate trench portion 40 on the front surface of the semiconductor substrate 10.

[0063] The emitter electrode 52 and the gate metal layer 50 are formed from a metal-containing material. For example, at least a portion of each electrode may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). Each electrode may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. Each electrode may further have a plug formed by embedding tungsten or the like in the contact hole so as to be in contact with the barrier metal and the aluminum or the like.

[0064] The well region 17 is provided overlapping with the gate metal layer 50. The well region 17 is also provided extending to a predetermined width in areas that do not overlap with the gate metal layer 50. In this example, the well region 17 is provided away from the Y-axis end of the contact hole 54 towards the gate metal layer 50. The well region 17 is a second conductivity type region with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 17 is P+ type.

[0065] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction on the front surface 21 of the semiconductor substrate 10. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the arrangement direction. In this example, the diode section 80 has a plurality of dummy trench sections 30 provided along the arrangement direction. In this example, the diode section 80 does not have gate trench sections 40.

[0066] The transistor section 70 has one or more gate trench sections 40 arranged at predetermined intervals along the arrangement direction of each trench. The gate conductive portion inside the gate trench section 40 is electrically connected to the gate metal layer 50 and the gate potential is applied. The transistor section 70 may also have one or more dummy trench sections 30 arranged at predetermined intervals along the arrangement direction. A potential different from the gate potential is applied to the dummy conductive portion inside the dummy trench section 30. In this example, the dummy conductive portion is electrically connected to the emitter electrode 52 and the emitter potential is applied.

[0067] In the transistor section 70, one or more gate trench sections 40 and one or more dummy trench sections 30 may be alternately formed along the arrangement direction. The dummy trench sections 30 are arranged at predetermined intervals along the arrangement direction in the diode section 80 and the boundary region 90. The transistor section 70 may also consist only of gate trench sections 40 without the dummy trench sections 30.

[0068] The gate trench portion 40 in this example may have two extended portions 41 (the trench portion which is linear along the extension direction) that extend along the extension direction perpendicular to the arrangement direction, and a connecting portion 43 that connects the two extended portions 41. In Figure 2A, the extension direction is the Y-axis direction.

[0069] In the transistor section 70, the dummy trench section 30 is provided between each extended portion 41 of the gate trench section 40. One dummy trench section 30 may be provided between each extended portion 41, or multiple dummy trench sections 30 may be provided. The dummy trench section 30 may have a linear shape extending in the extension direction, and may have an extended portion 31 and a connecting portion 33, similar to the gate trench section 40. The semiconductor device 100 shown in Figure 2A includes both a linear dummy trench section 30 without a connecting portion 33 and a dummy trench section 30 with a connecting portion 33. The direction in which the extended portion 41 of the gate trench section 40 or the extended portion 31 of the dummy trench section 30 extends longer in the extension direction is defined as the longitudinal direction of the trench section. The longitudinal direction of the gate trench section 40 or the dummy trench section 30 may coincide with the extension direction. In this example, the extension direction and longitudinal direction are the Y-axis direction. The direction in which multiple gate trench sections 40 or dummy trench sections 30 are arranged is defined as the short-axis direction of the trench section. The short-axis direction may coincide with the arrangement direction. The short-axis direction may also be perpendicular to the longitudinal direction. In this example, the longitudinal direction and the short-axis direction are perpendicular. In this example, the arrangement direction and the short-axis direction are the X-axis direction.

[0070] At the connection portion 33 at the tip of the gate trench portion 40, the gate conductive portion within the gate trench portion 40 is connected to the connection portion 25. The gate trench portion 40 may be provided so as to protrude toward the connection portion 25 side from the dummy trench portion 30 in the extension direction (Y-axis direction). This protruding portion of the gate trench portion 40 is connected to the connection portion 25.

[0071] The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located in the well region 17 when viewed from above. In other words, at the Y-axis end of each trench portion, the bottom in the depth direction of each trench portion is covered by the well region 17. This makes it possible to mitigate electric field concentration at the bottom of each trench portion.

[0072] In the arrangement direction, mesa portions are provided between each trench portion. A mesa portion refers to the region sandwiched between the trench portions within the semiconductor substrate 10. For example, the upper end of a mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of a mesa portion is the same as the depth position of the lower end of a trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench portion in the stretching direction (Y-axis direction).

[0073] The boundary region 90 is provided adjacent to the diode region 80 in the transistor region 70. The boundary region 90 is a mesa region on the front side of the semiconductor substrate 10 where the emitter region 12 of the first conductivity type is not provided, and the collector region 22 is provided on the back side of the semiconductor substrate 10. The boundary region 90 may have a base region 14 on the front surface 21. In Figure 2A, the position of the cathode region 82 provided on the back side of the semiconductor substrate 10 is shown when projected onto the front side. A dummy trench region 30 is provided in the boundary region 90.

[0074] Mesa portions 71, 81, and 91 are mesa portions provided in the transistor portion 70, the diode portion 80, and the boundary region 90, respectively. In this specification, when simply referred to as a mesa portion, it refers to mesa portions 71, 81, and 91, respectively. A mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be the portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. The extended portion of each trench portion may be considered as a single trench portion. That is, the region sandwiched between two extended portions may be considered as a mesa portion.

[0075] The mesa portion 71 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 71 in contact with the gate trench portion 40 may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0076] Each of the contact region 15 and emitter region 12 in the mesa portion 71 extends from one trench portion to the other in the X-axis direction. As an example, the contact region 15 and emitter region 12 of the mesa portion 71 are arranged alternately along the extension direction (Y-axis direction) of the trench portion.

[0077] In other examples, the contact region 15 and emitter region 12 of the mesa portion 71 may be arranged in a stripe pattern along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 may be provided in the region in contact with the trench portion, and the contact region 15 may be provided in the region sandwiched between the emitter regions 12.

[0078] The mesa portion 81 of the diode portion 80 does not have an emitter region 12. A base region 14 may be provided on the upper surface of the mesa portion 81.

[0079] A contact hole 54 is provided above each mesa portion. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in the regions corresponding to the base region 14 and the well region 17. The contact holes 54 may be located in the center in the alignment direction (X-axis direction) of the mesa portions 71.

[0080] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. The doping concentration of the cathode region 82 is higher than that of the drift region 18, which will be described later. In the region on the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. In Figure 2A, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0081] The cathode region 82 is positioned away from the well region 17 in the Y-axis direction. This ensures a distance between the cathode region 82 and the P-type region (well region 17), which has a relatively high doping concentration and is formed to a deep position, thereby improving pressure resistance and suppressing the injection of holes from the well region 17. In this example, the end of the cathode region 82 in the Y-axis direction is positioned further from the well region 17 than the end of the contact hole 54 in the Y-axis direction. In other examples, the end of the cathode region 82 in the Y-axis direction may be positioned between the well region 17 and the contact hole 54.

[0082] Figure 2B shows an example of the c-c' cross-section in Figure 2A. The c-c' cross-section is the XZ plane passing through the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the c-c' cross-section. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0083] The drift region 18 is a region of a first conductivity type provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0084] The buffer region 20 is a first conductivity type region located below the drift region 18. In this example, the buffer region 20 is located closer to the back surface 23 of the semiconductor substrate 10 than to the center of the semiconductor substrate 10 in the depth direction. In this example, the buffer region 20 is N-type as an example. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0085] The collector region 22 and the cathode region 82 are provided on the back surface 23 of the semiconductor substrate 10. The collector region 22 is provided below the buffer region 20 in the transistor section 70. The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 may be the boundary between the transistor section 70 and the diode section 80.

[0086] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal. At least a portion of the collector electrode 24 may be made of a metal such as aluminum (Al), or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu).

[0087] The base region 14 is a second conductive region located above the drift region 18 in the mesa portions 71, 91, and 81. The base region 14 is located in contact with the gate trench portion 40. The base region 14 may be located in contact with the dummy trench portion 30.

[0088] The emitter region 12 is provided in the mesa portion 71 between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. The emitter region 12 does not need to be provided in the mesa portion 91.

[0089] The contact area 15 is provided above the base area 14 in the mesa portion 91. The contact area 15 is provided in contact with the gate trench portion 40 in the mesa portion 91. In other cross-sections, the contact area 15 may be provided on the front surface 21 of the mesa portion 71.

[0090] The storage region 16 is a first conductivity type region located on the front surface 21 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the storage region 16 is N+ type. The storage region 16 is provided in the mesa portion 71. The storage region 16 may also be provided in the mesa portions 81 and 91.

[0091] Furthermore, the storage region 16 is provided in contact with the gate trench portion 40. The storage region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the storage region 16 is higher than the doping concentration of the drift region 18. By providing the storage region 16, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0092] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and storage region 16 is provided, each trench penetrates these regions as well and reaches the drift region 18. The statement that a trench penetrates a doping region is not limited to those manufactured in the order of forming the doping region before forming the trenches. Even when doping regions are formed between trenches after the trenches have been formed, the trenches are still considered to penetrate the doping region.

[0093] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, on the inside of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38.

[0094] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces an adjacent base region 14 on the mesa portion 71 side, with the gate insulating film 42 in between. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is created on the surface layer of the interface in contact with the gate trench within the base region 14.

[0095] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 by an interlayer insulating film 38.

[0096] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Contact holes 55 and 56 may also be provided through the interlayer insulating film 38.

[0097] The lifetime control unit 150 is provided on the semiconductor substrate 10 and includes a lifetime killer. The lifetime control unit 150 may be a region in the semiconductor substrate 10 where a lifetime killer is intentionally formed by injecting impurities into the interior of the semiconductor substrate 10. In one example, the lifetime control unit 150 is formed by injecting helium into the semiconductor substrate 10. By providing the lifetime control unit 150, the turn-off time can be reduced and the tail current can be suppressed, thereby reducing losses during switching.

[0098] A lifetime killer is a carrier recombination center. A lifetime killer may be a lattice defect. For example, a lifetime killer may be a vacancy, a double vacancy, a composite defect between these and the elements constituting the semiconductor substrate 10, or a dislocation. Alternatively, a lifetime killer may be a noble gas element such as helium or neon, or a metallic element such as platinum. A lifetime killer may also be a recombination center formed on the implantation side of the semiconductor substrate 10 after hydrogen ions have been implanted into the implantation surface, beyond the stationary hydrogen. An electron beam may be used to form the lattice defect. The dose of impurities for forming the lifetime control unit 150 is 0.5E10cm². －２ Above, 1.0E13cm －２ Even if the following applies, 5.0E10cm －２ The above is 5.0E11cm －２ The following is also possible: The acceleration energy for forming the lifetime control unit 150 may be 100 keV or more and 100 MeV or less.

[0099] The lifetime killer concentration is the concentration of carrier recombination centers. The lifetime killer concentration may also be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and double vacancies, the concentration of composite defects between these vacancies and the elements constituting the semiconductor substrate 10, or the concentration of dislocations. Furthermore, the lifetime killer concentration may also be the chemical concentration of noble gas elements such as helium and neon, or the chemical concentration of metallic elements such as platinum.

[0100] The lifetime control unit 150 includes at least one of the front-side lifetime control region 151 or the back-side lifetime control region 152. The front-side lifetime control region 151 is provided closer to the front surface 21 than to the center in the depth direction of the semiconductor substrate 10. The back-side lifetime control region 152 is provided closer to the back surface 23 than to the center in the depth direction of the semiconductor substrate 10. In this example, the back-side lifetime control region 152 is provided in the buffer region 20.

[0101] The lifetime control unit 150 may be formed by injecting impurity ions for forming a lifetime killer from the back surface 23 side. The impurity ions for forming a lifetime killer are sometimes simply referred to as impurity ions. The impurity ions are, for example, helium ions. This makes it possible to avoid affecting the front surface 21 side of the semiconductor device 100. For example, the lifetime control unit 150 is formed by injecting helium ions from the back surface 23 side. Here, whether the lifetime control unit 150 is formed by injection from the front surface 21 side or from the back surface 23 side can be determined by obtaining the state of the front surface 21 side by the SR method or by measuring the leakage current.

[0102] The methods for forming the front-side lifetime control region 151 and the back-side lifetime control region 152 may be the same or different. Both the front-side lifetime control region 151 and the back-side lifetime control region 152 may be formed by implanting impurity ions from the back surface 23. The front-side lifetime control region 151 may be formed by implanting impurity ions from the front surface 21, and the back-side lifetime control region 152 may be formed by implanting impurity ions from the back surface 23. Both the front-side lifetime control region 151 and the back-side lifetime control region 152 may be formed by implanting impurity ions from the front surface 21. The dose of impurity ions used when forming the front-side lifetime control region 151 and the back-side lifetime control region 152 may be the same or different.

[0103] Figure 3 shows an example of the a-a' cross-section in Figure 1. The a-a' cross-section is the YZ plane passing through the gate pad 112 and the edge termination structure 170. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, a gate pad 112, a gate metal layer 50, an electrode layer 174, a collector electrode 24, and a protective film 180 in the a-a' cross-section. The gate pad 112, the gate metal layer 50, and the electrode layer 174 are formed above the semiconductor substrate 10 and the interlayer insulating film 38. The protective film 180 is formed above the semiconductor substrate 10, the interlayer insulating film 38, the gate pad 112, the gate metal layer 50, and the electrode layer 174.

[0104] The edge termination structure 170 in this example has a guard ring structure and a channel stopper structure. The guard ring structure may include a plurality of guard ring sections 172. The guard ring structure in this example includes five guard ring sections 172. Each guard ring section 172 may be provided on the front surface 21 so as to surround the active section 160. The number of guard ring sections 172 is not limited to this example.

[0105] The guard ring structure may have the function of spreading the depletion layer generated in the active section 160 to the outside of the semiconductor substrate 10. This prevents electric field concentration inside the semiconductor substrate 10. Therefore, the breakdown voltage of the semiconductor device 100 can be improved compared to when the guard ring structure is not provided.

[0106] The guard ring portion 172 is a P+ type semiconductor region formed near the front surface 21 by ion implantation. The guard ring portion 172 is electrically connected to the electrode layer 174. The electrode layer 174 may be made of the same material as the gate metal layer 50 or the gate pad 112.

[0107] Multiple guard ring portions 172 are electrically insulated from each other by an interlayer insulating film 38. The depth of the bottom of the guard ring portion 172 may be the same as the depth of the bottom of the well region 17. The depth of the bottom of the guard ring portion 172 may be deeper than the depth of the bottom of the gate trench portion 40 and the dummy trench portion 30.

[0108] The channel stopper structure includes a channel stopper region 176 and an electrode layer 174. The channel stopper region 176 is electrically connected to the electrode layer 174 through an opening in the interlayer insulating film 38. The conductivity type of the channel stopper region 176 may be a first conductivity type or a second conductivity type. In this example, the conductivity type of the channel stopper region 176 is N+ type. The channel stopper region 176 has the function of terminating the depletion layer generated in the active portion 160 at the outer edge of the semiconductor substrate 10.

[0109] The well region 17 may be provided such that the distance between the innermost guard ring portion 172 in the edge termination structure 170 and the outer end of the well region 17 is close. An oxide film 39 may be provided above the well region 17 and between the connection portion 25. The oxide film 39 may be formed in the same process as the dummy insulating film 32 or the gate insulating film 42. Alternatively, the oxide film 39 may be formed in a process such as forming a field oxide film with a thicker film thickness.

[0110] The protective film 180 has a first end 182 and a second end 184. The first end 182 has a first taper angle θ1. The taper angle is the angle that the end of the protective film 180 makes with respect to the direction parallel to the front surface 21 of the semiconductor substrate 10. The second end 184 has a second taper angle θ2 that is different from the first taper angle θ1. The first end 182 and the second end 184 may be formed by different processes. However, if the taper angles of each end can be made different, the first end 182 and the second end 184 may be formed by the same process.

[0111] The first end 182 may be the end of the protective film 180 closest to the edge 102 of the semiconductor substrate 10. The second end 184 may be the end of the protective film 180 above the front-side metal layer (in this example, the gate pad 112). For example, the second end 184 is the end of the protective film 180 above the first front-side metal (in this example, the gate pad 112).

[0112] The first taper angle θ1 may be greater than the second taper angle θ2. The first taper angle θ1 may be between 40 degrees and 45 degrees. In this example, the first taper angle θ1 is 45 degrees. The second taper angle θ2 may be between 25 degrees and 30 degrees. In this example, the second taper angle θ2 is 30 degrees.

[0113] When the first and second ends of the protective film are formed by the same process, the first taper angle and the second taper angle may be approximately equal.

[0114] At the first end closest to the edge of the semiconductor substrate, a larger first taper angle may be preferable to widen the dicing line. In this case, if the second end above the metal layer on the front side is formed by the same process and the second taper angle is also large, the wire bonding tool and the protective film may come into contact during the wire bonding process above the metal layer on the front side, potentially leading to problems such as poor wire neck breakage, poor appearance, and / or reduced reliability due to cracks in the protective film.

[0115] Therefore, at the second end above the metal layer on the front side, a smaller second taper angle may be preferable. In this case, if the first end closest to the edge of the semiconductor substrate is formed by the same process and the first taper angle is also small, the dicing line becomes narrower, which can lead to clogging of the dicing blade and a decrease in dicing quality. Alternatively, if the scribe width between adjacent semiconductor devices before dicing is increased to widen the dicing line, the number of devices per wafer decreases, which can increase costs.

[0116] In the semiconductor device 100 of this example, the protective film 180 has a first end 182 having a first taper angle θ1 and a second end 184 having a second taper angle θ2 different from the first taper angle θ1. This allows for a wider dicing line while preventing contact between the wire bonding tool and the protective film 180. Therefore, it is possible to improve the quality of dicing and / or reduce costs by increasing the number of devices per wafer, while preventing wire neck breakage defects, appearance defects, and reliability degradation due to cracks in the protective film 180. Details of the effects of the semiconductor device 100 will be described later.

[0117] The thickness T of the protective film 180 may be 2 μm or more and 30 μm or less, or 3 μm or more and 30 μm or less. The thickness T of the protective film 180 may be the thickness from the front surface 21 of the semiconductor substrate 10.

[0118] Figure 4A shows an example of the wire bonding process. In this figure, the internal structure near the front surface 21 of the semiconductor substrate 10 is omitted.

[0119] In the semiconductor device 100 of this example, the second end portion 184 has a second taper angle θ2, which is 25 degrees or more and 30 degrees or less. This prevents contact between the wire bonding tool and the protective film 180 during the wire bonding process in which the wire 188 is bonded to the gate pad 112. Therefore, defects such as wire neck breakage, appearance defects, and reduced reliability due to cracks in the protective film 180 can be prevented.

[0120] Figure 4B shows an example of a wire bonding process according to a comparative example. In this figure, the internal structure near the front surface 21 of the semiconductor substrate 10 is omitted.

[0121] In the semiconductor device according to the comparative example, the second end 184 has a second taper angle θ2' that is approximately equal to the taper angle of the first end 182, for example, the second taper angle θ2' is 40 degrees or more. Therefore, in the wire bonding process in which the wire 188 is bonded to the gate pad 112, the wire bonding tool and the protective film 180 may come into contact. Consequently, problems such as wire neck breakage defects, appearance defects, and / or reduced reliability due to cracks in the protective film 180 may occur.

[0122] Figure 5A shows an example of the region near the dicing line of the semiconductor device 100 before dicing. In this figure, the internal structure near the front surface 21 of the semiconductor substrate 10 is omitted. For example, the area to the left of the dicing line becomes semiconductor device 100-1 after dicing, and the area to the right of the dicing line becomes semiconductor device 100-2 after dicing.

[0123] In the semiconductor device 100 of this example, the first end portion 182 has a first taper angle θ1, which is 40 degrees or more and 45 degrees or less. This allows for a wider dicing line. Therefore, the quality of dicing can be improved and / or the number of devices per wafer can be increased to reduce costs.

[0124] Figure 5B shows an example of the region near the dicing line of semiconductor device 500 before dicing, according to a comparative example. In this figure, the internal structure near the front surface 21 of the semiconductor substrate 10 is omitted. For example, the area to the left of the dicing line becomes semiconductor device 500-1 after dicing, and the area to the right of the dicing line becomes semiconductor device 500-2 after dicing.

[0125] In the semiconductor device 500 of the comparative example, the first end 182 has a first taper angle θ1' that is approximately equal to the taper angle of the second end 184, for example, the first taper angle θ1' is 30 degrees or less. As a result, the dicing line becomes narrower, which can lead to clogging of the dicing blade and a decrease in dicing quality. Alternatively, if the scribe width between adjacent semiconductor devices 500-1 and 500-2 before dicing is increased to widen the dicing line, the number of devices per wafer decreases, which can increase costs.

[0126] Figure 6A shows an example of a b-b' cross-section in Figure 1. The b-b' cross-section is the XZ plane passing through the active portion 160 and the edge termination structure portion 170. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a plating layer 53, a gate metal layer 50, an electrode layer 174, a collector electrode 24, and a protective film 180 in the b-b' cross-section. The emitter electrode 52, the gate metal layer 50, and the electrode layer 174 are formed above the semiconductor substrate 10 and the interlayer insulating film 38. The protective film 180 is formed above the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, the gate metal layer 50, and the electrode layer 174. The plating layer 53 is formed above the emitter electrode 52. Note that the plating layer 53 may be omitted.

[0127] The plating layer 53 is formed from a material such as gold, copper, or nickel alloy, and is formed as a single layer or in layers. Wiring such as a lead frame may be soldered to the upper surface of the plating layer 53.

[0128] The protective film 180 has a first end 182 and a third end 186. The protective film 180 has a second end 184 in a cross section different from the b-b' cross section (for example, an a-a' cross section). The third end 186 may be formed in the same process as the first end 182, or in a different process. The third end 186 may be formed in the same process as the second end 184, or in a different process. In this example, the third end 186 is formed in a different process than the first end 182, and in the same process as the second end 184.

[0129] The third end 186 may be the end of the protective film 180 above the front-side metal layer (in this example, the emitter electrode 52). For example, the third end 186 is the end of the protective film 180 above the second front-side metal (in this example, the emitter electrode 52). The third end 186 may have a third taper angle θ3. In this example, the third taper angle θ3 is equal to the second taper angle θ2.

[0130] When a plating layer 53 is provided, a triple point exists between the second surface metal (for example, the emitter electrode 52), the plating layer 53, and the protective film 180. In this case, peeling may occur starting from the triple point due to stress during assembly, etc. A smaller taper angle at the triple point increases the resistance to peeling. Therefore, in the semiconductor device 100 of this example, since the third taper angle θ3 is equal to the second taper angle θ2, the resistance to peeling during assembly can be improved.

[0131] Figure 6B shows an example of the b-b' cross-section in Figure 1. The semiconductor device 100 in this example differs from the embodiment in Figure 6A in that the size of the third taper angle θ3 is different.

[0132] In this example, the third end portion 186 is formed using the same process as the first end portion 182, but using a different process than the second end portion 184. Therefore, the third taper angle may be equal to the first taper angle θ1.

[0133] When picking up multiple semiconductor devices 100 after dicing them from a wafer, the devices may be picked up from the second front-side metal (for example, the emitter electrode 52), which has a relatively large surface area. In the semiconductor device 100 of this example, the third taper angle θ3 is equal to the first taper angle θ1, so the adsorption area of ​​the second front-side metal is widened, and it is possible to prevent damage to the protective film 180 during the adsorption process.

[0134] As explained in relation to Figures 6A and 6B, the third taper angle θ3 may be equal to the first taper angle θ1 or equal to the second taper angle θ2. That is, the third end 186 may be formed in the same process as the first end 182 or in the same process as the second end 184. For example, the third end 186 is the end of the protective film 180 above the second front-side metal (in this example, the emitter electrode 52) which has a larger area than the first front-side metal (in this example, the gate pad 112), and the setting of which end's taper angle the third taper angle θ3 is equal to may be changed according to the design of the semiconductor device 100.

[0135] Furthermore, if the second front metal surface has a roughly rectangular shape, the third taper angle θ3 may be different at the third end 186 on the longer side and the third end 186 on the shorter side. For example, the third taper angle θ3 on the longer side may be equal to the first taper angle θ1, and the third taper angle θ3 on the shorter side may be equal to the second taper angle θ2, or the third taper angle θ3 on the longer side may be equal to the second taper angle θ2, and the third taper angle θ3 on the shorter side may be equal to the first taper angle θ1.

[0136] Figure 7 is a flowchart showing an example of the manufacturing process for a semiconductor device 100. The manufacturing process in this example is an example of a method for manufacturing the front-side metal layer and the protective film 180. In other words, the manufacturing process for the semiconductor device 100 may include other steps not shown in the flowchart of this example, such as a step for forming the internal structure near the front surface 21 of the semiconductor substrate 10.

[0137] In step S100, a front-side metal layer is provided above the semiconductor substrate 10. Step S100 may include the step of providing a first front-side metal (e.g., a gate pad 112), and may include the step of providing a second front-side metal (e.g., an emitter electrode 52). Step S100 may also include the step of providing another metal layer, such as the gate metal layer 50 or an electrode layer 174, which does not have an edge for the protective film 180.

[0138] In step S110, a protective film 180 is provided above the semiconductor substrate 10, with the first end 182 and the second end 184 having different taper angles. For example, the first end 182 has a first taper angle θ1, and the second end 184 has a second taper angle θ2 that is different from the first taper angle θ1.

[0139] Figure 8A is a flowchart showing an example of step S110 in which a protective film 180 is provided. The manufacturing method in this example is an example of a manufacturing method when the material of the protective film 180 is a photosensitive material. The protective film 180 may be a photosensitive polyimide film or a photosensitive polybenzoxazole film.

[0140] Step S110 of providing the protective film 180 may include Step S112 of providing a first end 182 having a first taper angle θ1 to the protective film 180, and Step S114 of providing a second end 184 having a second taper angle θ2 different from the first taper angle θ1 to the protective film 180. The first end 182 may be the end of the protective film 180 closest to the dicing line of the semiconductor substrate 10. The second end 184 may be the end of the protective film 180 above the metal layer on the front side. The first taper angle θ1 may be larger than the second taper angle θ2. Step S112 of providing the first end 182 and Step S114 of providing the second end 184 may be different processes.

[0141] Step S112, which provides the first end portion 182, may include step S1120, which involves exposing the protective film 180 above the dicing line of the semiconductor substrate 10. In step S1120, the portion where the first end portion 182 is to be provided may be exposed. Step S112, which provides the first end portion 182, may include step S1122, which involves developing the protective film 180. Step S1122 forms the first end portion 182 closest to the dicing line.

[0142] Step S114, which provides the second end portion 184, may include step S1140, which involves exposing the protective film 180 above the front metal layer. In step S1140, the portion to which the second end portion 184 is provided may be exposed. Step S114, which provides the second end portion 184, may include step S1142, which involves developing the protective film 180. Step S1142 forms the second end portion 184 above the front metal layer.

[0143] Step S114, which involves providing the second end 184, may be performed after step S112, which involves providing the first end 182. Further details of steps S112 and S114 will be described later.

[0144] Figure 8B is a flowchart showing an example of step S110 for providing the protective film 180. The manufacturing method in this example is an example of a manufacturing method when the material of the protective film 180 is a photosensitive material. The manufacturing method in this example differs from the example in Figure 8A in that the step of providing the second end 184 is performed before step S112 for providing the first end 182. Otherwise, it may be the same as the example in Figure 8A. That is, in the manufacturing method when the material of the protective film 180 is a photosensitive material, the order of steps S112 and S114 does not matter. Further details of steps S112 and S114 will be described later.

[0145] Figure 9 shows an example of the manufacturing process for the semiconductor device 100. The manufacturing process in this example is, for example, an example of a manufacturing process based on the flowchart in Figure 8A. However, as explained in relation to Figures 8A and 8B, the order of step S112, which provides the first end 182, and step S114, which provides the second end 184, is not important.

[0146] In step S1120, the protective film 180 above the dicing line of the semiconductor substrate 10 is exposed. For example, in step S1120, exposure is performed with focus at a first focus position 1820. The distance from the first focus position 1820 to the semiconductor substrate 10 is the first distance L1.

[0147] In step S1122, the protective film 180 is developed. Step S1122 forms the first end portion 182 closest to the dicing line.

[0148] In step S1140, the protective film 180 above the front metal layer is exposed. In this example, the front metal layer is the gate pad 112. For example, in step S1140, exposure is performed with focus at the second focus position 1840. The distance from the second focus position 1840 to the front metal layer is the second distance L2.

[0149] In step S1142, the protective film 180 is developed. Step S1142 forms the second end portion 184 above the metal layer on the front side.

[0150] The first distance L1 may be smaller than the second distance L2. For example, the first distance is between 1% and 45% of the second distance L2. If the material of the protective film 180 is a photosensitive material, the taper angle after development changes depending on the focus position during exposure. For example, the further the focus position is from the bottom surface of the protective film 180, the smaller the taper angle becomes. By making the first distance L1 smaller than the second distance L2, the first taper angle θ1 can be made larger than the second taper angle θ2.

[0151] In this example, an example in which the second end portion 184 is provided above the first front-side metal (gate pad 112 in this example) has been described, but the third end portion 186 above the second front-side metal (for example, emitter electrode 52) may be provided by a similar process. For example, if the third taper angle θ3 is equal to the second taper angle θ2, the process of providing the third end portion 186 can be carried out in the same process as the process of providing the second end portion 184. As another example, if the third taper angle is equal to the first taper angle θ1, the process of providing the third end portion 186 can be carried out in the same process as the process of providing the first end portion 182. That is, the third end portion 186 may be formed by exposure and development to a focus position corresponding to the focus position in the process of providing the end portion with equal taper angles.

[0152] Figure 10 is a flowchart showing an example of step S110 for providing the protective film 180. The manufacturing method in this example is an example of a manufacturing method when the material of the protective film 180 is a non-photosensitive material. The protective film 180 may be a non-photosensitive polyimide film or a non-photosensitive polybenzoxazole film.

[0153] Step S110 of providing the protective film 180 may include Step S112 of providing a first end 182 having a first taper angle θ1 to the protective film 180, and Step S114 of providing a second end 184 having a second taper angle θ2 different from the first taper angle θ1 to the protective film 180. The first end 182 may be the end of the protective film 180 closest to the dicing line of the semiconductor substrate 10. The second end 184 may be the end of the protective film 180 above the metal layer on the front side. The first taper angle θ1 may be larger than the second taper angle θ2. Step S112 of providing the first end 182 and Step S114 of providing the second end 184 may be different processes.

[0154] Step S112, which provides the first end 182, may include step S1124, which provides a resist above the non-photosensitive material. The resist is, for example, a photosensitive resist. Step S112, which provides the first end 182, may include step S1126, which bakes the non-photosensitive material and the resist. Step S112, which provides the first end 182, may include step S1128, which exposes the resist above the dicing line of the semiconductor substrate 10. In step S1128, the portion to which the first end 182 is to be provided may be exposed. Step S112, which provides the first end 182, may include step S1130, which develops the resist. Step S112, which provides the first end 182, may include step S1132, which etches the non-photosensitive material above the dicing line. Step S1132 forms the first end 182 closest to the dicing line.

[0155] Step S114 for providing the second end 184 may include step S1144 for providing a resist above the non-photosensitive material. The resist is, for example, a photosensitive resist. Step S114 for providing the second end 184 may include step S1146 for baking the non-photosensitive material and the resist. Step S114 for providing the second end 184 may include step S1148 for exposing the resist above the front metal layer. In step S1148, the portion for providing the second end 184 may be exposed. Step S114 for providing the second end 184 may include step S1150 for developing the resist. Step S114 for providing the second end 184 may include step S1152 for etching the non-photosensitive material above the front metal layer. Step S1152 forms the second end 184 above the front metal layer.

[0156] Step S114, which provides the second end 184, may be performed after step S112, which provides the first end 182. When the material of the protective film 180 is a non-photosensitive material, the order of steps S112 and S114 as in this example is preferred because the taper angle of each end depends on the thermal history. Further details of steps S112 and S114 will be described later.

[0157] Figure 11 shows an example of the manufacturing process for the semiconductor device 100. The manufacturing process in this example is, for example, an example of a manufacturing process based on the flowchart in Figure 10.

[0158] In step S1124, a resist 190 is provided above the non-photosensitive material that will become the protective film 180. For example, the thickness T1 of the resist 190 in step S112, when the first end portion 182 is provided, is 2 μm or more and 3.5 μm or less. In step S1126, the non-photosensitive material and the resist 190 are baked. In step S1128, the resist 190 above the dicing line of the semiconductor substrate 10 is exposed.

[0159] In step S1130, the resist 190 is developed. In step S1132, the non-photosensitive material above the dicing line is etched. Step S1132 forms the first end 182 closest to the dicing line.

[0160] In step S1144, a resist 190 is provided above the non-photosensitive material that will become the protective film 180. For example, the thickness T2 of the resist 190 in step S114, where the second end portion 184 is provided, is 3 μm or more and 4.5 μm or less. The thickness T2 of the resist 190 in step S114, where the second end portion 184 is provided, may be thicker than the thickness T1 of the resist 190 in step S112, where the first end portion 182 is provided.

[0161] In step S114, where the second end portion 184 is provided, the second taper angle θ2 is small, so when etching the non-photosensitive material, the non-photosensitive material below the resist 190 may be etched, and the portion of the resist 190 that forms an overhang shape may become longer. By making the thickness T2 of the resist 190 in step S114, where the second end portion 184 is provided, 3 μm or more, it is possible to prevent the resist 190 from breaking when etching the non-photosensitive material.

[0162] If the step S114 for providing the second end 184 is performed after the step S112 for providing the first end 182, the resist 190 in the step S114 for providing the second end 184 may also be provided above the first end 182.

[0163] In step S1146, the non-photosensitive material and the resist 190 are baked. In step S1148, the resist 190 above the front metal layer is exposed. In this example, the front metal layer is the gate pad 112.

[0164] In step S1150, the resist 190 is developed. In step S1152, the non-photosensitive material above the front metal layer (gate pad 112 in this example) is etched. Step S1152 forms the second end portion 184 above the front metal layer.

[0165] If the material of the protective film 180 is a non-photosensitive material, the taper angle after etching changes depending on the thermal history during etching. For example, the greater the thermal history, the smaller the taper angle. By performing the step S114 of providing the second end 184 after the step S112 of providing the first end 182, the thermal history in the step S114 of providing the second end 184 can be made greater than the thermal history in the step S112 of providing the first end 182, and the first taper angle θ1 can be made greater than the second taper angle θ2.

[0166] For example, the bake temperature and bake time in step S1126, which is the baking step in step S112 for providing the first end portion 182, may be set to an appropriate temperature and time that provides a thermal history necessary to achieve the first taper angle θ1. Similarly, the bake temperature and bake time in step S1146, which is the baking step in step S114 for providing the second end portion 184, may be set to an appropriate temperature and time that provides a thermal history necessary to achieve the second taper angle θ2.

[0167] The bake temperature in step S1146, which is the baking step in step S114 for providing the second end portion 184, may be higher than the bake temperature in step S1126, which is the baking step in step S112 for providing the first end portion 182. The bake time in step S1146, which is the baking step in step S114 for providing the second end portion 184, may be longer than the bake time in step S1126, which is the baking step in step S112 for providing the first end portion 182. In addition, a separate bake step may be provided after step S112 for providing the first end portion 182 and before step S114 for providing the second end portion 184.

[0168] In this example, we have described an example in which the second end portion 184 is provided above the first front-side metal (gate pad 112 in this example), but the third end portion 186 above the second front-side metal (for example, emitter electrode 52) may be provided by a similar process. For example, if the third taper angle θ3 is equal to the second taper angle θ2, the process of providing the third end portion 186 can be carried out in the same process as the process of providing the second end portion 184. As another example, if the third taper angle is equal to the first taper angle θ1, the process of providing the third end portion 186 can be carried out in the same process as the process of providing the first end portion 182. That is, the third end portion 186 may be formed at a timing that has a thermal history corresponding to the process of providing an end portion that makes the taper angles equal.

[0169] Although the invention has been described using embodiments, the technical scope of the present invention is not limited to the scope described in the embodiments above. It will be apparent to those skilled in the art that various modifications or improvements can be made to the embodiments described above. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0170] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform them in that order.

[0171] 10... Semiconductor substrate, 12... Emitter region, 14... Base region, 15... Contact region, 16... Storage region, 17... Well region, 18... Drift region, 20... Buffer region, 21... Front surface, 22... Collector region, 23... Back surface, 24... Collector electrode, 25... Connection portion, 30... Dummy trench portion, 31... Stretched portion, 32... Dummy insulating film, 33... Connection portion, 34... Dummy conductive portion, 38... Interlayer insulating film, 39... Oxide film, 40... Gate trench portion, 41... Stretched portion, 42... Gate insulating film, 43... Connection portion, 44... Gate conductive portion, 50... Gate metal layer, 52... Emitter electrode, 53... Plating layer, 54... Contact hole, 55... Contact hole, 56... Tact hole, 70... Transistor section, 71... Mesa section, 80... Diode section, 81... Mesa section, 82... Cathode region, 90... Boundary region, 91... Mesa section, 100... Semiconductor device, 102... Edge, 112... Gate pad, 130... Gate wiring, 150... Lifetime control section, 151... Front side lifetime control region, 152... Back side lifetime control region, 160... Active section, 170... Edge termination structure section, 172... Guard ring section, 174... Electrode layer, 176... Channel stopper region, 180... Protective film, 182... First end, 184... Second end, 186... Third end, 188... Wire, 190... Resist, 1820... First focus position, 1840... Second focus position

Claims

1. A semiconductor device comprising: a semiconductor substrate; a front-side metal layer provided above the semiconductor substrate; and a protective film provided above the semiconductor substrate, wherein the protective film has a first end having a first taper angle and a second end having a second taper angle different from the first taper angle.

2. The semiconductor device according to claim 1, wherein the first end is the end of the protective film closest to the edge of the semiconductor substrate, and the second end is the end of the protective film above the front-side metal layer.

3. The semiconductor device according to claim 2, wherein the first taper angle is greater than the second taper angle.

4. The semiconductor device according to claim 2, wherein the first taper angle is 40 degrees or more and 45 degrees or less.

5. The semiconductor device according to claim 2, wherein the second taper angle is 25 degrees or more and 30 degrees or less.

6. The semiconductor device according to claim 1, wherein the front-side metal layer has a plurality of front-side metals, including a first front-side metal and a second front-side metal having a larger area than the first front-side metal, the first end is the end of the protective film closest to the edge of the semiconductor substrate, and the second end is the end of the protective film above the first front-side metal.

7. The semiconductor device according to claim 6, wherein the protective film has a third end having a third taper angle above the second front metal, and the third taper angle is equal to the second taper angle.

8. The semiconductor device according to claim 6, wherein the protective film has a third end having a third taper angle above the second front metal, and the third taper angle is equal to the first taper angle.

9. The semiconductor device according to any one of claims 1 to 8, wherein the protective film is an organic film.

10. The semiconductor device according to claim 9, wherein the protective film is a polyimide film or a polybenzoxazole film.

11. The semiconductor device according to any one of claims 1 to 8, wherein the thickness of the protective film is 2 μm or more and 30 μm or less.

12. A method for manufacturing a semiconductor device, comprising the steps of: providing a front-side metal layer above a semiconductor substrate; and providing a protective film above the semiconductor substrate having a first end and a second end with different taper angles.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the step of providing the protective film comprises: providing the protective film with the first end having a first taper angle; and providing the protective film with the second end having a second taper angle different from the first taper angle.

14. The method for manufacturing a semiconductor device according to claim 13, wherein the first end is the end of the protective film closest to the dicing line of the semiconductor substrate, and the second end is the end of the protective film above the front-side metal layer.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the first taper angle is greater than the second taper angle.

16. The method for manufacturing a semiconductor device according to claim 13, wherein the step of providing the first end and the step of providing the second end are different steps.

17. The method for manufacturing a semiconductor device according to any one of claims 13 to 16, wherein the material of the protective film is a photosensitive material, the step of providing the first end comprises the step of exposing the protective film above the dicing line of the semiconductor substrate, and the step of providing the second end comprises the step of exposing the protective film above the surface metal layer.

18. The method for manufacturing a semiconductor device according to claim 17, wherein the first distance from the first focus position to the semiconductor substrate in the step of exposing the protective film above the dicing line is smaller than the second distance from the second focus position to the front side metal layer in the step of exposing the protective film above the front side metal layer.

19. The method for manufacturing a semiconductor device according to claim 18, wherein the first distance is 1% or more and 45% or less of the second distance.

20. The method for manufacturing a semiconductor device according to claim 17, wherein the step of providing the second end is performed after the step of providing the first end.

21. The method for manufacturing a semiconductor device according to claim 17, wherein the step of providing the second end is performed before the step of providing the first end.

22. The method for manufacturing a semiconductor device according to any one of claims 13 to 16, wherein the material of the protective film is a non-photosensitive material, and the step of providing the first end comprises: providing a resist above the non-photosensitive material; baking the non-photosensitive material and the resist; exposing the resist above the dicing line of the semiconductor substrate; and etching the non-photosensitive material above the dicing line, and the step of providing the second end comprises: providing a resist above the non-photosensitive material; baking the non-photosensitive material and the resist; exposing the resist above the front metal layer; and etching the non-photosensitive material above the front metal layer.

23. The method for manufacturing a semiconductor device according to claim 22, wherein the thickness of the resist in the step of providing the first end is 2 μm or more and 3.5 μm or less, and the thickness of the resist in the step of providing the second end is 3 μm or more and 4.5 μm or less.

24. The method for manufacturing a semiconductor device according to claim 22, wherein the step of providing the second end is performed after the step of providing the first end.

25. The method for manufacturing a semiconductor device according to claim 22, wherein the bake temperature in the baking step of the step of providing the second end is higher than the bake temperature in the baking step of the step of providing the first end.

26. The method for manufacturing a semiconductor device according to claim 22, wherein the baking time in the baking stage of the stage of providing the second end is longer than the baking time in the baking stage of the stage of providing the first end.

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