Solid-state imaging element

Abstract

[Problem] To make it possible to configure a capacitive element without increasing a circuit scale. [Solution] The present invention comprises: a plurality of pixels arranged in columns and having, in a first layer, a charge-voltage conversion unit that converts charges corresponding to the amount of incident light into a voltage, the plurality of pixels being composed of a plurality of pixel groups; a reference signal supply unit formed in a layer different from the first layer, and supplying a prescribed reference signal to the charge-voltage conversion unit; and a comparator formed in a second layer stacked on the first layer, and comparing a prescribed reference voltage and the voltage of a signal line for transmitting an analog pixel signal outputted from a pixel to which the reference signal has been supplied, wherein the signal line is composed of a plurality of first signal lines for each of the plurality of pixel groups.

Description

Solid-state imaging device

[0001] The present disclosure relates to a solid-state imaging device.

[0002] There has been known a solid-state imaging device including a mechanism that switches the capacitance of a charge-voltage converter (FD) that holds signal charges transferred from a photoelectric conversion element by using a capacitive element (see, for example, Patent Document 1).

[0003] WO 2023 / 210203

[0004] However, the capacitive element used for capacitance switching is mainly disposed on a wiring in an insulating layer. For this reason, there is a risk that a dedicated process such as addition of a wiring layer is required, or the circuit scale including the insulating layer increases.

[0005] Therefore, the present disclosure provides a solid-state imaging device capable of forming a capacitive element without increasing the circuit scale.

[0006] In order to solve the above problem, according to the present disclosure, there is provided a solid-state imaging device including: a photoelectric conversion element formed on a semiconductor substrate and generating signal charges by photoelectric conversion; and a capacitive element configured along a first direction from a first surface of the semiconductor substrate toward a second surface opposite to the first surface, the capacitive element holding the signal charges generated by the photoelectric conversion element.

[0007] The capacitive element may include: a first electrode configured along the first direction; a first insulating film surrounding the periphery of the first electrode along the first direction; and a second electrode surrounding the periphery of the first insulating film along the first direction.

[0008] A second insulating film surrounding the periphery of the second electrode along the first direction may be further included.

[0009] A conductor surrounding the periphery of the second insulating film along the first direction is further included, and a negative potential may be applied to the conductor.

[0010] A plurality of the capacitive elements may be configured to be connectable in parallel to a peripheral portion of the photoelectric conversion element.

[0011] The capacitive element may have a columnar shape.

[0012] The plurality of photoelectric conversion elements are formed on the semiconductor substrate in a two-dimensional matrix, and trenches are formed in a two-dimensional grid surrounding the plurality of photoelectric conversion elements in a second direction along the first surface and a third direction perpendicular to the second direction along the first surface, and the capacitive elements may be configured within the trenches.

[0013] Multiple capacitive elements, including the aforementioned intersection region, may be configured to be connected in parallel.

[0014] The capacitive element may be configured in a cross-shaped region including the aforementioned intersection region.

[0015] The width of the trench along the first surface in the intersection region may be wider than that of other regions.

[0016] The second electrode may further include a fixed charge film of a predetermined potential surrounding it along the first direction.

[0017] The first insulating film may also be configured in a direction along the first plane perpendicular to the first direction, and may cover the end of the first electrode on the second plane side.

[0018] The second electrode may also be configured in a direction along the first plane perpendicular to the first direction and cover the first insulating film along the first plane; the second insulating film may also be configured in a direction along the first plane perpendicular to the first direction and cover the second electrode along the first plane; and the conductor may also be configured in a direction along the first plane perpendicular to the first direction and cover the second insulating film along the first plane.

[0019] The first insulating film is also configured in a direction along a first plane perpendicular to the first direction and covers the end of the first electrode on the second plane side, and the second electrode may further include a third insulating film which is configured in a direction along a first plane perpendicular to the first direction and covers the first insulating film along the first plane, and is configured in a direction along a first plane perpendicular to the first direction and covers the second electrode along the first plane.

[0020] In the semiconductor substrate, the plurality of photoelectric conversion elements may be formed in a two-dimensional matrix, and the plurality of capacitive elements may be configured to be connected in parallel within the region of the photoelectric conversion elements.

[0021] The capacitive element is configured to penetrate the semiconductor substrate, and the second electrode may also be configured in a direction along the first plane perpendicular to the first direction.

[0022] The capacitive element may further include a fixed charge film of a predetermined potential that penetrates the semiconductor substrate, is configured in a direction along the first surface perpendicular to the first direction, and covers the first electrode and the end of the first insulating film on the second surface side.

[0023] The semiconductor substrate may further include: a charge-voltage conversion unit formed on the semiconductor substrate and holding the signal charge transferred from the photoelectric conversion element; a capacitance switching transistor connecting the pre-charge-voltage conversion unit and the capacitive element; a reset transistor that discharges the charge from the pre-charge-voltage conversion unit; and an amplification transistor that outputs a signal corresponding to the signal charge of the charge-voltage conversion unit.

[0024] The device may further include at least the capacitance switching transistor and a second semiconductor substrate on which the diffusion layer for the amplification transistor is formed and which is laminated on the second surface side of the semiconductor substrate, and at least the capacitance switching transistor and the gate electrode for the amplification transistor are formed and which is laminated on the surface of the second semiconductor substrate facing the first surface side.

[0025] A diagram showing an example configuration of a solid-state image sensor capable of forming capacitive elements on a semiconductor substrate. A circuit diagram showing an example of the circuit configuration of one pixel provided in the pixel array section. A plan view showing an example of the layout of capacitive elements on a semiconductor substrate. A diagram showing an example of the AA' cross section of Figure 3 and an example of the configuration of an equivalent layer outside the pixel. A diagram showing an example of the manufacturing method of the pixel array section. A plan view showing an example of a capacitive element according to the second embodiment. A plan view showing an example of a different shape of capacitive element a according to the second embodiment. A plan view showing yet another different shape of capacitive element according to the second embodiment. A plan view showing an example of the layout of capacitive elements on a semiconductor substrate according to the third embodiment. A diagram showing an example of the BB' cross section of Figure 9. A diagram showing another example of the AA' cross section of Figure 6. A diagram showing yet another example of the BB' cross section of Figure 9. A diagram showing yet another example of the AA' cross section of Figure 3. A plan view showing an example of the layout of capacitive elements on a semiconductor substrate according to the seventh embodiment. A diagram showing an example of the CC' cross section of Figure 14. A diagram showing yet another example of the AA' cross section of Figure 3. A plan view showing an example of the layout of capacitive elements on a semiconductor substrate according to the ninth embodiment. A diagram showing an example of the configuration of the DD' cross section of Figure 17. A diagram showing another example of the configuration in the DD' cross section of Figure 17. A plan view showing an example of the configuration of a solid-state image sensor according to the 11th embodiment.

[0026] The following description will focus on the main components of the solid-state image sensor, with reference to the drawings. While the description will primarily focus on the main components of the solid-state image sensor, there may be other components and functions not shown or described. The following description does not exclude any components or functions not shown or described.

[0027] (First Embodiment) <Example of Solid-State Image Sensor Configuration> First, an example of a solid-state image sensor configuration to which this technology is applied will be described. Figure 1 is a diagram showing an example of a solid-state image sensor configuration in which capacitive elements can be configured on a semiconductor substrate.

[0028] The solid-state image sensor 11 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. This solid-state image sensor 11 is, for example, a back-illuminated image sensor that receives light from a subject, converts it into photoelectric energy, and generates an image signal to capture an image.

[0029] The photoelectric conversion element of the solid-state image sensor 11 collects light from the subject via, for example, a microlens (on-chip lens). In a back-illuminated image sensor, a wiring layer is formed on the side facing the microlens, on which wiring for transistors and the like that which drive each pixel is provided.

[0030] The solid-state image sensor 11 consists of a pixel array section 21, a vertical drive section 22, a column processing section 23, a horizontal drive section 24, a system control section 25, a pixel drive line 26, a vertical signal line 27, a signal processing section 28, and a data storage section 29.

[0031] In the solid-state image sensor 11, a semiconductor substrate and a pixel array section 21 are formed on the semiconductor substrate (see Figures 3 and 4 described later), and a vertical drive section 22 to a system control section 25 are further integrated on the pixel array section 21.

[0032] The pixel array 21 consists of pixels, each having a photoelectric conversion element that generates and stores an electric charge corresponding to the amount of light incident from the subject. The pixels are arranged in two dimensions in the horizontal (row) and vertical (column) directions in the figure.

[0033] For example, in the pixel array section 21, a pixel drive line 26 is wired along the row direction for each pixel row consisting of pixels arranged in the row direction, and a vertical signal line 27 is wired along the column direction for each pixel column consisting of pixels arranged in the column direction.

[0034] The vertical drive unit 22 consists of a shift register, an address decoder, and the like, and drives each pixel of the pixel array unit 21 simultaneously or row by row by supplying signals to each pixel via a plurality of pixel drive lines 26.

[0035] The column processing unit 23 reads a signal from each pixel in each pixel column of the pixel array unit 21 via the vertical signal line 27, and generates a pixel signal by performing noise reduction processing, correlated double sampling processing, A / D (Analog to Digital) conversion processing, etc.

[0036] The horizontal drive unit 24 consists of a shift register and an address decoder, and sequentially selects the unit circuits corresponding to the pixel rows of the column processing unit 23. Through this selective scanning by the horizontal drive unit 24, the pixel signals processed for each unit circuit in the column processing unit 23 are sequentially output to the signal processing unit 28.

[0037] The system control unit 25 consists of a timing generator that generates various timing signals, and controls the drive of the vertical drive unit 22, the column processing unit 23, and the horizontal drive unit 24 based on the timing signals generated by the timing generator.

[0038] The signal processing unit 28 temporarily stores data in the data storage unit 29 as needed, performs signal processing such as arithmetic processing on the pixel signals supplied from the column processing unit 23, and outputs an image signal consisting of each pixel signal.

[0039] <Pixel Circuit Configuration> Next, the circuit configuration of each pixel 51 in the pixel array section 21 described above will be explained. Figure 2 is a circuit diagram showing an example of the circuit configuration of one pixel 51 provided in the pixel array section 21.

[0040] In Figure 2, each pixel 51 of the pixel array 21 is composed of a photoelectric conversion element (PD) 61, a transfer transistor (TG) 62, a charge-voltage conversion unit (FD) 63, a capacitance switching transistor (FDG) 64, a capacitance element 65, a reset transistor (RST) 66, an amplification transistor (AMP) 67, and a selection transistor (SEL) 68.

[0041] The photoelectric conversion element (PD) 61 is, for example, a photoelectric conversion element consisting of a PN junction, which receives light from an object and generates and stores an electric charge corresponding to the amount of light received through photoelectric conversion.

[0042] The transfer transistor (TG) 62 is provided between the photoelectric conversion element 61 and the charge-voltage conversion unit 63, and transfers the charge stored in the photoelectric conversion element 61 to the charge-voltage conversion unit 63 in accordance with the drive signal Tg applied to the gate electrode of the transfer transistor 62.

[0043] For example, in FIG. 2, the transfer transistor 62, the capacitance switching transistor 64, the reset transistor 66, and the selection transistor 68 are each formed of, for example, an N-channel MOS transistor.

[0044] Drive signals Tg, Fdg, Rst, and Sel are supplied to the gate electrodes of these transistors 62, 64, 66, and 68, respectively. These drive signals are pulse signals in which a high level state is an active state (ON state) and a low level state is an inactive state (OFF state).

[0045] Therefore, for example, in the transfer transistor 62, when the drive signal Tg supplied to the gate electrode of the transfer transistor 62 becomes an active state and the transfer transistor 62 is turned ON, the charge accumulated in the photoelectric conversion element 61 is transferred to the charge-voltage conversion unit 63.

[0046] The charge-voltage conversion unit 63 is a floating diffusion region (FD: Floating Diffusion) that converts charge transferred from the photoelectric conversion element 61 via the transfer transistor 62 into an electric signal, for example a voltage signal, and outputs the electric signal. A reset transistor 66 is connected to the charge-voltage conversion unit 63, and a vertical signal line 27 is also connected thereto via an amplification transistor 67 and a selection transistor 68.

[0047] Furthermore, a capacitive element (MIM) 65 is connected to the charge-voltage conversion unit 63 via a capacitance switching transistor 64. The capacitance switching transistor 64 is turned ON and OFF in accordance with the drive signal Fdg, thereby switching the connection state between the charge-voltage conversion unit 63 and the capacitive element 65 to either an electrically connected state or an electrically disconnected state.

[0048] That is, the drive signal Fdg is supplied to the gate electrode constituting the capacitance switching transistor 64, and when this drive signal Fdg is turned ON, the potential immediately below the capacitance switching transistor 64 becomes deep, and the charge-voltage conversion unit 63 and the capacitive element 65 are electrically connected to each other.

[0049] In contrast, when the drive signal Fdg is turned off, the potential directly below the capacitance switching transistor 64 becomes shallower, and the charge-voltage conversion unit 63 and the capacitance element 65 are electrically disconnected.

[0050] Therefore, by turning the drive signal Fdg on and off, capacitance can be added to the charge-voltage conversion unit 63, thereby changing the sensitivity of the pixels. Specifically, if the change in accumulated charge is ΔQ, the change in voltage at that time is ΔV, and the capacitance value is C, then the relationship ΔV = ΔQ / C holds.

[0051] In this way, the sensitivity of the pixels in the solid-state image sensor 11 can be changed as needed by turning the drive signal Fdg on and off. For example, when the drive signal Fdg is turned on, the capacitive element 65 is electrically connected to the charge-voltage conversion unit 63, so that a portion of the charge transferred from the photoelectric conversion element 61 to the charge-voltage conversion unit 63 is accumulated not only in the charge-voltage conversion unit 63 but also in the capacitive element 65. Details of the capacitive element 65 will be described later.

[0052] The reset transistor 66 is an element that appropriately initializes (resets) each region from the charge-voltage conversion unit 63 to the capacitive element 65. Its drain is connected to the power supply of the power supply voltage VDD, and its source is connected to the charge-voltage conversion unit 63. The drive signal Rst is applied as a reset signal to the gate electrode of the reset transistor 66.

[0053] Furthermore, when the drive signal Rst is activated, the reset transistor 66 becomes conductive, and the potential of the charge-voltage conversion unit 63, etc., is reset to the level of the power supply voltage VDD. In other words, the charge-voltage conversion unit 63, etc., is initialized.

[0054] The amplifying transistor 67 has its gate electrode connected to the charge-voltage conversion unit 63 and its drain connected to the power supply voltage VDD, and serves as the input to a source follower circuit that reads out the charge obtained by photoelectric conversion in the photoelectric conversion element 61. In other words, the source of the amplifying transistor 67 is connected to the vertical signal line 27 via the selection transistor 68, thereby forming a source follower circuit with a constant current source connected to one end of the vertical signal line 27.

[0055] The selection transistor 68 is connected between the source of the amplification transistor 67 and the vertical signal line 27, and the drive signal Sel is supplied to the gate electrode of the selection transistor 68 as a selection signal. When the drive signal Sel is activated, the selection transistor 68 becomes conductive and the pixel on which the selection transistor 68 is provided is selected. When a pixel is selected, the signal output from the amplification transistor 67 is read out to the column processing unit 23 via the vertical signal line 27.

[0056] Furthermore, in each pixel, multiple drive lines are wired, for example, for each pixel row, as pixel drive lines 26 in Figure 1. Drive signals Tg, Fdg, Rst, and Sel are supplied to the pixel from the vertical drive unit 22 through the multiple drive lines as pixel drive lines 26. Figure 1 is a block diagram showing the schematic configuration of the imaging device 1 according to this embodiment. In this specification, the imaging device 1 may be referred to as an image sensor. As shown in Figure 1, the imaging device 1 includes a pixel array unit 2, a vertical scanning circuit 3, a first reference signal (RFEslope) generation circuit 4, a sunspot correction circuit 5, a second reference signal generation circuit (DAC) 6, an AD conversion unit (SS-ADC) 7, a horizontal transfer circuit 8, and a timing control circuit 9. Note that the example of the circuit configuration of the pixel 51 according to this embodiment is just one example and is not limited thereto.

[0057] <Configuration of Capacitive Elements> Here, with reference to Figures 3 and 4, an example of the configuration of the capacitive elements 65 in the solid-state image sensor 11 will be described. Figure 3 is a plan view showing an example of the layout of the capacitive elements 65 on the semiconductor substrate 70. Figure 4 shows an example of the configuration of the AA' cross section of Figure 3 and an example of the configuration of an equivalent layer outside the pixel 51. For example, a color filter and a light-receiving lens are configured on the back side (light incident side) of the semiconductor substrate 70.

[0058] As shown in Figure 3, one pixel 51 is, for example, rectangular and is provided with a photoelectric conversion element (PD) 61. As described above, the pixels 51 are formed in a two-dimensional array on the semiconductor substrate 70. That is, multiple photoelectric conversion elements (PDs) 61 are formed in a two-dimensional array on the semiconductor substrate 70. The first direction from the first surface S1 (see Figure 4) of the semiconductor substrate 70 toward the second surface S2 opposite the first surface S1 is defined as the Z direction. The second direction perpendicular to the Z direction and along the first surface S1 is defined as the X direction, and the third direction perpendicular to the X direction and along the first surface S1 is defined as the Y direction.

[0059] As shown in Figure 4, the capacitive element 65 is configured along the Z direction from the first surface S1 of the semiconductor substrate 70 to the second surface S2 facing the first surface S1, and holds the signal charge generated by the photoelectric conversion element (PD) 61. This capacitive element 65 has a first electrode 69a configured along the Z direction, a first insulating film 69b surrounding the first electrode 69a along the Z direction, and a second electrode 69c surrounding the first insulating film 69b along the Z direction. The capacitive element 65 may sometimes be referred to as an additional capacitance section.

[0060] As shown again in Figure 3, trenches T are formed along the X and Y directions of the second surface S2, surrounding the multiple photoelectric conversion elements (PDs) 61 in a two-dimensional grid. Capacitive elements 65 are configured in the intersection regions of the trenches that intersect in the X and Y directions. This makes it possible to connect the four pixels 51 adjacent to the intersection region to the capacitive elements 65.

[0061] The capacitive element 65 is formed, for example, in a columnar shape along the Z direction within a trench. A conductor, which is a negative bias electrode 71, is formed within the trench T. This conductor is, for example, polysilicon. The planar shape of the columnar capacitive element 65 is square, circular, etc., but is not limited to these.

[0062] The insulating film 78 surrounds the second electrode 69c (see Figure 4) along the Z direction. That is, the insulating film 78 is formed between the negative bias electrode 71 and the second electrode 69c.

[0063] The semiconductor substrate 70 includes a charge-voltage conversion unit (FD) 63 that holds the signal charge transferred from the photoelectric conversion element 61. The semiconductor substrate 70 also has a power line (PWL) arranged on it. Furthermore, the semiconductor substrate 70 has a diffusion layer comprising a transfer transistor 62, a capacitance switching transistor 64, a capacitance element 65, a reset transistor 66, an amplification transistor 67, and a selection transistor 68.

[0064] Within the first insulating film layer 82a on the second surface S2 side of the semiconductor substrate 70, the gate electrodes of the transfer transistor 62, the capacitance switching transistor 64, the capacitance element 65, the reset transistor 66, the amplification transistor 67, and the selection transistor 68 are configured.

[0065] More specifically, as shown in Figure 4, the semiconductor substrate 70 is made of a silicon substrate. The semiconductor substrate 70 has, for example, a p-well layer near the surface on the second surface S2 side, and photoelectric conversion elements (PDs) 61 of a different conductivity type than the p-well layer in other regions. The semiconductor substrate 70 also has a charge-voltage conversion section (FD) 63 within the p-well layer as a semiconductor region of a different conductivity type (specifically n-type) than the p-well layer.

[0066] The fixed charge film 72 continuously covers the first surface S1 on the light-receiving side of the semiconductor substrate 70. The fixed charge film 72 is formed, for example, from an insulating film having a negative fixed charge. This suppresses the generation of dark current caused by interface states.

[0067] The insulating layer 80 comprises a first insulating film layer 82a and a second insulating film layer 82b. The first insulating film layer 82a comprises at least the gate electrodes 62G, 64G, and 67G of the transfer transistor 62, the capacitive switching transistor 64, and the amplifying transistor 67. The diffusion layer of the semiconductor substrate 70 comprises at least the source and drain electrodes SD1 and SD2 of the capacitive switching transistor 64. Similarly, the source and drain electrodes SD3 and SD4 of the amplifying transistor 67 and the source and drain electrodes of the transfer transistor 62 are formed therein. Note that source and drain electrodes refer to either source electrodes or drain electrodes. For example, if source and drain electrode SD1 is the source electrode, then source and drain electrode SD2 is the drain electrode.

[0068] Wirings 76a to 76e are formed in the second insulating film layer 82b. Wiring 76a is connected to the gate electrode 64G of the capacitive switching transistor 64, and a drive signal Fdg is supplied to it.

[0069] The source and drain electrodes SD2 of the capacitance switching transistor 64, the gate electrode 67G of the amplification transistor 67, and the charge-voltage conversion unit (FD) 63 are connected to the wiring 76b via contact plugs 74g, 74h, and 74b. In this way, the source and drain electrodes SD2 of the capacitance switching transistor 64, the gate electrode 67G of the amplification transistor 67, and the charge-voltage conversion unit (FD) 63 are electrically connected.

[0070] In this embodiment, the trench T is formed to penetrate the semiconductor substrate 70. Inside the trench T, polysilicon is formed from the first surface S1 of the semiconductor substrate 70 to the first insulating film layer 82a, and a negative bias electrode 71 is formed.

[0071] The negative bias electrode 71 is formed in the same grid pattern as the through-trenches T, surrounding each photoelectric conversion element (PD) 61 when viewed from the thickness direction of the semiconductor substrate 70. As a result, by applying a negative bias to the negative bias electrode 71, the through-trenches T side of the photoelectric conversion elements (PD) 61 can be made to a high-hole concentration state (hole accumulation state), and the generation of dark current around the through-trenches T can be suppressed.

[0072] The second electrode 69c is connected to the wiring 76c via the contact plug 74c. The wiring 76c is set to a reference potential. In this way, the capacitive element 65 constitutes a MIM capacitor (Metal-Insulator-Metal Capacitor), which is a capacitive device having a metal-insulator-metal structure, for example.

[0073] The first electrode 69a is connected to the wiring 76d via the contact plug 74d. The wiring 76d is connected to the source / drain electrode SD1 of the capacitive switching transistor 64 via the contact plug 74f. In this way, one electrode 69c of the capacitive element 65 is set to a reference potential, and the other electrode 69a is connected to the source / drain electrode SD1 of the capacitive switching transistor 64.

[0074] As described above, by configuring the capacitive elements 65 along the Z-direction from the first surface S1 of the semiconductor substrate 70 toward the second surface S2 opposite the first surface S1, it becomes possible to configure a larger volume area than with MIM capacitance (Metal-Insulator-Metal Capacitor) using a general BEOL (Back-End-Of-Line) process, thereby improving process efficiency. Furthermore, by configuring the capacitive elements 65 along the Z-direction of the semiconductor substrate 70, complex wiring processing is unnecessary compared to when they are configured together with wiring 76 within the insulating layer 80.

[0075] Outside the pixels of the pixel array 21, a semiconductor substrate 70 and an insulating layer 80 are configured, similar to the pixels 51. The insulating layer 80 has a first insulating film layer 82a and a second insulating film layer 82b. Wiring 76e is configured on the first insulating film layer 82a. By applying a negative potential to the wiring 76e, a negative potential is applied to the negative bias electrode 71 surrounding each pixel 51 of the pixel array 21.

[0076] Figure 5 shows an example of a manufacturing method for the pixel array section 21. As shown in Figure 5, the manufacturing method for the capacitive element 65 will be mainly described.

[0077] First, as shown in Figures 5(a) and 5(b), dry etching is performed on the second surface S2 of the semiconductor substrate 70 to form a trench T that penetrates the semiconductor substrate 70, and polysilicon, which is a conductor, is formed inside the trench T.

[0078] Next, as shown in Figure 5(c), dry etching is performed on the polysilicon in the formation region of the capacitive element 65 to form columnar trenches within the polysilicon. Subsequently, an insulating film 78 is formed on the inner and bottom surfaces of the columnar trenches within the polysilicon.

[0079] Next, as shown in Figure 5(c), a first electrode 69a is formed on the inner surface of the insulating film 78. Subsequently, a first insulating film 69b is formed on the inner surface of the first electrode 69a, and then a second electrode 69c is formed on the first insulating film 69b.

[0080] Next, as shown in Figure 5(e), impurities are doped to form the source and drain electrodes of the charge-voltage conversion unit (FD) 63, the transfer transistor (TG) 62, the capacitance switching transistor (FDG) 64, the reset transistor 66, the amplification transistor (AMP) 67, and the selection transistor (SEL) 68. Subsequently, the gate electrodes of the transfer transistor (TG) 62, the capacitance switching transistor (FDG) 64, the reset transistor 66, the amplification transistor (AMP) 67, and the selection transistor (SEL) 68 are formed on the first insulating film layer 82a and stacked on the semiconductor substrate 70.

[0081] Next, as shown in Figure 5(f), contact plugs 74a to h are formed on the first insulating film layer 82a. Subsequently, as shown in Figure 5(g), wiring 76a to d is formed on the second insulating film layer 82b and laminated on the first insulating film layer 82a.

[0082] In this way, the capacitive element 65 can be produced by a combination of etching and film deposition processes on the semiconductor substrate 70. This also makes it possible to reduce the number of processing steps compared to when the capacitive element 65 is formed within the first insulating film layer 82a and the second insulating film layer 82.

[0083] As described above, in this embodiment, the solid-state image sensor 11 has capacitive elements 65 configured along the Z-direction from the first surface S1 of the semiconductor substrate 70 toward the second surface S2 opposite the first surface S1. This allows the width of the semiconductor substrate 70 in the Z-direction to be used as the region of the capacitive elements 65, and the facing area between the first electrode 69a, the second electrode 69c and the first insulating film 69b to be made wider. Furthermore, by configuring the capacitive elements 65 along the Z-direction of the semiconductor substrate 70, complex wiring processing is eliminated compared to the case where the capacitive elements 65 are configured together with the wiring 76 within the insulating layer 80.

[0084] (Second Embodiment) The solid-state image sensor 11 according to the second embodiment differs from the solid-state image sensor 11 according to the first embodiment in that the capacitance of the capacitive element 65 can be configured to be larger. The differences from the solid-state image sensor 11 according to the first embodiment will be explained below.

[0085] Figure 6 is a plan view showing an example of a capacitive element 65 according to the second embodiment. In the following description, for the sake of simplicity, descriptions of transistors and the like may be omitted. As shown in Figure 6, a plurality of capacitive elements 65 are configured to be connected in parallel around the photoelectric conversion element 61. In this case, the insulating film 78 is shared by the plurality of capacitive elements 65. Also, a plurality of contact plugs 74c (see Figure 4) are configured to be connected in parallel. Similarly, a plurality of contact plugs 74d (see Figure 4) are configured to be connected in parallel. This makes it possible to further increase the capacitance that can be connected to the charge-voltage conversion unit 63.

[0086] As described above, a trench T is formed surrounding the photoelectric conversion element 61 in a two-dimensional grid. Furthermore, a capacitive element 65 is configured in the intersection region T of the trenches that intersect in the X and Y directions. In other words, multiple capacitive elements 65 are configured in a cross-shaped region including the intersection region. This makes it possible to connect the four pixels 51 adjacent to the intersection region to the capacitive element 65, and also makes it possible to configure the capacitance of the capacitive element 65 to be larger.

[0087] Figure 7 is a plan view showing an example of a different shape of capacitive element 65a according to the second embodiment. As shown in Figure 7, the cross-shaped first electrode 69a, first insulating film 69b, and second electrode 69c of the capacitive element 65a are configured in a cross-shaped region including the intersection region. This makes it possible to connect the four pixels 51 touching the intersection region to the capacitive element 65, and also makes it possible to configure the capacitance of the capacitive element 65d to be even larger.

[0088] Figure 8 is a plan view showing an example of a different shape of capacitive element 65b according to the second embodiment. As shown in Figure 8, the intersection region of the trench T is made wider, and the area of ​​the XY plane of the capacitive element 65b can be made larger than that of the capacitive element 65.

[0089] As explained above, by using a wider area within the trench T, it becomes possible to further increase the capacitance of the capacitive element 65b.

[0090] (Third Embodiment) The solid-state image sensor 11 according to the third embodiment differs from the solid-state image sensor 11 according to the first embodiment in that the trench T is made of an insulating film 78a and the area around the capacitive element 65 is made of a fixed charge film 72. The differences from the solid-state image sensor 11 according to the first embodiment will be explained below.

[0091] Figure 9 is a plan view showing an example of the layout of the capacitive element 65 in the semiconductor substrate 70 according to the third embodiment. Figure 10 is a diagram showing an example of the configuration of the BB' cross section of Figure 9. As shown in Figures 9 and 10, it differs from the solid-state image sensor 11 according to the first embodiment in that the inside of the trench T is made of an insulating film 78a and the area around the capacitive element 65 is made of a fixed charge film 72.

[0092] The fixed charge film 72 continuously covers the light-receiving surface S1 and the side surface of the semiconductor substrate 70 of the photoelectric conversion element 61. The fixed charge film 72 is formed, for example, of an insulating film having a negative fixed charge. This makes it possible to suppress the generation of dark current caused by interface states on the light-receiving surface S1 and the side surface of the photoelectric conversion element 61.

[0093] (Fourth Embodiment) The solid-state image sensor 11 according to the fourth embodiment differs from the solid-state image sensor 11 according to the first embodiment in that the length of the capacitive element 65c in the Z direction is shorter. The differences from the solid-state image sensor 11 according to the first embodiment will be explained below.

[0094] Figure 11 shows another example of the AA' cross-section in Figure 3. As shown in Figure 11, it differs from the capacitive element 65 according to the first embodiment in that the length of the capacitive element 65c in the Z direction is made shorter. This makes it possible to further facilitate the formation of the capacitive element 65f.

[0095] (Fifth Embodiment) The solid-state image sensor 11 according to the fifth embodiment differs from the solid-state image sensor 11 according to the third embodiment in that the capacitive element 65d is configured to have a shorter length in the Z direction. The differences from the solid-state image sensor 11 according to the third embodiment will be explained below.

[0096] Figure 12 shows another example of the BB' cross-section in Figure 9. As shown in Figure 12, it differs from the capacitive element 65 according to the third embodiment in that the length of the capacitive element 65d in the Z direction is shorter. In addition, a fixed charge film 72 is also formed on the first surface S1 side of the trench T. This makes it possible to further facilitate the formation of the capacitive element 65g.

[0097] (Sixth Embodiment) The solid-state image sensor 11 according to the sixth embodiment differs from the solid-state image sensor 11 according to the first embodiment in that the second electrode 69c of the capacitive element 65e is integrally formed with the electrode on the first surface S1 side. The differences from the solid-state image sensor 11 according to the first embodiment will be explained below.

[0098] Figure 13 shows yet another configuration example of the AA' cross-section in Figure 3. As shown in Figure 13, it differs from the solid-state image sensor 11 according to the first embodiment in that the second electrode 69c is integrally formed with the electrode on the first surface S1 side. In addition, an insulating film 82c is formed on the first surface S1 side. This makes it possible to make contact with the second electrode 69c from the back surface, the first surface S1 side.

[0099] (Seventh Embodiment) The solid-state image sensor 11 according to the seventh embodiment differs from the solid-state image sensor 11 according to the first embodiment in that a plurality of capacitive elements 65 are configured in the region of the photoelectric conversion element 61 in the pixel 51. The differences from the solid-state image sensor 11 according to the first embodiment will be explained below.

[0100] Figure 14 is a plan view showing an example of the layout of capacitive elements 65 in a semiconductor substrate 70 according to the seventh embodiment. Figure 15 is a diagram showing an example of the configuration of the CC' cross section of Figure 14. As shown in Figures 14 and 15, it differs from the solid-state image sensor 11 according to the first embodiment in that multiple capacitive elements 65 are configured in the region of the photoelectric conversion element 61 in the pixel 51. Multiple capacitive elements 65 can be connected in parallel.

[0101] This makes it possible to further increase the capacitance of the multiple capacitive elements 65. The pixel 51, which is composed of multiple capacitive elements 65, can be corrected in relation to the image area by defect correction processing, etc.

[0102] (Eighth Embodiment) The solid-state image sensor 11 according to the eighth embodiment differs from the solid-state image sensor 11 according to the first embodiment in that it further stacks a second semiconductor substrate 90 and forms a diffusion layer for at least a capacitance switching transistor 64 and an amplification transistor 67. The differences from the solid-state image sensor 11 according to the first embodiment will be explained below.

[0103] Figure 16 shows yet another configuration example of the AA' cross-section of Figure 3. As shown in Figure 16, the second semiconductor substrate 90 is laminated between the first insulating film layer 82a and the second insulating film layer 82b. The second semiconductor substrate 90 is configured with at least the source and drain electrodes SD1 to SD4 of the capacitance switching transistor 64 and the amplification transistor 67.

[0104] In this way, by stacking the second semiconductor substrate 90 between the first insulating film layer 82a and the second insulating film layer 82b, the degree of freedom in transistor placement can be further improved.

[0105] (Ninth Embodiment) The solid-state image sensor 11 according to the ninth embodiment differs from the solid-state image sensor 11 according to the first embodiment in that the negative bias electrode 71 in the trench T is a second electrode 69c. The differences from the solid-state image sensor 11 according to the first embodiment will be explained below.

[0106] Figure 17 is a plan view showing an example of the layout of the capacitive element 65f in the semiconductor substrate 70 according to the ninth embodiment. Figure 18 is a diagram showing an example of the configuration of the DD' cross section of Figure 17. As shown in Figures 17 and 18, it differs from the solid-state image sensor 11 according to the first embodiment in that the negative bias electrode 71 is the second electrode 69c.

[0107] The process of creating the second electrode 69c becomes unnecessary, and the formation of the capacitive element 65f can be further simplified.

[0108] (Tenth Embodiment) The solid-state image sensor 11 according to the tenth embodiment differs from the solid-state image sensor 11 according to the ninth embodiment in that the capacitive element 65g has a second electrode 69c which is integrally formed with the electrode on the first surface S1 side. The differences from the solid-state image sensor 11 according to the ninth embodiment will be explained below.

[0109] Figure 19 shows another example of the configuration in the DD' cross-section of Figure 17. As shown in Figure 19, it differs from the solid-state image sensor 11 according to the ninth embodiment in that the capacitive element 65g is integrally formed with the electrode on the first surface S1 side.

[0110] This allows the second electrode 69g to be contacted from the first surface S1 side, which is the back surface.

[0111] (Eleventh Embodiment) The solid-state image sensor 11 according to the eleventh embodiment differs from the solid-state image sensor 11 according to the ninth embodiment in that it comprises a pixel section 51a with four photoelectric conversion elements 61. The differences from the solid-state image sensor 11 according to the first embodiment will be described below.

[0112] Figure 20 is a plan view showing an example of the configuration of a solid-state image sensor 11 according to the 11th embodiment. As shown in Figure 20, the pixel section 51a is composed of four photoelectric conversion elements 61.

[0113] The transfer transistor (TG) 62 is positioned close to the charge-voltage conversion unit (FD) 63. This suppresses the capacitance of the charge-voltage conversion unit (FD) 63. On the other hand, the capacitance switching transistor (FDG) 64 is positioned close to the capacitance element 65. This makes it possible to further improve wiring efficiency.

[0114] Furthermore, this technology can take the following configuration.

[0115] (1) A solid-state image sensor comprising: a photoelectric conversion element formed on a semiconductor substrate and generating a signal charge by photoelectric conversion; and a capacitive element configured along a first direction from a first surface of the semiconductor substrate toward a second surface opposite the first surface and holding the signal charge generated by the photoelectric conversion element.

[0116] (2) The solid-state image sensor according to (1), wherein the capacitive element comprises a first electrode configured along a first direction, a first insulating film surrounding the first electrode along the first direction, and a second electrode surrounding the first insulating film along the first direction.

[0117] (3) The solid-state image sensor according to (2), further comprising a second insulating film surrounding the second electrode along the first direction.

[0118] (4) The solid-state image sensor according to (3), further comprising a conductor surrounding the second insulating film along the first direction, wherein a negative potential is applied to the conductor.

[0119] (5) A solid-state image sensor according to any one of (1) to (4), wherein a plurality of the capacitive elements are configured to be connected in parallel to the peripheral portion of the photoelectric conversion element.

[0120] (6) The solid-state image sensor described in (1), wherein the capacitive element is columnar in shape.

[0121] (7) The solid-state image sensor according to (1), wherein a plurality of photoelectric conversion elements are formed on the semiconductor substrate in a two-dimensional matrix, and trenches are formed in a two-dimensional grid surrounding the plurality of photoelectric conversion elements in a second direction along the first surface and a third direction perpendicular to the second direction along the first surface, and the capacitive elements are configured within the trenches.

[0122] (8) The solid-state image sensor according to (7), wherein the capacitive elements are configured in the intersection region of trenches that intersect the second and third directions.

[0123] (9) The solid-state image sensor according to (8), wherein a plurality of capacitive elements, including the cross region, are configured to be connected in parallel.

[0124] (10) The solid-state image sensor according to (8), wherein the capacitive elements are configured in a cross-shaped region including the intersection region.

[0125] (11) The solid-state image sensor according to (7), wherein the width of the trench along the first surface in the cross region is wider than that of other regions.

[0126] (12) The solid-state image sensor according to (2), further comprising a fixed charge film of a predetermined potential surrounding the second electrode along the first direction.

[0127] (13) The solid-state image sensor according to (4), wherein the first insulating film is also configured in a direction along the first plane perpendicular to the first direction and covers the end of the first electrode on the second plane side.

[0128] (14) The solid-state image sensor according to (13), wherein the second electrode is also configured in a direction along the first plane perpendicular to the first direction and covers the first insulating film along the first plane, the second insulating film is also configured in a direction along the first plane perpendicular to the first direction and covers the second electrode along the first plane, and the conductor is also configured in a direction along the first plane perpendicular to the first direction and covers the second insulating film along the first plane.

[0129] (15) The solid-state image sensor according to (14), wherein the first insulating film is also configured in a direction along a first plane perpendicular to the first direction and covers the end of the first electrode on the second plane side, the second electrode further comprises a third insulating film which is also configured in a direction along a first plane perpendicular to the first direction and covers the first insulating film along the first plane, and is also configured in a direction along a first plane perpendicular to the first direction and covers the second electrode along the first plane.

[0130] (16) The solid-state image sensor according to any one of (1) to (4), wherein, in the semiconductor substrate, a plurality of the photoelectric conversion elements are formed in a two-dimensional matrix, and a plurality of the capacitive elements are configured to be connected in parallel in the region of the photoelectric conversion elements.

[0131] (17) The solid-state image sensor according to (2), wherein the capacitive element is configured to penetrate the semiconductor substrate, and the second electrode is also configured in a direction along the first plane perpendicular to the first direction.

[0132] (18) The solid-state image sensor according to (2), wherein the capacitive element is configured to penetrate the semiconductor substrate and is configured in a direction along the first surface perpendicular to the first direction, and further comprises a fixed charge film of a predetermined potential that covers the first electrode and the end of the first insulating film on the second surface side.

[0133] (19) The solid-state image sensor according to (1), further comprising: a charge-voltage conversion unit formed on the semiconductor substrate and holding the signal charge transferred from the photoelectric conversion element; a capacitive switching transistor connecting the pre-charge-voltage conversion unit and the capacitive element; a reset transistor for discharging the charge from the pre-charge-voltage conversion unit; and an amplification transistor for outputting a signal corresponding to the signal charge of the charge-voltage conversion unit.

[0134] (20) The solid-state image sensor according to (19), further comprising: (20) a second semiconductor substrate on which at least the capacitance switching transistor and the diffusion layer of the amplification transistor are formed and which is laminated on the second surface side of the semiconductor substrate; and (20) a second insulating film layer on which at least the capacitance switching transistor and the gate electrode of the amplification transistor are formed and which is laminated on the surface of the second semiconductor substrate facing the first surface side.

[0135] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0136] 11: Solid-state image sensor, 51: Pixel, 61: Photoelectric converter (PD), 62: Transfer transistor (TG), 63: Charge-to-voltage converter (FD), 64: Capacitance switching transistor (FDG), 65: Capacitance element, 65a-65g: Capacitance elements, 66: Reset transistor (RST), 67: Amplifier transistor (AMP), 68: and selection transistor (SEL), 69a: First electrode, 69b: First insulating film, 69c: Second electrode 69c, 70: Semiconductor substrate, 71: Negative bias electrode (conductor), 78: Insulating film, 80: Insulating layer, 82a: First insulating film layer, 82b: Second insulating film layer 82b, S1: First surface, S2: Second surface, T: Trench

Claims

1. A solid-state image sensor comprising: a photoelectric conversion element formed on a semiconductor substrate and generating a signal charge by photoelectric conversion; and a capacitive element configured along a first direction from a first surface of the semiconductor substrate toward a second surface opposite the first surface and holding the signal charge generated by the photoelectric conversion element.

2. The solid-state image sensor according to claim 1, wherein the capacitive element comprises a first electrode configured along a first direction, a first insulating film surrounding the first electrode along the first direction, and a second electrode surrounding the first insulating film along the first direction.

3. The solid-state image sensor according to claim 2, further comprising a second insulating film surrounding the second electrode along the first direction.

4. The solid-state image sensor according to claim 3, further comprising a conductor surrounding the second insulating film along the first direction, wherein a negative potential is applied to the conductor.

5. The solid-state image sensor according to claim 1, wherein a plurality of capacitive elements are configured to be connected in parallel to the peripheral portion of the photoelectric conversion element.

6. The solid-state image sensor according to claim 1, wherein the capacitive element has a columnar shape, and the surface along the first surface is rectangular or circular.

7. The solid-state image sensor according to claim 1, wherein a plurality of photoelectric conversion elements are formed on the semiconductor substrate in a two-dimensional matrix, trenches are formed in a two-dimensional grid surrounding the plurality of photoelectric conversion elements in a second direction along the first surface and a third direction perpendicular to the second direction along the first surface, and the capacitive elements are configured within the trenches.

8. The solid-state image sensor according to claim 7, wherein the capacitive element is configured in the intersection region of trenches that intersect the second and third directions.

9. The solid-state image sensor according to claim 8, wherein a plurality of capacitive elements, including the crossover region, are configured to be connected in parallel.

10. The solid-state image sensor according to claim 8, wherein the capacitive elements are configured in a cross-shaped region including the intersection region.

11. The solid-state image sensor according to claim 7, wherein the width of the trench along the first surface in the intersection region is wider than that of other regions.

12. The solid-state image sensor according to claim 2, further comprising a fixed charge film of a predetermined potential surrounding the second electrode along the first direction.

13. The solid-state image sensor according to claim 4, wherein the first insulating film is also configured in a direction along the first surface perpendicular to the first direction and covers the end of the first electrode on the second surface side.

14. The solid-state image sensor according to claim 13, wherein the second insulating film is also configured in a direction along the first plane perpendicular to the first direction and covers the second electrode along the first plane, and the conductor is also configured in a direction along the first plane perpendicular to the first direction and covers the second insulating film along the first plane.

15. The solid-state image sensor according to claim 13, wherein the first insulating film is also configured in a direction along a first plane perpendicular to the first direction and covers the end of the first electrode on the second plane side, the second electrode is also configured in a direction along a first plane perpendicular to the first direction and covers the first insulating film along the first plane, and further comprises a third insulating film configured in a direction along a first plane perpendicular to the first direction and covers the second electrode along the first plane.

16. The solid-state image sensor according to claim 1, wherein, in the semiconductor substrate, a plurality of the photoelectric conversion elements are formed in a two-dimensional matrix, and a plurality of the capacitive elements are configured to be connected in parallel in the region of the photoelectric conversion elements.

17. The solid-state image sensor according to claim 2, wherein the capacitive element is configured to penetrate the semiconductor substrate, and the second electrode is also configured in a direction along the first plane perpendicular to the first direction.

18. The solid-state image sensor according to claim 2, wherein the capacitive element is configured to penetrate the semiconductor substrate and is configured in a direction along the first surface perpendicular to the first direction, and further comprises a fixed charge film of a predetermined potential that covers the first electrode and the end of the first insulating film on the second surface side.

19. The solid-state image sensor according to claim 1, further comprising: a charge-voltage conversion unit formed on the semiconductor substrate and holding the signal charge transferred from the photoelectric conversion element; a capacitive switching transistor connecting the pre-charge-voltage conversion unit and the capacitive element; a reset transistor for discharging the charge from the pre-charge-voltage conversion unit; and an amplification transistor for outputting a signal corresponding to the signal charge of the charge-voltage conversion unit.

20. The solid-state image sensor according to claim 19, further comprising: a second semiconductor substrate on which at least the capacitance switching transistor and the diffusion layer for the amplification transistor are formed and which is laminated on the second surface side of the semiconductor substrate; and a second insulating film layer on which at least the capacitance switching transistor and the gate electrode for the amplification transistor are formed and which is laminated on the surface of the second semiconductor substrate facing the first surface side.

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