Semiconductor device

Abstract

A semiconductor device (101) comprises a semiconductor element (11), a heat sink (21), a core layer (31), a build-up layer (32), and a heat dissipating insulation layer (40). The build-up layer (32) is provided with a first layer part and a second layer part. The first layer part has: a first resin part (321), which is a portion of a resin part; a first conductor pattern (33a1, 33a2), which is a portion of a conductor pattern and which is provided to the first resin part (321); and a first via (341), which is a portion of a via and which is provided to the first resin part (321). The second layer part has a second resin part (322), which is a portion of the resin part, a second conductor pattern (33), which is a portion of the conductor pattern and which is provided to the second resin part (322), and a second via (342), which is a portion of the via and which is provided to the second resin part (322). The second layer part is laminated on the first layer part.

Description

Semiconductor device Cross-reference to Related Applications

[0001] This application is based on Patent Application No. 2025-40482 filed in Japan on March 13, 2025, and the entire content of the base application is incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device.

[0003] Conventionally, as an example of a semiconductor device, there is a substrate with a built-in MOS transistor disclosed in Patent Document 1. The substrate with a built-in MOS transistor includes four insulating resin layers and wiring layers located on each surface of the insulating resin layers. Two MOS transistors are embedded in the third insulating resin layer. An electrode formed on the lower surface of the MOS transistor is connected to a wiring layer via a via provided penetrating through the first and second insulating resin layers. Further, an electrode formed on the upper surface of the MOS transistor is connected to another wiring layer via a via provided penetrating through the third insulating resin layer.

[0004] Japanese Unexamined Patent Publication No. 2020-53593

[0005] Incidentally, the via is provided directly above the electrode of the MOS transistor. Further, the via is formed by forming a hole in the insulating resin layer with a laser or the like and providing a conductive member in the hole. The laser for forming the hole is applied under uniform same energy conditions. Therefore, in the semiconductor device, when there is thickness variation in the insulating resin layer, there is a risk that damage may occur to the MOS transistor. Further, from the above viewpoint or from other viewpoints not mentioned, further improvements are required for semiconductor devices.

[0006] An object of the present disclosure is to provide a semiconductor device in which damage is suppressed.

[0007] The semiconductor device disclosed herein is a semiconductor device comprising a semiconductor element, comprising: a heat sink on which the semiconductor element is mounted on its surface side; a core layer having one surface and an opposite surface, with a through hole extending from one surface to the opposite surface, and the heat sink being disposed in the through hole; a heat dissipation insulating layer in contact with the opposite surface and the back surface of the heat sink; and at least one build-up layer provided opposite the surface and one surface, having a resin portion, a conductor pattern including a portion provided in the resin portion and electrically connected to the semiconductor element, and vias, wherein the one build-up layer comprises: a first resin portion which is part of the resin portion; a first conductor pattern which is part of the conductor pattern and provided in the first resin portion; a first layer portion which is part of the via and provided in the first resin portion and has first vias; a second resin portion which is part of the resin portion; a second conductor pattern which is part of the conductor pattern and provided in the second resin portion; and a second via which is part of the via and provided in the second resin portion, and is laminated on the first layer portion.

[0008] Thus, the semiconductor device is constructed with a single build-up layer comprising a first layer and a second layer. Therefore, it is easy to make the thickness of the first and second resin parts of the semiconductor device thin. Also, because the first and second resin parts are thin, thickness variations can be suppressed. As a result, it is easy to create via holes in the first and second resin parts even with a relatively low-energy laser. Consequently, damage to the semiconductor device is suppressed.

[0009] The various embodiments disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference numerals in parentheses in this section are illustrative in their correspondence with the embodiments described later and are not intended to limit the technical scope. The objectives, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the accompanying drawings.

[0010] This is a plan view showing the schematic configuration of the semiconductor device in the first embodiment. This is a cross-sectional view along the line II-II in Figure 1. This is a cross-sectional view of part III in Figure 2. This is a partial cross-sectional view showing the schematic configuration of the semiconductor device. This is a circuit diagram to which the semiconductor device is applied. This is a cross-sectional view of the semiconductor device in the second embodiment. This is a plan view showing the schematic configuration of the heat sink and semiconductor element. This is a plan view showing a modified example of the second embodiment. This is a cross-sectional view of the semiconductor device in the third embodiment. This is a plan view showing the schematic configuration of the heat sink and semiconductor element. This is a plan view showing the schematic configuration of the built-in substrate. This is a plan view showing the heat sink, core layer, and semiconductor element in the fourth embodiment. This is a plan view showing the wiring of the first layer LA in the fourth embodiment. This is a plan view showing the wiring of the second layer LA in the fourth embodiment. This is a plan view showing the overlap of the wiring in the fourth embodiment. This is a cross-sectional view along the line XVI-XVI in Figure 15. This is a plan view showing the heat sink, core layer, and semiconductor element in the fifth embodiment. This is a plan view showing the wiring of the first layer LA in the fifth embodiment. This is a plan view showing the wiring of the second layer LA in the fifth embodiment. This is a plan view showing the overlap of the wiring in the fifth embodiment. This is a cross-sectional view along the line XXI-XXI in Figure 20. This is a plan view showing the schematic configuration of the semiconductor device in the sixth embodiment. This is a cross-sectional view along the line XIII-XXIII in Figure 22. This is a plan view showing the schematic configuration of the semiconductor device in the seventh embodiment. This is a cross-sectional view along the line XXV-XXV in Figure 24. This is a plan view showing the schematic configuration of the semiconductor device in the eighth embodiment. This is a cross-sectional view along the line XXVII-XXVII in Figure 26. This is a plan view showing the schematic configuration of the heat sink and semiconductor element. This is a cross-sectional view showing the state after build-up. This is a cross-sectional view showing the state after drilling holes on the recognition marks. This is a cross-sectional view showing the state after drilling holes based on the recognition marks. This is a plan view showing the schematic configuration of the semiconductor device in the ninth embodiment. This is a cross-sectional view along the line XXXIII-XXXIII in Figure 32. This is a cross-sectional view showing the schematic configuration of the semiconductor device in the ninth embodiment. This is a plan view showing the schematic configuration of the metal plate after etching. This is a cross-sectional view along the line XXXVI-XXXVI in Figure 35. This is a plan view showing the schematic configuration of the integrated substrate after wiring formation. This is a cross-sectional view along the line XXXVIII-XXXVIII in Figure 37.This is a cross-sectional view showing the schematic configuration of an integrated substrate after back surface formation. This is a cross-sectional view of a semiconductor device in the 11th embodiment. This is a cross-sectional view of a semiconductor device in the 12th embodiment. This is a cross-sectional view showing the schematic configuration of a core layer. This is a cross-sectional view showing the schematic configuration of a core layer in a modified example. This is a plan view showing the schematic configuration of a semiconductor device in the 13th embodiment. This is a side view from the direction of the XLV arrow in Figure 44. This is a cross-sectional view along the line XLVI-XLVI in Figure 44. This is a plan view showing the schematic configuration of a semiconductor device in a modified example. This is a side view from the direction of the XLVIII arrow in Figure 47.

[0011] In the following, several embodiments for carrying out this disclosure will be described with reference to the drawings. In each embodiment, parts corresponding to matters described in a prior embodiment may be denoted by the same reference numerals, and redundant descriptions may be omitted. If only a part of the configuration is described in each embodiment, other parts of the configuration can be referred to and applied to other embodiments described earlier.

[0012] (First Embodiment) The semiconductor device 101 of the first embodiment will be described with reference to Figures 1 to 5. The semiconductor device 101 can be applied to, for example, a power converter. The semiconductor device 101 can also be applied to an in-vehicle transformer or charger. In this embodiment, as an example, a semiconductor device 101 equipped with two semiconductor elements 11 and 12 is used. The two semiconductor elements 11 and 12 are connected in series. The first semiconductor element 11 is an upper arm element. The second semiconductor element 12 is a lower arm element. However, the semiconductor device 101 only needs to be equipped with at least one semiconductor element.

[0013] <Overall Configuration of the Semiconductor Device> The semiconductor device 101 comprises semiconductor elements 11 and 12, heat sinks 21 and 22, a wiring board 30, a heat dissipation insulating layer 40, a back metal layer 50, and the like. The semiconductor device 101 has a structure in which the semiconductor elements 11 and 12 and the heat sinks 21 and 22 are embedded in the wiring board 30. The semiconductor device 101 can also be called a semiconductor package or a power semiconductor package.

[0014] The semiconductor elements 11 and 12 generate heat when they operate. Therefore, the semiconductor device 101 is provided with heat sinks 21 and 22. The semiconductor elements 11 and 12 are mounted on the surface S22 side of the heat sinks 21 and 22 (Figure 4). A heat dissipation insulating layer 40 is bonded to the heat sinks 21 and 22. A back metal layer 50 is bonded to the back metal layer 50 on the opposite side of the surface to which the heat sinks 21 and 22 are bonded. The semiconductor device 101 has the back metal layer 50 as part of the portion that is exposed to the outside.

[0015] Therefore, the heat from the semiconductor elements 11 and 12 is transferred to the heat dissipation insulating layer 40 and the back metal layer 50 via the heat sinks 21 and 22. Then, the heat from the semiconductor elements 11 and 12 is dissipated from the back metal layer 50 to the outside of the semiconductor device 101.

[0016] <Semiconductor Element> The first semiconductor element 11 and the second semiconductor element 12 have the same configuration. Therefore, the following explanation will use the first semiconductor element 11. Also, in the following, it will simply be referred to as semiconductor element 11. These points are the same in other embodiments and modifications.

[0017] The semiconductor element 11 can be, for example, a MOSFET, an IGBT, or a transistor. It can also be said that the semiconductor element 11 can be a semiconductor switching element. The semiconductor element 11 can also be a power element. Here, a vertical semiconductor element with a vertical structure is used as the semiconductor element 11. The semiconductor element 11 can use Si, SiC, GaN, etc. as its main components. That is, the semiconductor element 11 can be, for example, a Si-IGBT, a SiC-MOSFET, or a GaN-transistor. Note that the IGBT may also be an RC-IGBT.

[0018] Furthermore, the semiconductor element 11 can also be a lateral semiconductor element having a lateral structure. Examples of lateral semiconductor elements include GaN-based lateral transistors with GaN as the main component. In the lateral semiconductor element, a gate electrode, source electrode, drain electrode, etc., are formed on the element surface S12, which will be explained later. Also, for stable operation, the back surface potential of the lateral semiconductor element is connected to the source electrode on the element surface S12 side. Similarly, in a configuration in which the wiring board 30 is equipped with a lateral semiconductor element, wiring from the heat sink 21 to the element surface S12 is required.

[0019] Furthermore, in this embodiment, the same elements are used as the first semiconductor element 11 and the second semiconductor element 12. However, the first semiconductor element 11 and the second semiconductor element 12 may be different. For example, the first semiconductor element 11 and the second semiconductor element 12 may be different in size or of type.

[0020] As shown in Figure 4, the semiconductor element 11 has an element-facing surface S11 that faces the heat sink 21 (bottom 211) and an element surface S12 that is the opposite surface of the element-facing surface S11. For example, the semiconductor element 11 has an element-facing surface S11 which is a flat surface and an element surface S12 which is a flat surface.

[0021] The semiconductor element 11 has electrodes on the element-facing surface S11 and the element surface S12. The semiconductor element 11 has a gate electrode, a source electrode, and a Kelvin source electrode on the element surface S12. The semiconductor element 11 also has a drain electrode on the element-facing surface S11. The source electrode and drain electrode are also called main electrodes. The gate electrode and Kelvin source electrode are also called signal electrodes. The surface of each electrode is coated with copper plating or the like to improve connectivity with vias 34, etc. The drain electrode corresponds to the opposing surface electrode.

[0022] The semiconductor element 11 can adopt a configuration described in other embodiments, as shown in Figures 7 and 10. The source electrode corresponds to the surface electrode. Furthermore, the semiconductor elements 11 and 12 in this disclosure can be the semiconductor element 11 used in the second embodiment or the semiconductor element 11 used in the third embodiment.

[0023] <Heat Sinks> As shown in Figures 1 and 2, the semiconductor device 101 is equipped with two heat sinks 21 and 22. The first heat sink 21 is on which the first semiconductor element 11 is mounted. The second heat sink 22 is on which the second semiconductor element 12 is mounted. In this way, the two heat sinks 21 and 22 are individually equipped with the two semiconductor elements 11 and 12.

[0024] Heatsinks 21 and 22 have the same configuration. Therefore, the following explanation will use the first heatsink 21. The first heatsink 21 will also be simply referred to as heatsink 21. These points are the same for other modifications as well.

[0025] As shown in Figure 4, the heat sink 21 has a heat sink surface S22 and a heat sink opposite surface S21 which is the opposite side of the heat sink surface S22. The heat sink surface S22 and the heat sink opposite surface S21 are, for example, flat surfaces. The heat sink surface S22 corresponds to the front surface of the heat sink 21. The heat sink opposite surface S21 corresponds to the back surface of the heat sink 21. The heat sink surface S22 is also referred to as the front surface S22, and the heat sink opposite surface S21 is also referred to as the back surface S21. It can also be said that the heat sink 21 has an annular heat sink side surface that is connected to the heat sink surface S22 and the heat sink opposite surface S21.

[0026] The heat sink 21 is a plate-shaped or block-shaped component. The heat sink 21 is mainly composed of metals such as aluminum or copper. The heat sink 21 is made of a material with a higher thermal conductivity than the core layer 31, which will be explained later.

[0027] As shown in Figures 2 to 5, the heat sink 21 is provided with a recess 213 that is recessed relative to the heat sink surface S22. The recess 213 is the area where the semiconductor element 11 is mounted. The recess 213 is formed by a bottom portion 211 and an annular side wall 212. The side wall 212 is a surface that is continuous with the bottom portion 211 and the heat sink surface S22. The bottom portion 211 is, for example, a flat surface. The state in which the semiconductor element 11 is mounted in the recess 213 can also be called the element mounting state. The heat sink 21 has the semiconductor element 11 mounted on the surface S22 side.

[0028] As shown in Figure 2 and other figures, the heatsink 21 has a thickness similar to that of the core layer 31. In other words, the heatsink 21 is considerably thicker than the pattern wiring 33, which will be explained later. Therefore, the heatsink 21 has a larger heat capacity than the pattern wiring 33. Also, the heatsink 21 has a thicker plate thickness than the pattern wiring 33.

[0029] The thickness of the heatsink 21 differs between the area where the recess 213 is provided and the surrounding area. The thickness of the surrounding area is sufficiently greater than the thickness of the pattern wiring 33. Also, the thickness of the area where the recess 213 is provided is sufficiently greater than the thickness of the pattern wiring 33. The thickness of the area where the recess 213 is provided corresponds to the distance between the bottom 211 and the opposite surface S21 of the heatsink. The thickness of the surrounding area corresponds to the distance between the heatsink surface S22 and the opposite surface S21 of the heatsink.

[0030] Furthermore, the thickness here is the length along a virtual straight line perpendicular to the heat sink surface S22 and the heat sink opposite surface S21. This virtual straight line coincides with the thickness direction of the heat sink 21 and the depth direction of the recess 213. The thickness direction of the heat sink 21 can also be called the plate thickness direction. The thickness direction of the heat sink 21 can also be called the stacking direction of the semiconductor elements 11 relative to the heat sink 21. The direction perpendicular to the stacking direction is also called the planar direction.

[0031] The recess 213 is on which the semiconductor element 11 is mounted via a connecting member 60. The semiconductor element 11 is electrically connected to the heat sink 21 via the connecting member 60. The connecting member 60 connects the drain electrode of the semiconductor element 11 to the heat sink 21. The connecting member 60 is a conductive bonding material. The connecting member 60 can be made of, for example, a sintered metal material such as silver or copper. The connecting member 60 can also be called a die attach material or die bonding material. Furthermore, the connecting member 60 can be made of pressureless sintered Ag (silver), paste, solder, etc. Pressureless sintered Ag is a material for bonding by sintering silver particles without applying pressure. The recess 213 has an opening area such that the side wall 212 and the semiconductor element 11 do not come into contact.

[0032] In the manufacturing method of the semiconductor device 101, the semiconductor element 11 is mounted in the recess 213 by applying pressure (pressing) with the connecting member 60 positioned between the semiconductor element 11 and the bottom portion 211 (die attach bonding process). Therefore, it is preferable that the depth of the recess 213 be shallower than the combined thickness of the semiconductor element 11 and the connecting member 60. This allows for appropriate pressure to be applied to the semiconductor element 11.

[0033] Therefore, in the mounted state, it is preferable that the element surface S12 is at a higher position than the heat sink surface S22. In other words, the semiconductor element 11 is mounted in the recess 213 such that the element surface S12 protrudes from the heat sink surface S22. Alternatively, in the mounted state, the element surface S12 may be on the same virtual plane as the heat sink surface S22. The virtual plane is a plane that is substantially parallel to the element surface S12 and the heat sink surface S22.

[0034] The thickness of the semiconductor element 11 corresponds to the distance between the element surface S12 and the element-facing surface S11. Alternatively, the thickness of the semiconductor element 11 can be said to be the length along the aforementioned hypothetical straight line.

[0035] <Wiring board> As shown in Figures 1 and 2, the wiring board 30 comprises a core layer 31, a build-up layer 32, and a solder resist 35 as a protective film. The core layer 31 is provided with a heat dissipation insulating layer 40. The heat dissipation insulating layer 40 is provided with a back metal layer 50. Therefore, it can be said that the wiring board 30 comprises a heat dissipation insulating layer 40 and a back metal layer 50. Note that the semiconductor device 101 does not necessarily have a back metal layer 50. Similarly, in other embodiments to be described later, the back metal layer 50 may not be provided.

[0036] In Figure 1, the parts exposed from the solder resist 35 are shown with solid lines, and the parts hidden by the solder resist 35 are shown with dashed lines. Figure 2 is a diagram showing cross-sections of the semiconductor elements 11, 12, heat sinks 21, 22, core layer 31, build-up layer 32, pads 331-335, and solder resist 35.

[0037] As shown in Figure 2, the core layer 31 has a core surface S32 and a core opposite surface S31 which is the opposite surface of the core surface S32. The core surface S32 corresponds to one surface. The core opposite surface S31 corresponds to the opposite surface.

[0038] The core layer 31 is mainly composed of an electrically insulating material. For example, the core layer 31 is made up of multiple electrically insulating resin layers laminated together. Each resin layer is as thick as, or thicker than, the pattern wiring 33, which will be described later. Therefore, the core layer 31 is a material that is sufficiently thicker than the pattern wiring 33. The thickness of the core layer 31 is the length in the same direction as the thickness of the heat sink 21. The core layer 31 may also be a single-layer electrically insulating resin material having a thickness similar to that of multiple laminated resin layers. The core layer 31 can also be called the core material.

[0039] The core layer 31 has through holes 311 extending from the core surface S32 to the opposite core surface S31. The through holes 311 are the regions where the heat sinks 21 and 22 are placed. The through holes 311 have an opening area sufficient to form a gap between them and the heat sinks 21 and 22. Therefore, the through holes 311 can also be considered the gap between the core layer 31 and the heat sinks 21 and 22.

[0040] The core layer 31 is provided with two through-holes 311, each for which two heat sinks 21 and 22 are individually positioned. In other words, the core layer 31 is provided with a through-hole 311 for which the first heat sink 21 is positioned and a through-hole 311 for which the second heat sink 22 is positioned. Thus, the core layer 31 is provided with the same number of through-holes 311 as the heat sinks 21 and 22. The first heat sink 21 with the first semiconductor element 11 mounted on it and the second heat sink 22 with the second semiconductor element 12 mounted on it are positioned in the through-holes 311.

[0041] As shown in Figure 2, a build-up layer 32 is provided on the core surface S32. The semiconductor device 101 has one build-up layer 32. In other words, the semiconductor device 101 has only one build-up layer 32. However, the semiconductor device 101 may have multiple build-up layers 32. That is, the semiconductor device 101 may have a two-layer build-up layer 32, as described later for semiconductor devices 104 and 105. In this case, at least the second build-up layer has a first layer and a second layer, which will be described later. The first build-up layer may have a first layer and a second layer.

[0042] The build-up layer 32 is provided facing the core surface S32 and the heat sink surface S22. It can also be said that the build-up layer 32 is laminated and provided facing the core surface S32 and the heat sink surface S22. Furthermore, the build-up layer 32 is also provided facing the element surface S12.

[0043] The build-up layer 32 has electrically insulating resin portions 321 and 322. The build-up layer 32 also has conductive patterns 33, 33a1, 33a2 and vias 34, 341, 342, which are provided on the resin portions 321 and 322 and include portions electrically connected to the semiconductor elements 11 and 12. The conductive patterns 33, 33a1, 33a2 and vias 34, 341, 342 are conductive materials.

[0044] At least part of the conductor patterns 33, 33a1, 33a2 function as wiring. At least part of the vias 34, 341, 342 function as wiring. The conductor patterns 33, 33a1, 33a2 and the vias 34, 341, 342 may also be collectively referred to as wiring. The build-up layer 32 is provided for leading out wiring. The build-up layer 32 can also be called a wiring layer. The resin portion is also referred to as prepreg.

[0045] As shown in FIGS. 2, 3 and 4, the one-layer build-up layer 32 has a first layer portion and a second layer portion. In the build-up layer 32, the first layer portion and the second layer portion are stacked. In the present embodiment, as an example, the build-up layer 32 in which the first layer portion and the second layer portion are stacked in this order from the core surface S32 to the heat sink surface S22 is employed.

[0046] The first layer portion includes a first resin portion 321 that is part of the resin portion, first conductor patterns 33a1 and 33a2 that are part of the conductor pattern and provided in the first resin portion 321, and a first via 341 that is part of the via and provided in the first resin portion 321. In other words, it can be said that the build-up layer 32 has the first conductor patterns 33a1, 33a2 and the first via 341 in the resin portions 321, 322.

[0047] Note that the first resin portion 321 does not need to be flush with the surface S21 opposite to the heat sink. That is, an adhesive or the like may be provided between the heat sinks 21 and 22 and the heat dissipation insulating layer 40 which will be described later.

[0048] The second layer portion includes a second resin portion 322 that is part of the resin portion, a second conductor pattern 33 that is part of the conductor pattern and provided in the second resin portion 322, and a second via 342 that is part of the via and provided in the second resin portion. The second conductor pattern 33 can also be referred to as pattern wiring 33. Note that the first via 341 and the second via 342 may also be collectively referred to as the via 34. The pattern wiring 33 may also be simply referred to as the conductor pattern 33.

[0049] The first resin portion 321 is provided in contact with the element surface S12, the heat sink surface S22, and the core surface S32. The first resin portion 321 is also provided in the gap 311 between the heat sinks 21, 22 and the core layer 31. In the gap 311, the first resin portion 321 is in contact with the heat sinks 21, 22 and the core layer 31. Therefore, the first resin portion 321 covers the semiconductor elements 11, 12 and the heat sinks 21, 22.

[0050] The second resin portion 322 is provided in contact with the first layer. The second resin portion 322 has a layer surface S33 (Figures 2 and 3). The layer surface S33 is a surface that is substantially parallel to the core surface S32 and the element surface S12.

[0051] The first resin portion 321 is mainly composed of an electrically insulating resin. In other words, the first resin portion 321 does not contain glass cloth. On the other hand, the second resin portion 322 contains an electrically insulating resin and glass cloth 322a. Thus, the build-up layer 32 has a configuration in which the first resin portion 321, which is in contact with the semiconductor elements 11, 12 and the heat sinks 21, 22, does not contain glass cloth. Furthermore, at least the first resin portion 321 is placed between the glass cloth 322a and the semiconductor elements 11, 12 and the heat sinks 21, 22. Therefore, the semiconductor device 101 has a configuration in which the glass cloth 322a does not come into contact with the semiconductor elements 11, 12 and the heat sinks 21, 22. As a result, the semiconductor device 101 can suppress the occurrence of a decrease in withstand voltage.

[0052] As shown in Figures 2 and 3, the first conductor patterns 33a1 and 33a2 have a current-carrying portion 33a2 that is electrically connected to the semiconductor elements 11 and 12, and a floating portion 33a1 that is electrically separated from the semiconductor elements 11 and 12.

[0053] As shown in Figure 2, the floating portion 33a1 is located inside the resin portions 321 and 322. The floating portion 33a1 is positioned between the heat sinks 21 and 22 and the pattern wiring 33. Therefore, the semiconductor device 101 can improve the electrical insulation between the heat sinks 21 and 22 and the pattern wiring 33 compared to a configuration in which the floating portion 33a1 is electrically connected to the semiconductor elements 11 and 12.

[0054] On the other hand, the energized portion 33a2 functions as wiring together with the pattern wiring 33 and via 34. As shown in Figures 1, 2, and 3, the energized portion 33a2 and the pattern wiring 33 are provided facing the core surface S32 and the element surface S12. In other words, the energized portion 33a2 and the pattern wiring 33 include a portion facing the core surface S32 and a portion facing the element surface S12.

[0055] Furthermore, it can be said that at least a portion of the energized portion 33a2 is provided in the opposing regions of the semiconductor elements 11 and 12 and the opposing regions of the heat sinks 21 and 22. Similarly, it can be said that at least a portion of the pattern wiring 33 is provided in the opposing regions of the semiconductor elements 11 and 12 and the opposing regions of the heat sinks 21 and 22. Note that the opposing regions are regions that face each other in the stacking direction.

[0056] The conductive parts 33a2 and patterned wiring 33 are provided at multiple locations. In other words, the conductive parts 33a2 and patterned wiring 33 are made of a patterned thin film of copper or the like. The conductive parts 33a2 and patterned wiring 33 can be considered part of the layered wiring. The conductive parts 33a2, patterned wiring 33 and vias 34 correspond to the parts that are electrically connected to the semiconductor elements 11 and 12. The thin film of copper or the like before patterning can also be called a conductive film.

[0057] The pattern wiring 33 is provided on the surface of the second resin part 322. The pattern wiring 33 is partially covered by the solder resist 35. In other words, the solder resist 35 covers the pattern wiring 33 with some parts of the pads 331 and other components exposed. It can also be said that the pattern wiring 33 is covered by the solder resist 35 with some parts exposed. As a result, the pattern wiring 33 is protected by the solder resist 35. Furthermore, the semiconductor device 101 ensures the electrical insulation of the pattern wiring 33 by the solder resist 35.

[0058] The pattern wiring 33 includes pads 331 to 337, which are exposed from the solder resist 35 (Figure 1). In other words, the pattern wiring 33 includes a P pad 331, a first gate pad 332, an O pad 333, a second gate pad 334, an N pad 335, a first Kelvin source pad 336, and a second Kelvin source pad 337. Pads 331 to 337 correspond to pads for external connections.

[0059] The P pad 331 is a high-potential terminal. The N pad 335 is a low-potential terminal. The O pad 333 is an output terminal. Each of the pads 331 to 337 is electrically connected to, for example, a circuit board provided outside the semiconductor device 101. These pads 331 to 337 can also be called electrodes or external connection parts. The P pad 331, O pad 333, and N pad 335 can also be called power connection parts. The first gate pad 332, the second gate pad 334, the first Kelvin source pad 336, and the second Kelvin source pad 337 can also be called signal connection parts. Hereafter, the first gate pad 332, the second gate pad 334, the first Kelvin source pad 336, and the second Kelvin source pad 337 will be collectively referred to as the signal pad 332.

[0060] As shown in Figure 1, the pattern wiring 33 is divided into sections containing pads 331 to 337. The sections of the pattern wiring 33 containing pads 331 to 337 are described by replacing the pads 331 to 337 with the wiring section. That is, the section containing pad P 331 is described as the P wiring section. The section containing the first gate pad 332 is described as the first gate wiring section. The section containing O pad 333 is described as the O wiring section. The section containing the second gate pad 334 is described as the second gate wiring section. The section containing N pad 335 is described as the N wiring section. The section containing the first Kelvin source pad 336 is described as the first Kelvin source wiring section. The section containing the second Kelvin source pad 337 is described as the second Kelvin source wiring section.

[0061] The P-wiring section is provided facing the peripheral portion of the first semiconductor element 11 on the first heat sink 21. The P-wiring section is connected to the first heat sink 21 via a current-carrying section 33a2 and vias 34. Here, an example is adopted in which the P-wiring section and the first heat sink 21 are connected by multiple vias 34. The P-wiring section is provided facing a part of the heat sink surface S22.

[0062] The O-wiring section is provided extending from the source electrode of the first semiconductor element 11 to the peripheral portion of the second semiconductor element 12 on the second heat sink 22. The O-wiring section is connected to the source electrode of the first semiconductor element 11 and the second heat sink 22 via a current-carrying section 33a2 and vias 34. Here, an example is taken in which the O-wiring section and the source electrode are connected by multiple vias 34. Similarly, an example is taken in which the O-wiring section and the second heat sink 22 are connected by multiple vias 34. The O-wiring section is provided facing a part of the heat sink surface S22.

[0063] In this way, the O-wiring section electrically connects the source electrode of the first semiconductor element 11 and the drain electrode of the second semiconductor element 12. In other words, the pattern wiring 33 electrically connects the first semiconductor element 11 and the second semiconductor element 12.

[0064] The N-circuit section is provided extending from the source electrode of the second semiconductor element 12 to outside the opposing region of the second semiconductor element 12. The N-circuit section is connected to the source electrode of the second semiconductor element 12 via the energizing section 33a2 and vias 34. Here, an example is adopted in which the N-circuit section and the source electrode are connected by multiple vias 34.

[0065] The first gate wiring section is provided extending from the gate electrode of the first semiconductor element 11 to outside the opposing region of the first semiconductor element 11. The first gate wiring section is connected to the gate electrode of the first semiconductor element 11 via the energizing section 33a2 and via 34. The second gate wiring section is provided extending from the gate electrode of the second semiconductor element 12 to outside the opposing region of the second semiconductor element 12. The second gate wiring section is connected to the gate electrode of the second semiconductor element 12 via via 34.

[0066] The first Kelvin source wiring section is provided extending from the Kelvin source electrode of the first semiconductor element 11 to outside the opposing region of the first semiconductor element 11. The first Kelvin source wiring section is connected to the Kelvin source electrode of the first semiconductor element 11 via a current-carrying section 33a2 and a via 34. The second Kelvin source wiring section is provided extending from the Kelvin source electrode of the second semiconductor element 12 to outside the opposing region of the second semiconductor element 12. The second Kelvin source wiring section is connected to the Kelvin source electrode of the second semiconductor element 12 via a via 34.

[0067] Vias 34 are provided at multiple locations on the resin parts 321 and 322. The build-up layer 32 includes vias 34 electrically connected to the gate electrode, source electrode, and Kelvin source electrode of the first semiconductor element 11, and the gate electrode, source electrode, and Kelvin source electrode of the second semiconductor element 12. The build-up layer 32 also includes vias 34 electrically connected to the first heat sink 21 and the second heat sink 22. Each source electrode is connected to multiple vias 34. Similarly, each heat sink 21 and 22 is connected to multiple vias 34.

[0068] Here, we will explain the thickness of the first and second layers. The thickness here refers to the length along the lamination direction. The thickness of the first layer is the thickness of the first resin part 321 and the first conductor patterns 33a1 and 33a2. The thickness of the second layer is the thickness of the second resin part 322 and the pattern wiring 33. The thickness of the first and second layers can also be said to be the thickness of the parts located in the opposing regions of the heat sinks 21 and 22 and the semiconductor elements 11 and 12. Note that the thickness of the first layer does not include the parts located in the gap 311.

[0069] As shown in Figure 3, the thickness of the first layer is thinner than the thickness of the second layer. More specifically, the thickness of the first resin part 321 is thinner than the thickness of the second resin part 322. Also, the thickness of the first conductor patterns 33a1 and 33a2 is thinner than the thickness of the pattern wiring 33. Furthermore, as shown in Figure 4, in the state before the heat sinks 21 and 22 and the core layer 31 are formed, the thickness of the first layer is thinner than the thickness of the second layer.

[0070] As shown in Figure 2, a heat dissipation insulating layer 40 is provided on the core opposite surface S31 and the heat sink opposite surface S21. The heat dissipation insulating layer 40 is in contact with the core opposite surface S31 and the heat sink opposite surface S21. Preferably, the entire surface of the core opposite surface S31 and the entire surface of the heat sink opposite surface S21 are in contact with the heat dissipation insulating layer 40. It can also be said that the heat dissipation insulating layer 40 is directly connected to the core opposite surface S31 and the heat sink opposite surface S21. The heat dissipation insulating layer 40 contains a filler with good thermal conductivity and an electrically insulating resin containing the filler. In other words, the heat dissipation insulating layer 40 contains a filler and an electrically insulating resin. The heat dissipation insulating layer 40 has high thermal conductivity and is an electrically insulating layer.

[0071] The heat dissipation insulating layer 40 is primarily provided to dissipate the heat transferred to the heat sinks 21 and 22. Furthermore, the heat dissipation insulating layer 40 is provided to electrically insulate the heat sinks 21 and 22 from the back metal layer 50 while reducing the thermal resistance between the heat sinks 21 and 22 and the back metal layer 50.

[0072] Thus, the wiring board 30 does not have a build-up layer including wiring such as vias 34 on the core-opposite side S31 of the core layer 31. In other words, the core layer 31 and the heat sinks 21 and 22 are connected to the heat dissipation insulating layer 40 without vias 34. In other words, the semiconductor device 101 does not have vias 34 on the back side relative to the heat sinks 21 and 22 and the core layer 31. It can be said that the semiconductor device 101 has a heat dissipation insulating layer 40 instead of vias 34 as a heat dissipation path to the back side.

[0073] As shown in Figure 2, the back metal layer 50 is provided in contact with the heat dissipation insulating layer 40. The back metal layer 50 is a thin film mainly composed of a metal such as copper. Furthermore, as shown in Figures 1 and 4, it is preferable that the back metal layer 50 also has a wide area facing the heat sinks 21 and 22. For this reason, the back metal layer 50 includes an extension L2 that extends beyond the ends of the heat sinks 21 and 22. The facing area can also be called the projection area in the plate thickness direction. The surface of the heat dissipation insulating layer 40 on which the back metal layer 50 is provided can also be called the metal forming surface.

[0074] Furthermore, it is preferable that the heat dissipation insulating layer 40 does not contain glass cloth. In other words, the heat dissipation insulating layer 40 contains filler and an electrically insulating resin without containing glass cloth. For example, the heat dissipation insulating layer 40 is composed only of filler and resin. Therefore, the amount of filler in the heat dissipation insulating layer 40 can be increased compared to a configuration that includes glass cloth. As mentioned above, the filler has good thermal conductivity. Also, the filler is a component that improves heat dissipation. Therefore, the heat dissipation insulating layer 40 can achieve high heat dissipation. Glass cloth corresponds to glass fibers.

[0075] As described above, the semiconductor device 101 comprises at least one semiconductor element 11, 12, at least one heat sink 21, 22, a core layer 31, a build-up layer 32, and a heat dissipation insulating layer 40. The semiconductor elements 11, 12 are mounted on the surface S22 side of the heat sinks 21, 22. The core layer 31 has one surface S32 and an opposite surface S31, and is provided with a through hole 311, in which the heat sinks 21, 22 are arranged. The heat dissipation insulating layer 40 is in contact with the opposite surface S31 and the back surface S21 of the heat sinks 21, 22. The build-up layer 32 is provided facing the surface S22 and one surface S32, and has a resin portion and wiring (conductor patterns and vias) provided in the resin portion that are electrically connected to the semiconductor elements 11, 12. The semiconductor device 101 has this basic configuration.

[0076] Furthermore, the semiconductor device 101 has a configuration in which a single build-up layer 32 has a first layer and a second layer. The first layer has a first resin portion 321 which is part of the resin portion, first conductor patterns 33a1 and 33a2 which are part of the conductor pattern and are provided on the first resin portion 321, and a first via 341 which is part of the via and is provided on the first resin portion 321. The second layer has a second resin portion 322 which is part of the resin portion, a second conductor pattern 33 which is part of the conductor pattern and is provided on the second resin portion 322, and a second via 342 which is part of the via and is provided on the second resin portion 322.

[0077] <Manufacturing Method> Here, we will explain the manufacturing method of the semiconductor device 101. First, we will explain the manufacturing method of the first semiconductor element 11 and the first heat sink 21 to be embedded in the wiring board 30. The same applies to the manufacturing method of the second semiconductor element 12 and the second heat sink 22.

[0078] A first semiconductor element 11 and a first heat sink 21 are prepared. Here, a first heat sink 21 with a recess 213 is prepared. The recess 213 is formed in the first heat sink 21 by machining or die casting.

[0079] Subsequently, the connecting member 60 is attached to the element-facing surface S11. For example, the connecting member 60 is attached by transfer or other means. Then, the first semiconductor element 11 with the connecting member 60 attached is mounted on the bottom portion 211. At this time, the first semiconductor element 11 is pressed towards the bottom portion 211 (die attach bonding process). When a metal sintered material is used as the connecting member 60, the first semiconductor element 11 is mounted by heating and pressurizing the connecting member 60.

[0080] In this way, the first semiconductor element 11 and the first heat sink 21 are electrically connected. The first heat sink 21 on which the first semiconductor element 11 is mounted, and the second heat sink 22 on which the second semiconductor element 1 is mounted, can also be considered semiconductor components.

[0081] Next, the process of embedding semiconductor components in the wiring board 30 will be described. First, a core layer 31 is prepared. Then, through holes 311 are formed in the region of the core layer 31 where the semiconductor components will be placed. The through holes 311 are formed, for example, by punching.

[0082] Next, the core layer 31 is placed on the heat dissipation insulating layer 40, which has a back metal layer 50 (layup). The heat dissipation insulating layer 40 can also be called a high thermal conductivity insulating layer prepreg. After that, the semiconductor material is placed in the through hole 311 (layup). The structure in which the semiconductor material, heat dissipation insulating layer 40, and back metal layer 50 are arranged on the core layer 31 is also called the core material.

[0083] Subsequently, as shown in Figure 4, a build-up layer 32 is formed on the core member. As described above, the build-up layer 32 comprises a first layer and a second layer. Therefore, the first layer is first formed on the core member.

[0084] A first member, which will become the first layer, is placed on the core member, with a conductive thin film 33a3 formed on the first resin part 321 before patterning. Then, the first member is pressed towards the core member in the direction of the white arrow (pressing process). As a result, a part of the first resin part 321 enters into the gap 311 between the core layer 31 and the heat sinks 21 and 22. In this way, the semiconductor member is embedded in the wiring board 30. At this time, the heat dissipation insulating layer 40 may be connected to the core layer 31 and the heat sinks 21 and 22.

[0085] Subsequently, a first via 341 is formed in the first member. A filled via is formed as the first via 341 (filled via formation step). That is, a hole is made in the conductive thin film 33a3 and the first resin part 321 using a laser or the like. At this time, a hole is made that reaches the electrodes of the semiconductor elements 11 and 12 in order to bring the first via 341 into contact with the electrodes of the semiconductor elements 11 and 12. A conductor is embedded in the hole to form the first via 341. Thus, the first via 341 and the electrodes of the semiconductor elements 11 and 12 are electrically connected.

[0086] Then, the conductive thin film 33a3 is patterned to form the first conductive patterns 33a1 and 33a2 (pattern wiring formation step). As a result, the first layer is formed as shown in Figure 5.

[0087] Next, a second layer is formed on the first layer. A second member, which will become the second layer, is placed on the first layer, with a conductive thin film formed on the second resin portion 322 before patterning. Then, the second layer is formed by performing a filled via formation process and a pattern wiring formation process, similar to the first layer. However, in the filled via formation process for the second layer, it is not necessary to create holes that reach the electrodes of the semiconductor elements 11 and 12.

[0088] Subsequently, a solder resist 35 is formed (solder resist formation step). This forms the pads 331 to 337. Reference numerals 33 and 33a3 in Figure 4 indicate conductive thin films such as copper before patterning.

[0089] <Effects> As described above, the semiconductor device 101 is constructed with a single build-up layer 32 having a first layer and a second layer. Therefore, the semiconductor device 101 can be made thinner by reducing the thickness of the first resin part 321 and the second resin part 322. Also, because the first resin part 321 and the second resin part 322 are thin, thickness variations can be suppressed. Therefore, it is easy to create via holes in the first resin part 321 and the second resin part 322 even with a laser of relatively low energy.

[0090] Therefore, damage to the semiconductor elements 11 and 12 is suppressed in the semiconductor device 101. In other words, the semiconductor device 101 can improve reliability by reducing damage to the semiconductor elements 11 and 12.

[0091] In particular, the semiconductor device 101 employs a build-up layer 32 that is stacked in the order of a first layer and a second layer from the core surface S32 and the heat sink surface S22. Furthermore, the thickness of the first layer is thinner than the thickness of the second layer. The thickness variation of the first layer is smaller than that of the second layer. In addition, holes can be made in the first layer with a laser of lower energy than when holes are made in the second layer. As a result, damage to the semiconductor elements 11 and 12 is further suppressed in the semiconductor device 101.

[0092] However, the semiconductor device 101 may have a first layer and a second layer of the same thickness. Also, the thickness of the second layer of the semiconductor device 101 may be thinner than the thickness of the first layer. In other words, the semiconductor device 101 only needs to have a single build-up layer 32 that has a first layer and a second layer. This makes it easier to make the thickness of the first and second layers of the semiconductor device 101 thinner than a build-up layer that has only a resin portion, a conductor pattern and a pair of vias. Therefore, the reliability of the semiconductor device 101 can be improved as described above.

[0093] (Disclosure of Technical Ideas) This specification discloses several technical ideas as described in the following paragraphs. Some paragraphs may be written in a polydependent form, where subsequent paragraphs alternately refer to preceding paragraphs. Furthermore, some paragraphs may be written in a polydependent form, where they refer to other polydependent paragraphs. These paragraphs written in a polydependent form define several technical ideas.

[0094] <Technical Idea Group A> (Technical Idea A1) A semiconductor device comprising semiconductor elements (11, 12), comprising: a heat sink (21, 22) on which the semiconductor elements are mounted on the surface (S22) side; a core layer (31) having one surface (S32) and an opposite surface (S31) to the one surface, with a through hole (311) provided from the one surface to the opposite surface, and the heat sink being positioned in the through hole; a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink; and at least one build-up layer (32) provided opposite the surface and the one surface, having a resin portion (321, 322), a conductor pattern (33, 33a1, 33a2) and vias (34, 341, 342) including a portion provided in the resin portion and electrically connected to the semiconductor elements, wherein the one build-up layer is A semiconductor device comprising: a first resin portion (321) which is part of the resin portion; a first conductor pattern (33a1, 33a2) which is part of the conductor pattern and provided in the first resin portion; a first layer portion having a first via (341) which is part of the via and provided in the first resin portion; a second resin portion (322) which is part of the resin portion; a second conductor pattern (33) which is part of the conductor pattern and provided in the second resin portion; and a second layer portion laminated on the first layer portion, having a second via (342) which is part of the via and provided in the second resin portion.

[0095] (Technical Concept A2) The semiconductor device according to Technical Concept A1, wherein the first layer is thinner than the second layer, and the first layer and the second layer are stacked in that order from the surface and the one surface.

[0096] (Technical Concept A3) The semiconductor device according to Technical Concept A2, wherein the second resin part contains an electrically insulating resin and glass cloth (322a), and the first resin part mainly consists of an electrically insulating resin.

[0097] (Technical Concept A4) The semiconductor device according to any one of Technical Concepts A1 to A3, wherein the first conductor pattern has a current-carrying portion (33a2) electrically connected to the semiconductor element and a floating portion (33a1) electrically separated from the semiconductor element.

[0098] (Technical Concept A5) A semiconductor device according to any one of Technical Concepts A1 to A4, wherein a plurality of the build-up layers are stacked.

[0099] (Technical Idea A6) The semiconductor device according to any one of Technical Ideas A1 to A5, wherein the semiconductor device is a vertical semiconductor device and has electrodes on both sides of the device facing surface (S11) that faces the heat sink and the device surface (S12) that is the opposite side of the device facing surface, and the electrodes on the device facing surface are connected to the conductor pattern via the heat sink.

[0100] (Technical Concept A7) A semiconductor device according to any one of Technical Concepts A1 to A6, comprising two semiconductor elements and two heat sinks on which the two semiconductor elements are individually mounted, wherein the core layer is provided with two through holes in which the two heat sinks are individually arranged, and the conductor pattern electrically connects the two semiconductor elements.

[0101] (Technical Idea A8) The heat sink is provided with a recessed area (213) that is recessed to the surface, the semiconductor element is mounted in the recess via a connecting member (60), and the depth of the recess is shallower than the combined thickness of the semiconductor element and the connecting member, according to any one of the technical ideas A1 to A7.

[0102] Preferred embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above embodiments, and various modifications are possible without departing from the spirit of the present disclosure.

[0103] (Second Embodiment) The semiconductor device 102 of the second embodiment will be described with reference to Figures 6 to 8. In this embodiment, the differences from the first embodiment will be mainly described. The second embodiment differs from the first embodiment in that it is equipped with a protective film 70. Also, the configuration of the build-up layer 32 in the second embodiment differs from that of the first embodiment. However, the second embodiment can also use the build-up layer 32 of the first embodiment. In the second embodiment, the build-up layer 32 of the fourth and fifth embodiments, which will be described later, can also be used. Figure 6 is a cross-sectional view corresponding to Figure 2.

[0104] As shown in Figure 6, the semiconductor device 102 has a configuration similar to the basic configuration of the semiconductor device 101. The build-up layer 32 of the semiconductor device 102 is provided facing the surface S22 and one surface S32, and has a resin portion 323 and wiring (conductor patterns 33 and vias 34) provided on the resin portion 323 and electrically connected to the semiconductor elements 11 and 12. The resin portion 323 contains glass cloth 322a. In other words, the resin portion 323, like the second resin portion 322, contains an electrically insulating resin and glass cloth 322a.

[0105] Figure 7 is a plan view showing the schematic configuration of the semiconductor element 11 on the element surface S12 side. Reference numeral 11a denotes a source electrode. Reference numeral 11b denotes a signal electrode such as a gate electrode or a Kelvin source electrode. Note that the configuration of the semiconductor element 11 is not limited to the configuration shown in Figure 7. For example, as described in the third embodiment, the semiconductor element 11 may have a plurality of source electrodes 11a. Also, the semiconductor element 11 may have three or more signal electrodes 11b.

[0106] Incidentally, one possible example of a semiconductor device is a configuration comprising a core layer, a heat sink placed in a through-hole in the core layer, and a build-up layer. Furthermore, the build-up layer could be made of an electrically insulating resin and glass cloth.

[0107] In such semiconductor devices, if there is insufficient resin in the build-up layer, the glass cloth may come into contact with the heat sink. Furthermore, contact between the glass cloth and the heat sink may cause malfunctions in the semiconductor device.

[0108] As shown in Figures 6 and 7, the semiconductor device 102 is provided with an electrically insulating protective film 70 on the surface S22 of the heat sinks 21 and 22. The protective film 70 can be made of an insulating material such as polyamide. The protective film 70 can be formed by coating it onto the surface S22. The protective film 70 is provided along the gap 311 at the edge of the surface S22. In other words, the protective film 70 is provided at the boundary between the surface S22 and the gap 311. It can also be said that the protective film 70 is provided along each edge of the surface S22. Furthermore, it can also be said that the protective film 70 is provided in a position surrounding the source electrode 11a and the signal electrode 11b.

[0109] For example, an annular gap 311 is formed between the core layer 31 and the heat sinks 21 and 22. That is, the gap 311 is formed in an annular shape so as to surround each heat sink 21 and 22. In this case, it is preferable that the protective film 70 be provided in an annular shape at the edge of the surface S22.

[0110] However, the protective film 70 does not have to be provided in an annular shape. The protective film 70 is the boundary with the gap 311 on the surface S22, and may be provided along only a portion of the edges of the surface S22.

[0111] <Effects> As a result, the semiconductor device 102 can prevent the glass cloth 322a from entering the gap 311. Therefore, the semiconductor device 102 can prevent the glass cloth 322a from coming into contact with the heat sinks 21 and 22 when it enters the gap 311. Furthermore, the semiconductor device 102 can prevent the glass cloth 322a from coming into contact with the heat sinks 21 and 22 in the gap 311. Therefore, the semiconductor device 102 can prevent malfunctions from occurring. It is preferable that the build-up layer 32 has a glass cloth 322a with a fiber shape that is less likely to enter the gap 311.

[0112] <Modification> As shown in Figure 8, the semiconductor device 102 may have a protective film 70 covering the entire surface S22. As shown in the above embodiment, vias 34 are connected to the heat sinks 21 and 22. Therefore, the entire surface S22 is the area excluding the connection portion of the vias 34 on the surface S22. This prevents the semiconductor device 102 from coming into contact with the heat sinks 21 and 22 and the glass cloth 322a.

[0113] Furthermore, during the manufacturing process, such as the pressing process, the semiconductor device 102 may be subjected to pressure from the solder resist 35 side towards the heat dissipation insulating layer 40 while the heat dissipation insulating layer 40 or the back metal layer 50 side is placed on a stand. Even when subjected to such pressure, the semiconductor device 102 can prevent contact between the heat sinks 21 and 22 and the glass cloth 322a.

[0114] Furthermore, it is conceivable that cracks may form between the resin part 323 and the glass cloth 322a, or that the resin part 323 and the glass cloth 322a may delaminate, when pressure is applied to the semiconductor device 102. In this case, the semiconductor device 102 may experience a decrease in its withstand pressure. However, since the semiconductor device 102 is provided with a protective film 70 over the entire surface S22, even if cracks or delamination occur, a decrease in withstand pressure can be suppressed.

[0115] <Technical Idea Group B> (Technical Idea B1) A semiconductor device comprising semiconductor elements (11, 12), the semiconductor elements being mounted on the surface (S22) side of a heat sink (21, 22); a core layer (31) having one surface (S32) and an opposite surface (S31) of the one surface, with a through hole (311) extending from the one surface to the opposite surface, and the heat sink being positioned in the through hole; a build-up layer (32) provided opposite the surface and the one surface, having a resin part (323) including glass cloth (322a), and wiring (33, 34) provided in the resin part, including a part electrically connected to the semiconductor elements; a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink; and an electrically insulating protective film (70) provided on the surface.

[0116] (Technical Concept B2) The semiconductor device according to Technical Concept B1, wherein an annular gap is formed between the core layer and the heat sink, and the protective film is provided along the gap at the edge of the surface.

[0117] (Technical Concept B3) The semiconductor device according to Technical Concept B1, wherein the wiring has a conductor pattern and vias, the vias are connected to the surface, and the protective film is provided over the entire surface except for the via connections.

[0118] (Third Embodiment) The semiconductor device 103 of the third embodiment will be described with reference to Figures 9 to 11. In this embodiment, the differences from the first embodiment will be mainly described. In this embodiment, the differences from the first embodiment will be mainly described. The third embodiment differs from the first embodiment in that it includes a built-in substrate 80. Figure 9 is a cross-sectional view corresponding to Figure 2.

[0119] Furthermore, the third embodiment differs from the first embodiment in the configuration of the build-up layer 32. However, the third embodiment may also adopt the build-up layer 32 of the first embodiment. In the third embodiment, the build-up layer 32 of the fourth and fifth embodiments, which will be described later, may also be adopted. In the third embodiment, the protective film 70 of the second embodiment may be included. In the third embodiment, a resin portion 323 containing glass cloth 322a may be adopted.

[0120] Incidentally, as an example of a semiconductor device, a configuration can be considered that includes a core layer, a heat sink on which semiconductor elements are mounted and placed in through-holes of the core layer, and a build-up layer provided on the core layer and the heat sink. The build-up layer also includes a resin portion and wiring provided in the resin portion. The wiring includes pattern wiring and vias for electrically connecting the pattern wiring to the electrodes of the semiconductor elements.

[0121] Such semiconductor devices are constructed by drilling holes in the resin using a laser. At this time, holes are made that reach the electrodes of the semiconductor element in order to bring the vias into contact with the electrodes of the semiconductor element. In other words, holes are made in the region of the resin facing the electrodes. Then, conductors are embedded in these holes to form vias.

[0122] However, the semiconductor element is embedded in the resin. In other words, the semiconductor element cannot be directly seen from outside the resin. Therefore, when drilling a hole, it is conceivable to measure the distance from a reference mark provided in the core layer to the position where the hole will be drilled.

[0123] In this case, the distance between the reference mark and the electrode varies from one unit to another. In other words, the distance between the reference mark and the electrode will vary from unit to unit. Therefore, increasing the tolerance may be considered. Consequently, if the electrode is small, the position where the hole is drilled may fall outside the opposing area of ​​the electrode. To suppress this, increasing the size of the electrode may be considered.

[0124] However, increasing the size of the electrodes without changing their performance will increase the size of the semiconductor device. This could lead to an increase in the size and cost of the semiconductor device itself.

[0125] As shown in Figure 9, the semiconductor device 103 has the same basic configuration as the semiconductor device 101. Furthermore, the semiconductor device 103 includes a built-in substrate 80.

[0126] The embedded substrate 80 is provided at least between the semiconductor elements 11 and 12 and the build-up layer 32. In other words, the embedded substrate 80 is embedded in the resin portion 323 of the build-up layer 32. Furthermore, the embedded substrate 80 is provided between the semiconductor elements 11 and 12 and the pattern wiring 33.

[0127] Furthermore, in this embodiment, as an example, an internal substrate 80 is used, which is provided not only between the semiconductor elements 11, 12 and the build-up layer 32, but also between the heat sinks 21, 22 and the build-up layer 32. The internal substrate 80 is provided between the semiconductor elements 11, 12 and the pattern wiring 33, and between the heat sinks 21, 22 and the pattern wiring 33.

[0128] The internal substrates 80 are provided in correspondence with each semiconductor element 11, 12. In other words, the number of internal substrates 80 is the same as the number of semiconductor elements 11, 12. Therefore, in this embodiment, the semiconductor device 103 is equipped with two internal substrates 80.

[0129] The two internal substrates 80 are configured similarly. That is, the relationship between one internal substrate 80 and the semiconductor element 11, heat sink 21, and via 34 is the same as the relationship between the other internal substrate 80 and the semiconductor element 12, heat sink 22, and via 34. In the following description, we will use the internal substrate 80 that is positioned opposite the semiconductor element 11. Note that the two internal substrates 80 may be provided as a single unit. That is, the internal substrate 80 may have a portion corresponding to the first semiconductor element 11 and a portion corresponding to the second semiconductor element 12.

[0130] The internal substrate 80 is preferably large enough to cover the entire surface of the heat sink 21 on which the semiconductor element 11 is mounted. The entire surface of the heat sink 21 is the entire area of ​​the heat sink surface S22. The size is the area in the planar direction.

[0131] As a result, even if the resin portion 323 of the semiconductor device 103 contains glass cloth 322a, contact between the glass cloth 322a and the heat sinks 21 and 22 can be suppressed. Therefore, the electrical insulation properties of the semiconductor device 103 can be improved. However, the built-in substrate 80 only needs to be facing at least the semiconductor element 11 in the stacking direction.

[0132] As shown in Figure 10, in this embodiment, as an example, a semiconductor element 11 having two source electrodes 11a and five signal electrodes 11b is used. The semiconductor element 11 is a vertical semiconductor element. Similar to the first embodiment, the semiconductor element 11 has electrodes on both sides of the element facing surface S11 that faces the heat sink 21 and the element surface S12 which is the opposite side of the element facing surface S11. However, the semiconductor element 11 may have the same configuration as in Figure 7.

[0133] The heat sink 21 is provided with a position-fixing portion 21a. The position-fixing portion 21a protrudes from the heat sink surface S22. Positioning will be explained later.

[0134] As shown in Figure 11, the internal substrate 80 has an electrically insulating base material 81 and conductive substrate wiring 82-87 provided on the base material 81. The internal substrate 80 is attached to the semiconductor element 11 and the heat sink 21. The wiring 33 and 34 of the build-up layer 32 are electrically connected to the semiconductor element 11 and the heat sink 21 via the substrate wiring 82-87.

[0135] The internal substrate 80 has a first facing surface with the semiconductor element 11 and the heat sink 21, and a second facing surface with the pattern wiring 33. The first and second facing surfaces are the front and back surfaces of the internal substrate 80. The internal substrate 80 is a printed circuit board with substrate wiring 82 to 87 provided on both sides. The internal substrate 80 is a flexible substrate. However, a rigid substrate can also be used instead of a flexible substrate for the internal substrate 80.

[0136] The internal substrate 80 has substrate wiring 82 to 87, which consists of element-side wiring 82, 83, and 84 provided on the first opposing surface, and pattern-side wiring 85, 86, and 87 provided on the second opposing surface. The element-side wiring 82, 83, and 84 face the semiconductor element 11 and the heat sink 21. The pattern-side wiring 85, 86, and 87 face the build-up layer 32 (pattern wiring 33).

[0137] The element-side wiring 82 is the portion facing the source electrode 11a. The element-side wiring 82 is electrically connected to the pattern-side wiring 85 via a conductive interlayer connection portion provided on the substrate 81. The element-side wiring 82 can also be called the element-side main pad. The pattern-side wiring 85 can also be called the pattern-side main pad. The pattern-side wiring 85 corresponds to a pad. The source electrode 11a corresponds to a surface electrode.

[0138] The element-side wiring 83 includes a portion facing the signal electrode 11b. One end of the element-side wiring 83 can also be called an element-side signal pad. The pattern-side wiring 86 can also be called a pattern-side signal pad. One end of the element-side wiring 83 is electrically connected to the pattern-side wiring 86 via a conductive interlayer connection portion provided on the substrate 81.

[0139] The element-side wiring 83 and the interlayer connection are finer than the pattern wiring 33 and vias 34 of the build-up layer 32. Therefore, the semiconductor device 103 can be electrically connected to the pattern wiring 33 and vias 34 without increasing the size of the semiconductor element 11. Furthermore, since the semiconductor device 103 does not need to increase the size of the semiconductor element 11, the size of the semiconductor device 103 itself can be suppressed, and cost reduction can be expected.

[0140] The element-side wiring 84 is the part facing the heat sink 21. The element-side wiring 84 is electrically connected to the pattern-side wiring 87 via a conductive interlayer connection provided on the base material 81. The element-side wiring 84 can also be called the heat sink-side pad. The pattern-side wiring 87 can also be called the pattern-side pad.

[0141] The element-side main pad 82 is electrically connected to the source electrode 11a via the connecting member 61. The element-side signal pad 83 is electrically connected to the signal electrode 11b via the connecting member 61. The heat sink-side pad 84 is electrically connected to the heat sink 21 via the connecting member 61. The drain electrode of the semiconductor element 11 is electrically connected to the heat sink-side pad 84 via the heat sink 21. The connecting member 61 is conductive. The connecting member 61 can be made of, for example, solder or sintered material. The connecting member 61 can also be called a metal bonding layer.

[0142] On the other hand, the pattern-side main pad 85 is electrically connected to the O pad 333 via via 34. The pattern-side signal pad 86 is electrically connected to the signal pad 332 via via 34. The pattern-side pad 87 is electrically connected to the P pad 331 via via 34.

[0143] Note that the internal substrate 80 on the second semiconductor element 12 side has different connection destinations for the pattern-side main pad 85 and pattern-side pad 87 compared to the internal substrate 80 on the first semiconductor element 11 side. The pattern-side main pad 85 is electrically connected to the N pad 335 via via 34. The pattern-side pad 87 is electrically connected to the O pad 333 via via 34.

[0144] As shown in Figure 9, the peripheral portions of each pad 82-84 are connected to the heat sink 21 via adhesive 62. The peripheral portion is the area surrounding each pad 82-84 on the first opposing surface. The peripheral portion is an area that is not electrically connected to the semiconductor element 11 or the heat sink 21. The adhesive 62 has electrical insulating properties and can also be called an insulating adhesive 62.

[0145] The internal substrate 80 may be provided with positioning holes 81a. The positioning holes 81a are used to position the internal substrate 80 relative to the heat sinks 21 and 22. The positioning holes 81a are provided at a position opposite to the positioning protrusions 21a.

[0146] The positioning hole portion 81a is a through hole that penetrates the base material 81 in the thickness direction. In other words, the positioning hole portion 81a is a hole that reaches from the first opposing surface to the second opposing surface. Alternatively, the positioning hole portion 81a may be a bottomed hole that is recessed with respect to the surface facing the heat sink 21. When the internal substrate 80 is placed on the heat sink 21, the positioning projection portion 21a is positioned in the positioning hole portion 81a.

[0147] This allows the semiconductor device 103 to position the internal substrate 80 and the heat sink 21, and the internal substrate 80 and the semiconductor element 11. The semiconductor device 103 can improve the accuracy of attaching the internal substrate 80 to the semiconductor element 11 and the heat sink 21. Therefore, the element-side main pad 82 is positioned opposite the source electrode 11a without misalignment. The element-side signal pad 83 is positioned opposite the signal electrode 11b without misalignment. The heat sink-side pad 84 is positioned opposite the heat sink 21 without misalignment.

[0148] However, the semiconductor device 103 may have a position-fixing portion on the internal substrate 80 and a position-fixing hole on the heat sink 21. Furthermore, the semiconductor device 103 does not need to have a position-fixing hole 81a and a position-fixing portion 21a.

[0149] The element-side main pad 82 has an area equivalent to that of the source electrode 11a. Therefore, the element-side main pad 82 in Figure 11 can be considered as the source electrode 11a. The signal electrode 11b has a smaller area than the source electrode 11a. The pattern-side main pad 85 preferably has a larger area than the source electrode 11a. Similarly, the pattern-side signal pad 86 preferably has a larger area than the signal electrode 11b. The area referred to here is the area in the planar direction.

[0150] This makes it easier for the semiconductor device 103 to connect vias 34 to the pattern-side main pads 85 and pattern-side signal pads 86. In other words, the semiconductor device 103 makes it easier to electrically connect the source electrodes 11a and signal electrodes 11b with vias 34 than when the vias 34 are directly connected to the source electrodes 11a and signal electrodes 11b. As a result, the semiconductor device 103 can easily form wiring in the build-up layer 32.

[0151] As shown in Figures 9 and 11, the internal substrate 80 has a through-hole 81b that penetrates in the thickness direction. The through-hole 81b is a hole that extends from the first opposing surface to the second opposing surface of the internal substrate 80. A part of the resin portion 323 of the build-up layer 32 is placed in the through-hole 81b. In other words, the resin portion 323 is embedded in the through-hole 81b. This allows the semiconductor device 103 to improve the bonding strength between the internal substrate 80 and the build-up layer 32.

[0152] <Effects> As described above, the semiconductor device 103 has a built-in substrate 80 positioned between the semiconductor elements 11 and 12 and the build-up layer 32. Therefore, the semiconductor device 103 can suppress damage to the semiconductor elements 11 and 12 caused by the laser when forming the vias 34. Thus, the reliability of the semiconductor device 103 can be improved. In addition, the built-in substrate 80 will be irradiated with the laser. Therefore, the pattern-side wiring 85, 86, and 87 are made of a thickness that will not disappear even when irradiated with the laser.

[0153] The internal circuit board 80 may be connected to the semiconductor element 11 in advance and then connected to the heat sink 21. In this case, the semiconductor element 11 to which the internal circuit board 80 is connected will be mounted on the heat sink 21. However, the internal circuit board 80 may also be connected to the semiconductor element 11 and the heat sink 21 after the semiconductor element 11 has been mounted on the heat sink 21.

[0154] Furthermore, the internal substrate 80 may have through holes in the portions facing the source electrode 11a and the signal electrode 11b. In this case, the internal substrate 80 may be electrically connected to the source electrode 11a and the signal electrode 11b by plating or embedding a conductive material in the through holes. The conductive material can be AgSn or the like.

[0155] <Technical Idea Group C> (Technical Idea C1) A semiconductor device comprising semiconductor elements (11, 12), comprising: a heat sink (21, 22) on which the semiconductor elements are mounted on the surface (S22) side; a core layer (31) having one surface (S32) and an opposite surface (S31) of the one surface, with a through hole (311) provided from the one surface to the opposite surface, and the heat sink being positioned in the through hole; a build-up layer (32) provided opposite the surface and the one surface, having a resin portion (323) and wiring (33, 34) provided on the resin portion including a portion electrically connected to the semiconductor elements; a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink; and a built-in substrate (80) provided at least between the semiconductor elements and the build-up layer, having an electrically insulating substrate (81) and conductive substrate wiring (82-87) provided on the substrate, The aforementioned wiring is electrically connected to the semiconductor element via the substrate wiring in the semiconductor device.

[0156] (Technical Concept C2) The semiconductor device according to technical concept C1, wherein the built-in substrate is provided between the semiconductor element and the build-up layer, as well as between the heat sink and the build-up layer, and the wiring is electrically connected to the heat sink via the substrate wiring.

[0157] (Technical Concept C3) The semiconductor device according to technical concept C2, wherein the semiconductor device is a vertical semiconductor device and has electrodes on both sides of the device facing surface (S11) that faces the heat sink and the device surface (S12) that is the opposite side of the device facing surface, and the opposing surface electrode, which is the electrode on the device facing surface, is connected to the substrate wiring via the heat sink.

[0158] (Technical Concept C4) The semiconductor device according to Technical Concept C3, wherein the built-in substrate is part of the substrate wiring and has a pad (85) electrically connected to the surface electrode (11a) which is the electrode on the surface of the element, and the pad faces the build-up layer and has a larger area than the surface electrode.

[0159] (Technical idea C5) The semiconductor device according to any one of technical ideas C2 to C4, wherein the heat sink has a position-fixing portion (21a) that protrudes from the surface, and the built-in substrate has a position-fixing hole portion (81a) in which the position-fixing portion is located.

[0160] (Technical Concept C6) The built-in substrate has a through-hole portion (81b) that penetrates in the thickness direction, and the through-hole portion is a part of the resin portion as described in any one of the technical concepts C2 to C5.

[0161] (Technical Concept C7) The semiconductor device according to any one of the technical concepts C1 to C6, wherein the built-in substrate is a flexible substrate having flexibility.

[0162] (Fourth Embodiment) The semiconductor device 104 of the fourth embodiment will be described with reference to Figures 12 to 16. In this embodiment, the differences from the first embodiment will be mainly described. The fourth embodiment differs from the first embodiment in that it includes a sleeve 33t1 and a terminal portion 33t2. Also, the configuration of the build-up layer 32 in the fourth embodiment differs from that of the first embodiment.

[0163] However, the fourth embodiment may also employ the build-up layer 32 of the first embodiment. The fourth embodiment may also include the protective film 70 of the second embodiment. The fourth embodiment may also include the built-in substrate 80 of the third embodiment. The fourth embodiment may employ a resin portion 323 containing glass cloth 322a.

[0164] Incidentally, as an example of a semiconductor device, one can consider a configuration comprising a core layer, a heat sink on which semiconductor elements are mounted (stacked) and placed in through-holes of the core layer, and a build-up layer provided on the core layer and the heat sink. Furthermore, the semiconductor device is provided with external connection terminals that are connected to the signal electrodes of the semiconductor elements and protrude from the build-up layer. The external connection terminals protrude in a direction perpendicular to the stacking direction of the heat sink and semiconductor elements. In such a configuration, there is a risk that the size of the semiconductor device in the perpendicular direction will increase.

[0165] Therefore, the semiconductor device 104 aims to reduce its size in the orthogonal direction. As shown in Figure 16, the semiconductor device 104 has the same basic configuration as the semiconductor device 101.

[0166] First, the wiring of the build-up layer 32 will be explained using Figures 12 to 15. The wiring example in this embodiment is just one example. Figure 12 shows the heat sink surface S22 of the heat sinks 21 and 22 and the element surface S12 of the semiconductor elements 11 and 12.

[0167] As shown in Figure 12, the element surface S12 of the first semiconductor element 11 is provided with a source electrode as the main electrode 11me and a plurality of signal electrodes 11se. The element surface S12 of the second semiconductor element 12 is provided with a source electrode as the main electrode 12me and a plurality of signal electrodes 12se. The signal electrodes 11se and 12se are gate electrodes, source electrodes, Kelvin source electrodes, etc.

[0168] Multiple vias 34 are provided on the main electrodes 11me and 12me. At least one via 34 is provided on each signal electrode 11se and 12se.

[0169] The heat sink surface S22 is provided with a group of vias including a plurality of vias 34. The first heat sink 21 is provided with two groups of vias. The second heat sink 22 is provided with one group of vias.

[0170] As shown in Figure 13, the first layer LA1 is provided with a P pad 331, an O pad 333, an N pad 335, and a signal pad 332. The first layer LA1 is also provided with P wiring sections 33p, O wiring sections 33o, and N wiring sections 33n. As shown in Figure 16 and other figures, the first layer LA1 is a surface wiring layer. The first layer LA1 is part of the conductor pattern.

[0171] The N-circuit section 33n is provided on the second semiconductor element 12. The N-circuit section 33n is connected to the main electrode 12me via a plurality of vias 34.

[0172] The P-wiring section 33p is provided extending from the first heatsink 21 to the second heatsink 22. The P-wiring section 33p is connected to the first heatsink 21 via a plurality of vias 34. The P-wiring section 33p is also connected to the second heatsink 22 via a plurality of vias 34. Furthermore, the P-pad 331 is provided between the N-pad 335 and the N-wiring section 33n. In other words, in this wiring example, the P-pad 331, O-pad 333, and N-pad 335 are not arranged in a straight line. Note that the P-pad 331 is part of the P-wiring section 33p.

[0173] The O-wiring section 33o extends from the first semiconductor element 11 to just before the O-pad 333. The O-wiring section 33o includes a portion on the first semiconductor element 11 and a portion that becomes the O-pad 333. The O-wiring section 33o is connected to the main electrode 11me via a plurality of vias 34.

[0174] In this embodiment, as an example, a semiconductor device 104 is used that has a surface heat dissipation insulating layer 40t instead of a solder resist 35. The surface heat dissipation insulating layer 40t may be made of the same material as the heat dissipation insulating layer 40, or it may be made of a different material. The surface heat dissipation insulating layer 40t partially covers the first layer LA1. The P pad 331 and the like are parts exposed from the surface heat dissipation insulating layer 40t. The surface heat dissipation insulating layer 40t can also be used in other embodiments.

[0175] Furthermore, in this embodiment, as an example, a semiconductor device 104 equipped with a surface metal layer 50t is employed. That is, the semiconductor device 104 has a back metal layer 50 on one surface and a surface metal layer 50t on the opposite surface. The surface metal layer 50t may be made of the same material as the back metal layer 50, or it may be made of a different material. Thus, the semiconductor device 104 can be said to have a double-sided heat dissipation structure. Note that the surface metal layer 50t can also be used in other embodiments.

[0176] As shown in Figure 14, the second layer LA2 is provided with an N wiring section 33n, an O wiring section 33o, and a P wiring section 33p. The second layer LA2 is also provided with a plurality of signal wiring sections 33s. The signal wiring section 33s includes a first gate wiring section, a second gate wiring section, a first Kelvin source wiring section, and a second Kelvin source wiring section.

[0177] The N-circuit section 33n is provided on the second semiconductor element 12, extending to the region opposite the N-pad 335. The N-circuit section 33n is connected to the main electrode 12me via a plurality of vias 34. In addition, a plurality of vias for connection to the N-pad 335 are provided on the N-circuit section 33n. The second layer LA2 is the second wiring layer from the surface, as shown in Figure 16 and other figures. The second layer LA2 is part of the conductor pattern.

[0178] The O-wiring section 33o is provided extending from the first semiconductor element 11 to the second heat sink 22 and the region opposite the O-pad 333. The O-wiring section 33o is connected to the main electrode 11me via a plurality of vias 34. The O-wiring section 33o is also connected to the second heat sink 22 via a plurality of vias 34. In addition, a plurality of vias are provided on the O-wiring section 33o for connection to the O-pad 333.

[0179] The P-wiring section 33p is provided in the region opposite the first heat sink 21, facing the P-wiring section 33p in the first layer LA1. The P-wiring section 33p is provided in two locations. That is, the P-wiring section 33p is provided on both sides of the O-wiring section 33o. The P-wiring section 33p is provided with multiple vias for connecting to the P-wiring section 33p in the first layer LA1.

[0180] The signal wiring section 33s extends from above the signal electrodes 11se and 12se to above the signal pad 332. One end of the signal wiring section 33s is connected to the signal electrodes 11se and 12se via a via 34. A sleeve 33t1 and a terminal section 33t2 are provided on the other end of the signal wiring section 33s. Note that the sleeve 33t1 and terminal section 33t2 are not limited to the other end of the signal wiring section 33s, but may be arranged on the signal wiring section 33s.

[0181] When the heat sinks 21 and 22 are stacked with the first layer LA1 and the second layer LA2, the wiring sections 33p, 33o, and 33n overlap as shown in Figure 15. Then, as shown in Figure 16, the P wiring section 33p and the N wiring section 33n are arranged in parallel. Although not shown in the figure, the O wiring section 33o and the P wiring section 33p are also arranged in parallel. The build-up layer 32 includes the first layer LA1 and the second layer LA2 on which the pattern wiring 33 is stacked. Therefore, the build-up layer 32 can also be said to be a two-layer build-up layer. Furthermore, the build-up layer 32 can also be said to comprise a first build-up layer and a second build-up layer. The first build-up layer includes the resin section 323 and the first layer LA1. The second build-up layer includes the resin section 323 and the second layer LA2.

[0182] As shown in Figure 16, the semiconductor device 104 comprises a plurality of sleeves 33t1 and a plurality of terminal portions 33t2. Each sleeve 33t1 and each terminal portion 33t2 is provided in a pair. However, the semiconductor device 104 only needs to have at least one sleeve 33t1 and at least one terminal portion 33t2.

[0183] The sleeve 33t1 is a cylindrical member having a through hole into which the terminal portion 33t2 is inserted. The sleeve 33t1 is provided on the resin portion 323. The sleeve 33t1 is arranged in the stacking direction with respect to the pattern wiring 33 (signal wiring portion 33s). The sleeve 33t1 is a conductive member. The sleeve 33t1 is electrically connected to the signal wiring portion 33s. The sleeve 33t1 corresponds to a cylindrical member.

[0184] The terminal portion 33t2 is provided as an external connection terminal. The terminal portion 33t2 is inserted into a through hole in the sleeve 33t1. The terminal portion 33t2 is a conductive material. The terminal portion 33t2 is a linearly arranged terminal. The terminal portion 33t2 can be said to have a shape that aligns with the stacking direction. The terminal portion 33t2 is a pin-shaped member or a rod-shaped member.

[0185] The terminal portion 33t2 is electrically connected to the wiring of the build-up layer 32. In this embodiment, as an example, the terminal portion 33t2 connected to the signal wiring portion 33s is used. Therefore, the terminal portion 33t2 is a signal terminal electrically connected to the signal electrode 11b. It is preferable that the semiconductor device 104 is provided so as to reach the opposing region of the core layer 31 in order to connect the signal wiring portion 33s and the terminal portion 33t2.

[0186] As shown in Figure 15, multiple sleeves 33t1 are arranged in one direction. Each terminal portion 33t2 is individually inserted into each sleeve 33t1.

[0187] <Effects> As described above, the semiconductor device 104 includes a sleeve 33t1 arranged in the stacking direction relative to the pattern wiring 33, and a terminal portion 33t2 inserted into the sleeve 33t1. In other words, the semiconductor device 104 has a terminal portion 33t2 that is aligned with the stacking direction. Therefore, the semiconductor device 104 can suppress an increase in size in the orthogonal direction.

[0188] <Technical Idea Group D> (Technical Idea D1) A semiconductor device comprising semiconductor elements (11, 12), the semiconductor elements being mounted on the surface (S22) side of a heat sink (21, 22); a core layer (31) having one surface (S32) and an opposite surface (S31) to the one surface, with a through hole (311) extending from the one surface to the opposite surface, and the heat sink being positioned in the through hole; a build-up layer (32) laminated opposite the surface and the one surface, having a resin portion (323), a conductor pattern (33) and vias (34) provided in the resin portion and including a portion electrically connected to the semiconductor elements; a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink; at least one cylindrical member (33t1) provided in the resin portion and arranged in the lamination direction relative to the conductor pattern; and a terminal portion (33t2) inserted into the cylindrical member and electrically connected to the conductor pattern.

[0189] (Technical Concept D2) The semiconductor device according to technical concept D1, wherein the conductor pattern is provided so as to reach the region opposite the core layer.

[0190] (Technical Concept D3) A semiconductor device according to technical concept D1 or D2, comprising a plurality of cylindrical members arranged in one direction and a plurality of terminal portions inserted into each cylindrical member.

[0191] (Technical Concept D4) The terminal portion is a signal terminal, as described in any one of the technical concepts D1 to D3, for the semiconductor device.

[0192] (Fifth Embodiment) The semiconductor device 104 of the fifth embodiment will be described with reference to Figures 17 to 21. In this embodiment, the differences from the first embodiment will be mainly described. The fifth embodiment differs from the first embodiment in that it is equipped with a protective metal layer 90. Therefore, the configuration of the build-up layer 32 in the fifth embodiment differs from that of the first embodiment.

[0193] However, the fifth embodiment can also be adopted in a configuration in which only one layer of pattern wiring 33 is provided, as in the first embodiment. The fifth embodiment may include the protective film 70 of the second embodiment. The fifth embodiment may include the built-in substrate 80 of the third embodiment. The fifth embodiment may include the sleeve 33t1 and terminal portion 33t2 of the fourth embodiment. The fifth embodiment can employ a resin portion 323 containing glass cloth 322a.

[0194] Incidentally, as an example of a semiconductor device, a configuration can be considered that includes a core layer, a heat sink on which semiconductor elements are mounted (stacked) and placed in through-holes of the core layer, and a build-up layer provided on the core layer and the heat sink. The build-up layer has a resin portion and a conductor pattern and vias provided in the resin portion that are electrically connected to the semiconductor elements. A portion of the conductor pattern is provided on the surface of the resin portion and is partially covered by a protective film. The protective film is a solder resist 35 or a heat dissipation insulating layer 40, 40t.

[0195] Such semiconductor devices may develop cracks in the resin portion located between the heatsink and the protective film. Furthermore, if these cracks extend to the protective film, the heatsink will be exposed to the external space of the semiconductor device. As a result, the electrical insulation properties of the heatsink may deteriorate.

[0196] Therefore, the semiconductor device 105 aims to ensure electrical insulation. As shown in Figures 20 and 21, the semiconductor device 105 has a configuration similar to the basic configuration of the semiconductor device 101. Also, as an example, the semiconductor device 105, like the semiconductor device 104, has a surface heat dissipation insulating layer and a surface metal layer 50 provided on the build-up layer 32.

[0197] The surface heat dissipation insulating layer 40 is made of the same material as the heat dissipation insulating layer 40. The surface metal layer 50 is made of the same material as the back metal layer 50. Therefore, in Figure 21, the same reference numeral 40 is assigned to the surface heat dissipation insulating layer and the heat dissipation insulating layer. Also, the same reference numeral 50 is assigned to the surface metal layer and the back metal layer.

[0198] First, the wiring of the build-up layer 32 will be explained using Figures 17 to 19. The wiring example in this embodiment is just one example. Figure 17 shows the heat sink surface S22 of the heat sinks 21 and 22 and the element surface S12 of the semiconductor elements 11 and 12.

[0199] As shown in Figure 17, the heat sink surface S22 is provided with a group of vias including multiple vias 34. Each heat sink 21, 22 is provided with one group of vias. The spacing between the semiconductor elements 11, 12 and each group of vias is different. The spacing between the group of vias and the first semiconductor element 11 is narrower than the spacing between the group of vias and the second semiconductor element 12.

[0200] The element surface S12 of the first semiconductor element 11 is provided with a source electrode as the main electrode 11me and a plurality of signal electrodes 11se. The element surface S12 of the second semiconductor element 12 is provided with a source electrode as the main electrode 12me and a plurality of signal electrodes 12se. The signal electrodes 11se and 12se are gate electrodes, source electrodes, Kelvin source electrodes, etc.

[0201] Multiple vias 34 are provided on the main electrodes 11me and 12me. At least one via 34 is provided on each signal electrode 11se and 12se.

[0202] As shown in Figure 18, the first layer LA1 is provided with P pads 331, O pads 333, and N pads 335. The first layer LA1 is also provided with N wiring section 33n and O wiring section 33o. The first layer LA1 is a surface wiring layer, as shown in Figure 21 and other figures. The first layer LA1 is part of the conductor pattern.

[0203] The N-wiring section 33n is provided extending from the second semiconductor element 12 to the first heat sink 21. The N-wiring section 33n is connected to the main electrode 12me via a plurality of vias 34. By extending onto the first heat sink 21, the N-wiring section 33n functions as a heat diffusion wiring section.

[0204] The O-wiring section 33o is provided extending from the first semiconductor element 11 to the via group of the second heat sink 22. The O-wiring section 33o is connected to the main electrode 11me via a plurality of vias 34. The O-wiring section 33o is also connected to the second heat sink 22 via the via group of the second heat sink 22. The O-pad 333 is part of the O-wiring section 33o.

[0205] As shown in Figure 19, the second layer LA2 is provided with N wiring section 33n, O wiring section 33o, and P wiring section 33p. The second layer LA2 is also provided with a plurality of signal wiring sections 33s. The signal wiring sections 33s include a first gate wiring section, a second gate wiring section, a first Kelvin source wiring section, and a second Kelvin source wiring section. As shown in Figure 21 and other figures, the second layer LA2 is the second wiring layer from the surface. The second layer LA2 is part of the conductor pattern.

[0206] The N-circuit section 33n is provided on the second semiconductor element 12, extending to the region opposite the N-pad 335. The N-circuit section 33n is connected to the main electrode 12me via a plurality of vias 34. In addition, a plurality of vias for connection to the N-pad 335 are provided on the N-circuit section 33n.

[0207] The O-wiring section 33o is provided in two locations. The first O-wiring section 33o is provided extending from the first semiconductor element 11 to the second heat sink 22. The O-wiring section 33o is connected to the main electrode 11me via a plurality of vias 34. By extending the O-wiring section 33o onto the second heat sink 22, it functions as a heat diffusion wiring section.

[0208] The second O-wiring section 33o is provided in the region opposite the O-pad 333. Multiple vias 34 for connecting to the O-pad 333 are provided on the O-wiring section 33o.

[0209] The P-wiring section 33p is provided across the region facing the via group of the first heatsink 21 and the P-pad 331. The P-wiring section 33p is connected to the via group of the first heatsink 21. Multiple vias 34 for connection to the P-pad 331 are provided on the P-wiring section 33p.

[0210] The signal wiring section 33s extends from above the signal electrodes 11se and 12se. One end of the signal wiring section 33s is connected to the signal electrodes 11se and 12se via a via 34. Another via 34 is provided on the other end of the signal wiring section 33s.

[0211] When the heat sinks 21 and 22 are stacked with the first layer LA1 and the second layer LA2, the wiring sections 33p, 33o, and 33n overlap as shown in Figure 20. As shown in Figure 21 and other figures, the O wiring section 33o and the N wiring section 33n are arranged in parallel. This allows the semiconductor device 123 to reduce its inductance. As a result, the semiconductor device 123 can be made smaller and its switching speed improved. The build-up layer 32 includes the first layer LA1 and the second layer LA2 on which the pattern wiring 33 is stacked. Therefore, the build-up layer 32 can also be said to be a two-layer build-up layer. Furthermore, the build-up layer 32 can be said to comprise a first build-up layer and a second build-up layer. The first build-up layer includes the resin section 323 and the first layer LA1. The second build-up layer includes the resin section 323 and the second layer LA2.

[0212] Furthermore, as shown in Figure 20, the semiconductor device 105 is equipped with a protective metal layer 90. The protective metal layer 90 is mainly composed of metal. The protective metal layer 90 is made of the same material as, for example, the N wiring section 33n. However, the protective metal layer 90 is electrically isolated from the conductor patterns (wiring sections) such as the N wiring section 33n. In other words, the protective metal layer 90 is provided at a distance from each wiring section 33p, 33o, and 33n. Note that the protective metal layer 90 is not shown in Figures 18 and 19.

[0213] The protective metal layer 90 is positioned opposite the gap 311 in the stacking direction. Preferably, the protective metal layer 90 is positioned opposite the core layer 31 and the heat sinks 21 and 22 in the stacking direction. It can also be said that the protective metal layer 90 is positioned opposite the side surface of the heat sink in the stacking direction.

[0214] <Effects> As described above, the semiconductor device 105 is equipped with a protective metal layer 90. Therefore, the resin portion 323 is sandwiched between the heat sinks 21 and 22 and the protective metal layer 90. The semiconductor device 105 can balance the coefficients of linear expansion in the resin portion 323, the heat sinks 21 and 22, and the protective metal layer 90. Therefore, the semiconductor device 105 can suppress the occurrence of cracks in the resin portion 323.

[0215] Furthermore, as described above, cracks may occur in the resin portion 323 of the semiconductor device 105. In particular, cracks are prone to occur in the resin portion 323, starting from the area where it contacts the heat sink sides of the heat sinks 21 and 22. However, the protective metal layer 90 of the semiconductor device 105 can prevent cracks from reaching the surface heat dissipation insulating layer 40 on the resin portion 323. In other words, the semiconductor device 105 can prevent cracks from occurring in both the resin portion 323 and the surface heat dissipation insulating layer 40. Therefore, the semiconductor device 105 can prevent the heat sinks 21 and 22 from being exposed to the outside space due to cracks.

[0216] Therefore, the semiconductor device 105 can ensure the electrical insulation of the heat sinks 21 and 22. In other words, the semiconductor device 105 can improve the electrical insulation of the heat sinks 21 and 22. Furthermore, the protective metal layer 90 can be configured to be electrically separated from the conductor pattern, thereby improving the degree of freedom in its placement.

[0217] However, the protective metal layer 90 is not limited to the above. The protective metal layer 90 only needs to be positioned opposite the gap 311 in the lamination direction.

[0218] Figure 21 is a cross-sectional view of the semiconductor device 105 in a modified example. Figure 21 corresponds to a cross-sectional view along the line XXI-XXI in Figure 20. The N wiring section 33n and the O wiring section 33o may include a protective metal layer 90 provided so as to reach the opposing region in the gap 311 between the core layer 31 and the heat sinks 21 and 22. The protective metal layer 90 is part of the N wiring section 33n. The protective metal layer 90 is also part of the O wiring section 33o. Therefore, the protective metal layer 90 is mainly composed of metal. It can also be said that the protective metal layer 90 is electrically connected to the conductor pattern. As a result, the semiconductor device 105 can reduce the number of parts compared to a configuration in which the protective metal layer 90 is separate from the conductor pattern.

[0219] <Technical Idea Group E> (Technical Idea E1) A semiconductor device comprising semiconductor elements (11, 12), the semiconductor elements being mounted on the surface (S22) side of a heat sink (21, 22); a core layer (31) having one surface (S32) and an opposite surface (S31) of the one surface, with a through hole (311) extending from the one surface to the opposite surface, and the heat sink being positioned in the through hole; a build-up layer (32) provided opposite the surface and the one surface, having a resin portion (323) and wiring (33, 34, 90) provided on the resin portion, including a portion electrically connected to the semiconductor elements; and a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink, wherein the build-up layer comprises a protective metal layer (90) mainly composed of metal, positioned opposite the gap between the core layer and the heat sink.

[0220] (Technical Concept E2) The semiconductor device according to technical concept E1, wherein the protective metal layer is arranged opposite the core layer and the heat sink in addition to the gap.

[0221] (Technical Idea E3) The semiconductor device according to technical idea E1 or E2, wherein the protective metal layer is electrically isolated from the wiring.

[0222] (Technical Concept E4) The semiconductor device according to technical concept E1 or E2, wherein the protective metal layer is electrically connected to the wiring.

[0223] (Sixth Embodiment) The semiconductor device 106 of the sixth embodiment will be described with reference to Figures 22 and 23. In this embodiment, the differences from the first embodiment will be mainly described. The sixth embodiment differs from the first embodiment in that it includes a ceramic plate 41. Also, the sixth embodiment differs from the first embodiment in the configuration of the build-up layer 32.

[0224] However, the sixth embodiment may also employ the build-up layer 32 of the first embodiment. The sixth embodiment may also employ the build-up layer 32 of the fourth or fifth embodiment. The sixth embodiment may include the protective film 70 of the second embodiment. The sixth embodiment may include the built-in substrate 80 of the third embodiment. The sixth embodiment may include the sleeve 33t1 and terminal portion 33t2 of the fourth embodiment. The sixth embodiment may include the protective metal layer 90 of the fifth embodiment. The sixth embodiment may employ a resin portion 323 containing glass cloth 322a.

[0225] Incidentally, one example of a semiconductor device is a configuration comprising a core layer, a heat sink on which semiconductor elements are mounted and positioned in through-holes of the core layer, a build-up layer provided on the core layer and the heat sink, and a heat-dissipating insulating layer in contact with the back surface of the heat sink. In such a semiconductor device, further improvement in heat dissipation is desired.

[0226] Therefore, the semiconductor device 106 aims to improve heat dissipation. As shown in Figures 22 and 23, the semiconductor device 106 has the same basic configuration as the semiconductor device 101. Furthermore, the semiconductor device 106 has a ceramic plate 41 provided on the build-up layer 32.

[0227] The ceramic plate 41 is located on the opposite side of the build-up layer 32 from the heat sinks 21, 22 and the core layer 31. The ceramic plate 41 can be made of an oxide-based ceramic or a nitride-based ceramic, both of which have good thermal conductivity. More specifically, it can be made of alumina, aluminum nitride, silicon nitride, etc.

[0228] As shown in Figure 23, the ceramic plate 41 is attached to the pattern wiring 33 via grease 63. Grease 63 is also provided between the pattern wiring 33. The grease 63 has electrical insulating properties. As a result, the semiconductor device 106 can improve the electrical insulation of the pattern wiring 33. The ceramic plate 41 may also be connected to the build-up layer 32 with an adhesive or the like.

[0229] As shown in Figures 22 and 23, the ceramic plate 41 has an opening in the portion facing the pads 331 to 337. This allows the semiconductor device 106 to expose the pads 331 to 337.

[0230] <Effects> The semiconductor device 106 has a heat-dissipating insulating layer 40 on its back side and a ceramic plate 41 on its front side. Therefore, the semiconductor device 106 can improve heat dissipation compared to a configuration that does not have a ceramic plate 41 on its front side.

[0231] When the heat dissipation insulating layer 40 is provided on the build-up layer 32, high temperature and high pressure pressing is required. However, the semiconductor device 106 can be connected to the build-up layer 32 with adhesive or grease 63. Therefore, the semiconductor device 106 can be easily manufactured.

[0232] The heat dissipation insulating layer 40 is difficult to embed between the patterned wiring 33. However, the semiconductor device 106 has grease 63 provided between the patterned wiring 33. Therefore, the semiconductor device 106 can be easily manufactured.

[0233] When the heat dissipation insulating layer 40 was placed on the build-up layer 32, the edges sometimes peeled off or cracks formed between it and the build-up layer 32. However, when the ceramic plate 41 was attached to the build-up layer 32 via grease 63, no peeling or cracking occurred.

[0234] Furthermore, the heat dissipation insulating layer 40 is more expensive than the ceramic plate 41. Therefore, the semiconductor device 106 can be expected to be less expensive than a configuration with heat dissipation insulating layers 40 on both sides.

[0235] <Technical Idea Group F> (Technical Idea F1) A semiconductor device comprising semiconductor elements (11, 12), the semiconductor elements being mounted on a surface (S22) side of a heat sink (21, 22); a core layer (31) having one surface (S32) and an opposite surface (S31) to the one surface, with a through hole (311) extending from the one surface to the opposite surface, and the heat sink being positioned in the through hole; a build-up layer (32) provided opposite the surface and the one surface, having a resin portion (323) and wiring (33, 34) provided in the resin portion including a portion electrically connected to the semiconductor elements; a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink; and a ceramic plate (41) provided on the build-up layer opposite to the heat sink and the core layer.

[0236] (Technical idea F2) The semiconductor device according to technical idea F1, wherein a portion of the wiring is exposed to the outside from the resin part, and the ceramic plate is attached to the wiring via grease (63).

[0237] (Technical idea F3) The exposed portion of the wiring has pads (331-337) for external connection, and the ceramic plate has an opening in the portion facing the pad, as described in technical idea F1 or F2.

[0238] (Seventh Embodiment) The semiconductor device 107 of the seventh embodiment will be described with reference to Figures 24 and 25. In this embodiment, the differences from the fourth embodiment will be mainly described. The seventh embodiment differs from the fourth embodiment in that it is provided with an insertion terminal portion 332a. In other words, the semiconductor device 107 is similar to the build-up layer 32 of the semiconductor device 104. However, the semiconductor device 107 does not have a terminal portion 33t2 and a sleeve 33t1. The semiconductor device 107 is provided with a signal pad 332 that is electrically connected to a signal wiring portion 33s via a via 34.

[0239] Furthermore, the seventh embodiment may also employ the build-up layer 32 from the first embodiment. The seventh embodiment may also employ the build-up layer 32 from the fifth embodiment. The seventh embodiment may include the protective film 70 from the second embodiment. The seventh embodiment may include the built-in substrate 80 from the third embodiment. The seventh embodiment may include the protective metal layer 90 from the fifth embodiment. The seventh embodiment may include the ceramic plate 41 from the sixth embodiment.

[0240] Incidentally, one example of a semiconductor device is a configuration comprising a core layer, a heat sink on which semiconductor elements are mounted and positioned in through-holes of the core layer, a build-up layer provided on the core layer and the heat sink, and a heat-dissipating insulating layer in contact with the back surface of the heat sink. In such a semiconductor device, a connection structure that allows for easy connection to external devices is desired.

[0241] Therefore, the semiconductor device 107 is designed to be easily connected to external devices. As shown in Figures 24 and 25, the semiconductor device 107 has a configuration similar to the basic configuration of the semiconductor device 101. Furthermore, the semiconductor device 107 is equipped with an insertion terminal portion 332a.

[0242] The insertion terminal portion 332a is the part that is inserted into the terminal hole (female connector) of an external device. As shown in Figures 24 and 25, the insertion terminal portion 332a comprises at least a signal pad 332 and a part of the resin portion 323. The insertion terminal portion 332a also comprises a part of the solder resist 35. As shown in Figure 24, the semiconductor device 107 has a plurality of signal pads 332 arranged in one direction. The insertion terminal portion 332a has a plurality of signal pads 332.

[0243] However, the insertion terminal portion 332a does not include the core layer 31 or the heat sinks 21 and 22. In other words, the insertion terminal portion 332a is thinner than the surrounding area. The thickness is the length in the stacking direction. The semiconductor device 107 is thinned by, for example, removing the core layer 31 and resin portion 323 directly beneath the multiple signal pads 332. The insertion terminal portion 332a is provided within a predetermined range from the side wall of the semiconductor device 107.

[0244] In this embodiment, as an example, an insertion terminal section 332a is used which has a signal pad 332, one of the external connection pads 331 to 337. However, the insertion terminal section 332a may have any of the other pads 331, 333 to 337.

[0245] <Effects> As described above, the semiconductor device 107 is equipped with an insertion terminal portion 332a. Therefore, the semiconductor device 107 can be electrically connected to an external device by inserting the insertion terminal portion 332a into the terminal hole of the external device. In other words, the semiconductor device 107 can be electrically connected to an external device without wire bonding. Therefore, the semiconductor device 107 can be easily connected to an external device.

[0246] <Technical Idea Group G> (Technical Idea G1) A semiconductor device comprising semiconductor elements (11, 12), the heat sink (21, 22) on which the semiconductor elements are mounted on the surface (S22) side, a core layer (31) having one surface (S32) and a surface opposite to the one surface (S31), with a through hole (311) provided from the one surface to the opposite surface, and the heat sink being positioned in the through hole, a build-up layer (32) provided opposite the surface and the one surface, having a resin portion (323) and wiring (33, 34) provided in the resin portion including a portion electrically connected to the semiconductor elements, a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink, and an insertion terminal portion (332a) that is thinner than the surrounding area, wherein the wiring has at least one external connection pad (331-335) exposed to the outside from the resin portion. The insertion terminal portion is a semiconductor device having the pad.

[0247] (Technical Concept G2) The semiconductor device according to Technical Concept G1, wherein the pad has a plurality of signal pads arranged in one direction, and the insertion terminal portion has a plurality of the signal pads.

[0248] (Eighth Embodiment) The semiconductor device 108 of the eighth embodiment will be described with reference to Figures 26 to 31. In this embodiment, the differences from the first embodiment will be mainly described. The eighth embodiment differs from the first embodiment in that it is equipped with positioning marks 21b and 22b. Also, the eighth embodiment has a different build-up layer 32 configuration from the first embodiment. However, the eighth embodiment can also use the build-up layer 32 of the first embodiment. In the eighth embodiment, the build-up layer 32 of the fourth or fifth embodiment can also be used.

[0249] In the eighth embodiment, the protective film 70 of the second embodiment may be provided. In the eighth embodiment, the built-in substrate 80 of the third embodiment may be provided. In the eighth embodiment, the sleeve 33t1 and terminal portion 33t2 of the fourth embodiment may be provided.

[0250] Furthermore, the eighth embodiment may include the protective metal layer 90 in the fifth embodiment. The eighth embodiment may also include the ceramic plate 41 in the sixth embodiment. The eighth embodiment may also include the insertion terminal portion 332a in the seventh embodiment.

[0251] Incidentally, as an example of a semiconductor device, a configuration can be considered that includes a core layer, a heat sink on which semiconductor elements are mounted and placed in through-holes of the core layer, and a build-up layer provided on the core layer and the heat sink. The build-up layer also includes a resin portion and wiring provided in the resin portion. The wiring includes pattern wiring and vias for electrically connecting the pattern wiring to the electrodes of the semiconductor elements.

[0252] Such semiconductor devices are constructed by drilling holes in the resin using a laser. At this time, holes are made that reach the electrodes of the semiconductor element in order to bring the vias into contact with the electrodes of the semiconductor element. In other words, holes are made in the region of the resin facing the electrodes. Then, conductors are embedded in these holes to form vias.

[0253] However, the semiconductor element is embedded in the resin. In other words, the semiconductor element cannot be directly seen from outside the resin. Therefore, when drilling a hole, it is conceivable to measure the distance from a reference mark provided in the core layer to the position where the hole will be drilled.

[0254] In this case, the distance between the reference mark and the electrode varies from one unit to another. In other words, the distance between the reference mark and the electrode will vary from unit to unit. Therefore, increasing the tolerance may be considered. Consequently, if the electrode is small, the position where the hole is drilled may fall outside the opposing area of ​​the electrode. To suppress this, increasing the size of the electrode may be considered.

[0255] However, increasing the size of the electrodes without changing performance increases the overall size of the semiconductor device. Therefore, semiconductor devices may become more expensive.

[0256] Therefore, the semiconductor device 108 aims to suppress the increase in size. As shown in Figures 26, 27, and 28, the semiconductor device 108 has a configuration similar to the basic configuration of the semiconductor device 101. Furthermore, the semiconductor device 108 is equipped with heat sinks 21 and 22 provided with positioning marks 21b and 22b. In this embodiment, as an example, a semiconductor element 11 similar to that in Figure 10 is used. However, the semiconductor element 11 may have a configuration similar to that in Figure 7.

[0257] The first heat sink 21 is provided with alignment marks 21b. The second heat sink 22 is provided with alignment marks 22b. Alignment marks 21b and 22b are configured similarly. Therefore, the following explanation will use the first heat sink 21. Alignment marks 21b are also called alignment marks.

[0258] As shown in Figures 27 and 28, the first heat sink 21 is provided with a recessed positioning mark 21b relative to the heat sink surface S22. In this case, the positioning mark 21b can also be described as a recessed positioning mark 21b.

[0259] As shown in Figure 28, the positioning mark 21b is composed of two orthogonal grooves. However, the positioning mark 21b is composed of two intersecting grooves, and the angle between the two grooves does not have to be 90 degrees. The positioning mark 21b may also be round or square in shape. The shape in which the two grooves intersect is also simply called an intersecting shape.

[0260] In the drilling process, which will be explained later, the positioning marks 21b are detected (recognized) by X-rays or the like. Then, in the drilling process, holes are made using the detected positioning marks 21b as a reference. Intersecting positioning marks 21b are easier to detect with X-rays than circular or square shapes. In other words, intersecting shapes are easier to recognize even if they shift during laser drilling than circular or square shapes.

[0261] The positioning mark 21b is provided with an embedded member 21b1, which is mainly composed of metal. In other words, the positioning mark 21b is filled with the embedded member 21b1. The embedded member 21b1 is embedded in the depression that is the positioning mark 21b. The embedded member 21b1 may also be mainly composed of resin.

[0262] As shown in Figure 27, the build-up layer 32 may have vias 34 in the region opposite the positioning mark 21b. In this case, the semiconductor device 108 will drill holes for forming the vias 34 in the resin portion 323 on the positioning mark 21b. Therefore, the positioning mark 21b can be detected from the holes without using X-rays during the drilling process. The vias 34 on the positioning mark 21b do not need to be electrically connected to the heat sink 21. In other words, the vias 34 may be dummy vias that are different from the wiring of the build-up layer 32.

[0263] The positioning mark 221b has a tapered shape. However, the positioning mark 221b does not have to have a tapered shape. Furthermore, the positioning mark 21b may be a portion that protrudes from the heat sink surface S22. In this case, the positioning mark 21b may be made of the same material as the first heat sink 21. The positioning mark 21b may be provided as part of the first heat sink 21. In this case, the positioning mark 21b can also be called a convex positioning mark 21b.

[0264] Furthermore, the build-up layer 32 may have a resin portion 323 in the region opposite the positioning mark 21b. In this case, it is preferable that the embedded member 21b1 is made of a material that is recognizable by X-rays. In other words, the embedded member 21b1 is made of a material that does not transmit X-rays. If the embedded member 21b1 is mainly composed of metal, for example, tungsten or lead can be used. This makes the positioning mark 21b easier to detect by X-rays.

[0265] Furthermore, the positioning mark 21b may be provided separately from the first heat sink 21. In this case, the positioning mark 21b can be made of an X-ray-impermeable material such as tungsten or lead, making it easier to detect by X-rays.

[0266] Here, we will explain a part of the manufacturing method of the semiconductor device 108. First, as shown in Figure 29, a resin portion 323 which will become the build-up layer 32 and a conductive film before patterning are provided on the core layer 31 and the heat sinks 21 and 22. The conductive film is patterned to become the pattern wiring 33. Therefore, for convenience, the conductive film is designated as reference numeral 33 here.

[0267] Next, as shown in Figure 30, detection holes 34h are provided in the resin portion 323 and the conductive film 33 on the positioning marks 21b and 22b. The detection holes 34h are for detecting the positioning marks 21b and 22b (drilling step). Note that if the positioning marks 21b and 22b are detected by X-rays or the like, the detection holes 34h are not necessary.

[0268] Then, as shown in Figure 31, via holes 34h1 are made in the resin portion 323 and the conductive film 33, using the positioning marks 21b and 22b as a reference (drilling step). The via holes 34h1 are holes that reach the electrodes of the semiconductor elements 11 and 12. In other words, by making the via holes 34h1, the electrodes of the semiconductor elements 11 and 12 are exposed.

[0269] More specifically, the electrode distance from each electrode of the first semiconductor element 11 to the positioning mark 21b is predetermined. Similarly, the electrode distance from each electrode of the second semiconductor element 12 to the positioning mark 22b is predetermined. Then, the positioning marks 21b and 22b are detected, and via holes 34h1 are provided at a distance equal to the electrode distance from the positions of the positioning marks 21b and 22b. Via holes 34h1 are holes in which vias 34, which are connected to the electrodes of the semiconductor elements 11 and 12, are formed.

[0270] This allows via holes 34h1 to be provided in the resin portion 323 and the conductive film 33 at positions facing the electrodes of the semiconductor elements 11 and 12. Subsequently, conductors are embedded in the detection holes 34h and the via holes 34h1 to form vias 34. Plating or other treatments may be performed when forming the vias 34.

[0271] <Effects> As described above, the semiconductor device 108 is equipped with heat sinks 21 and 22 that have positioning marks 21b and 22b which serve as reference when making holes in the resin part. Therefore, the semiconductor device 108 can improve the positional accuracy of the vias 34 compared to forming via holes 34h1 for vias 34 based on the core layer. In other words, the semiconductor device 108 makes it easier to form vias 34 on the electrodes of the semiconductor elements 11 and 12.

[0272] Therefore, the semiconductor device 108 can connect the electrodes and vias 34 without increasing the size of the electrodes of the semiconductor elements 11 and 12. Thus, the semiconductor device 108 can avoid increasing its physical size.

[0273] <Technical Idea Group H> (Technical Idea H1) A semiconductor device comprising semiconductor elements (11, 12), the heat sink (21, 22) on which the semiconductor elements are mounted on its surface (S22), a core layer (31) having one surface (S32) and an opposite surface (S31) to the one surface, with a through hole (311) provided from the one surface to the opposite surface, and the heat sink being positioned in the through hole, a build-up layer (32) provided opposite the surface and the one surface, having a resin portion (323) and wiring (33, 34) provided in the resin portion including a portion electrically connected to the semiconductor elements, and a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink, wherein the wiring has vias provided in the holes of the resin portion, and the surface of the heat sink is provided with positioning marks (21b, 22b) that serve as a reference when providing holes in the resin portion.

[0274] (Technical Concept H2) The semiconductor device according to Technical Concept H1, wherein the positioning mark is recessed relative to the surface and an embedded member (21b1) mainly composed of metal is provided.

[0275] (Technical Concept H3) The semiconductor device according to Technical Concept H1, wherein the positioning mark is recessed relative to the surface and an embedded member (21b1) mainly composed of resin is provided.

[0276] (Technical Concept H4) The semiconductor device according to technical concept H2 or H3, wherein the build-up layer has the resin portion provided in the region opposite the position mark, and the embedded member is mainly composed of a material that does not transmit X-rays.

[0277] (Technical Idea H5) The semiconductor device according to any one of Technical Ideas H1 to H4, wherein the build-up layer is provided with vias in the region opposite to the positioning mark.

[0278] (Ninth Embodiment) The semiconductor device 108 of the ninth embodiment will be described with reference to Figures 32 and 33. In this embodiment, the differences from the fifth embodiment will be mainly described. The ninth embodiment differs from the fifth embodiment in that it is equipped with a support column 36. In other words, the semiconductor device 109 is similar to the build-up layer 32 of the semiconductor device 105. However, the semiconductor device 109 does not have a protective metal layer 90.

[0279] Furthermore, the ninth embodiment may also employ the build-up layer 32 of the first embodiment. The ninth embodiment may also employ the build-up layer 32 of the fourth embodiment. The ninth embodiment may include the protective film 70 of the second embodiment. The ninth embodiment may include the built-in substrate 80 of the third embodiment. The ninth embodiment may include the sleeve 33t1 and terminal portion 33t2 of the fourth embodiment. The ninth embodiment may include the protective metal layer 90 of the fifth embodiment.

[0280] Furthermore, the ninth embodiment may include the ceramic plate 41 in the sixth embodiment. The ninth embodiment may also include the insertion terminal portion 332a in the seventh embodiment. The ninth embodiment may also include the positioning marks 21b and 22b in the eighth embodiment.

[0281] Incidentally, as an example of a semiconductor device, a configuration can be considered that includes a core layer, a heat sink on which semiconductor elements are mounted and placed in through-holes of the core layer, a build-up layer provided on the core layer and the heat sink, and a heat dissipation insulating layer in contact with the back surface of the heat sink. In such a semiconductor device, pressure may be applied when attaching the heat dissipation insulating layer or when attaching it to a cooler. Therefore, the semiconductor device 109 may malfunction due to the applied pressure.

[0282] Therefore, the semiconductor device 109 aims to suppress malfunctions. As shown in Figures 32 and 33, the semiconductor device 109 has the same basic configuration as the semiconductor device 101. Furthermore, the semiconductor device 109 is equipped with a support column 36. In this embodiment, as in the fifth embodiment, the surface heat dissipation insulating layer is designated with reference numeral 40 and the surface metal layer is designated with reference numeral 50.

[0283] As shown in Figure 33, the build-up layer 32 has support columns 36 provided perpendicular to the heat sink surface S22. The support columns 36 have a portion of the conductor pattern 361 and vias 362. In other words, the support columns 36 include the conductor pattern 361, which is part of the conductor film that becomes the pattern wiring 33, and vias 362 similar to vias 34. The conductor pattern 361 can also be called a support column pattern. The vias 362 can also be called support column vias.

[0284] Furthermore, the support column 36 has support column patterns 361 and support column vias 362 arranged in a stacking direction. In addition, the support column 36 has multiple support column patterns 361 and multiple support column vias 362 stacked on top of each other. In this embodiment, as an example, a support column 36 is used in which two support column patterns 361 and two support column vias 362 are arranged alternately.

[0285] The support column 36 is electrically isolated from the pattern wiring 33 and vias 34. However, the support column 36 may be electrically connected to the pattern wiring 33 and vias 34. The support column 36 is provided so as to reach at least the surface heat dissipation insulating layer 40 from the heat sinks 21 and 22.

[0286] Furthermore, as shown in Figure 32, the semiconductor device 109 is equipped with a plurality of support columns 36. Preferably, the support columns 36 are provided at at least four corners of the heat sinks 21 and 22. In this embodiment, as an example, an example is adopted in which six support columns 36 are provided for each heat sink 21 and 22.

[0287] During the manufacturing process for forming the heat dissipation insulating layer 40, the semiconductor device 109 is placed on a base so that the back metal layer 50 is in contact with the base. As shown in Figure 33, the semiconductor device 109 may be subjected to pressure in the direction of the white arrow. Furthermore, when the semiconductor device 109 is attached to a cooler, it may be subjected to pressure in the direction of the white arrow while the back metal layer 50 is in contact with the cooler. The support column 36 is provided to protect the semiconductor elements 11 and 12 from such pressure on the resin portion 323.

[0288] <Effects> As described above, the semiconductor device 109 is equipped with a support column 36. Therefore, even if the semiconductor device 109 is pressurized as described above, it is possible to suppress the application of excessive force to the semiconductor elements 11, 12 and the resin part 323. Furthermore, even if the semiconductor device 109 has warping or thickness variations, it is possible to suppress the application of excessive force to the semiconductor elements 11, 12 and the resin part 323 due to pressurization. In other words, the semiconductor device 109 can protect the semiconductor elements 11, 12 and the resin part 323. Thus, the semiconductor device 109 can suppress malfunctions of the semiconductor elements 11, 12 and the resin part 323 due to pressurization. Therefore, the reliability of the semiconductor device 109 can be improved.

[0289] <Technical Idea Group I> (Technical Idea I1) A semiconductor device comprising semiconductor elements (11, 12), wherein the semiconductor elements are mounted on the surface (S22) side of a heat sink (21, 22); a core layer (31) having one surface (S32) and an opposite surface (S31) to the one surface, with a through hole (311) extending from the one surface to the opposite surface, and the heat sink being positioned in the through hole; a build-up layer (32) provided opposite the surface and the one surface, having a resin portion (323) and wiring (33, 34) provided on the resin portion including a portion electrically connected to the semiconductor elements; and a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink, wherein the build-up layer has a support portion (36) provided in a direction perpendicular to the surface.

[0290] (Technical Concept I2) The semiconductor device according to Technical Concept I1, wherein the wiring has a conductor pattern and vias, and the support portion has a portion of the conductor pattern and vias.

[0291] (Technical Concept I3) The semiconductor device according to Technical Concept I1, wherein the support column is electrically isolated from the wiring.

[0292] (Technical Concept I4) The semiconductor device according to any one of Technical Concepts I1 to I3, wherein the support columns are provided at at least four corners of the heat sink.

[0293] (Tenth Embodiment) The semiconductor device 110 of the tenth embodiment will be described with reference to Figures 34 to 39. In this embodiment, the differences from the first embodiment will be mainly described. The tenth embodiment differs in the manufacturing method of the semiconductor device 110. Also, in the tenth embodiment, the resin part 323 and the opposite surface S21 of the heat sink are flush.

[0294] The tenth embodiment differs from the first embodiment in the configuration of the build-up layer 32. However, the tenth embodiment can also employ the build-up layer 32 of the first embodiment. In the tenth embodiment, the build-up layer 32 of the fourth or fifth embodiment can also be employed.

[0295] Furthermore, in the tenth embodiment, a semiconductor device 110 without a core layer 31 is employed. However, the semiconductor device 110 may also have a core layer 31.

[0296] Other embodiments can be manufactured using the same manufacturing method as the tenth embodiment. The tenth embodiment may include the protective film 70 of the second embodiment. The tenth embodiment may include the built-in substrate 80 of the third embodiment. The tenth embodiment may include the sleeve 33t1 and terminal portion 33t2 of the fourth embodiment. The tenth embodiment may include the protective metal layer 90 of the fifth embodiment. The tenth embodiment may include the ceramic plate 41 of the sixth embodiment.

[0297] Furthermore, the tenth embodiment may include the insertion terminal portion 332a in the seventh embodiment. The tenth embodiment may also include the positioning marks 21b and 22b in the eighth embodiment. The tenth embodiment may also include the support column portion 36 in the ninth embodiment.

[0298] Incidentally, as an example of a semiconductor device, a configuration can be considered that includes a heat sink on which semiconductor elements are mounted, and a build-up layer provided on the heat sink. The build-up layer also includes a resin portion and wiring provided on the resin portion. The wiring includes pattern wiring and vias for electrically connecting the pattern wiring to the electrodes of the semiconductor elements.

[0299] Such semiconductor devices are constructed by drilling holes in the resin using a laser. At this time, holes are made that reach the electrodes of the semiconductor element in order to bring the vias into contact with the electrodes of the semiconductor element. In other words, holes are made in the region of the resin facing the electrodes. Then, conductors are embedded in these holes to form vias.

[0300] However, the semiconductor element is embedded in the resin. In other words, the semiconductor element cannot be directly seen from outside the resin. Therefore, when drilling a hole, it is conceivable to measure the distance from a reference mark provided in the core layer to the position where the hole will be drilled.

[0301] In this case, the distance between the reference mark and the electrode varies from one unit to another. In other words, the distance between the reference mark and the electrode will vary from unit to unit. Therefore, increasing the tolerance may be considered. Consequently, if the electrode is small, the position where the hole is drilled may fall outside the opposing area of ​​the electrode. To suppress this, increasing the size of the electrode may be considered.

[0302] However, increasing the size of the electrodes without changing performance increases the overall size of the semiconductor device. Therefore, semiconductor devices may become more expensive.

[0303] Therefore, the manufacturing method of this embodiment aims to suppress the increase in the size of the semiconductor device 110. As shown in Figure 34, the manufacturing method of the semiconductor device 110 uses a multi-unit substrate 200 in which a plurality of heat sinks 21 and 22 are integrated. Furthermore, the semiconductor device 107 has a configuration in which the core layer 31 is not included in the basic configuration of the semiconductor device 101.

[0304] In this embodiment, a semiconductor device 110 comprising a first semiconductor element 11 and a first heat sink 21 is used. The same applies to a semiconductor device 110 comprising a second semiconductor element 12 and a second heat sink 22.

[0305] A method for manufacturing the semiconductor device 110 will be explained using Figures 35 to 39. In this manufacturing method, a multi-connected substrate 200 is first formed (multi-connected substrate formation step). As shown in Figures 35 and 36, in the multi-connected substrate formation step, a multi-connected substrate 200 in which multiple first heat sinks 21 are connected is formed by partially removing a flat metal plate by etching or the like. Therefore, the multi-connected substrate 200 has multiple parts that will become first heat sinks 21 integrally provided. Here, the parts that will become first heat sinks 21 on the multi-connected substrate 200 are referred to as first heat sinks 21. In addition, in the multi-connected substrate formation step, recesses 213 are formed on the first heat sinks 21 on which the first semiconductor elements 11 are mounted.

[0306] In Figure 36, the symbol EA indicates the area where the metal plate was removed by etching. Similarly, the recess 213 is also an area where the metal plate was removed by etching. After etching, the metal plate is left with the first heat sink 21 and the connecting portion 210.

[0307] The connecting portion 210 is the part that connects multiple first heat sinks 21. The connecting portion 210 is also a part that will be removed in the splitting process, which will be explained later. The connecting portion 210 is thinner than the first heat sinks 21 to facilitate removal in the splitting process.

[0308] More specifically, in the splitting process, in addition to the connecting portion 210, the opposing portion of the first heat sink 21 is also removed. Therefore, the multi-connection substrate 200 can be said to include multiple first heat sinks 21 and connecting portions 210, as well as the opposing portions of multiple first heat sinks 21. The opposing portions have the same thickness as the connecting portion 210 and are the portions that are removed in the splitting process.

[0309] Next, as shown in Figures 37 and 38, the first semiconductor element 11 is mounted and a build-up layer 32 is formed (mounting process, wiring formation process). As shown in Figure 38, in the mounting process, the first semiconductor element 11 is mounted in the recess 213. Then, as shown in Figure 38, in the wiring formation process, the build-up layer 32 is formed. In the wiring formation process, vias 34, pattern wiring 33, and solder resist 35 are formed. Note that in Figure 38, the connecting member 60 is omitted for the sake of simplifying the drawing.

[0310] When forming the via 34, a hole is made in the resin part 323 or the like that reaches the electrode of the first semiconductor element 11, as described above. At this time, the hole is made in the resin part 323 or the like with a part of the first heat sink 21 as a reference. Therefore, it is preferable that the first heat sink 21 is provided with the positioning mark 21b in the eighth embodiment. In this case, the second heat sink 22 will be provided with the positioning mark 22b.

[0311] At the stage when the wiring formation process is completed, an integrated substrate is formed in which multiple semiconductor device parts 110 are integrated. In other words, Figures 37 and 38 are a plan view and a cross-sectional view showing the integrated substrate. One side S21a of the multi-connected substrate 200 is exposed on the integrated substrate.

[0312] Next, a removal process is performed to remove the connecting portion 210. As shown in Figure 38, in the removal process, the integrated substrate is removed from one side S21a to the cut line CL. The integrated substrate can be removed by etching or cutting. The distance between one side S21a and the cut line CL is, for example, equivalent to the thickness of the connecting portion 210.

[0313] Once the removal process is complete, the opposite surface S21 of the heat sink will be exposed (Figure 39). Furthermore, the opposite surface S21 of the heat sink will be flush with the resin part 323. Therefore, no step is formed between the opposite surface S21 of the heat sink and the resin part 323.

[0314] In the removal process, the multi-unit substrate 200 is mainly removed. However, in the removal process, the resin part 323 may be removed together with the multi-unit substrate 200.

[0315] Next, a heat dissipation insulating layer 40 and a back metal layer 50 are formed on the opposite side S21 of the heat sink (back surface formation step). The heat dissipation insulating layer 40 is provided, for example, over the entire area of ​​the opposite side S21 of the heat sink on the integrated substrate. On the other hand, the back metal layer 50 is provided, for example, for each opposing region of each first heat sink 21. However, the disclosure is not limited thereto. The heat dissipation insulating layer 40 may be provided for each opposing region of each first heat sink 21. The back metal layer 50 may be provided over the entire area of ​​the opposite side S21 of the heat sink on the integrated substrate.

[0316] Next, as shown in Figure 39, a division process is performed to divide the integrated substrate into multiple semiconductor devices 110. In the division process, the integrated substrate is divided using a dicing line DL. As a result, the integrated substrate is divided into multiple semiconductor devices 110. In other words, the integrated substrate is broken down into multiple semiconductor devices 110.

[0317] <Effects> The semiconductor device 110 has a heat sink opposite surface S21 and a resin part 323 that are flush. Therefore, it is easy to provide a heat dissipation insulating layer 40 on the heat sink opposite surface S21 and the resin part 323 of the semiconductor device 110. In other words, the semiconductor device 110 can improve the reliability of the connection between the heat sink opposite surface S21 and the resin part 323 and the heat dissipation insulating layer 40.

[0318] Furthermore, as described above, this manufacturing method uses a multi-connected substrate 200 to manufacture multiple semiconductor devices 110. Therefore, in this manufacturing method, the build-up layer 32 is formed on the first heat sink 21 while it remains in a multi-connected state. In other words, in this manufacturing method, the pattern wiring 33 and vias 34 are formed on the multiple first heat sinks 21 while they are integrated.

[0319] Thus, in this manufacturing method, since the vias 34 are formed in the state of the multi-layer substrate 200, the positional accuracy between the position where the holes for the vias 34 are drilled and the drilling reference can be improved. In other words, in this manufacturing method, the positional accuracy of the vias 34 can be improved compared to forming the build-up layer 32 on the individual first heat sink 21. In this manufacturing method, the positional accuracy when drilling holes on the first semiconductor element 11 in the resin part 323, etc., can be improved.

[0320] Therefore, in this manufacturing method, the electrodes and vias 34 can be connected without increasing the size of the electrodes of the first semiconductor element 11. Thus, in this manufacturing method, it is possible to suppress an increase in the size of the semiconductor device 110.

[0321] <Technical Idea Group J> (Technical Idea J1) A semiconductor device comprising semiconductor elements (11, 12), the semiconductor elements being mounted on the surface (S22) side of a heat sink (21, 22); a core layer (31) having one surface (S32) and an opposite surface (S31) to the one surface, with a through hole (311) extending from the one surface to the opposite surface, and the heat sink being positioned in the through hole; a build-up layer (32) provided opposite the surface and the one surface, having a resin portion (323) and wiring (33, 34) provided in the resin portion including a portion electrically connected to the semiconductor elements; and a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink, wherein the resin portion is provided so as to reach the back surface, and the opposite surface is provided flush with the back surface.

[0322] (Technical Idea J2) A method for manufacturing a semiconductor device, wherein the semiconductor device comprises: semiconductor elements (11, 12); heat sinks (21, 22) on which the semiconductor elements are mounted on the surface (S22) side; a core layer (31) having one surface (S32) and an opposite surface (S31) to the one surface, with a through hole (311) provided from the one surface to the opposite surface, and the heat sink being disposed in the through hole; a build-up layer (32) provided opposite the surface and the one surface, having a resin portion (323) and wiring (33, 34) provided on the resin portion including a portion electrically connected to the semiconductor element; and a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink, wherein the build-up layer is formed such that the resin portion is disposed between the heat sinks when a plurality of the heat sinks are connected by a connecting portion (210). A manufacturing method comprising forming the build-up layer, removing the heat sink from the back surface to form a flush back surface and the opposite surface, and cutting the connecting portion to separate it into multiple semiconductor devices.

[0323] (Eleventh Embodiment) The semiconductor device 111 of the eleventh embodiment will be described with reference to Figure 40. Figure 40 is a cross-sectional view corresponding to Figure 2. In this embodiment, the differences from the first embodiment will be mainly described. The eleventh embodiment differs from the first embodiment in that it is equipped with a thermal spray coating 64. Also, the eleventh embodiment has a different build-up layer 32 configuration from the first embodiment. However, the eleventh embodiment can also use the build-up layer 32 of the first embodiment. In the eleventh embodiment, the build-up layer 32 of the fourth or fifth embodiment can also be used.

[0324] In the 11th embodiment, the protective film 70 of the second embodiment may be provided. In the 11th embodiment, the built-in substrate 80 of the third embodiment may be provided. In the 11th embodiment, the sleeve 33t1 and terminal portion 33t2 of the fourth embodiment may be provided. In the 11th embodiment, the protective metal layer 90 of the fifth embodiment may be provided. In the 11th embodiment, the ceramic plate 41 of the sixth embodiment may be provided.

[0325] Furthermore, the 11th embodiment may include the insertion terminal portion 332a in the 7th embodiment. The 11th embodiment may also include the positioning marks 21b and 22b in the 8th embodiment. The 11th embodiment may also include the support column portion 36 in the 9th embodiment.

[0326] Incidentally, as an example of a semiconductor device, a configuration can be considered that includes a core layer, a heat sink on which semiconductor elements are mounted and positioned in through-holes of the core layer, a build-up layer provided on the core layer and heat sink, and a heat-dissipating insulating layer in contact with the back surface of the heat sink. Furthermore, the build-up layer includes a resin portion that is in contact with the heat sink and core layer.

[0327] In such semiconductor devices, the thermal expansion coefficients of the heat sink and the resin part differ significantly. Here, the thermal expansion coefficient is the thermal expansion coefficient in the thickness direction (lamination direction). Therefore, significant stress can occur at the interface between the heat sink and the resin part of the semiconductor device. Consequently, due to thermal stress during the manufacturing process and thermal stress over time during operation, cracks may develop in the heat dissipation insulating layer, potentially leading to a decrease in electrical insulation performance.

[0328] Therefore, the semiconductor device 111 aims to suppress a decrease in electrical insulation. As shown in Figure 40, the semiconductor device 111 has a configuration similar to the basic configuration of the semiconductor device 101.

[0329] Furthermore, as shown in Figure 40, the semiconductor device 111 is provided with a thermal spray coating 64 having electrical insulation and thermal conductivity, which is provided between the heat sinks 21 and 22 and the heat dissipation insulating layer 40.

[0330] In this embodiment, as an example, heat sinks 21 and 22 with chamfered corners 21r on the heat dissipation insulating layer 40 side are used. Specifically, heat sinks 21 and 22 have a configuration in which the corners 21r are R-chamfered. However, heat sinks 21 and 22 may also have a configuration in which the corners 21r are C-chamfered. Furthermore, as in the first embodiment, heat sinks 21 and 22 do not need to have chamfered corners.

[0331] The thermal spray coating 64 is a coating film formed using thermal spraying technology. In other words, the thermal spray coating 64 is formed on the surface of the heat sinks 21 and 22 with the material in a state of molten or semi-molten state at high temperature. The thermal spray coating 64 has air bubbles 64a. The material of the thermal spray coating 64 is, for example, aluminum nitride or silicon nitride.

[0332] The thermal spray coating 64 is provided at least on the opposite surface S21 of the heat sink. Preferably, the thermal spray coating 64 is also provided on the corners 21r of the heat sinks 21 and 22. The corners 21r can also be considered to be provided on the opposite surface S21 of the heat sink and on the heat sink sides of the heat sinks 21 and 22. Therefore, it can be said that the thermal spray coating 64 is provided not only on the opposite surface S21 of the heat sink but also on a part of the heat sink sides of the heat sinks 21 and 22. Note that the heat sink sides of the heat sinks 21 and 22 are surfaces that are continuous with the heat sink surface S22 and the opposite surface S21 of the heat sink.

[0333] Furthermore, the thermal spray coating 64 preferably has a thickness of, for example, 10 μm to 100 μm. The thickness is the length in the lamination direction.

[0334] Furthermore, the lower limit of the thermal spray coating thickness 64 is set to a thickness such that it is greater than the dielectric breakdown voltage of the thermal spray coating 64 relative to the breakdown voltage required for the semiconductor device 111. In other words, it is preferable that the thickness of the thermal spray coating 64 is such that dielectric breakdown does not occur.

[0335] On the other hand, the upper limit of the thermal spray coating 64 thickness is set to a thickness that can ensure the thermal conductivity required by the semiconductor device 111. In other words, the thickness of the thermal spray coating 64 is preferably such that it can ensure the heat dissipation of the semiconductor elements 11 and 12.

[0336] <Effects> As described above, the semiconductor device 111 is provided with a thermal spray coating 64 between the heat sinks 21 and 22 and the heat dissipation insulating layer 40. As a result, the semiconductor device 111 can maintain electrical insulation even if cracks occur in the heat dissipation insulating layer 40. Therefore, the semiconductor device 111 can suppress the decrease in electrical insulation compared to a configuration without the thermal spray coating 64.

[0337] The heat dissipation insulating layer 40 is more prone to cracking in areas close to the corners 21r of the heat sinks 21 and 22. However, the thermal spray coating 64 is also applied to the corners 21r of the heat sinks 21 and 22. Therefore, the semiconductor device 111 can suppress cracks in the heat dissipation insulating layer 40 from reaching the heat sinks 21 and 22. Thus, the semiconductor device 111 can suppress the decrease in electrical insulation performance more effectively than a configuration in which the thermal spray coating 64 is not applied to the corners 21r.

[0338] The thermal spray coating 64 contains air bubbles 64a. In this case, the thermal spray coating 64 can absorb the stress caused by the difference in thermal expansion coefficients between the heat sinks 21, 22 and the resin part 323. Therefore, the semiconductor device 111 can suppress the occurrence of cracks in the heat dissipation insulating layer 40 due to this stress. Thus, the semiconductor device 111 can suppress the decrease in electrical insulation performance more effectively than a configuration without the thermal spray coating 64. The thermal spray coating 64 has electrical insulation and thermal conductivity and can also be described as a stress-absorbing layer containing air bubbles 64a.

[0339] In this way, the semiconductor device 111 can ensure electrical insulation through the thermal spray coating 64. Therefore, the thickness of the heat dissipation insulating layer 40 can be reduced. As a result, cost reduction can be expected for the semiconductor device 111.

[0340] <Technical Idea Group K> (Technical Idea K1) A semiconductor device comprising semiconductor elements (11, 12), the semiconductor elements being mounted on the surface (S22) side of a heat sink (21, 22); a core layer (31) having one surface (S32) and an opposite surface (S31) of the one surface, with a through hole (311) extending from the one surface to the opposite surface, and the heat sink being positioned in the through hole; a build-up layer (32) provided opposite the surface and the one surface, having a resin portion (323) and wiring (33, 34) provided on the resin portion, including a portion electrically connected to the semiconductor elements; a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink; and a thermal spray coating (64) having electrical insulating and thermal conductive properties provided between the heat sink and the heat dissipation insulating layer.

[0341] (Technical Concept K2) The thermal spray coating has bubbles (64a) as described in Technical Concept K1.

[0342] (Technical Idea K3) The semiconductor device according to technical idea K1 or K2, wherein the thermal spray coating is aluminum nitride or silicon nitride.

[0343] (Technical Idea K4) The thermal spray coating has a film thickness of 10 μm to 100 μm, as described in any one of the technical ideas K1 to K3 for the semiconductor device.

[0344] (Technical idea K5) The semiconductor device according to any one of technical ideas K1 to K4, wherein the thermal spray coating is provided not only between the heat sink and the heat dissipation insulating layer, but also at the corner (21r) of the heat sink.

[0345] (Technical idea K6) The semiconductor device described in technical idea K5, wherein the corners are chamfered.

[0346] (Twelfth Embodiment) The semiconductor device 112 of the twelfth embodiment will be described with reference to Figures 41 to 43. Figure 41 is a cross-sectional view corresponding to Figure 2. Figures 42 and 43 are enlarged views of the core layer 31.

[0347] This embodiment mainly describes the differences from the first embodiment. The twelfth embodiment differs from the first embodiment in the configuration of the core layer 31. Also, the twelfth embodiment differs from the first embodiment in the configuration of the build-up layer 32. However, the twelfth embodiment can also use the build-up layer 32 from the first embodiment. The twelfth embodiment can also use the build-up layer 32 from the fourth or fifth embodiment.

[0348] Furthermore, the twelfth embodiment may include the protective film 70 of the second embodiment. The twelfth embodiment may include the built-in substrate 80 of the third embodiment. The twelfth embodiment may include the sleeve 33t1 and terminal portion 33t2 of the fourth embodiment. The twelfth embodiment may include the protective metal layer 90 of the fifth embodiment. The twelfth embodiment may include the ceramic plate 41 of the sixth embodiment.

[0349] Furthermore, the twelfth embodiment may include the insertion terminal portion 332a in the seventh embodiment. The twelfth embodiment may also include the positioning marks 21b and 22b in the eighth embodiment. The twelfth embodiment may also include the support column portion 36 in the ninth embodiment. The twelfth embodiment may also include the thermal spray coating 64 in the tenth embodiment.

[0350] Incidentally, as an example of a semiconductor device, a configuration can be considered that includes a core layer, a heat sink on which semiconductor elements are mounted and positioned in through-holes of the core layer, a build-up layer provided on the core layer and heat sink, and a heat-dissipating insulating layer in contact with the back surface of the heat sink. Furthermore, the build-up layer includes a resin portion that is in contact with the heat sink and core layer.

[0351] In such semiconductor devices, the thermal expansion coefficients of the heat sink and the core layer differ significantly. Here, the thermal expansion coefficient is the thermal expansion coefficient in the thickness direction (layering direction). Therefore, large forces can be generated at the interface between the heat sink and the resin part, and at the interface between the core layer and the resin part. Consequently, due to thermal stress during the manufacturing process and thermal stress over time during operation, cracks may develop in the heat dissipation insulating layer and the resin part between the core layer and the heat sink, potentially leading to a decrease in electrical insulation performance.

[0352] Therefore, the semiconductor device 112 aims to suppress a decrease in electrical insulation. As shown in Figure 41, the semiconductor device 112 has the same configuration as the basic configuration of the semiconductor device 101.

[0353] Furthermore, as shown in Figure 42, the core layer 31 is constructed by laminating a metal layer 31a and a glass cloth 31b. In other words, the core layer 31 has a metal layer 31a and a glass cloth 31b embedded in an electrically insulating resin. The metal layer 31a is mainly composed of a metal such as copper. Preferably, the metal layer 31a is made of the same material as the heat sinks 21 and 22. Alternatively, the metal layer 31a may be made of the same material as the pattern wiring 33. In this embodiment, as an example, a core layer 31 is used in which three metal layers 31a are laminated via resin and glass cloth 31b. However, the core layer 31 only needs to have one metal layer 31a and a glass cloth 31b embedded in an electrically insulating resin. Therefore, the core layer 31 may have two metal layers 31a or four or more metal layers 31a laminated together.

[0354] <Effects> As described above, the semiconductor device 112 has a core layer 31 in which a metal layer 31a and a glass cloth 31b are laminated. Therefore, the semiconductor device 112 can bring the thermal expansion coefficients of the core layer 31 and the heat sinks 21 and 22 closer together. In other words, the semiconductor device 112 can reduce the difference in thermal expansion coefficients between the core layer 31 and the heat sinks 21 and 22.

[0355] Therefore, the semiconductor device 112 can suppress the generation of large forces at the interface between the heat sinks 21, 22 and the resin portion 323, and at the interface between the core layer 31 and the resin portion 323. Furthermore, the semiconductor device 112 can suppress the occurrence of cracks in the heat dissipation insulating layer 40 and the resin portion 323 between the core layer 31 and the heat sinks 21, 22 due to thermal stress during the manufacturing process and thermal stress over time during operation. Consequently, the semiconductor device 112 can suppress a decrease in electrical insulation performance. In other words, the semiconductor device 112 can suppress a decrease in electrical insulation performance more effectively than a configuration with a core layer consisting only of resin and glass cloth.

[0356] <Modified Version> As shown in the modified version in Figure 43, the core layer 31 may include core layer vias 31c that connect adjacent metal layers 31a. The core layer vias 31c are filled vias or through vias. The modified semiconductor device 112 can reduce the difference in thermal expansion coefficients between the core layer 31 and the heat sinks 21, 22 compared to the twelfth embodiment. Therefore, the modified semiconductor device 112 can suppress the decrease in electrical insulation performance compared to the twelfth embodiment.

[0357] <Technical Idea Group L> (Technical Idea L1) A semiconductor device comprising semiconductor elements (11, 12), wherein the semiconductor elements are mounted on the surface (S22) side of a heat sink (21, 22); a core layer (31) having one surface (S32) and an opposite surface (S31) to the one surface, with a through hole (311) extending from the one surface to the opposite surface, and the heat sink being positioned in the through hole; a build-up layer (32) provided opposite the surface and the one surface, having a resin portion (323) and wiring (33, 34) provided on the resin portion, including a portion electrically connected to the semiconductor elements; and a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink, wherein the core layer is laminated with a metal layer (31a) and a glass cloth (31b).

[0358] (Technical Concept L2) The semiconductor device according to technical concept L1, wherein the core layer comprises a plurality of the metal layers stacked on top of each other, and further comprises core layer vias (31c) connecting the metal layers.

[0359] (Third Embodiment) The semiconductor device 1000 of the thirteenth embodiment will be described with reference to Figures 44 to 48. In this embodiment, the differences from the first embodiment will be mainly described. The thirteenth embodiment differs from the first embodiment in that, in addition to the semiconductor device 101, it is equipped with a cooler 300 and a fixing member 400. In this embodiment, a semiconductor device 1000 equipped with a semiconductor device 101 is used. However, the semiconductor device 1000 may be equipped with semiconductor devices 102 to 112 instead of semiconductor device 101. Note that in Figures 44, 47, etc., the illustration of each pad 331 to 337 has been omitted.

[0360] Incidentally, one possible configuration of a semiconductor device is one comprising a core layer, a heat sink on which semiconductor elements are mounted and positioned in through-holes of the core layer, a build-up layer provided on the core layer and the heat sink, and a heat-dissipating insulating layer in contact with the back surface of the heat sink. Another possible configuration of a semiconductor device is one comprising such a semiconductor device and a cooler on which the semiconductor device is mounted. The cooler is provided to improve the heat dissipation of the semiconductor device. However, further improvements in heat dissipation are desired for semiconductor devices.

[0361] Therefore, as shown in Figures 44 and 45, the semiconductor device 1000 includes a semiconductor device 101 and a cooler 300, as well as a fixing member 400 for fixing the semiconductor device 101 to the cooler 300. The semiconductor device 101 has a configuration similar to the basic configuration of the semiconductor device 101 described above.

[0362] In this embodiment, as an example, a semiconductor device 101 is used in which a surface metal layer 51 is provided on the opposite side of the back metal layer 50. The surface metal layer 51 is provided on the build-up layer 32. The surface metal layer 51 is the same as the surface metal layer 50t. Therefore, it can be said that the semiconductor device 101 has a double-sided heat dissipation structure with a back metal layer 50 and a surface metal layer 51. The back metal layer 50 corresponds to the back member. The surface metal layer 51 corresponds to the surface member.

[0363] The cooler 300 is mainly composed of metals such as aluminum and copper. The cooler 300 is made of a material with a higher thermal conductivity than the core layer 31. As shown in Figures 44 and 45, the cooler 300 includes a base 310 and a plurality of heat dissipation fins 320 provided on the base 310. The cooler 300 (base 310) has a mounting surface S301 on which the semiconductor device 101 is mounted and a surface S302 opposite to the mounting surface S301. The cooler 300 may also have a flow path for a coolant such as cooling water.

[0364] As shown in Figures 44 and 45, at least one semiconductor device 101 is mounted on the mounting surface S301. In this embodiment, as an example, an example in which three semiconductor devices 101 are mounted is adopted. The heat dissipation fins 320 are provided on the opposite surface S302. The heat dissipation fins 320 are portions that protrude from the opposite surface S302.

[0365] As shown in Figures 45 and 46, the semiconductor device 101 is mounted with its back metal layer 50 facing the mounting surface S301. The semiconductor device 101 is attached to the base 310 by adhesive 65. In other words, the back metal layer 50 is connected to the base 310 (mounting surface S301) by adhesive 65.

[0366] The adhesive 65 is preferably one with good thermal conductivity. For example, the adhesive 65 can be a TIM such as grease or a thermal conductive sheet. Alternatively, the adhesive 65 can be a bonding material (sintered material) made by sintering a paste of copper or silver at high temperatures. Furthermore, the adhesive 65 can be a bonding material that can be sintered at low temperatures without pressure, such as pressureless sintered Ag (silver). TIM is an abbreviation for Thermal Interface Material. The adhesive 65 can also be called a bonding material.

[0367] Note that the semiconductor device 101 does not necessarily have a back metal layer 50. In this case, the semiconductor device 101 has an adhesive 65 applied to the heat dissipation insulating layer 40. The heat dissipation insulating layer 40 is then connected to the base 310 by the adhesive 65. The adhesive 65 can be considered a back material.

[0368] As shown in Figure 46, the semiconductor device 101 and the cooler 300 may also be provided with mating portions 50a and 330 that fit together. The cooler 300 has a mating projection 330 that protrudes from the mounting surface S301 as a mating portion. The back metal layer 50 has a mating recess 50a into which the mating projection 330 is inserted as a mating portion. This allows the semiconductor device 1000 to improve the mounting accuracy of the semiconductor device 101 on the cooler 300.

[0369] The semiconductor device 101 may be provided with a fitting projection, and the cooler may be provided with a fitting recess. Furthermore, the semiconductor device 101 and the cooler 300 do not necessarily have fitting portions 50a and 330.

[0370] The fixing member 400 is a plate-shaped spring member. The fixing member 400 is a member for fixing the semiconductor device 101 to the cooler 300 by applying pressure to the semiconductor device 101 in the direction of the mounting surface S301. It can also be said that the fixing member 400 presses the semiconductor device 101 against the cooler 300 in the stacking direction. In other words, the semiconductor device 101 is attached to the cooler 300 by the fixing member 400. The semiconductor device 101 is sandwiched between the fixing member 400 and the cooler 300.

[0371] The fixing member 400 secures multiple semiconductor devices 101 to the cooler 300 all at once. However, the fixing member 400 may also secure only one semiconductor device 101 to the cooler 300.

[0372] The semiconductor device 101 and the cooler 300 are connected by an adhesive 65. Therefore, the fixing member 400 can also be described as a pressing member that presses the semiconductor device 101 against the cooler 300, or a pressurizing member that applies pressure to the semiconductor device 101 toward the cooler 300. Furthermore, the semiconductor device 101 is fixed to the cooler 300 by the fixing member 400. Therefore, the semiconductor device 1000 does not necessarily need to have an adhesive 65. Moreover, instead of the adhesive 65, the semiconductor device 1000 may be provided with a heat dissipation member that reduces the thermal resistance between the semiconductor device 101 and the cooler 300. The heat dissipation member may be grease or a thermal conductive sheet that does not have adhesive properties.

[0373] As shown in Figures 44 and 45, the fixing member 400 has a rectangular shape in plan view. The fixing member 400 has a contact portion 430 that contacts the surface of the semiconductor device 101 opposite to the back metal layer 50, and a plurality of connection portions 410 that are connected to the contact portion 430 and connected to the cooler 300. The fixing member 400 also has an intermediate portion 420 between the contact portion 430 and the connection portions 410. The intermediate portion 420 is connected to the contact portion 430 and the connection portions 410. In other words, the plurality of connection portions 410 are connected to the contact portion 430 via the intermediate portion 420.

[0374] The connecting portion 410 is connected to the base portion 310 by soldering or welding. The contact portion 430 is in contact with the surface metal layer 51, which is the side of the semiconductor device 101 opposite to the back metal layer 50.

[0375] With the fixing member 400 having its connecting portion 410 connected to the base portion 310, the contact portion 430 pressurizes the semiconductor device 101. It can also be said that the contact portion 430 is pressing the semiconductor device 101 toward the cooler 300 (base portion 310).

[0376] <Effects> In this way, the semiconductor device 1000 pressurizes the semiconductor device 101 against the cooler 300 using the fixing member 400. As a result, the semiconductor device 1000 can improve the degree of contact between the semiconductor device 101 and the cooler 300, and reduce the contact resistance between them. Therefore, the semiconductor device 1000 can improve the heat dissipation of the semiconductor device 101. In other words, the semiconductor device 1000 can improve heat dissipation compared to a configuration in which the semiconductor device 101 and the cooler 300 are only connected by adhesive 65.

[0377] Furthermore, if sinter material is used as the adhesive 65 in the semiconductor device 1000, the fixing member 400 can pressurize the adhesive 65 placed between the semiconductor device 101 and the cooler 300. As a result, the semiconductor device 1000 can properly connect the semiconductor device 101 and the cooler 300 with the adhesive 65. Thus, the semiconductor device 1000 can improve the heat dissipation of the semiconductor device 101.

[0378] <Modified Version> As shown in the modified versions in Figures 47 and 48, the semiconductor device 1000 may employ a plate-shaped wire member as the fixing member 500. The fixing member 500 has a rectangular shape in plan view. The fixing member 500 is a conductive material. The fixing member 500 is provided individually for each of the multiple semiconductor devices 101. Two fixing members 500 are provided for each semiconductor device 101. Note that three or more fixing members 500 may be provided for each semiconductor device 101. This improves the fixing force provided by the fixing member 500.

[0379] The semiconductor device 101 is fixed to the cooler 300 by at least two fixing members 500. The semiconductor device 101 has metal parts 33d to which the fixing members 500 are bonded. The metal parts 33d, like the pattern wiring 33, are patterned with a thin film (conductive material) such as copper. In other words, the metal parts 33d can be said to be a part that is electrically separated from the pattern wiring 33 by patterning. The metal parts 33d are exposed from the solder resist 35, etc., as in each pad 331 to 337.

[0380] As shown in Figure 48, the fixing member 500 is provided extending from the metal part 33d to the mounting surface S301. The fixing member 500 is connected to the metal part 33d and the mounting surface S301. The fixing member 500 is connected to the metal part 33d and the mounting surface S301 by, for example, a wedge bonding method. In this way, the fixing member 500 presses the semiconductor device 101 toward the mounting surface S301, fixing the semiconductor device 101 to the cooler 300. The fixing member 500, like the fixing member 400, can also be called a pressing member or a pressurizing member. The modified semiconductor device 1000 can achieve the same effects as the 13th embodiment.

[0381] <Technical Idea Group M> (Technical Idea M1) A semiconductor device comprising at least one semiconductor device (100-112) and a cooler (300) to which the semiconductor device is attached, wherein the semiconductor device comprises: semiconductor elements (11, 12); heat sinks (21, 22) on which the semiconductor elements are mounted on the surface (S22) side; a core layer (31) having one surface (S32) and an opposite surface (S31) of the one surface, with a through hole (311) provided from the one surface to the opposite surface, and the heat sink being placed in the through hole; a build-up layer (32) provided opposite the surface and the one surface, having a resin part (323) and wiring (33, 34) provided on the resin part and including a part electrically connected to the semiconductor element; and a heat dissipation insulating layer (40) in contact with the opposite surface and the back surface (S21) of the heat sink. A semiconductor device comprising: a back surface member (50) in contact with the heat dissipation insulating layer on the side opposite to the heat sink and in contact with the cooler, wherein the cooler has a mounting surface (S301) on which the semiconductor device is mounted, and further comprises fixing members (400, 500) for pressing the semiconductor device in the direction of the mounting surface to fix the semiconductor device to the cooler.

[0382] (Technical Concept M2) The semiconductor device according to technical concept M1, wherein the cooler and the back surface member are provided with fitting portions (50a, 330) that fit together with each other.

[0383] (Technical Concept M3) The semiconductor device according to technical concept M1 or M2, wherein the back surface member is an adhesive or a metal material.

[0384] (Technical Concept M4) The semiconductor device according to any one of Technical Concepts M1 to M3, wherein the fixing member is a plate-shaped spring member and comprises a contact portion (430) that contacts the surface of the semiconductor device opposite to the back surface member, and a plurality of connecting portions (410) connected to the contact portion and connected to the cooler.

[0385] (Technical Concept M5) The semiconductor device according to technical concept M4, wherein the fixing member fixes a plurality of the semiconductor devices to the cooler all at once.

[0386] (Technical Concept M6) The fixing member is a plate-shaped wire member, which is provided extending from a metal portion (33d) exposed on the side of the semiconductor device opposite to the back surface member to the mounting surface, and is connected to the metal portion and the mounting surface, according to any one of the technical concepts M1 to M3.

[0387] (Technical Concept M7) The semiconductor device according to any one of Technical Concepts M1 to M6, comprising a surface member (51) mainly composed of metal, provided on the side opposite to the back surface member.

Claims

A semiconductor device comprising semiconductor elements (11, 12), A heat sink (21, 22) on which the semiconductor element is mounted on the surface (S22) side, A core layer (31) having one surface (S32) and the opposite surface (S31) of the one surface, with a through hole (311) extending from the one surface to the opposite surface, and the heat sink being placed in the through hole, A heat dissipation insulating layer (40) that is in contact with the opposite surface and the back surface (S21) of the heat sink, The device comprises a resin portion (321, 322) provided opposite to the aforementioned surface and the aforementioned surface, and having at least one build-up layer (32) having a conductor pattern (33, 33a1, 33a2) and vias (34, 341, 342) provided on the resin portion and including a portion electrically connected to the semiconductor element, The aforementioned single build-up layer is A first layer having a first resin portion (321) which is part of the resin portion, a first conductor pattern (33a1, 33a2) which is part of the conductor pattern and provided on the first resin portion, and a first via (341) which is part of the via and provided on the first resin portion, A semiconductor device comprising: a second resin portion (322) which is part of the aforementioned resin portion; a second conductor pattern (33) which is part of the aforementioned conductor pattern and provided in the second resin portion; and a second via (342) which is part of the aforementioned via and provided in the second resin portion, and a second layer portion laminated on the first layer portion. 　 The first layer is thinner than the second layer. The semiconductor device according to claim 1, wherein the first layer and the second layer are stacked in that order from the surface and the one surface. 　 The second resin part contains an electrically insulating resin and glass cloth (322a), The semiconductor device according to claim 2, wherein the first resin part mainly consists of an electrically insulating resin. 　 The semiconductor device according to any one of claims 1 to 3, wherein the first conductor pattern has a current-carrying portion (33a2) electrically connected to the semiconductor element and a floating portion (33a1) electrically separated from the semiconductor element. 　 A semiconductor device according to any one of claims 1 to 3, wherein a plurality of the build-up layers are stacked. 　 The semiconductor element is a vertical semiconductor element, and has electrodes on both sides: an element-facing surface (S11) that faces the heat sink and an element surface (S12) that is the opposite side of the element-facing surface. The semiconductor device according to any one of claims 1 to 3, wherein the electrode on the element-facing surface is connected to the conductor pattern via the heat sink. 　 The two semiconductor elements, The system comprises two heat sinks on which two of the semiconductor elements are individually mounted, The core layer is provided with two through holes in which the two heat sinks are individually arranged. The semiconductor device according to any one of claims 1 to 3, wherein the conductor pattern electrically connects two semiconductor elements. 　 The heat sink is provided with a recess (213) that is recessed relative to the surface, The semiconductor element is mounted in the recess via a connecting member (60). The semiconductor device according to any one of claims 1 to 3, wherein the depth of the recess is shallower than the combined thickness of the semiconductor element and the connecting member.

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