Light detection device

Abstract

The present disclosure relates to a light detection device that makes it possible to electrically separate, from a substrate region of a pixel array region, a substrate region of a peripheral region in which a circuit region is formed. The light detection device comprises: a pixel array region which has a plurality of pixels arranged in a matrix manner; and a peripheral circuit region which is outward of the pixel array region. The pixel array region and the peripheral circuit region have a separation part in which a negative bias is applied to a first conductor layer inside a trench that is formed in a semiconductor substrate. The peripheral circuit region has, on the outer periphery of the separation part to which the negative bias is applied in plan view, a guard ring that is a separation part in which the negative bias is not applied to the first conductor layer inside the trench. The technology of the present disclosure is applicable to, for example, an imaging device that generates and outputs an imaging signal corresponding to the amount of incident light.

Description

Photodetector device

[0001] The present disclosure relates to a photodetector device, and particularly to a photodetector device configured to enable electrical isolation between a substrate region in a peripheral region where a circuit region is formed and a substrate region in a pixel array region.

[0002] Patent Document 1 discloses a photodetector device that suppresses the generation of dark current by embedding a conductor in a pixel isolation portion in the region between photoelectric conversion portions of a semiconductor substrate and applying a negative bias to the conductor.

[0003] Japanese Patent Application Laid-Open No. 2023-144526

[0004] When a circuit region is provided in a peripheral region outside the pixel array region in plan view, it is necessary to electrically isolate the substrate region of the peripheral region from the substrate region of the pixel array region.

[0005] The present disclosure has been made in view of such circumstances, and aims to enable electrical isolation between a substrate region of a peripheral region where a circuit region is formed and a substrate region of a pixel array region.

[0006] According to one aspect of the present disclosure, a photodetector device comprises: a pixel array region in which a plurality of pixels are arranged in a matrix; and a peripheral circuit region outside the pixel array region, wherein the pixel array region and the peripheral circuit region each include an isolation portion in which a negative bias is applied to a first conductor layer inside a trench formed in a semiconductor substrate, and the peripheral circuit region has, in plan view, a guard ring on an outer periphery of the isolation portion to which the negative bias is applied, wherein the guard ring is an isolation portion in which no negative bias is applied to the first conductor layer inside the trench.

[0007] In one aspect of the present disclosure, there are provided a pixel array region in which a plurality of pixels are arranged in a matrix, and a peripheral circuit region outside the pixel array region. The pixel array region and the peripheral circuit region are each provided with an isolation portion in which a negative bias is applied to a first conductor layer inside a trench formed in a semiconductor substrate. In the peripheral circuit region, a guard ring, which is an isolation portion to which no negative bias is applied to the first conductor layer inside the trench, is provided on an outer periphery of the isolation portion to which the negative bias is applied in plan view.

[0008] The light detection device may be a standalone device or a module incorporated into another device.

[0009] This figure shows a schematic configuration of a photodetector applying the technology of this disclosure. This figure shows the equivalent circuit of a pixel. This is a plan view of the photodetector. This is a cross-sectional view taken along the line X-X' in Figure 3. This is a plan view of Figure 3 with a light-shielding film and a light-shielding film contact area added. This is a plan view showing a modified example of the light-shielding film contact area. This is a cross-sectional view showing the detailed structure of the separation section. This is a cross-sectional view showing the detailed structure of the negative bias contact section. This is a cross-sectional view showing a first modified example of the negative bias contact section. This is a cross-sectional view showing a second modified example of the negative bias contact section. This is a plan view illustrating a modified example of the guard ring. This is a block diagram illustrating an example of the configuration of an electronic device applying the technology of this disclosure. This figure illustrates an example of the use of an image sensor.

[0010] The following describes embodiments for implementing the technology of this disclosure (hereinafter referred to as "embodiments") with reference to the attached drawings. The description will proceed in the following order: 1. Outline configuration example of the light detection device 2. Equivalent circuit of the pixel 3. Plan view of the light detection device 4. Cross-sectional view of the light detection device 5. Cross-sectional view of the separation section 6. Modified example of the guard ring 7. Summary 8. Example of the configuration of the electronic equipment 9. Example of the use of the image sensor

[0011] In this specification and the drawings, identical or similar parts are denoted by the same or similar reference numerals, thereby omitting redundant explanations as appropriate. The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings.

[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly.

[0013] The technology disclosed herein can be applied to a photodetector having a pixel array section in which pixels are arranged two-dimensionally in a matrix, and which converts incident light into photoelectric light and outputs a pixel signal corresponding to the amount of light. The light to be detected may be light in the visible light region including wavelengths such as R (Red), G (Green), and B (Blu), or it may be light in the invisible light region such as infrared light. Alternatively, it may be light from both the visible and invisible light regions. The photodetector can be used as an imaging device that generates and outputs an imaging signal corresponding to the amount of incident light, or as a light receiving device (distance measuring sensor) in a distance measuring system that receives light (reflected light) reflected from an object when infrared light is irradiated as active light, and measures the distance to the subject using a direct ToF (Time of Flight) or indirect ToF (Time of Flight) method.

[0014] <1. Schematic Configuration Example of a Photodetector> Figure 1 is a diagram showing an example of the functional configuration of a photodetector to which the technology of this disclosure is applied.

[0015] The photodetector 1 in Figure 1 is configured to have a pixel array region 3 in which a plurality of pixels 2 are arranged in a matrix on a semiconductor substrate 21 using silicon (Si) as the semiconductor, and a peripheral circuit region 42 (Figure 3). The peripheral circuit region 42 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

[0016] Pixel 2 consists of a photodiode, which is a photoelectric conversion unit, and a plurality of pixel transistors. The plurality of pixel transistors consist of, for example, four transistors: a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor, each of which is a MOS transistor (MOS FET).

[0017] Pixel 2 can also be a shared pixel structure. This shared pixel structure consists of multiple photodiodes, multiple transfer transistors, one shared floating diffusion transistor, and one shared other pixel transistor. In other words, in the shared pixel structure, each pixel 2 has a photodiode and a transfer transistor, and the other pixel transistors are shared and used by multiple pixels 2.

[0018] The control circuit 8 receives the input clock and data that commands the operating mode, and outputs data such as internal information of the light detection device 1. Based on the vertical synchronization signal, horizontal synchronization signal, and master clock, the control circuit 8 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc.

[0019] The vertical drive circuit 4 is configured, for example, by a shift register, and selects a predetermined pixel drive wiring 10, supplies pulses to the selected pixel drive wiring 10 to drive the pixels 2, and drives the pixels 2 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 2 in the vertical direction row by row, and supplies a signal based on the signal charge generated in the photoelectric conversion unit of each pixel 2 according to the amount of light received to the column signal processing circuit 5 through the vertical signal line 9.

[0020] The column signal processing circuit 5 is located for each column of pixels 2 and performs signal processing such as noise reduction on the signals output from each row of pixels 2 for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD conversion to remove pixel-specific fixed pattern noise.

[0021] The horizontal drive circuit 6 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 11.

[0022] The output circuit 7 processes the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 11 and outputs them. The output circuit 7 may, for example, only perform buffering, or it may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal section 13 exchanges signals with the outside.

[0023] The light detection device 1 configured as described above has a structure called a column AD method, in which column signal processing circuits 5 that perform CDS processing and AD conversion processing are arranged in each column. The light detection device 1 generates a signal corresponding to the amount of light received by each pixel 2 in the pixel array region 3 and outputs it to the outside. The light detection device 1 can be used, for example, as an imaging device that detects the distribution of incident light amounts of infrared light or visible light and captures it as an image, or as a light receiving device in a distance measuring system that receives light (reflected light) reflected from an object when infrared light is irradiated as active light, and measures the distance to the subject using a direct ToF method or an indirect ToF method.

[0024] <2. Equivalent Circuit of Pixel> Figure 2 shows the equivalent circuit of pixel 2.

[0025] Pixel 2 includes, for example, a photodiode PD which is a photoelectric conversion unit, a transfer transistor TG electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TG. Pixel 2 also includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. The transfer transistor TG, reset transistor RST, amplification transistor AMP, and selection transistor SEL are, for example, n-type MOS transistors (MOS FETs).

[0026] A photodiode (PD) converts incident light into electricity, generating an electric charge (signal charge) corresponding to the amount of incident light received. In a photodiode (PD), the cathode is electrically connected to the source of a transfer transistor (TG), and the anode is electrically connected to a reference potential line (e.g., ground).

[0027] The transfer transistor TG controls the transfer of charge generated by the photodiode PD. When the transfer transistor TG is turned ON, it transfers the charge generated by the photodiode PD to the floating diffusion FD. In the transfer transistor TG, the drain is electrically connected to the floating diffusion FD, and the gate is electrically connected to the pixel drive wiring. This pixel drive wiring is part of the pixel drive wiring 10 described in Figure 1.

[0028] The floating diffusion transistor (FD) is a charge storage unit that temporarily stores the charge transferred from the photodiode (PD), and also a charge-voltage conversion unit that generates a voltage corresponding to the amount of charge. The floating diffusion transistor (FD) is electrically connected to the gate of the amplification transistor (AMP) and the source of the reset transistor (RST).

[0029] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on by the pixel drive wiring supplied to the gate, it resets the potential of the floating diffusion FD to the potential of the power line VDD. This pixel drive wiring is part of the pixel drive wiring 10 described in Figure 1. When the potential of the floating diffusion FD is reset, the reset transistor RST is also controlled to be turned on at the same time.

[0030] The amplification transistor AMP generates a signal with a voltage corresponding to the level of charge accumulated in the floating diffusion FD as a pixel signal. The amplification transistor AMP is connected in series with the selection transistor SEL and is connected to the vertical signal line 9 via the selection transistor SEL. This amplification transistor AMP, together with the load circuit in the column signal processing circuit 5 connected to the vertical signal line 9, constitutes a source follower. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing circuit 5 via the vertical signal line 9. The drain of the amplification transistor AMP is connected to the power line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL.

[0031] The selection transistor SEL controls the output timing of the pixel signal. The source of the selection transistor SEL is connected to the vertical signal line 9, and the gate of the selection transistor SEL is connected to the pixel drive wiring. When the selection transistor SEL is turned on by the pixel drive wiring supplied to its gate, it outputs the pixel signal from the amplification transistor AMP to the vertical signal line 9. This pixel drive wiring is part of the pixel drive wiring 10 described in Figure 1.

[0032] The selection transistor SEL may be located between the power line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP. The source of the amplification transistor AMP (the output terminal of pixel 2) is electrically connected to the vertical signal line 9, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

[0033] The pixel 2, configured as described above, converts incident light into photoelectric light according to the control of the vertical drive circuit 4, and outputs a pixel signal corresponding to the amount of light received to the column signal processing circuit 5 via the vertical signal line 9.

[0034] <3. Plan view of the light detection device> Figure 3 is a plan view of the light detection device 1.

[0035] The photodetector 1 is composed of a semiconductor chip using a single semiconductor substrate 21, and has a pixel array region 3 in an inner rectangular area when viewed from above, a peripheral circuit region 42 outside of that, and a pad region 43 in the outer peripheral area. The photodetector 1 can also be composed of a semiconductor chip with a stacked structure in which one or two other semiconductor substrates are stacked on a single semiconductor substrate 21.

[0036] Multiple pixels 2 are arranged in a matrix within the pixel array region 3. As will be described later in Figure 4, the pixels 2 in the pixel array region 3 include normal pixels 2A that output a pixel signal corresponding to the amount of incident light, and OPB pixels 2B whose light incident surface is covered with a light-shielding film 103 and which output a pixel signal that corresponds to a reference black level.

[0037] A peripheral circuit region 42, located between the pixel array region 3 and the pad region 43, contains at least a portion of logic circuits such as a vertical drive circuit 4 and a horizontal drive circuit 6. The logic circuits include elements such as diodes, transistors, MOS capacitors, and MIM capacitors (hereinafter referred to as peripheral elements). A guard ring 71 is provided on the inner side of the peripheral circuit region 42, close to the pixel array region 3, so as to surround the outer periphery of the pixel array region 3. The guard ring 71 electrically isolates a predetermined potential (e.g., negative bias) applied to the pixel isolation portion of the pixel array region 3 so as not to affect the outer peripheral elements. Outside the guard ring 71, a dummy pixel region 72 is provided, which has a pixel isolation portion similar to that of the pixels 2 in the pixel array region 3.

[0038] Multiple electrode pads 91 are arranged in the pad area 43. In Figure 1, the multiple electrode pads 91 in the pad area 43 correspond to the input / output terminal section 13. The example in Figure 3 shows an example in which multiple electrode pads 91 are arranged on each side of a rectangular semiconductor chip, but it is sufficient for multiple electrode pads 91 to be arranged in a row along at least one of the four sides of the rectangle. A pad guard ring 92 is provided around each electrode pad 91. A scribe guard ring 93, which is a guard ring for scribing, is provided on the outermost periphery of the pad area 43.

[0039] <4. Cross-sectional view of the photodetector> Figure 4 is a cross-sectional view taken along the X-X' line in Figure 3.

[0040] As explained in Figure 3, the pixel array region 3, peripheral circuit region 42, and pad region 43 are arranged in the order of pixel array region 3, peripheral circuit region 42, and pad region 43 from the center outward of the semiconductor chip (semiconductor substrate 21). The pixel array region 3 has an effective pixel region 41A where a plurality of normal pixels 2A are arranged, and an OPB region 41B where a plurality of OPB pixels 2B are arranged.

[0041] In FIG. 4, the first surface FA, which is the upper surface of the semiconductor substrate 21, is the back surface of the semiconductor substrate 21 and serves as a light incident surface through which light enters. The second surface FB opposite to the first surface FA of the semiconductor substrate 21 is the front surface of the semiconductor substrate 21 on which the wiring layer 22 is formed.

[0042] On the first surface FA, which is the light incident surface of the semiconductor substrate 21, an antireflection film 101 and an insulating film 102 are formed in a stacked manner, and a light shielding film 103 is further formed on the upper surface of the insulating film 102. The antireflection film 101 is composed of an oxide film such as hafnium oxide (HfO2), aluminum oxide (Al2O3), or titanium oxide (TiO2), for example. The insulating film 102 is composed of an oxide film such as silicon oxide (SiO2), for example. A metal material such as tungsten (W), aluminum (Al), or copper (Cu) is used as the material of the light shielding film 103, for example. In the effective pixel region 41A, the light shielding film 103 is provided only at pixel boundary portions, and is formed over the entire region in the OPB region 41B and the peripheral circuit region 42. A light shielding film contact region 104 is provided at a predetermined position in the peripheral circuit region 42. In the light shielding film contact region 104, the antireflection film 101 and the insulating film 102 are not formed on the semiconductor substrate 21, and the light shielding film 103 is directly connected to the substrate region 141 of the semiconductor substrate 21.

[0043] Although a color filter layer and an on-chip lens are formed further above the light shielding film 103 on the first surface FA side of the semiconductor substrate 21, their illustration is omitted.

[0044] The wiring layer 22 formed on the second surface FB side of the semiconductor substrate 21 includes a plurality of layers of metal wiring 121 and an interlayer insulating film 122. The metal wiring 121 is formed of a metal film such as copper (Cu), tungsten (W), aluminum (Al), or gold (Au), for example. The interlayer insulating film 122 is formed of, for example, silicon oxide (SiO2) or the like. In FIG. 4, only two layers of the plurality of layers of metal wiring 121 that are close to the semiconductor substrate 21 are shown, but the number of stacked layers of the metal wiring 121 is three or more.

[0045] In the semiconductor substrate 21 of the pixel array region 3, a photodiode PD is formed for each pixel 2 by forming an N-type semiconductor region 142 for each pixel in a substrate region 141 formed of a P-type semiconductor region. The N-type semiconductor region 142 is a charge storage region that stores the charge converted by photoelectricity. The photodiode PD is physically and electrically separated from adjacent pixels by a separation section 151 formed in a grid pattern in a plan view, and the separation section 151 constitutes a pixel separation section that separates the pixels 2. The detailed structure of the separation section 151 will be described later in Figure 7, but the separation section 151 is constructed by embedding a conductor layer inside a trench, and a negative bias is applied to the embedded conductor layer.

[0046] In the pixel array region 3, a pixel transistor Tr is formed at the interface of the second surface FB of the semiconductor substrate 21 that is in contact with the wiring layer 22. This transistor performs functions such as reading out the charge accumulated in the photodiode PD of each pixel 2. The pixel transistor Tr is one of the transfer transistor TG, reset transistor RST, amplification transistor AMP, and selection transistor SEL as described in Figure 2.

[0047] In the peripheral circuit region 42, on the side of the pixel array region 3, a separation portion 151 similar to the separation portion 151 formed in the pixel array region 3 is formed. In a cross-sectional view, a negative bias is supplied from the contact electrode 123 of the wiring layer 22 to the conductor layer inside the trench to a predetermined separation portion 151A, which is one of the multiple separation portions 151 formed in the planar direction (lateral direction in Figure 4), thereby applying a negative bias to the interior of each separation portion 151 in the peripheral circuit region 42 and the pixel array region 3. The detailed structure of the separation portion 151A, which is a negative bias contact portion, will be described later in Figure 8.

[0048] The guard ring 71 is formed on the outer side in the planar direction of the plurality of isolation portions 151 provided in the peripheral circuit region 42. The guard ring 71 is configured in the same manner as the isolation portions 151 except that no negative bias is applied to the conductor layer inside the trench. Further outside the guard ring 71 in the planar direction, a plurality of isolation portions 152 forming a dummy pixel region 72 are provided. The isolation portions 152 of the dummy pixel region 72 are also configured in the same manner as the isolation portions 151 except that no negative bias is applied to the conductor layer inside the trench.

[0049] Each of the isolation portions 151, the guard ring 71, and the isolation portions 152 is formed to have the same structure except for whether a negative bias is applied to the conductor layer inside the trench (the first conductor layer 212 described later in FIGS. 7 and 8). The guard ring 71 and the isolation portions 152 in the peripheral circuit region 42 are formed at the same pitch (pixel pitch) as the isolation portions 151 in the pixel array region 3. Accordingly, the isolation portions 151, the guard ring 71, and the isolation portions 152 can be formed by the same process.

[0050] The GND potential is supplied from the contact electrode 124 of the wiring layer 22 to the substrate region 141 in the dummy pixel region 72, and the substrate region 141 labeled "GND" in FIG. 4 is set to the GND potential. A light-shielding film contact region 104 is provided on the first surface FA of the semiconductor substrate 21 in the dummy pixel region 72, and the light-shielding film 103 is directly connected to the substrate region 141 set to the GND potential, whereby the light-shielding film 103 is controlled to the GND potential.

[0051] On the other hand, the substrate region 141 labeled "Flo" on the pixel array region 3 side of the dummy pixel region 72 is a high-resistance region that is electrically floating. The substrate regions 141 on both sides of the guard ring 71 are also electrically floating regions. The substrate regions 141 on both sides of the isolation portion 151A to which a negative bias is supplied from the contact electrode 123 of the wiring layer 22 may be floating, or may be set to a negative bias to reinforce the negative bias in the isolation portion 151.

[0052] On the second surface FB side of the semiconductor substrate 21 outside the guard ring 71 within the peripheral circuit region 42, a circuit region 73 is provided in which one or more peripheral elements constituting logic circuits such as a vertical drive circuit 4 and a horizontal drive circuit 6 are formed. Furthermore, if the semiconductor chip as the photodetector 1 is composed of a stacked structure of multiple semiconductor substrates, a portion of the logic circuits, including the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, output circuit 7, and control circuit 8, are also formed on the other semiconductor substrate stacked with the semiconductor substrate 21.

[0053] The pad region 43 includes a pad opening 94 and a pad guard ring 92 provided around the pad opening 94. The pad opening 94 penetrates the semiconductor substrate 21 to an electrode pad 91 formed in the wiring layer 22. The electrode pad 91, exposed at the bottom of the pad opening 94, is electrically connected to the outside by bonding wires or the like.

[0054] In the photodetector 1, as described above, a guard ring 71 to which a negative bias is not applied is provided outside the pixel array region 3, which has a separation section 151 to which a negative bias is applied, thereby electrically separating the substrate region 141 of the circuit region 73 from the substrate region 141 of the pixel array region 3.

[0055] Furthermore, the light detection device 1 is configured to electrically float the substrate regions 141 on both sides of the guard ring 71, and to set the substrate region 141 further outside the floating substrate region 141 to GND potential. This allows peripheral elements to be placed in the circuit region 73 without worrying about negative bias. Since there is no need to form an electrical isolation structure to prevent well potential short circuits when placing peripheral elements, the electrical isolation structure does not become complex, and the chip size can be reduced when forming a logic circuit of the same scale.

[0056] In the light detection device 1, the light-shielding film 103 formed on the light incident surface side of the semiconductor substrate 21 is electrically isolated from the conductor layer in the isolation section 151 to which a negative bias is applied, so that the light-shielding film 103 is not negatively biased. This prevents the occurrence of an output difference due to the influence of a negative bias between the effective pixel region 41A, where the light-shielding film 103 is formed only at the pixel boundary, and the OPB region 41B, where it is formed over the entire pixel region.

[0057] In the photodetector 1, each electrode pad 91 of the pad region 43 is provided on the wiring layer 22 side of the semiconductor substrate 21, rather than on the light incident surface side. If the electrode pads 91 are provided on the light incident surface side of the semiconductor substrate 21, the probe may be damaged or stressed, or parasitic capacitance may occur between the semiconductor substrate 21 and the electrode pads 91. By providing the electrode pads 91 on the wiring layer 22 side of the semiconductor substrate 21, these effects can be avoided.

[0058] Figure 5 is a diagram that further shows the light-shielding film 103 and the light-shielding film contact area 104 in addition to the plan view shown in Figure 3. In Figure 5, the light-shielding film 103 formed on the insulating film 102 is indicated by broad hatching.

[0059] As shown in Figure 5, the light-shielding film contact region 104 is positioned to surround the pixel array region 3, overlapping with the dummy pixel region 72 of the peripheral circuit region 42.

[0060] Alternatively, the light-shielding contact regions 104 may be intermittently arranged in positions that overlap with the dummy pixel regions 72 of the peripheral circuit region 42, as shown in Figure 6. In Figure 6, the light-shielding contact regions 104 are arranged to surround the pixel array region 3 in a dashed line pattern with predetermined spacings. In regions where the light-shielding film 103 is not directly connected to the first surface FA of the semiconductor substrate 21, the light-shielding film 103 is formed on the upper surface of the anti-reflective film 101 and the insulating film 102, similar to other regions of the peripheral circuit region 42.

[0061] <5. Cross-sectional view of the separation section> Figure 7 is a cross-sectional view showing the detailed structure of the separation section 151 provided in the pixel array area 3 and the peripheral circuit area 42.

[0062] The separation section 151 includes a first trench 201 on the first surface FA side of the semiconductor substrate 21 and a second trench 202 on the second surface FB side. The semiconductor substrate 21 is penetrated by the first trench 201 and the second trench 202, and the substrate region 141 of each pixel 2 is physically and electrically isolated. The connection section 203 between the first trench 201 and the second trench 202 is provided at a position closer to the second surface FB than to the first surface FA of the semiconductor substrate 21. The opening width (opening area) of the first trench 201 is narrower than the opening width of the second trench 202. The first trench 201 has a shape without a taper where the opening width is the same at any depth position, but it may also be a trench with a forward taper shape where the opening width gradually decreases from the first surface FA to the second surface FB side of the semiconductor substrate 21. The second trench 202 is also a trench with the same opening width at any depth position, but it may also be a trench with a tapered shape.

[0063] Inside the first trench 201, a first insulating layer 211, a first conductor layer 212, a second insulating layer 213, and an air gap 214 are provided, extending inward from the side wall. In other words, the air gap 214 is located in the center of the width of the first trench 201, the second insulating layer 213 is provided on both sides of the air gap 214, the first conductor layer 212 is provided on both sides of the second insulating layer 213, and the first insulating layer 211 is provided on both sides of the first conductor layer 212. The second trench 202 has the first insulating layer 211 and the first conductor layer 212 on the side facing the first trench 201, and an insulating layer 215 on the second surface FB side. For the first insulating layer 211 and first conductor layer 212 on the first trench 201 side, the first insulating layer 211 is formed on the side wall side, and the first conductor layer 212 is embedded inside the first insulating layer 211. The first insulating layer 211 of the first trench 201 and the first insulating layer 211 of the second trench 202 are formed simultaneously. For the materials of the first insulating layer 211 in the first trench 201, the second insulating layer 213, and the insulating layer 215 on the second surface FB side, for example, SiO2, SiC, SiON, etc. can be used. The material of the insulating layer 215 may also be a high-dielectric constant (High-k) insulating material. Examples of high-dielectric constant insulating materials include hafnium oxide (HfO2), aluminum oxide (Al2O3), titanium oxide (TiO2), and STO (Strontium Titanium Oxide). For the first conductive layer 212, silicon materials doped with impurities such as BDAS (Bron Doped Amorphous Silicon), PDAS (Phosphorus Doped Amorphous Silicon), and B-poly (Bron Doped Poly-silicon) can be used.

[0064] Figure 8 is a cross-sectional view showing the detailed structure of the isolation section 151A, which is a negative bias contact section to which a negative bias is supplied from the wiring layer 22, among the isolation sections 151 provided in the pixel array region 3 and the peripheral circuit region 42.

[0065] Compared to the separation section 151 described in Figure 7, the isolation section 151A, which is a negative bias contact section, has a second conductor layer 216 instead of the insulating layer 215 embedded in the second trench 202 on the second surface FB side. The other configurations are the same as those of the separation section 151 described in Figure 7. The second conductor layer 216 is connected to the contact electrode 123 of the wiring layer 22, and the negative bias supplied via the metal wiring 121 and the contact electrode 123 is supplied to the second conductor layer 216 and the first conductor layer 212 inside the trench of the separation section 151A.

[0066] (First Modified Example) Figure 9 is a cross-sectional view showing a first modified example of the separation section 151A, which is the negative bias contact section.

[0067] In the separation section 151A shown in Figure 8, the contact electrode 123 of the wiring layer 22 was directly connected to the second conductor layer 216 embedded in the second trench 202 on the second surface FB side. In contrast, in the first modified example shown in Figure 9, a P-type high-concentration semiconductor region (P-type diffusion layer) 221 is formed in a region adjacent to the second conductor layer 216, having the same conductivity type as the substrate region 141 but with a higher impurity concentration than the substrate region 141, and the contact electrode 123 of the wiring layer 22 is connected to this P-type high-concentration semiconductor region 221. The negative bias is supplied from the contact electrode 123 to the P-type high-concentration semiconductor region 221, and then supplied to the first conductor layer 212 via the P-type high-concentration semiconductor region 221 and the second conductor layer 216.

[0068] (Second Modification) Figure 10 is a cross-sectional view showing a second modification of the separation section 151A, which is the negative bias contact section.

[0069] The second modified example shown in Figure 10 illustrates a configuration example where a negative bias is supplied from the first surface FA side of the semiconductor substrate 21. The through-electrode 231 is a silicon through-silicon electrode (TSV) that penetrates the semiconductor substrate 21 and connects to the metal wiring 121 of the wiring layer 22. The contact electrode 232 is formed in a region overlapping with the first trench 201 on the first surface FA side of the semiconductor substrate 21 and connects to the first conductor layer 212 in the separation section 151A. The connecting electrode 233 connects the through-electrode 231 and the contact electrode 232. As a result, the negative bias supplied to the metal wiring 121 of the wiring layer 22 is extracted to the first surface FA side of the semiconductor substrate 21 using the through-electrode 231 and applied to the first conductor layer 212 of the separation section 151A via the connecting electrode 233 and the contact electrode 232.

[0070] <6. Modified Guard Rings> Next, modified guard rings 71 will be described with reference to Figures 11 and 12.

[0071] Figures 11A to D and 12A and B are plan views showing one corner of a guard ring 71, which has a roughly rectangular shape in plan view.

[0072] Figure 11A is a plan view of the corner of the guard ring 71 described in Figure 3. The width of the guard ring 71 can be the same as that of the pad guard ring 92 and the scribe guard ring 93. This shape and arrangement of the guard ring 71 is referred to as the basic shape of the guard ring 71.

[0073] Figure 11B is a first modified example of the guard ring 71, and is a plan view showing an example in which the basic shape of Figure 11A is arranged in three layers. In this example, the basic shape of the guard ring 71 is arranged in three layers, but it may be any other number of layers, such as n layers (n > 1).

[0074] Figure 11C is a plan view showing a second modified example of the guard ring 71. In the second modified example, the corners of the basic shape shown in Figure 11A are rounded off, and the guard ring 71 is formed so that the corners do not intersect at 90 degrees but are connected at obtuse angles.

[0075] Figure 11D is a plan view showing a third modified example of the guard ring 71. The guard ring 71 of the third modified example has a cross shape in which the straight portion of the basic shape A in Figure 11 protrudes by a predetermined amount at the corners.

[0076] Figure 12A is a plan view showing a fourth modified example of the guard ring 71. The guard ring 71 of the fourth modified example is formed in a ladder shape by repeatedly extending rectangles at equal pitches. The repeating pitch of the rectangles forming the ladder shape is set to be the same as, for example, the pitch of pixel 2 (pixel pitch).

[0077] Figure 12B is a plan view showing a fifth modified example of the guard ring 71. The guard ring 71 of the fifth modified example is formed in a ladder shape with rectangles repeatedly extended at equal pitches, and at the corners of the rectangles that are repeated at equal pitches, it has cross portions that protrude by a predetermined amount in a direction perpendicular to the extension direction that circles the pixel array region 3. The repeating pitch of the rectangles that form the ladder shape is set to be the same as, for example, the pitch of the pixels 2 (pixel pitch).

[0078] <7. Summary> As described above, the light detection device 1 has a pixel array region 3 in which a plurality of pixels 2 are arranged in a matrix, a peripheral circuit region 42 outside the pixel array region 3, and a pad region 43 located on the outer periphery. The pixel array region 3 and the peripheral circuit region 42 have isolation portions 151 to which a negative bias is applied to the first conductor layer 212 inside a trench formed in the semiconductor substrate 21. In a plan view, the peripheral circuit region 42 has a guard ring 71 on the outer periphery of the isolation portion 151 to which a negative bias is applied, which is an isolation portion 151 to which a negative bias is not applied to the first conductor layer 212 inside the trench. This makes it possible to electrically separate the substrate region 141 of the peripheral circuit region 42 in which the circuit region 73 is formed from the substrate region 141 of the pixel array region 3.

[0079] The separation section 151, guard ring 71, and separation section 152 are arranged in the planar direction of the semiconductor substrate 21 at the same pitch as the pixel pitch, with the separation section 152 positioned on the opposite side of the separation section 151, with the guard ring 71 as the boundary. Multiple separation sections 152 arranged at the same pitch as the pixel pitch constitute a dummy pixel region 72. Since the separation section 151, guard ring 71, and separation section 152 are formed with the same structure except for whether or not a negative bias is applied to the first conductor layer 212 inside the trench, it can be said that the first separation section, second separation section, and third separation section, all of the same structure, are arranged continuously at the pixel pitch from the pixel array region 3 side.

[0080] In the light detection device 1, the light-shielding film 103 formed on the light incident surface side of the semiconductor substrate 21 is electrically isolated from the first conductor layer 212 in the isolation section 151 to which a negative bias is applied, so that the light-shielding film 103 is not negatively biased. This prevents the occurrence of an output difference due to the influence of a negative bias between the effective pixel region 41A, where the light-shielding film 103 is formed only at the pixel boundary, and the OPB region 41B, where it is formed over the entire pixel region.

[0081] <8. Examples of Electronic Device Configurations> The light detection device 1 described above can be applied to various electronic devices, such as imaging systems like digital still cameras and digital video cameras, mobile phones equipped with imaging functions, or other devices equipped with imaging functions.

[0082] Figure 13 is a block diagram showing an example of the configuration of an electronic device.

[0083] As shown in Figure 13, the electronic device 301 comprises an optical system 302, a light detection device 303, a DSP (Digital Signal Processor) 304, a display device 305, an operating system 306, a memory 307, a recording device 308, and a power supply system 309. The DSP 304, display device 305, operating system 306, memory 307, recording device 308, and power supply system 309 are interconnected via a bus 310. The electronic device 301 is, for example, an imaging device capable of capturing still images and moving images.

[0084] The optical system 302 is composed of one or more lenses and guides the image light (incident light) from the subject to the light detection device 303, where it forms an image on the light-receiving surface (sensor part) of the light detection device 303.

[0085] The configuration of the photodetector 1 described above is applied to the photodetector 303. In the photodetector 303, electrons as signal charges are accumulated for a certain period of time according to the image formed on the light-receiving surface via the optical system 302. Then, a signal corresponding to the electrons accumulated in the photodetector 303 is supplied to the DSP 304.

[0086] The DSP 304 performs various signal processing on the signal from the light detection device 303 to generate an image, and temporarily stores the image data in the memory 307. The image data stored in the memory 307 is recorded in the recording device 308 or supplied to the display device 305 to display the image. The operation system 306 receives various operations from the user and supplies operation signals to each block of the electronic equipment 301, and the power supply system 309 supplies the power necessary to drive each block of the electronic equipment 301.

[0087] In the electronic device 301 configured in this way, by applying the above-described photodetector 1 as the photodetector 303, the substrate region 141 of the peripheral circuit region 42 where the circuit region 73 is formed can be electrically isolated from the substrate region 141 of the pixel array region 3. This allows peripheral elements to be arranged in the circuit region 73 without worrying about negative bias. The chip size of the photodetector 1, which is a semiconductor chip, can be reduced. Furthermore, since the light-shielding film 103 does not have a negative bias, it is possible to prevent output differences caused by the negative bias between the effective pixel region 41A and the OPB region 41B. As a result, even in the electronic device 301, high-quality captured images can be generated while maintaining miniaturization.

[0088] <9. Example of Image Sensor Use> Figure 14 shows an example of use when the above-mentioned light detection device 1 is an image sensor.

[0089] If the above-mentioned light detection device 1 is an image sensor, it can be used in various cases to sense light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0090] - Devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions. - Devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. - Devices used in home appliances such as TVs, refrigerators, and air conditioners that capture user gestures and allow device operation according to those gestures. - Devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception. - Devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition. - Devices used for beauty purposes, such as skin measuring devices that capture images of skin and microscopes that capture images of the scalp. - Devices used for sports purposes, such as action cameras and wearable cameras for sports use. - Devices used for agriculture, such as cameras that monitor the condition of fields and crops.

[0091] In the example described above, a photodetector was described in which the first conductivity type was P-type and the second conductivity type was N-type, and electrons were used as the signal charge. However, this disclosure can also be applied to a photodetector that uses holes as the signal charge. In this case, the first conductivity type can be N-type and the second conductivity type can be P-type, and the aforementioned semiconductor regions can be composed of semiconductor regions of the opposite conductivity types.

[0092] The technology disclosed herein is not limited to applications to photodetectors that detect the distribution of incident light intensity of visible light and capture it as an image, but is also applicable to photodetectors that capture the distribution of incident amounts of infrared rays, X-rays, or particles as an image, and in a broader sense, to all photodetectors (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance and capture it as an image.

[0093] In this specification, a system means a collection of multiple components (devices, modules (parts), etc.), regardless of whether all components are located in the same enclosure. Therefore, multiple devices housed in separate enclosures and connected via a network, and a single device containing multiple modules in one enclosure, are both considered systems.

[0094] The embodiments of the technology described herein are not limited to those described above, and various modifications are possible without departing from the spirit of the technology described herein.

[0095] The effects described herein are merely illustrative and not limiting; other effects may also occur.

[0096] The technology of this disclosure may adopt the following configurations: (1) A photodetector having a pixel array region in which a plurality of pixels are arranged in a matrix, and a peripheral circuit region outside the pixel array region, wherein the pixel array region and the peripheral circuit region have isolation portions to which a negative bias is applied to a first conductor layer inside a trench formed in a semiconductor substrate, and the peripheral circuit region has, in plan view, a guard ring on the outer periphery of the isolation portion to which the negative bias is applied, which is an isolation portion to which a negative bias is not applied to the first conductor layer inside the trench. (2) The photodetector according to (1), wherein, in plan view, the peripheral circuit region further has a circuit region on the outer periphery of the guard ring having one or more elements constituting a logic circuit. (3) The photodetector according to (1) or (2), wherein the separation portion of the pixel array region is a pixel separation portion that separates a photoelectric conversion portion consisting of a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type opposite to the first conductivity type for each pixel, the semiconductor region of the second conductivity type is a charge storage region that stores the photoelectrically converted charge, and a negative bias is supplied from the wiring layer to the first conductor layer inside the trench of one predetermined separation portion of the peripheral circuit region, and the substrate regions on both sides of the predetermined separation portion are semiconductor regions of the first conductivity type. (4) The photodetector according to any one of (1) to (3), wherein a negative bias is supplied from the wiring layer to the first conductor layer inside the trench of one predetermined separation portion of the peripheral circuit region, so that a negative bias is applied to the pixel array region inside the guard ring and the first conductor layer inside the trench of the separation portion of the peripheral circuit region in a plan view. (5) The photodetector according to (4), configured such that a negative bias is applied to a substrate region adjacent to one predetermined separation portion to which a negative bias is supplied from the wiring layer in a plan view. (6) The photodetector according to (4), having electrically floating substrate regions on the outside and inside of one predetermined separation portion to which a negative bias is supplied from the wiring layer in a plan view. (7) The photodetector according to any one of (1) to (6), wherein the substrate region adjacent to the guard ring in a plan view is an electrically floating region.(8) The optical detection device according to any one of (1) to (7), wherein the peripheral circuit region further has, in plan view, an isolation portion outside the guard ring to which a negative bias is not applied to the first conductor layer inside the trench. (9) The optical detection device according to any one of (1) to (8), wherein, in plan view, the peripheral circuit region outside the guard ring has a dummy pixel region having a plurality of isolation portions to which the negative bias is not applied, and the pitch of the plurality of isolation portions in the dummy pixel region is the same as the pitch of the isolation portions in the pixel array region. (10) The optical detection device according to (9), wherein the substrate region between the plurality of isolation portions in the dummy pixel region is a semiconductor region to which a GND potential is applied. (11) The optical detection device according to (10), wherein the semiconductor substrate has a light-shielding film on the light incident surface side, and the light-shielding film is directly connected to the substrate region of the dummy pixel region to which a GND potential is applied. (12) The light-shielding film contact area to which the light-shielding film and the substrate region to which the GND potential is applied is arranged to encircle the pixel array region, as described in (11). (13) The light-shielding film contact area to which the light-shielding film and the substrate region to which the GND potential is applied is arranged to intermittently surround the pixel array region, as described in (11). (14) The light-shielding film contact area to which the light-shielding film and the substrate region to which the GND potential is applied is arranged to intermittently surround the pixel array region, as described in (1) to (13).(15) The photodetector according to any one of (1) to (13), wherein the negative bias contact portion, which is an isolation portion of the peripheral circuit region into which a negative bias is supplied from the wiring layer to the first conductor layer inside the trench, has a second conductor layer embedded in a trench formed on the second surface side opposite to the first surface which is the light incident surface of the semiconductor substrate, and the semiconductor substrate has a high-concentration semiconductor region adjacent to the second conductor layer of the negative bias contact portion and having a higher impurity concentration than the substrate region, and the negative bias supplied from the wiring layer to the high-concentration semiconductor region is supplied to the first conductor layer via the second conductor layer of the negative bias contact portion. (16) The photodetector according to any one of (1) to (13), wherein the photodetector has a through electrode that penetrates the second surface opposite to the first surface which is the light incident surface of the semiconductor substrate, and the negative bias extracted to the first surface side of the semiconductor substrate using the through electrode is applied to the first conductor layer of the negative bias contact portion, which is an isolation portion of the peripheral circuit region into which a negative bias is supplied from the wiring layer to the first conductor layer inside the trench. (17) The light detection device according to any one of (1) to (16), wherein the guard ring is formed in n layers (n>1) on the outer periphery of the pixel array region. (18) The light detection device according to any one of (1) to (17), wherein the guard ring is formed in a ladder shape with the same repeating pitch as the pixel pitch of the pixel array region. (19) The light detection device according to any one of (1) to (18), wherein the width of the guard ring is the same as the width of the pad guard ring and the scribe guard ring.

[0097] 1. Light detection device, 2. Pixel, 2A. Normal pixel, 2B. OPB pixel, 3. Pixel array area, 21. Semiconductor substrate, 22. Wiring layer, 41A. Effective pixel area, 41B. OPB area, 42. Peripheral circuit area, 43. Pad area, 71. Guard ring, 72. Dummy pixel area, 73. Circuit area, 91. Electrode pad, 92. Pad guard ring, 93. Scribe guard ring, 94. Pad opening, 101. Anti-reflective film, 102. Insulating film, 103. Light-shielding film, 104. Light-shielding film contact area, 123, 124. Contact electrodes, 141. Substrate area, 142. Semiconductor area, 151, 151A, 152. Separation section, 201. First trench, 202. Second trench, 203. Connection section, 211. 1. First insulating layer, 212. First conductor layer, 213. Second insulating layer, 215. Insulating layer, 216. Second conductor layer, 221. High-density semiconductor region, 231. Through electrode, 232. Contact electrode, 233. Connecting electrode, 301. Electronic device, 303. Photodetector.

Claims

1. An optical detection device having a pixel array region in which a plurality of pixels are arranged in a matrix, and a peripheral circuit region outside the pixel array region, wherein the pixel array region and the peripheral circuit region have isolation portions to which a negative bias is applied to a first conductor layer inside a trench formed in a semiconductor substrate, and the peripheral circuit region, in a plan view, has a guard ring on the outer periphery of the isolation portion to which the negative bias is applied, which is an isolation portion to which a negative bias is not applied to the first conductor layer inside the trench.

2. The optical detection device according to claim 1, wherein the peripheral circuit region further comprises, in a plan view, a circuit region having one or more elements constituting a logic circuit outside the guard ring.

3. The photodetector according to claim 1, wherein the separation portion of the pixel array region is a pixel separation portion that separates a photoelectric conversion portion consisting of a semiconductor region of a first conductivity type and a semiconductor region of a second conductivity type opposite to the first conductivity type for each pixel, the semiconductor region of the second conductivity type is a charge storage region that stores the photoelectrically converted charge, and the peripheral circuit region is configured to supply a negative bias from a wiring layer to a first conductor layer inside the trench of one predetermined separation portion, and the substrate regions on both sides of the predetermined separation portion are semiconductor regions of the first conductivity type.

4. The photodetector according to claim 1, configured such that a negative bias is supplied from the wiring layer to the first conductor layer inside the trench of the separation portion of one predetermined separation portion of the peripheral circuit region, thereby applying a negative bias to the pixel array region inside the guard ring and the first conductor layer inside the trench of the separation portion of the peripheral circuit region in a plan view.

5. The photodetector according to claim 4, configured such that, in a plan view, a negative bias is applied to a substrate region adjacent to one predetermined separation portion to which a negative bias is supplied from the wiring layer.

6. The photodetector according to claim 4, having electrically floating substrate regions on the outside and inside of one predetermined separation portion to which a negative bias is supplied from the wiring layer in a plan view.

7. The photodetector according to claim 1, wherein, in a plan view, the substrate region adjacent to the guard ring is an electrically floating region.

8. The photodetector according to claim 1, wherein the peripheral circuit region, in a plan view, further has an isolation portion outside the guard ring where a negative bias is not applied to the first conductor layer inside the trench.

9. The photodetector according to claim 1, wherein, in a plan view, the peripheral circuit region outside the guard ring has a dummy pixel region having a plurality of separation portions to which the negative bias is not applied, and the pitch of the plurality of separation portions in the dummy pixel region is the same as the pitch of the separation portions in the pixel array region.

10. The photodetector according to claim 9, wherein the substrate region between the plurality of separation portions of the dummy pixel region is a semiconductor region to which a GND potential is applied.

11. The light detection device according to claim 10, wherein the light-shielding film is located on the light incident surface side of the semiconductor substrate, and the light-shielding film is directly connected to the substrate region of the dummy pixel region to which a GND potential is applied.

12. The light-shielding film contact region, to which the light-shielding film and the substrate region to which the GND potential is applied are connected, is arranged to encircle the pixel array region, as described in claim 11.

13. The photodetector according to claim 11, wherein the light-shielding film contact region, to which the light-shielding film and the substrate region to which the GND potential is applied are connected, is arranged to intermittently surround the periphery of the pixel array region.

14. The photodetector according to claim 1, wherein the negative bias contact portion, which is a separation portion in the peripheral circuit region that supplies a negative bias from the wiring layer to the first conductor layer inside the trench, has a second conductor layer embedded in a trench formed on the second surface side opposite to the first surface which is the light incident surface of the semiconductor substrate, and the negative bias supplied from the wiring layer to the second conductor layer of the negative bias contact portion is supplied to the first conductor layer inside the trench.

15. The photodetector according to claim 1, wherein the negative bias contact portion, which is a separation portion of the peripheral circuit region into which a negative bias is supplied from the wiring layer to the first conductor layer inside the trench, has a second conductor layer embedded in a trench formed on the second surface side opposite to the first surface which is the light incident surface of the semiconductor substrate, the semiconductor substrate has a high-concentration semiconductor region adjacent to the second conductor layer of the negative bias contact portion and having a higher impurity concentration than the substrate region, and the negative bias supplied from the wiring layer to the high-concentration semiconductor region is supplied to the first conductor layer via the second conductor layer of the negative bias contact portion.

16. The photodetector according to claim 1, which has a through electrode that penetrates a second surface of the semiconductor substrate opposite to a first surface which is the light incident surface, and is configured such that a negative bias extracted to the first surface side of the semiconductor substrate using the through electrode is applied to the first conductor layer of the negative bias contact portion, which is a separation portion of the peripheral circuit region that supplies a negative bias from the wiring layer to the first conductor layer inside the trench.

17. The light detection device according to claim 1, wherein the guard ring is formed in n layers (n > 1) on the outer periphery of the pixel array region.

18. The light detection device according to claim 1, wherein the guard ring is formed in a ladder shape with the same repeating pitch as the pixel pitch of the pixel array region.

19. The optical detection device according to claim 1, wherein the width of the guard ring is the same as the width of the pad guard ring and the scribe guard ring.

Images