Packaged device

Abstract

Provided is a packaged device in which heat from a logic chip is not readily conducted to a memory chip. This packaged device (100) comprises: a wiring board (10) that comprises a rewiring layer; a memory chip (20) that is mounted on the wiring board (10); an interposer (32) that is mounted on the wiring board (10); and one or more logic chips (31) that are mounted on the wiring board (10) with the the interposer (32) therebetween.

Description

Packaged device

[0001] The present disclosure relates to a packaged device.

[0002] In recent years, with the progress of high speed and high integration of semiconductor devices, FC-BGA (Flip Chip-Ball Grid Array) substrates on which semiconductor chips are mounted are also required to have narrower pitches for bonding terminals used for bonding to semiconductor chips and finer wiring in the substrate. For example, Patent Document 1 describes an integrated circuit package in which a High Bandwidth Memory (HBM) and a programmable integrated circuit die are mounted on an FC-BGA substrate via a silicon interposer.

[0003] Japanese Patent Publication No. 2019-525490

[0004] An object of the present disclosure is to provide a packaged device in which heat from a logic chip is less likely to be conducted to a memory chip.

[0005] According to one aspect of the present invention, there is provided a packaged device including: a wiring substrate formed of a redistribution layer; a memory chip mounted on the wiring substrate; an interposer mounted on the wiring substrate; and one or more logic chips mounted on the wiring substrate via the interposer.

[0006] According to another aspect of the present invention, the redistribution layer includes two or more layers stacked on each other, each of the two or more layers includes a conductor layer and an insulating layer embedding the conductor layer, and in at least one of the two or more layers, the insulating layer contains a cured product of photosensitive epoxy resin or polyimide. There is provided the packaged device according to the above aspect.

[0007] According to still another aspect of the present invention, the redistribution layer includes two or more layers stacked on each other, each of the two or more layers includes a conductor layer and an insulating layer embedding the conductor layer, and in at least one of the two or more layers, the insulating layer does not contain a filler. There is provided the packaged device according to any one of the above aspects.

[0008] According to yet another aspect of the present invention, a packaged device relating to any of the above aspects is provided, wherein the memory chip is a high-bandwidth memory.

[0009] According to yet another aspect of the present invention, a packaged device is provided in which the one or more logic chips are two or more logic chips, according to any of the above aspects.

[0010] According to yet another aspect of the present invention, a packaged device is provided which further comprises a first underfill layer interposed between the memory chip and the wiring board, a second underfill layer interposed between the interposer and the wiring board, and a resin layer integrally embedding the first underfill layer and the second underfill layer.

[0011] According to yet another aspect of the present invention, a packaged device is provided relating to any of the above aspects, wherein the shortest distance D between the orthogonal projection of the memory chip onto a plane parallel to the main surface of the wiring board and the orthogonal projection of the logic chip onto the plane is in the range of 50 μm to 30,000 μm.

[0012] According to yet another aspect of the present invention, a packaged device is provided relating to any of the above aspects, wherein the width of the wiring portion included in the redistribution layer is within the range of 2 μm to 6 μm.

[0013] According to yet another aspect of the present invention, a packaged device is provided in which the redistribution layer consists of two or more layers stacked on top of each other, and the thickness of the layers is in the range of 0.1 μm to 15 μm.

[0014] According to yet another aspect of the present invention, a packaged device is provided which has a plurality of bonding electrodes for bonding the memory chip to the wiring board, and the pitch of the bonding electrodes is in the range of 40 μm to 60 μm.

[0015] According to yet another aspect of the present invention, a packaged device is provided which relates to any of the above aspects, wherein the interposer is a silicon interposer.

[0016] According to yet another aspect of the present invention, a packaged device is provided relating to any of the above aspects, wherein the shortest distance D between the orthogonal projection of the memory chip onto a plane parallel to the main surface of the wiring board and the orthogonal projection of the logic chip onto the plane is in the range of 50 μm to 1500 μm.

[0017] According to yet another aspect of the present invention, a packaged device with a support is provided, comprising a packaged device according to any of the above aspects, and a support that faces the memory chip with the wiring board in between, and detachably supports the wiring board.

[0018] According to yet another aspect of the present invention, a method for manufacturing a packaged device is provided, comprising: forming a wiring board consisting of a redistribution layer on a support that detachably supports the wiring board; mounting a memory chip on the wiring board; mounting a logic chip mounted on an interposer on the wiring board such that the interposer is interposed between the wiring board and the logic chip; and peeling the support from the wiring board.

[0019] According to yet another aspect of the present invention, a method for manufacturing a packaged device is provided, wherein each of the two or more layers comprising the redistribution layer is formed by a damascene method.

[0020] According to this disclosure, a packaged device is provided in which heat from the logic chip is less likely to be conducted to the memory chip.

[0021] Figure 1 is a schematic cross-sectional view showing a packaged device according to one embodiment of the present invention. Figure 2 is a schematic cross-sectional view showing the first step in an example of a method for manufacturing the packaged device shown in Figure 1. Figure 3 is a schematic cross-sectional view showing the second step in an example of a method for manufacturing the packaged device shown in Figure 1. Figure 4 is a schematic cross-sectional view showing the third step in an example of a method for manufacturing the packaged device shown in Figure 1. Figure 5 is a schematic cross-sectional view showing the fourth step in an example of a method for manufacturing the packaged device shown in Figure 1. Figure 6 is a schematic cross-sectional view showing the fifth step in an example of a method for manufacturing the packaged device shown in Figure 1.

[0022] Embodiments of the present invention will be described below with reference to the drawings. The embodiments described below are more specific to any of the above aspects. The matters described below can be incorporated into each of the above aspects, individually or in combination.

[0023] The embodiments described below illustrate examples that embody the technical concept of the present invention, and the technical concept of the present invention is not limited to the materials, shapes, structures, and arrangements of the components described below. Various modifications can be made to the technical concept of the present invention within the technical scope defined by the claims described in the patent claims.

[0024] In the drawings referenced in the following description, components having similar or identical functions are given the same reference numerals. It should be noted that the drawings are schematic, and the relationships between dimensions in the thickness direction and dimensions perpendicular to the thickness direction (i.e., in-plane direction), as well as the relationships between dimensions in the thickness direction of multiple layers, may differ from reality. Therefore, specific dimensions should be determined by referring to the following description. It should also be noted that the dimensional relationships between two or more components may differ across multiple drawings.

[0025] In this disclosure, "upper surface" and "lower surface" refer to the two main surfaces of the plate-like member or the layer contained therein, namely the surface perpendicular to the thickness direction and having the largest area, and the back surface thereof, which are shown at the top and bottom in the drawings, respectively. Furthermore, "end surface" refers to the surface of the plate-like member or the layer contained therein that is located on the outer periphery when viewed from a direction parallel to the thickness direction. And "side surface" refers to a surface that is perpendicular to or inclined with respect to the in-plane direction.

[0026] Furthermore, in this disclosure, the phrase "AA on BB" is used independently of the direction of gravity. The state specified by the phrase "AA on BB" includes the state in which AA is in contact with BB. The phrase "AA on BB" does not exclude the interposition of one or more other components between AA and BB.

[0027] <Packaging Device> Figure 1 is a schematic cross-sectional view showing a packaging device according to one embodiment of the present invention.

[0028] The packaged device 100 shown in Figure 1 comprises a wiring board 10, a memory chip 20, an interposer 30 with a logic chip, a bonding conductor 40, and a sealing resin layer 50.

[0029] The wiring board 10 is a substrate provided on a substrate having a relatively large electrode pitch, such as a printed circuit board. The wiring board 10 consists of a redistribution layer. The redistribution layer consists of two or more layers stacked on top of each other. Each of the two or more layers includes a conductor layer and an insulating layer in which the conductor layer is embedded. The conductor layer included in each of the two or more layers is electrically connected to the conductor layer included in the adjacent layer.

[0030] Of the two or more layers, the conductive layers included in the layers corresponding to the upper and lower surfaces of the wiring board 10 each include bonding electrodes. The conductive layers included in the layers interposed between the layer corresponding to the upper surface of the wiring board 10 and the layer corresponding to the lower surface of the wiring board 10 include vias and wiring sections. A via section included in a certain layer is electrically connected to a conductive layer included in a layer provided on the lower surface of that layer. Also, a wiring layer included in a certain layer is electrically connected to a via section included in that layer. The width of the wiring section is preferably in the range of 0.3 μm to 6 μm, more preferably in the range of 2 μm to 6 μm, and even more preferably in the range of 2 μm to 15 μm.

[0031] Preferably, in at least one of the two or more layers, and more preferably in each of the two or more layers, the insulating layer includes, for example, a cured photosensitive epoxy resin or polyimide. Preferably, in at least one of the two or more layers, and more preferably in each of the two or more layers, the insulating layer does not contain a filler.

[0032] The conductive layer is made of a metallic material such as copper. The conductive layer may further include one or more other layers, such as an adhesion layer and a seed layer.

[0033] As described above, among the two or more layers, the conductive layers included in the layers corresponding to the upper and lower surfaces of the wiring board 10 each contain electrodes. Hereinafter, the electrodes on the upper and lower surfaces of the wiring board 10 will be referred to as the first electrode and the second electrode, respectively.

[0034] The first electrode has a plurality of bonding electrodes R1 used for bonding with the memory chip 20 and a plurality of bonding electrodes R2 used for bonding with the logic chip interposer 30.

[0035] The pitch of the bonding electrode R1 is preferably in the range of 30 μm to 60 μm, more preferably in the range of 40 μm to 60 μm, and even more preferably in the range of 40 μm to 50 μm.

[0036] The pitch of bonding electrode R2 is, for example, larger than the pitch of bonding electrode R1. The pitch of bonding electrode R2 is preferably in the range of 40 μm to 150 μm, and more preferably in the range of 100 μm to 150 μm.

[0037] The second electrode is used for bonding to a substrate such as a printed circuit board. The pitch of the second electrode is preferably in the range of 90 μm to 150 μm, and more preferably in the range of 100 μm to 150 μm.

[0038] The thickness of each of the two or more layers is preferably within the range of 0.1 μm to 15 μm, more preferably within the range of 1 μm to 15 μm, even more preferably within the range of 1 μm to 10 μm, and even more preferably within the range of 3 μm to 8 μm.

[0039] The thickness of the wiring board 10 is preferably in the range of 20 μm to 600 μm, and more preferably in the range of 30 μm to 60 μm.

[0040] The memory chip 20 is mounted on the wiring board 10. Preferably, the memory chip 20 is a high-bandwidth memory (HBM memory). The memory chip 20 has a bonding electrode M for bonding with a bonding electrode R1. The pitch of the bonding electrode M is the same as the pitch of the bonding electrode R1. In Figure 1, there is one memory chip 20, but there may be two or more memory chips 20.

[0041] The logic chip-equipped interposer 30 is mounted on the wiring board 10. The logic chip-equipped interposer 30 includes an interposer 32 and a logic chip 31 provided on the interposer 32.

[0042] The interposer 32 is, for example, a silicon interposer. The silicon interposer has particularly fine wiring sections. The interposer 32 has a bonding electrode I1 on its lower surface for bonding with a bonding electrode R2. The interposer 32 also has a bonding electrode I2 on its upper surface for bonding with a logic chip 31. The pitch of the bonding electrode R2 is the same as the pitch of the bonding electrode I2. The pitch of the bonding electrode I2 is preferably in the range of 40 μm to 60 μm, and more preferably in the range of 30 μm to 50 μm.

[0043] The logic chip 31 is mounted on the wiring board 10 via an interposer 32. The logic chip 31 is electrically connected to the memory chip 20 via the interposer 32 and the redistribution layer. The logic chip 31 is a device that has logical operation functions. The logic chip 31 has functions such as machine learning and deep learning. The logic chip 31 is, for example, an AI chip. The logic chip 31 has a bonding electrode L for bonding with a bonding electrode I2. The logic chip 31 and the interposer 32 are bonded via a bonding conductor. In Figure 1, the number of logic chips 31 is 1, but the number of logic chips 31 may be 2 or more.

[0044] It is preferable that the shortest distance between the orthographic projection of the memory chip 20 onto a plane parallel to the main surface of the wiring board 10 and the orthographic projection of the logic chip 31 onto said plane is in the range of not less than 50 μm and not more than 30000 μm, more preferably in the range of not less than 100 μm and not more than 30000 μm, still more preferably in the range of not less than 100 μm and not more than 4000 μm, and even more preferably in the range of not less than 500 μm and not more than 1000 μm. According to one example, the aforementioned shortest distance is in the range of not less than 50 μm and not more than 1500 μm. When the aforementioned shortest distance falls within the aforementioned range, heat from the logic chip 31 is particularly unlikely to be transferred to the memory chip 20.

[0045] The sealing resin layer 50 seals the memory chip 20 and the interposer with logic chip 30.

[0046] The sealing resin layer 50 includes, for example, a first underfill layer, a second underfill layer, and a resin layer. The first underfill layer is interposed between the memory chip 20 and the wiring board 10. The second underfill layer is interposed between the interposer 32 and the wiring board 10. The resin layer covers the memory chip 20 and the interposer with logic chip 30, and integrally embeds the first underfill layer and the second underfill layer.

[0047] As a material for the sealing resin layer 50, for example, a mixture of one or more resins selected from the group consisting of epoxy resins, urethane resins, silicone resins, polyester resins, oxetane resins, and maleimide resins, and a filler such as silica, titanium oxide, aluminum oxide, magnesium oxide, or zinc oxide can be used.

[0048] The materials of the first underfill layer, the second underfill layer, and the resin layer may each be different from each other, or may be the same as one or more of the other two materials.

[0049] Note that, in the sealing resin layer 50, the aforementioned resin layer may be omitted. In this case, it is preferable that the first underfill layer and the second underfill layer are in contact with each other. Also, in FIG. 1, the bonding electrodes I2 and the bonding electrodes L are omitted.

[0050] <Method for Manufacturing a Packaged Device> An example of a method for manufacturing a packaged device 100 will be described below with reference to Figures 2 to 6. In this method, a packaged device with a support is first manufactured, and then the support is peeled off to manufacture the packaged device 100. This method will be described in detail below.

[0051] First, as shown in Figure 2, a laminate is prepared that includes a support 1 having a support surface and a release layer 2 provided on the support surface.

[0052] The support 1 may or may not be light-transmitting. For example, the support 1 is transparent.

[0053] The material of the support 1 is, for example, glass, polycarbonate, acrylic, or silicon. The material of the support 1 is preferably glass. When the support 1 is made of glass, a support 1 with sufficient thickness has excellent shape retention properties, and using such a support 1 makes it easy to form a wiring substrate 10 having a fine wiring pattern.

[0054] The thickness of the support 1 is preferably 0.7 mm or more, and more preferably 1.1 mm or more. If the support 1 is too thin, warping and other problems are likely to occur.

[0055] The delamination layer 2 is a layer that causes delamination between the support 1 and the wiring board 10 by treatment such as heat or light irradiation.

[0056] Next, as shown in Figure 3, a wiring substrate 10 consisting of a redistribution layer is formed on a laminate containing the support 1 and the release layer 2. The redistribution layer is formed by building up each of the two or more layers described above. It is preferable that each of the two or more layers is formed by the damascene method. In this case, particularly fine wiring can be formed.

[0057] Next, as shown in Figure 4, a bonding conductor 40 is provided on the wiring board 10. Specifically, the bonding conductor 40 is provided on the first electrode of the wiring board 10. The bonding conductor 40 is, for example, a solder bump.

[0058] Next, as shown in Figure 5, the memory chip 20 and the logic chip-equipped interposer 30 are mounted on the wiring board 10 via the bonding conductor 40. Specifically, the memory chip 20 is mounted on the wiring board 10 by bonding the bonding electrode M and bonding electrode R1 with the bonding conductor 40. Then, the logic chip-equipped interposer 30 is mounted on the wiring board 10 by bonding the bonding electrode I1 and bonding electrode R2 with the bonding conductor 40. The order in which the memory chip 20 and the logic chip-equipped interposer 30 are mounted on the wiring board 10 is not particularly limited.

[0059] Next, as shown in Figure 6, the memory chip 20 and the interposer 30 with the logic chip are sealed with a sealing resin layer 50. For example, first, the gap between the memory chip 20 and the wiring board 10 is filled with a first underfill layer. Next, the gap between the interposer 32 and the wiring board 10 is filled with a second underfill layer. Then, the memory chip 20 and the interposer 30 with the logic chip are covered with a resin layer, and the first and second underfill layers are embedded together. The resin layer can be formed, for example, by compression molding or transfer molding. Note that one or more of the upper surfaces of the memory chip 20 and the logic chip 31 may be exposed from the resin layer.

[0060] Next, the support 1 and the release layer 2 are removed from the wiring substrate 10. For example, if the release layer 2 is one that exhibits a release effect when energy is applied from the outside, such as by laser light, and the support 1 is a glass plate, the support 1 can be removed from the wiring substrate 10 by irradiating the release layer 2 with laser light from the support 1 side. The release layer 2 can be removed by etching or polishing, for example. In this way, the packaged device 100 shown in Figure 1 is obtained.

[0061] Furthermore, a seed layer may be formed on the release layer 2 before forming the wiring board 10. In this case, the conductor layer can be formed using this seed layer. In this case, after peeling off the support 1, the seed layer is removed, for example, by etching or polishing.

[0062] Furthermore, the release layer 2 may be omitted. In this case, the support 1 can be removed from the wiring board 10 by, for example, a mechanical or chemical method. In one example, the support 1 can be removed by pressing a blade between the support 1 and the wiring board 10. In another example, the support 1 can be removed by dissolving it.

[0063] <Effects> In a packaged device (hereinafter referred to as the comparative example packaged device) that is the same as the packaged device 100 shown in Figure 1, except that the memory chip 20 is mounted on the interposer 32 together with the logic chip 31, the distance between the memory chip 20 and the logic chip 31 is short, for example, due to the miniaturization of the interposer 32. In this case, the heat generated by the operation of the logic chip 31 is easily conducted to the memory chip 20, so the durability of the memory chip 20 tends to decrease.

[0064] On the other hand, in the packaged device 100 described above, the memory chip 20 is mounted on the wiring board 10, and the logic chip 31 is mounted on the wiring board 10 via the interposer 32. Therefore, with the packaged device 100 described above, the distance between the memory chip 20 and the logic chip 31 can be increased. In this case, heat generated from the logic chip 31 is less likely to be conducted to the memory chip 20.

[0065] Furthermore, with the above-described packaged device 100, since the memory chip 20 is mounted on the wiring board 10, it has superior electrical characteristics such as propagation characteristics compared to the packaged device of the comparative example. When a silicon interposer is used as the interposer 32, the above-described packaged device 100 has particularly superior electrical characteristics compared to the packaged device of the comparative example.

[0066] Furthermore, in the packaged device 100 described above, only the logic chip 31 of the memory chip 20 and logic chip 31 is mounted on the interposer 32. Therefore, for example, if a defect is found in either the memory chip 20 or the logic chip 31 during inspection, it is easy to repair only the defective chip. As repair is easily possible with the packaged device 100 described above, the manufacturing method of the packaged device 100 described above can achieve excellent yield.

[0067] Furthermore, when manufacturing the logic chip 31 using EUV (Extreme Ultra-Violet) exposure, it is difficult to obtain packaged devices with a high yield. On the other hand, memory chips such as HBMs can be manufactured with a higher yield than in the above case. Thus, when mounting two chips with different yields onto a wiring board 10, a high yield can be achieved by mounting each of these two chips on the wiring board 10.

[0068] Furthermore, in the aforementioned packaged device 100, it is possible to miniaturize the interposer 32 compared to the packaged device in the comparative example. In this case, it is possible to reduce manufacturing costs.

[0069] By the way, for example, when attempting to mount a memory chip 20 such as an HBM on a substrate having a relatively large electrode pitch of 80 μm or more, such as an FC-BGA substrate, it is necessary to increase the pitch of the bonding electrodes of the memory chip 20. On the other hand, in the packaged device 100 described above, since the memory chip 20 is mounted on a wiring board 10 consisting of a redistribution layer, it is possible to mount the memory chip 20 on the wiring board without increasing the pitch of the bonding electrodes M of the memory chip 20.

[0070] 1...Support, 2...Release layer, 10...Wiring board, 20...Memory chip, 30...Interposer with logic chip, 31...Logic chip, 32...Interposer, 40...Bonding conductor, 50...Sealing resin layer, 100...Packaging device.

Claims

1. A packaged device comprising: a wiring board consisting of a redistribution layer; a memory chip mounted on the wiring board; an interposer mounted on the wiring board; and one or more logic chips mounted on the wiring board via the interposer.

2. The redistribution layer comprises two or more layers stacked on top of each other, each of the two or more layers comprising a conductor layer and an insulating layer in which the conductor layer is embedded, and in at least one of the two or more layers, the insulating layer comprises a cured product of a photosensitive epoxy resin or polyimide, as described in claim 1.

3. The packaged device according to claim 1, wherein the redistribution layer comprises two or more layers stacked on top of each other, each of the two or more layers comprising a conductor layer and an insulating layer in which the conductor layer is embedded, and in at least one of the two or more layers, the insulating layer does not contain a filler.

4. The packaged device according to claim 1, wherein the memory chip is a high-bandwidth memory.

5. The packaged device according to claim 1, wherein the one or more logic chips are two or more logic chips.

6. The packaged device according to claim 1, further comprising a first underfill layer interposed between the memory chip and the wiring board, a second underfill layer interposed between the interposer and the wiring board, and a resin layer integrally embedding the first underfill layer and the second underfill layer.

7. The packaged device according to claim 6, wherein the shortest distance D between the orthogonal projection of the memory chip onto a plane parallel to the main surface of the wiring board and the orthogonal projection of the logic chip onto the plane is in the range of 50 μm or more and 30,000 μm or less.

8. The packaged device according to claim 1, wherein the width of the wiring portion included in the redistribution layer is within the range of 2 μm to 6 μm.

9. The packaged device according to claim 1, wherein the redistribution layer consists of two or more layers stacked on top of each other, and the thickness of the layers is in the range of 1 μm to 15 μm.

10. The packaged device according to claim 1, wherein the memory chip has a plurality of bonding electrodes M for bonding to the wiring board, and the pitch of the bonding electrodes M is in the range of 40 μm or more and 60 μm or less.

11. The packaging device according to claim 1, wherein the interposer is a silicon interposer.

12. The packaged device according to claim 1, wherein the shortest distance D between the orthogonal projection of the memory chip onto a plane parallel to the main surface of the wiring board and the orthogonal projection of the logic chip onto the plane is in the range of 100 μm or more and 4000 μm or less.

13. A packaged device with a support comprising a packaged device according to any one of claims 1 to 12, and a support that faces the memory chip with the wiring board in between and detachably supports the wiring board.

14. A method for manufacturing a packaged device, comprising: forming a wiring board consisting of a redistribution layer on a support that removably supports the wiring board; mounting a memory chip on the wiring board; mounting a logic chip mounted on an interposer on the wiring board such that the interposer is interposed between the wiring board and the logic chip; and peeling the support from the wiring board.

15. The method for manufacturing a packaged device according to claim 14, wherein each of the two or more layers included in the redistribution layer is formed by a damascene method.

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