Insulated-gate semiconductor device
Patent Information
- Application Number
- PCT/JP2026/007181
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-13
- Filing Date
- 2026-02-26
- Publication Date
- 2026-09-17
Smart Images
Figure JP2026007181_17092026_PF_FP_ABST
Abstract
Description
Insulated gate semiconductor device
[0001] This disclosure relates to an insulated gate semiconductor device and a method for manufacturing the same.
[0002] Patent Document 1 discloses a semiconductor device in which a source region is formed along the side surface of a trench by oblique ion implantation of n-type impurities into the inner surface of the trench. Patent Document 2 discloses a p-type base region and n-type impurities formed by self-align implantation including oblique ion implantation from a contact trench. ＋ Type source regions are sequentially formed, and p is injected by self-alignment injection from the contact trench. ＋ This invention discloses a semiconductor device having a type base contact region formed thereon. Patent documents 3 and 4 describe a thin n ＋ After forming the source region, a contact trench is formed, and dense n is found on the side walls of the contact trench. ＋＋ A semiconductor device having a source region is disclosed.
[0003] Japanese Patent Publication No. 2018-117070, Japanese Patent Publication No. 2022-93891, Japanese Patent Publication No. 2003-101019, Japanese Patent Publication No. 2005-183547
[0004] In the conventional manufacturing process for insulated gate semiconductor devices, n ＋ After forming the emitter region (source region) of the mold, a contact trench is formed in the depth direction from the top surface of the emitter region. Forming the contact trench promotes hole discharge and suppresses latch-up. However, if the formation of the contact trench is hindered by particles generated during the manufacturing process, the hole discharge path becomes longer, potentially leading to latch-up failure.
[0005] In view of the above issues, this disclosure aims to provide an insulated gate type semiconductor device and a method for manufacturing the same that can suppress latch-up failure.
[0006] One aspect of the present disclosure is an insulated gate type semiconductor device comprising: a drift layer of a first conductivity type provided on a semiconductor substrate; a base region of a second conductivity type provided on the upper surface side of the drift layer; a main electrode region of a first conductivity type provided on the upper surface side of the base region; a contact portion embedded in a contact trench provided in the depth direction from the upper surface of the semiconductor substrate and in contact with the main electrode region at its side wall; and a base contact region of a second conductivity type provided below the contact trench and in contact with the base region, having a higher impurity concentration than the base region, wherein the peak position of the impurity concentration distribution of the main electrode region is parallel to the side surface of the contact trench.
[0007] Another aspect of the present disclosure is a method for manufacturing an insulated gate semiconductor device, comprising the steps of: forming a base region of a second conductivity type on the upper side of a drift layer of a first conductivity type; forming a contact trench in the depth direction from the upper surface of the base region; ion implanting impurities of the second conductivity type into the lower surface of the contact trench to form a base contact region of a second conductivity type having a higher impurity concentration than the base region; forming a main electrode region of a first conductivity type having ion implantation of impurities of the first conductivity type obliquely into the side surface of the contact trench; and embedding a contact portion in the contact trench.
[0008] According to this disclosure, it is possible to provide an insulated gate type semiconductor device and a method for manufacturing the same that can suppress latch-up failure.
[0009] This is a vertical cross-sectional view of an insulated gate semiconductor device according to the first embodiment. This is a horizontal cross-sectional view along the line A-A' in Figure 1. This is a vertical cross-sectional view along the line C-C' in Figure 2. This is a vertical cross-sectional view along the line D-D' in Figure 2. This is a cross-sectional view of a process illustrating the manufacturing method of an insulated gate semiconductor device according to the first embodiment. This is a cross-sectional view of a process following Figure 5 illustrating the manufacturing method of an insulated gate semiconductor device according to the first embodiment. This is a cross-sectional view of a process following Figure 6 illustrating the manufacturing method of an insulated gate semiconductor device according to the first embodiment. This is a cross-sectional view of a process following Figure 7 illustrating the manufacturing method of an insulated gate semiconductor device according to the first embodiment. This is a cross-sectional view of a process following Figure 8 illustrating the manufacturing method of an insulated gate semiconductor device according to the first embodiment. This is a cross-sectional view of a process following Figure 9 illustrating the manufacturing method of an insulated gate semiconductor device according to the first embodiment. This is a cross-sectional view of a process following Figure 10 illustrating the manufacturing method of an insulated gate semiconductor device according to the first embodiment. This is a cross-sectional view of a process following Figure 11 illustrating the manufacturing method of an insulated gate semiconductor device according to the first embodiment. This is a cross-sectional view of a process following Figure 12 illustrating the manufacturing method of an insulated gate semiconductor device according to the first embodiment. This is a cross-sectional view of a process following Figure 13 illustrating the manufacturing method of an insulated gate semiconductor device according to the first embodiment. This is a cross-sectional view of the process when particles are generated in the manufacturing method of an insulated gate semiconductor device according to the first embodiment. This is a cross-sectional view corresponding to Figure 1 when particles are generated in the insulated gate semiconductor device according to the first embodiment. This is a cross-sectional view corresponding to Figure 4 when particles are generated in the insulated gate semiconductor device according to the first embodiment. This is a cross-sectional view of the process for explaining the manufacturing method of an insulated gate semiconductor device according to a comparative example. This is a cross-sectional view of the process following Figure 18 for explaining the manufacturing method of an insulated gate semiconductor device according to a comparative example. This is a cross-sectional view of the process following Figure 19 for explaining the manufacturing method of an insulated gate semiconductor device according to a comparative example when particles are generated in the manufacturing method of an insulated gate semiconductor device according to a comparative example. This is a vertical cross-sectional view of an insulated gate semiconductor device according to the second embodiment. This is a horizontal cross-sectional view of an insulated gate semiconductor device according to the third embodiment.This is a vertical cross-sectional view of an insulated gate type semiconductor device according to the fourth embodiment.
[0010] The first to fourth embodiments of this disclosure will be described below with reference to the drawings. In the drawings referred to in the following description, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following description. Furthermore, it goes without saying that there are parts where the relationships and ratios of dimensions differ between drawings.
[0011] In the following explanation, the "first main electrode region" and the "second main electrode region" refer to the main electrode regions of a semiconductor device through which the main current flows in or out. The "first main electrode region" refers to the semiconductor region that is either the emitter region or the collector region in the case of an insulated-gate bipolar transistor (IGBT). In the case of a field-effect transistor (FET) or electrostatic induction transistor (SIT), it refers to the semiconductor region that is either the source region or the drain region. In the case of an electrostatic induction thyristor (SI thyristor) or gate turn-off (GTO) thyristor, it refers to the semiconductor region that is either the anode region or the cathode region. The "second main electrode region" refers to the semiconductor region that is either the emitter region or the collector region in the case of an IGBT, which is not the first main electrode region. In the case of an FET or SIT, it refers to the semiconductor region that is either the source region or the drain region in the case of an FET or SIT. In the case of SI thyristors and GTOs, the second main electrode region refers to either the anode region or the cathode region, which are not the first main electrode region. That is, if the first main electrode region is the source region, the second main electrode region refers to the drain region. If the first main electrode region is the emitter region, the second main electrode region refers to the collector region. If the first main electrode region is the anode region, the second main electrode region refers to the cathode region. When simply referred to as the "main electrode region," it comprehensively means either the first main electrode region or the second main electrode region, whichever is technically and contextually appropriate.
[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for the convenience of explanation and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly. Also, "top surface" may be read as "front surface," and "bottom surface" may be read as "back surface" or "bottom surface."
[0013] Furthermore, the following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. However, it is also acceptable to choose the conductivity types in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Also, the "+" and "-" attached to "n" and "p" indicate semiconductor regions with relatively higher or lower impurity concentrations, respectively, compared to semiconductor regions without "+" and "-" markings. However, even if two semiconductor regions are marked with the same "n," this does not mean that the impurity concentrations in each semiconductor region are exactly the same.
[0014] Furthermore, in the following explanation, "identical" impurity concentration, width, depth, or thickness, etc., includes not only cases where they are strictly identical, but also tolerances due to process variations, etc., that can be considered substantially identical. The tolerance range is, for example, ±10% compared to the case where they are strictly identical. Furthermore, in the following explanation, "parallel" and "perpendicular" include not only cases where they are strictly parallel and perpendicular, but also tolerances due to process variations, etc., that can be considered substantially parallel and perpendicular. The tolerance range is, for example, ±10° compared to the case where they are strictly parallel and perpendicular.
[0015] (First Embodiment) <Structure of Semiconductor Device> As an insulated gate type semiconductor device according to the first embodiment, an insulated gate type bipolar transistor (IGBT) will be described as an example. Figure 1 shows an example of an IGBT unit cell, but in reality, a large number of the unit cells shown in Figure 1 may be arranged to form a multichannel structure. Although not shown, an active section including the IGBT shown in Figure 1 as an active element may be provided, and a voltage-resistant structure (termination section) may be provided around the active section.
[0016] As shown in Figure 1, the insulated gate type semiconductor device according to the first embodiment has a semiconductor substrate 100 with a first conductivity type (n － The device includes an n-type drift layer 1. An n-type storage layer 2 with a higher impurity concentration than the drift layer 1 is provided on the upper surface of the drift layer 1. The lower surface of the storage layer 2 is in contact with the upper surface of the drift layer 1. By providing the storage layer 2, the carrier injection-enhancement effect (IE effect) can be increased, and the on-voltage can be reduced. Note that the storage layer 2 is not necessarily provided, and the drift layer 1 may be provided in the region of the storage layer 2.
[0017] A base region 3 of the second conductivity type (p-type) is provided on the upper side of the storage layer 2. The lower surface of the base region 3 is in contact with the upper surface of the storage layer 2. If the storage layer 2 is not provided, the lower surface of the base region 3 is in contact with the upper surface of the drift layer 1.
[0018] On the upper surface side of the base region 3, the first conductive type (n ＋ A first main electrode region (emitter region) 4a, 4b of type 3 is provided. The lower surfaces of the emitter regions 4a, 4b are in contact with the upper surface of the base region 3. The impurity concentration of the emitter regions 4a, 4b is higher than the impurity concentration of the drift layer 1 and the storage layer 2.
[0019] A plurality of trenches (hereinafter also referred to as "gate trenches") 5a, 5b are provided spaced apart from each other and in parallel from the upper surface of a semiconductor substrate 100 in the depth direction, which is a direction perpendicular to the upper surface of the semiconductor substrate 100. The plurality of gate trenches 5a, 5b have the same width and the same depth as each other. The plurality of gate trenches 5a, 5b penetrate through emitter regions 4a, 4b, a base region 3 and a storage layer 2 to reach a drift layer 1. The emitter regions 4a, 4b, the base region 3, the storage layer 2 and an upper portion of the drift layer 1 are in contact with side surfaces (side walls) of the plurality of gate trenches 5a, 5b.
[0020] Gate insulating films 6a, 6b are provided inside the gate trenches 5a, 5b so as to cover the bottom surfaces and side surfaces of the gate trenches 5a, 5b. As the gate insulating films 6a, 6b, for example, a silicon dioxide film (SiO ２ film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si ３ N ４ ) film, an aluminum oxide (Al ２ O ３ ) film, a magnesium oxide (MgO) film, a yttrium oxide (Y ２ O ３ ) film, a hafnium oxide (HfO ２ ) film, a zirconium oxide (ZrO ２ ) film, a tantalum oxide (Ta ２ O ５ ) film, a bismuth oxide (Bi ２ O ３ ) film, or a composite film obtained by laminating a plurality of these films can be employed.
[0021] In this embodiment, gate electrodes 7a and 7b are embedded inside at least one of the gate trenches 5a and 5b, and an electrode to which a different potential from that of the gate electrodes is applied may be embedded in the other side. However, in this embodiment, gate electrodes 7a and 7b are embedded inside the gate trenches 5a and 5b via gate insulating films 6a and 6b. The gate insulating films 6a and 6b and the gate electrodes 7a and 7b constitute an insulated gate type electrode structure (6a, 7a) and (6b, 7b). Figure 1 illustrates the case where the upper surfaces of the gate electrodes 7a and 7b coincide with the upper surfaces of the emitter regions 4a and 4b, but the upper surfaces of the gate electrodes 7a and 7b may be lower than the upper surfaces of the emitter regions 4a and 4b. As the material for the gate electrodes 7a and 7b, for example, a polysilicon film (doped polysilicon film) with high impurity concentrations of n-type impurities such as phosphorus (P) or p-type impurities such as boron (B) can be used.
[0022] Between adjacent gate trenches 5a and 5b, a trench (hereinafter also referred to as a "contact trench") 8 is provided in the depth direction from the upper surface of the emitter regions 4a and 4b. The contact trench 8 penetrates the emitter regions 4a and 4b. The side surface (side wall) of the contact trench 8 is in contact with the emitter regions 4a and 4b. The depth of the contact trench 8 is shallower than the depth of the gate trenches 5a and 5b.
[0023] Figure 1 illustrates a case where the side surface of the contact trench 8 has a tapered shape (forward taper shape) where the width of the contact trench 8 narrows from the opening of the contact trench 8 towards the bottom surface of the contact trench 8. However, the side surface of the contact trench 8 may be approximately perpendicular to the upper surfaces of the emitter regions 4a and 4b. Also, Figure 1 illustrates a case where the bottom surface of the contact trench 8 is flat, but the bottom surface of the contact trench 8 may be a curved surface that is convex downwards. Furthermore, the corner formed by the bottom surface and the side surface of the contact trench 8 may have curvature.
[0024] The emitter regions 4a and 4b are formed by obliquely ion-implanting n-type impurities into the side surfaces of the contact trench 8 and then performing heat treatment. Therefore, the position (peak position) of the maximum value (peak concentration) of the impurity concentration distribution of each of the emitter regions 4a and 4b is parallel to the side surface of the contact trench 8 on the side that is in contact with the respective emitter regions 4a and 4b, and forms a linear shape parallel to the side surface. For example, the peak position of the impurity concentration distribution of each of the emitter regions 4a and 4b is located at the side surface of the contact trench 8 on the side that is in contact with the respective emitter regions 4a and 4b, and forms a linear shape along the side surface. The deeper from the side surface of the contact trench 8, the lower the impurity concentration of the emitter regions 4a and 4b becomes. The gate trenches 5a and 5b side on the lower surface of the emitter regions 4a and 4b may have a curvature.
[0025] On the lower side of the contact trench 8, a second conductivity type (p ＋ -type) base contact region (contact region) 9 having a higher impurity concentration than the base region 3 is selectively provided. The base contact region 9 is in contact with the base region 3 and the emitter regions 4a and 4b. The lower end, which is the deepest portion of the emitter regions 4a and 4b in the depth direction, is located at a position deeper than the upper surface of the base contact region 9.
[0026] Between adjacent gate trenches 5a and 5b, the semiconductor region above the deepest position of the gate trenches 5a and 5b forms a mesa portion. The mesa portion includes an upper part of the drift layer 1, the accumulation layer 2, the base region 3, the base contact region 9, and the emitter regions 4a and 4b. When the accumulation layer 2 is not provided, the mesa portion includes an upper part of the drift layer 1, the base region 3, the base contact region 9, and the emitter regions 4a and 4b. The contact trench 8 is provided in an upper part of the mesa portion.
[0027] An interlayer insulating film 10 is provided on the upper surfaces of the emitter regions 4a and 4b, the gate insulating films 6a and 6b, and the gate electrodes 7a and 7b. The interlayer insulating film 10 is, for example, a non-doped silicon oxide film (SiO ２film), phosphorus-added silicon oxide film (PSG film), boron-added silicon oxide film (BSG film), boron and phosphorus-added silicon oxide film (BPSG film), silicon nitride film (Si ３ N ４ film), high-temperature oxide film (HTO film), or a laminated film of any of these.
[0028] The interlayer insulating film 10 is provided with a contact hole 10a penetrating the interlayer insulating film 10. The contact hole 10a is provided above the mesa portion at a position continuous with the contact trench 8.
[0029] A contact portion 11 is embedded in the contact trench 8 and the contact hole 10a. A side surface of the contact portion 11 is in ohmic contact with emitter regions 4a and 4b. A lower surface of the contact portion 11 is in ohmic contact with a base contact region 9. The contact portion 11 is composed of, for example, a barrier metal film and a contact plug. As the barrier metal film, for example, a single-layer film of titanium (Ti), titanium nitride (TiN), or the like, or a laminated film of Ti and TiN can be used. A metal such as tungsten (W) can be used for the contact plug. A metal silicide layer may be formed between the contact portion 11 and the emitter regions 4a, 4b and the base contact region 9.
[0030] A surface electrode (emitter electrode) 12 is provided on an upper surface side of the interlayer insulating film 10. The emitter electrode 12 is electrically connected to the emitter regions 4a, 4b and the base contact region 9 via the contact portion 11. A metal such as aluminum (Al), an Al alloy, copper (Cu), or the like can be used for the emitter electrode 12. Examples of the Al alloy include Al-silicon (Si), Al-copper (Cu)-Si, Al-Cu, and the like. The contact portion 11 may be formed of the same material as the emitter electrode 12, may be formed integrally with the emitter electrode 12, and may be included in the emitter electrode 12 as a part of the emitter electrode 12. The contact portion 11 may be formed of a material different from that of the emitter electrode 12.
[0031] On the lower side of the drift layer 1, a first conductivity type (n) with a higher impurity concentration than the drift layer 1 is present. ＋ A field stop (FS) layer 13 of type 1 is provided. The upper surface of the FS layer 13 is in contact with the lower surface of the drift layer 1. The FS layer 13 prevents the depletion layer, which spreads from the lower side of the base region 3, from reaching the second main electrode region (collector region) 14, which will be described later.
[0032] On the lower surface side of the FS layer 13, there is a second conductivity type (p ＋ A collector region 14 of type 14 is provided. The upper surface of the collector region 14 is in contact with the lower surface of the FS layer 13. The impurity concentration in the collector region 14 is higher than the impurity concentration in the base region 3.
[0033] In this embodiment, the semiconductor substrate 100 is made of, for example, a silicon (Si) substrate, but the semiconductor substrate 100 is not limited to a Si substrate, and can be made of, for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga ２ O ３ ), or a semiconductor substrate made of a semiconductor with a wider band gap than Si (wide bandgap semiconductor), such as diamond (C) or aluminum nitride (AlN).
[0034] A back electrode (collector electrode) 15 is provided on the lower side of the collector region 14. The collector electrode 15 can be made of, for example, a single layer of gold (Au) or a metal film stacked in the order of titanium (Ti), nickel (Ni), and gold (Au).
[0035] Figure 2 is a horizontal cross-sectional view along line A-A' of the insulated gate type semiconductor device according to the first embodiment shown in Figure 1. The vertical cross-sectional view along line B-B' in Figure 2 corresponds to Figure 1.
[0036] As shown in Figure 2, the gate trenches 5a and 5b have a linear (striped) planar pattern that extends parallel to each other in one direction (the vertical direction in Figure 2). The gate insulating films 6a and 6b and gate electrodes 7a and 7b embedded in the gate trenches 5a and 5b have a linear (striped) planar pattern that extends parallel to the extension direction of the gate trenches 5a and 5b (the vertical direction in Figure 2).
[0037] The base contact region 9 has a linear (striped) planar pattern that extends parallel to the extension direction of the gate trenches 5a and 5b (up and down direction in Figure 2). Although not shown in Figure 2, the contact trench 8 above the base contact region 9 also has a linear (striped) planar pattern that extends parallel to the extension direction of the gate trenches 5a and 5b (up and down direction in Figure 2).
[0038] The emitter regions 4a and 4b have multiple rectangular planar patterns that are intermittently (discontinuously) provided via the base region 3, parallel to the extension direction of the gate trenches 5a and 5b (the vertical direction in Figure 2). The emitter regions 4a and 4b and the base region 3 are provided parallel, alternately, and periodically to the extension direction of the gate trenches 5a and 5b (the vertical direction in Figure 2).
[0039] Figure 3 is a vertical cross-sectional view along the line C-C' in Figure 2. The horizontal cross-sectional view along the line A-A' in Figure 3 corresponds to Figure 2. As shown in Figure 3, in the cross-section where the emitter regions 4a and 4b are not visible, the base region 3 has a U-shaped cross-sectional shape. The upper surface of the base region 3 is in contact with the lower surface of the interlayer insulating film 10. The side surface of the contact trench 8 is in contact with the base region 3. In Figure 3, the case in which the base contact region 9 is in contact only with the lower surface of the contact portion 11 is illustrated, but it may have a U-shaped cross-sectional shape so as to be in contact with both the lower and side surfaces of the contact portion 11, and the upper surface of the contact portion 11 may be in contact with the lower surface of the interlayer insulating film 10.
[0040] Figure 4 is a vertical cross-sectional view along the line D-D' in Figure 2. The horizontal cross-sectional view along the line A-A' in Figure 4 corresponds to Figure 2. As shown in Figure 4, the accumulation layer 2, base region 3, base contact region 9, and contact portion 11 extend in one direction (left-right direction in Figure 4).
[0041] When the insulated gate semiconductor device according to the first embodiment is in operation, the emitter electrode 12 is at ground potential, a positive voltage is applied to the collector electrode 15, and when a positive voltage above a threshold is applied to the gate electrodes 7a and 7b, an inversion layer (channel) is formed on the side of the gate trenches 5a and 5b in the base region 3, and the device enters an ON state. In the ON state, current flows from the collector electrode 15 to the emitter electrode 12 via the collector region 14, FS layer 13, drift layer 1, storage layer 2, the inversion layer in the base region 3, and the emitter regions 4a and 4b. On the other hand, when the voltage applied to the gate electrodes 7a and 7b is below the threshold, an inversion layer is not formed in the base region 3, resulting in an OFF state, and no current flows from the collector electrode 15 to the emitter electrode 12.
[0042] According to the insulated gate type semiconductor device of the first embodiment, by providing the contact trench 8 and contact portion 11, hole discharge can be promoted and latch-up resistance can be improved. Furthermore, as will be described later, if the device is manufactured through a manufacturing process that generates particles, latch-up failure can be suppressed.
[0043] <Method for Manufacturing a Semiconductor Device> Next, an example of a method for manufacturing an insulated gate type semiconductor device according to the first embodiment will be described with reference to Figures 5 to 14, which correspond to the cross-sectional positions in Figure 1. It should be noted that the method for manufacturing a semiconductor device described below is just one example, and it is of course possible to realize this within the scope of the claims, including this modified example, by various other manufacturing methods.
[0044] First, the first conductivity type (n － A semiconductor substrate 100 is prepared, consisting of a silicon (Si) wafer of a specific type. － The mold region functions as the drift layer 1. Next, a portion of the upper part of the drift layer 1 is selectively removed using photolithography and dry etching. As a result, as shown in Figure 5, a plurality of gate trenches 5a and 5b are formed on the upper part of the drift layer 1.
[0045] Next, a gate insulating film is formed on the inside of the lower and side surfaces of the gate trenches 5a and 5b by thermal oxidation or chemical vapor deposition (CVD). Then, a polysilicon film (doped polysilicon film) with high concentrations of impurities such as phosphorus (P) and boron (B) is deposited by CVD or the like, filling the inside of the gate trenches 5a and 5b through the gate insulating film. Subsequently, the polysilicon film and gate insulating film on the drift layer 1 are selectively removed by photolithography and dry etching. As a result, as shown in Figure 6, an insulated gate type electrode structure (6a, 7a) and (6b, 7b) consisting of gate insulating films 6a and 6b and gate electrodes 7a and 7b of the polysilicon film is formed inside the gate trenches 5a and 5b.
[0046] Next, p-type impurities such as boron (B) are ion-implanted from the upper side of the drift layer 1, and a heat treatment is performed to form a p-type base region 3 on the upper side of the drift layer 1. Next, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted from the upper side of the drift layer 1, and a heat treatment is performed to form an n-type storage layer 2 on the upper side of the drift layer 1. The order of ion implantation for forming the storage layer 2 and for forming the base region 3 is not particularly limited, and the order may be changed. The heat treatment may also be performed at any timing. As a result, as shown in Figure 7, the storage layer 2 is formed on the upper side of the drift layer 1, and the base region 3 is formed on the upper side of the storage layer 2. No emitter region is formed on the upper side of the base region 3, and the upper surface of the base region 3 is exposed. Note that the storage layer 2 does not necessarily have to be formed.
[0047] Furthermore, before the steps of forming the gate trenches 5a and 5b shown in Figure 5, and the steps of forming the insulated gate electrode structures (6a, 7a) and (6b, 7b) shown in Figure 6, the steps of forming the n-type storage layer 2 and the p-type base region 3 shown in Figure 7 may be performed.
[0048] Next, an interlayer insulating film 10 is formed on the gate insulating films 6a and 6b, gate electrodes 7a and 7b, and the upper surface of the base region 3 by CVD or the like. Then, as shown in Figure 8, a photoresist film 21 is applied to the upper surface of the interlayer insulating film 10, and the photoresist film 21 is patterned using photolithography technology. Using the patterned photoresist film 21 as an etching mask, a portion of the interlayer insulating film 10 is selectively removed by dry etching or the like. As a result, a contact hole 10a is opened in the interlayer insulating film 10, exposing a portion of the upper surface of the base region 3.
[0049] Next, the photoresist film 21 and the interlayer insulating film 10 are used as etching masks to selectively remove a portion of the base region 3 exposed from the contact hole 10a by dry etching or the like. As a result, as shown in Figure 9, a contact trench 8 is formed on the upper part of the base region 3, continuous with the contact hole 10a.
[0050] Next, the photoresist film 21 and the interlayer insulating film 10 are used as ion implantation masks to implant p-type impurities such as boron (B) perpendicularly to the lower surface of the contact trench 8. As a result, as shown in Figure 10, an ion implantation region 9' of p-type impurities is formed so as to be in contact with the lower surface of the contact trench 8 and the base region 3. If the contact trench 8 has a forward tapered shape, the ion implantation region 9' of p-type impurities may be formed with a U-shaped cross-section so as to be in contact with the lower surface and side surface of the contact trench 8. After that, the photoresist film 21 is removed.
[0051] Next, a photoresist film 22 is applied to the upper surface of the interlayer insulating film 10, and the photoresist film 22 is patterned using photolithography technology. Using the patterned photoresist film 22 and the interlayer insulating film 10 as an ion implantation mask, n-type impurities such as phosphorus (P) or arsenic (As) are ion implanted obliquely into one of the pair of sides of the contact trench 8 (the left side of the contact trench 8 in Figure 11), as shown in Figure 11. This forms an ion implantation region 4a' of n-type impurities that is in contact with the side of the contact trench 8 and the base region 3, respectively.
[0052] Next, as shown in Figure 12, the photoresist film 22 and the interlayer insulating film 10 are used as ion implantation masks to ion implant n-type impurities such as phosphorus (P) or arsenic (As) at an oblique angle into the other of the pair of sides of the contact trench 8 (the right side of the contact trench 8 in Figure 12). This forms an ion implantation region 4b' of n-type impurities that is in contact with the side of the contact trench 8 and the base region 3, respectively. After that, the photoresist film 22 is removed.
[0053] Next, the implanted impurity ions are activated by heat treatment. As shown in Figure 13, the ion implantation region 9' for p-type impurities, the ion implantation region 4a' for n-type impurities, and the ion implantation region 4b' for n-type impurities become the base contact region 9, the emitter region 4a, and the emitter region 4b, respectively. The emitter regions 4a and 4b are in contact with the sides of the gate trenches 5a and 5b. If the ion implantation region 9' for p-type impurities is also formed on the side of the contact trench 8, the p-type impurities in the base contact region 9 on the side of the contact trench 8 are compensated for by the n-type impurities, reversing the conductivity type and becoming emitter regions 4a and 4b. The peak position of the impurity concentration distribution in the emitter regions 4a and 4b is parallel to the side of the contact trench 8 that is in contact with the emitter regions 4a and 4b, for example, at the position of the side of the contact trench 8 that is in contact with the emitter regions 4a and 4b. As shown in Figure 2, the emitter regions 4a and 4b are formed intermittently (discontinuously) on the planar pattern via the base region 3.
[0054] As shown in Figure 10, after forming the ion implantation region 9' of p-type impurities, the photoresist film 21 may not be removed. Instead, the photoresist film 21 and the interlayer insulating film 10 may be used as an ion implantation mask to diagonally implant n-type impurities into each of the pair of sides of the contact trench 8, thereby forming the ion implantation regions 4a' and 4b' of n-type impurities. In this case, the emitter regions 4a and 4b are formed to have a continuous linear planar pattern without passing through the base region 3. Thus, when the photoresist film 21 is used as a common ion implantation mask in the steps of forming the base contact region 9 and forming the emitter regions 4a and 4b, the step of forming the ion implantation regions 4a' and 4b' of n-type impurities may be performed before the step of forming the ion implantation region 9' of p-type impurities.
[0055] Next, contact portions 11, consisting of a barrier metal film and a contact plug, are embedded in the contact trench 8 and contact hole 10a by sputtering, vapor deposition, or dry etching. Then, as shown in Figure 14, emitter electrodes 12 are deposited on the upper surface of the contact portions 11 and the interlayer insulating film 10 by sputtering, vapor deposition, or the like.
[0056] Next, the drift layer 1 is ground from the bottom side to adjust its thickness to the product thickness. Then, n-type impurities such as phosphorus (P) or selenium (Se) are ion-implanted from the bottom side of the drift layer 1. ＋ A type FS layer 13 is formed. Next, p-type impurities such as boron (B) are ion-implanted from the lower side of the drift layer 1 at a lower acceleration voltage than when ion implanting was performed to form the FS layer 13. ＋ A collector region 14 of the type is formed. Subsequently, the implanted impurity ions are activated by heat treatment.
[0057] In the first embodiment of the manufacturing method for an insulated gate type semiconductor device, the heat treatment after ion implantation is performed collectively after multiple ion implantation steps, but it may also be performed individually after each ion implantation step. Furthermore, in the first embodiment of the manufacturing method for an insulated gate type semiconductor device, ion implantation is performed twice to form the ion implantation regions 4a' and 4b' of n-type impurities, but only one of either the ion implantation region 4a' or the ion implantation region 4b' of n-type impurities may be formed. Therefore, ion implantation to form the ion implantation region of n-type impurities may be performed only once.
[0058] Next, a collector electrode 15 made of gold (Au) or the like is formed on the lower surface side of the collector region 14 by sputtering or vapor deposition. After that, the semiconductor substrate is cut (diced) into individual pieces to complete the insulated gate type semiconductor device according to the first embodiment shown in Figure 1.
[0059] Here, we will describe the case in the manufacturing process of an insulated gate semiconductor device according to the first embodiment, where, as shown in Figure 8, a photoresist film 21 is applied to the upper surface of the interlayer insulating film 10, and then, as shown in Figure 15, particles 31 adhere to the photoresist film 21. The particles 31 are fine particles of metal or an insulator, and can be unintentionally generated from the manufacturing equipment or materials during the manufacturing process. The size and number of particles 31 are not particularly limited. The particles 31 are located above where the contact trench 8 in the mesa portion between adjacent gate trenches 5a and 5b is to be formed.
[0060] When particles 31 adhere to the photoresist film 21, in the process of forming the contact holes 10a and contact trenches 8 shown in Figure 9, the formation of the contact holes 10a and contact trenches 8 is inhibited by the particles 31 in the area directly beneath them. As a result, the cross-sectional structure of the mesa shown in Figure 15 is maintained.
[0061] In the process of forming the ion implantation region 9' of p-type impurities shown in Figure 10, the formation of contact holes 10a and contact trenches 8 is inhibited by the particles 31 in the area directly beneath the particles 31. Therefore, the formation of the ion implantation region 9' of p-type impurities is also inhibited, and the formation of the base contact region 9 after heat treatment is also inhibited. As a result, the cross-sectional structure of the mesa shown in Figure 15 is maintained.
[0062] In the process of forming the ion implantation regions 4a' and 4b' of n-type impurities shown in Figures 11 and 12, particles 31 are removed when the photoresist film 21 is removed. However, in the areas where particles 31 were attached, the formation of contact holes 10a and contact trenches 8 is inhibited, which also inhibits the formation of the ion implantation regions 4a' and 4b' of n-type impurities, and thus inhibits the formation of emitter regions 4a and 4b after heat treatment. As a result, the cross-sectional structure of the mesa shown in Figure 15 is maintained.
[0063] Figure 16 shows a cross-section corresponding to the vertical cross-sectional position of the insulated gate type semiconductor device according to the first embodiment shown in Figure 1, when manufactured through a manufacturing process in which particles 31 are generated. In Figure 16, the position where particles 31 are generated is schematically shown by a dashed line. As shown in Figure 16, although the contact trench 8 and contact portion 11 are not formed at the position where particles 31 are generated, the emitter regions 4a and 4b are also not formed on the upper surface side of the base region 3, so the hole discharge path does not become long, and latch-up failure can be suppressed.
[0064] Figure 17 shows a cross-section corresponding to the vertical cross-sectional position of the insulated gate type semiconductor device according to the first embodiment shown in Figure 4, when manufactured through a manufacturing process in which particles 31 are generated. In Figure 17, the location where particles 31 are generated is schematically shown with a dashed line. As shown in Figure 17, the contact portion 11 is divided at the location where particles 31 are generated. A part of the base region 3 protrudes between the divided contact portions 11, and the protruding portion is in contact with the lower surface of the interlayer insulating film 10.
[0065] <Comparative Example> Here, a method for manufacturing an insulated gate semiconductor device according to a comparative example will be described. The method for manufacturing an insulated gate semiconductor device according to the comparative example is the same as the method for manufacturing an insulated gate semiconductor device according to the first embodiment up to the step of forming the insulated gate electrode structures (6a, 7a) and (6b, 7b) shown in Figure 6.
[0066] Next, as shown in Figure 18, p-type and n-type impurities are sequentially ion-implanted and heat-treated, resulting in an n-type storage layer 2, a p-type base region 3, and n-type impurities on the upper part of the drift layer 1. ＋ A type emitter region 4 is formed. That is, the method for manufacturing an insulated gate semiconductor device according to the comparative example differs from the method for manufacturing an insulated gate semiconductor device according to the first embodiment in that, at this point, not only the storage layer 2 and the base region 3 are formed, but also the emitter region 4.
[0067] Next, an interlayer insulating film 10 is formed on the gate insulating films 6a and 6b, the gate electrodes 7a and 7b, and the upper surface of the emitter region 4. Then, a photoresist film 21 is applied to the upper surface of the interlayer insulating film 10, and the photoresist film 21 is patterned using photolithography technology. Using the patterned photoresist film 21 as an etching mask, contact holes 10a are opened in the interlayer insulating film 10 by dry etching or the like, as shown in Figure 19, and contact trenches 8 are formed to be continuous with the contact holes 10a. The contact trenches 8 are formed to penetrate the emitter region 4 and reach the base region 3.
[0068] Next, as shown in Figure 20, p-type impurities are ion-implanted into the lower surface of the contact trench 8 using the photoresist film 21 and the interlayer insulating film 10 as ion implantation masks, and then heat-treated, p ＋ A base contact region 9 of the mold is formed. Next, as shown in Figure 14, the contact portion 11 is embedded in the contact trench 8 and the contact hole 10a. The subsequent steps until the completion of the insulated gate type semiconductor device according to the comparative example are the same as the manufacturing method of the insulated gate type semiconductor device according to the first embodiment.
[0069] Here, we will explain the case in the manufacturing process of an insulated gate type semiconductor device according to a comparative example, where, as shown in Figure 21, a photoresist film 21 is applied to the upper surface of the interlayer insulating film 10, and then particles 31 adhere to the photoresist film 21.
[0070] When particles 31 adhere to the photoresist film 21, in the process of forming the contact holes 10a and contact trenches 8 shown in Figure 19, the formation of the contact holes 10a and contact trenches 8 is inhibited by the particles 31 in the area directly beneath them. Therefore, the cross-sectional structure of the mesa shown in Figure 21 is maintained.
[0071] In the process of forming the base contact region 9 shown in Figure 20, the formation of the contact hole 10a and the contact trench 8 is inhibited by the particle 31 in the area directly beneath the particle 31, and therefore the formation of the base contact region 9 is also inhibited. As a result, the cross-sectional structure of the mesa shown in Figure 21 is maintained.
[0072] Thus, in the manufacturing method of an insulated gate semiconductor device according to the comparative example, since the contact trench 8 is formed after the emitter region 4 is formed, if the formation of the contact trench 8 is hindered by the particles 31, the emitter region 4 is formed directly below the particles 31. As a result, the hole discharge path becomes longer, making it easier for latch-up failure to occur.
[0073] In contrast, according to the manufacturing method of an insulated gate type semiconductor device according to the first embodiment, emitter regions 4a and 4b are formed after the contact trench 8 is formed. Therefore, if the formation of the contact trench 8 is hindered by the particle 31, the emitter region is not formed directly below the particle 31. As a result, the hole discharge path does not become long, and latch-up failure can be suppressed.
[0074] (Second Embodiment) Figure 22 is a vertical cross-sectional view of an insulated gate semiconductor device according to the second embodiment, and corresponds to the position of the vertical cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 1. The insulated gate semiconductor device according to the second embodiment differs from the insulated gate semiconductor device according to the first embodiment in that the peak positions L1 and L2 of the impurity concentration distribution in the emitter regions 4a and 4b are located away from the side surface of the contact trench 8.
[0075] Figure 22 schematically shows the peak positions L1 and L2 of the impurity concentration distribution in the emitter regions 4a and 4b using dashed lines. The peak positions L1 and L2 are parallel to the side surface of the contact trench 8, located at predetermined distances D1 and D2 from the side surface of the contact trench 8, and are linear along the side surface. The predetermined distances D1 and D2 can be adjusted by the acceleration voltage of ion implantation for forming the emitter regions 4a and 4b. The further away from the peak positions L1 and L2, the lower the impurity concentration in the emitter regions 4a and 4b. The other configurations of the insulated gate semiconductor device according to the second embodiment are substantially the same as those of the insulated gate semiconductor device according to the first embodiment, so redundant explanations are omitted.
[0076] In the method for manufacturing an insulated gate semiconductor device according to the second embodiment, the acceleration voltage for ion implantation to form emitter regions 4a and 4b is higher than that of the method for manufacturing an insulated gate semiconductor device according to the first embodiment, and the emitter regions 4a and 4b are formed such that their peak positions L1 and L2 are away from the side surface of the contact trench 8. The other steps of the method for manufacturing an insulated gate semiconductor device according to the second embodiment are substantially the same as those of the method for manufacturing an insulated gate semiconductor device according to the first embodiment, so redundant explanations are omitted.
[0077] According to the second embodiment, similar to the first embodiment, after forming the contact trench 8, the emitter region 4 is formed by ion implantation and heat treatment of the side wall of the contact trench 8. Therefore, if the formation of the contact trench 8 is inhibited by the particles 31, the emitter region 4 is not formed, and thus latch-up failure can be suppressed.
[0078] (Third Embodiment) Figure 23 is a horizontal cross-sectional view of an insulated gate semiconductor device according to the third embodiment, and corresponds to the position of the horizontal cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 2. The insulated gate semiconductor device according to the third embodiment differs from the insulated gate semiconductor device according to the first embodiment in that the emitter regions 4a and 4b have a linear (striped) planar pattern that extends continuously in one direction without passing through the base region 3. The vertical cross-sectional view along the line B-B' in Figure 23 corresponds to Figure 1.
[0079] Other configurations of the insulated gate semiconductor device according to the third embodiment are substantially the same as those of the insulated gate semiconductor device according to the first embodiment, so redundant explanations will be omitted.
[0080] The method for manufacturing an insulated gate semiconductor device according to the third embodiment is the same as the method for manufacturing an insulated gate semiconductor device according to the first embodiment until the ion implantation region 9' of p-type impurities is formed, as shown in Figure 10. The method for manufacturing an insulated gate semiconductor device according to the third embodiment differs from the method for manufacturing an insulated gate semiconductor device according to the first embodiment in that the photoresist film 21 is not removed after the ion implantation region 9' of p-type impurities is formed, and the photoresist film 21 is used as an ion implantation mask when ion implanting to form the ion implantation regions 4a' and 4b' of n-type impurities shown in Figures 11 and 12.
[0081] Other steps in the manufacturing method of the insulated gate semiconductor device according to the third embodiment are substantially the same as those in the manufacturing method of the insulated gate semiconductor device according to the first embodiment, so redundant explanations will be omitted.
[0082] According to the third embodiment, similar to the first embodiment, after forming the contact trench 8, the emitter region 4 is formed by ion implantation and heat treatment of the side wall of the contact trench 8. Therefore, if the formation of the contact trench 8 is inhibited by particles 31, the emitter region 4 is not formed, and thus latch-up failure can be suppressed.
[0083] (Fourth Embodiment) Figure 24 is a vertical cross-sectional view of an insulated gate semiconductor device according to the fourth embodiment, and corresponds to the position of the vertical cross-section of the insulated gate semiconductor device according to the first embodiment shown in Figure 1. In the insulated gate semiconductor device according to the fourth embodiment, a gate electrode 7a is embedded inside the gate trench 5a via a gate insulating film 6a, and a dummy trench electrode 7c, which is not connected to the gate electrode, is embedded inside the dummy trench 5c via a dummy trench insulating film 6c. For example, the dummy trench electrode 7c is subjected to the same potential as the emitter electrode 12.
[0084] The method for manufacturing an insulated gate semiconductor device according to the fourth embodiment differs from the method for manufacturing an insulated gate semiconductor device according to the first embodiment in that it does not perform the step of forming the ion implantation region 4b' of n-type impurities shown in Figure 12. Since the dummy trench 5c does not function as a gate trench, the emitter region 4b is not required.
[0085] (Other Embodiments) Although the first to fourth embodiments have been described above, the descriptions and drawings that constitute part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments, examples and operational techniques will become apparent to those skilled in the art from this disclosure.
[0086] For example, while IGBTs were used as examples of insulated gate type semiconductor devices according to the first to fourth embodiments, the method is also applicable to reverse conduction type IGBTs (RC-IGBTs) and reverse blocking insulated gate type bipolar transistors (RB-IGBTs). Furthermore, the p of the IGBT shown in Figure 1 ＋ The collector area 14 of type n ＋ This is also applicable to MOSFETs with a drain region of the type . Furthermore, although trench gate type semiconductor devices were exemplified as insulated gate type semiconductor devices according to the first to fourth embodiments, this is also applicable to planar gate type semiconductor devices.
[0087] Furthermore, the configurations disclosed in the first to fourth embodiments can be combined as appropriate, within the bounds of consistency. Thus, this disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features relating to the claims that are appropriate based on the above description.
[0088] 1…Drift layer 2…Storage layer 3…Base region 4, 4a, 4b…Emitter region 4a', 4b'…Ion implantation region 5a, 5b…Gate trench 5c…Dummy trench 6a, 6b…Gate insulating film 6c…Dummy trench insulating film 7a, 7b…Gate electrode 7c…Dummy trench electrode 8…Contact trench 9…Base contact region 9'…Ion implantation region 10…Interlayer insulating film 10a…Contact hole 11…Contact area 12…Emitter electrode 13…FS layer 14…Collector region 15…Collector electrode 21, 22…Photoresist film 31…Particle 100…Semiconductor substrate D1, D2…Distance L1, L2…Peak position
Claims
1. An insulated gate semiconductor device comprising: a drift layer of a first conductivity type provided on a semiconductor substrate; a base region of a second conductivity type provided on the upper surface side of the drift layer; a main electrode region of a first conductivity type provided on the upper surface side of the base region; a contact portion embedded in a contact trench provided in the depth direction from the upper surface of the semiconductor substrate and in contact with the main electrode region at its side wall; and a base contact region of a second conductivity type provided below the contact trench and in contact with the base region, having a higher impurity concentration than the base region, wherein the peak position of the impurity concentration distribution of the main electrode region is parallel to the side surface of the contact trench.
2. The insulated gate semiconductor device according to claim 1, wherein the peak position is located on the side surface of the contact trench.
3. The insulated gate semiconductor device according to claim 1, wherein the peak position is located away from the side surface of the contact trench.
4. The insulated gate semiconductor device according to claim 1 or 2, wherein the lower end of the main electrode region is located deeper than the upper surface of the base contact region.
5. The insulated gate semiconductor device according to claim 1 or 2, further comprising: a gate trench provided in the depth direction from the upper surface of the semiconductor substrate and in contact with the main electrode region and the base region; and a gate electrode embedded in the gate trench via a gate insulating film.
6. The insulated gate semiconductor device according to claim 1 or 2, wherein the insulated gate semiconductor device is an insulated gate bipolar transistor.
7. The insulated gate semiconductor device according to claim 1 or 2, wherein the contact trench has a linear planar pattern extending in one direction, and in the direction of extension of the contact trench, a portion of the contact trench is separated via the base region.
8. The insulated gate semiconductor device according to claim 1 or 2, wherein the main electrode region has a linear planar pattern extending in one direction.
9. The insulated gate semiconductor device according to claim 1 or 2, wherein the main electrode region has an intermittent rectangular planar pattern through the base region.
10. A method for manufacturing an insulated gate semiconductor device, comprising: forming a base region of a second conductivity type on the upper surface side of a drift layer of a first conductivity type provided on a semiconductor substrate; forming a contact trench in the depth direction from the upper surface of the base region; forming a base contact region of a second conductivity type having a higher impurity concentration than the base region, wherein impurities of the second conductivity type are ion-implanted into the lower surface of the contact trench; forming a main electrode region of a first conductivity type, wherein impurities of the first conductivity type are ion-implanted diagonally into the side surface of the contact trench; and embedding a contact portion in the contact trench.
11. The method for manufacturing an insulated gate semiconductor device according to claim 10, wherein the step of forming the main electrode region includes the step of diagonally ion implanting the first conductivity type impurity into each of the pair of sides of the contact trench.
12. A method for manufacturing an insulated gate semiconductor device according to claim 10 or 11, further comprising the steps of: forming a gate trench in the depth direction from the upper surface of the semiconductor substrate; and embedding a gate electrode in the gate trench via a gate insulating film.