Device system, data processing apparatus, method for controlling device system, computer program, and computer-readable recording medium having computer program recorded thereon

Abstract

The present invention starts internal tests of an integrated circuit at an early stage. This device system comprises: a device that outputs data; and the integrated circuit including a device control circuit that controls the device, a data processing circuit that processes the data output by the device, and a test control circuit. The test control circuit executes the internal test of the device and the internal test of the data processing circuit in parallel, and executes the internal test of the device control circuit after completion of the internal test of the device.

Description

Device system, data processing apparatus, device system control method, computer program, and computer-readable recording medium having the computer program recorded thereon

[0001] The technology disclosed in the present specification relates to a device system, a data processing apparatus, a device system control method, a computer program, and a computer-readable recording medium having the computer program recorded thereon.

[0002] For example, with the development of autonomous driving (AD) systems and advanced driver assistance systems (ADAS), a plurality of sensors are mounted on vehicles. Examples of the sensors include LiDAR (light detection and ranging), CMOS (Complementary Metal Oxide Semiconductor) sensors, millimeter-wave radars, and the like, which are used for grasping the surrounding environment and estimating self-position when the vehicle is traveling. A data processing apparatus that processes data from sensors includes an integrated circuit, and the integrated circuit includes a device control circuit that controls the sensors, a data processing circuit that processes data output from the sensors, and a test control circuit.

[0003] Conventionally, some integrated circuits are provided with a self-diagnosis function such as LBIST (Logic Build-in-self-test). The self-diagnosis function is a function for executing an internal test in which the integrated circuit itself inspects whether or not the integrated circuit has a failure (see Patent Documents 1 to 3).

[0004] Japanese National Publication of International Patent Application No. 2020-518826, Japanese Unexamined Patent Application Publication No. 2022-51703, Japanese Unexamined Patent Application Publication No. 2021-135296

[0005] A data processing unit and devices (such as sensors) that are communicatively connected to the data processing unit constitute a device system. Some of these devices also have self-diagnostic functions. In conventional device systems, when the device system is started up, an internal test of the device begins first, and after the completion of that internal test, an internal test of the integrated circuit begins.

[0006] This specification discloses a technology capable of solving the above-mentioned problems.

[0007] The technologies disclosed herein can be implemented, for example, in the following forms:

[0008] (1) A device system disclosed herein is a device system comprising an integrated circuit including a device that outputs data, a device control circuit that controls the device, a data processing circuit that processes the data output by the device, and a test control circuit, wherein the test control circuit performs internal testing of the device and internal testing of the data processing circuit in parallel, and performs internal testing of the device control circuit after the completion of internal testing of the device. With this configuration, internal testing of some circuits within the integrated circuit can be performed in parallel with internal testing of the device, thereby enabling early commencement of internal testing of the integrated circuit.

[0009] (2) The above device system may further include a first interface for communication between the device control circuit and the data processing circuit, and the test control circuit may be configured to disable communication via the first interface during the period in which the internal test of the data processing circuit is being performed. This configuration makes it possible to suppress the effect of the output results from the internal test of the data processing circuit on the device control circuit via the first interface.

[0010] (3) The above device system may further include a second interface for communication between the device and the device control circuit, and the second interface may be disabled during the execution period of the internal test of the device control circuit. This configuration makes it possible to suppress the output results of the internal test of the device control circuit from affecting the device via the second interface.

[0011] (4) In the above device system, the test control circuit may be configured to start internal testing of the device and internal testing of the data processing circuit based on the startup of the device system, and to perform internal testing of the device control circuit while the device is operating after the device system has started up. With this configuration, by performing internal testing of the data processing circuit in addition to the device when the device system starts up, it is not necessary to perform internal testing of the data processing circuit while the device is operating. Therefore, it is possible to suppress the limitation of the device's execution time due to the execution of internal testing of the integrated circuit after the device system has started up.

[0012] (5) In the above device system, the integrated circuit may further include a setting change circuit that outputs an instruction signal to instruct a change in the settings of the device, and the device control circuit may be configured to receive the instruction signal from the setting change circuit and transmit it to the device. With this configuration, the device control circuit can also serve the role of passing the instruction signal from the setting change circuit to the device.

[0013] (6) The above device system may be provided with a third interface for communication between the device control circuit and the setting change circuit, and the communication via the third interface may be disabled during the execution period of the internal test of the device control circuit. With this configuration, it is possible to suppress the output results of the internal test of the device control circuit from affecting the setting change circuit via the third interface.

[0014] (7) A data processing device disclosed herein is a data processing device comprising an integrated circuit including a device control circuit for controlling a device that outputs data, a data processing circuit for processing the data output by the device, and a test control circuit, wherein the test control circuit performs internal testing of the device and internal testing of the data processing circuit in parallel, and performs internal testing of the device control circuit after completion of internal testing of the device. According to this data processing device, internal testing of the integrated circuit can be started earlier by performing it in parallel with internal testing of the device.

[0015] Furthermore, the technologies disclosed herein can be implemented in various forms, for example, as a device system, a data processing device, a method for controlling a device system (data processing device), a control program for controlling a device system (data processing device), and a computer-readable recording medium on which such computer program is stored.

[0016] Block diagram schematically showing the configuration of the sensor system of the embodiment. Explanatory diagram showing the operation of the sensor system at startup. Explanatory diagram showing the operation of the sensor system after completion of the internal test of the second test area. Explanatory diagram showing the operation of the sensor system while receiving sensor data. Explanatory diagram showing the operation of the sensor system after completion of the internal test of the first test area. Explanatory diagram showing the operation of the sensor system when the sensing operation settings are changed. Sequence diagram showing the processing process in the sensor system.

[0017] A. Embodiment: A-1. Configuration of Sensor System 1: This embodiment will be described with reference to Figures 1 to 7. Figure 1 is a block diagram schematically showing the configuration of the sensor system 1 of this embodiment. The sensor system 1 of this embodiment is mounted, for example, on a vehicle on which AD or ADAS is implemented. As shown in Figure 1, the sensor system 1 comprises a plurality of sensors 20, 22 and a sensor data processing device 10. The sensor system 1 is an example of a device system, and the sensors 20, 22 are examples of devices.

[0018] A-1-1. Sensors: As shown in Figure 1, the multiple sensors 20 and 22 are located outside the sensor data processing device 10 and are capable of communicating with the sensor data processing device 10. Examples of sensors 20 and 22 include, for example, optical sensors such as LiDAR (especially light-receiving elements (e.g., SPAD: Single-Photon-Avalanche-Diode)), image sensors such as CMOS sensors, cameras, millimeter-wave radar, sensors that detect changes in the external environment (such as ambient temperature), GPS (Global Positioning System) sensors, crank angle sensors, rotational speed sensors, knock sensors, motor rotation speed sensors, motor torque sensors, current sensors, acceleration sensors, and gyro sensors.

[0019] Each sensor 20, 22 has a self-diagnostic function. Each sensor 20, 22 incorporates, for example, a DFT (design for testability) circuit for self-diagnostic testing and is configured to perform a BIST (Built In Self Test).

[0020] A-1-2. Sensor data processing device: The sensor data processing device 10 includes an integrated circuit 11. The integrated circuit 11 is, for example, an ASIC (application specific integrated circuit), an FPGA (field programmable gate array), a DSP (digital signal processor), etc.

[0021] The integrated circuit 11 includes a data processing circuit 12, a setting change circuit 14, a test control circuit 16, a sensor control circuit 18, a first clamp circuit 30, and a second clamp circuit 32. The sensor control circuit 18 is an example of a device control circuit, the first clamp circuit 30 is an example of a first interface, and the second clamp circuit 32 is an example of a second interface.

[0022] The data processing circuit 12 processes the sensor data output by sensors 20 and 22. Data processing here refers to, for example, applying processing or transformation (such as image processing) or calculation processing to the received data.

[0023] Specifically, the data processing circuit 12 is communicated to the first sensor 20 via a first data interface L1. If the sensor 20 is, for example, a SPAD, the data processing circuit 12 performs operations such as addition, which integrates the output values ​​of multiple light-receiving data output by the sensor 20; histogram generation, which generates a histogram based on the light-receiving data; and calculation, which calculates the distance to an object based on the light-receiving timing of the light-receiving data. The data processing circuit 12 is communicated to the second sensor 22 via a second data interface L2. If the sensor 22 is, for example, a CMOS sensor, the data processing circuit 12 performs operations such as conversion, which converts analog data output by the sensor 20 into digital data; and detection, which detects a specific object based on the data output by the sensor 20.

[0024] The sensor control circuit 18 is a circuit for controlling each of the sensors 20 and 22. Specifically, the sensor control circuit 18 controls the sensing operation of each of the sensors 20 and 22, and performs initial operations such as initializing the sensing settings of each of the sensors 20 and 22 to the settings for internal testing (self-diagnostic testing) of each of the sensors 20 and 22 when the sensor system 1 (each of the sensors 20 and 22) is started up.

[0025] The setting change circuit 14 outputs an instruction signal to change the sensing settings of each sensor 20, 22. For example, after the sensor system 1 (each sensor 20, 22) is started up (initial operation as described above), the setting change circuit 14 outputs an instruction signal to change from the settings for internal testing to the settings for sensing operation (for example, the setting values ​​of parameters related to sensing operation (for example, resolution, image size, frame rate, etc.)).

[0026] The first clamp circuit 30 communicates with the setting change circuit 14 and the sensor control circuit 18. In this embodiment, the data processing circuit 12 is communicated with the sensor control circuit 18 via the setting change circuit 14 and the first clamp circuit 30. Based on the clamp start signal S1 from the test control circuit 16 (see Figure 2 described later), the first clamp circuit 30 fixes the signal level in the first clamp circuit 30 to a predetermined level, thereby disabling communication by the first clamp circuit 30.

[0027] The second clamp circuit 32 connects each of the sensors 20 and 22 to the sensor control circuit 18 in a communicative manner. Based on the clamp start signal S31 from the test control circuit 16 (see Figure 4 described later), the second clamp circuit 32 fixes the signal level in the second clamp circuit 32 to a predetermined level, thereby disabling communication by the second clamp circuit 32.

[0028] As will be described later, the test control circuit 16 controls the internal testing of each sensor 20, 22 and the internal testing of each circuit mounted on the integrated circuit 11.

[0029] In this embodiment, the integrated circuit 11 is divided into a plurality of test areas, and each test area is configured to perform internal tests on one or more circuits mounted in that test area. For example, a scan chain for scan testing is constructed on a test area basis. Specifically, the integrated circuit 11 is divided into a first test area EA and a second test area EB. The first test area EA is an area that includes a circuit (sensor control circuit 18) for performing initial operations on sensors 20 and 22. The second test area EB is an area that includes circuits (data processing circuit 12, setting change circuit 14) for performing processing other than initial operations.

[0030] A-2. Sensor System Operation: Figures 2 to 6 are explanatory diagrams showing the operation of the sensor system 1, and Figure 7 is a sequence diagram showing the processing process in the sensor system. In Figure 7, "SCC" means the sensor control circuit 18, "DSC" means the data processing circuit 12, "TCC" means the test control circuit 16, and "SC" means the setting change circuit 14.

[0031] (Sensor system startup): Figure 2 is an explanatory diagram showing the operation of the sensor system 1 during startup. For example, when the startup switch (not shown) of the sensor system 1 is turned on, power is supplied to each element constituting the sensor system 1 (see timing t0 in Figure 7). Next, the test control circuit 16 gives the clamp start signal S1 to the first clamp circuit 30. This disables communication by the first clamp circuit 30.

[0032] The test control circuit 16 sends a test instruction signal S2 to the scan circuit (not shown) of the second test area EB, instructing it to start an internal test (e.g., LBIST) for the second test area EB (see timing t1 in Figure 7). This initiates an internal test of the data processing circuit 12 and the setting change circuit 14 included in the second test area EB.

[0033] During the execution of the internal test on the second test area EB, the sensor control circuit 18 outputs an initial setting signal S3 to set the sensing settings of each sensor 20, 22 to the initial setting X for the internal test (see "SettingX" in Figure 7) (see timing t2 in Figure 7). At this time, communication by the second clamp circuit 32 is enabled. Therefore, the initial setting signal S3 is provided to the first sensor 20 via the second clamp circuit 32 and the first control interface L3. As a result, the first sensor 20 initializes its sensing settings and starts the internal test. The initial setting signal S3 is also provided to the second sensor 22 via the second clamp circuit 32 and the second control interface L4. As a result, the second sensor 22 initializes its sensing settings and starts the internal test. As a result, the internal test on the second test area EB and the internal test on each sensor 20, 22 are executed in parallel.

[0034] After outputting the initial setting signal S3, the sensor control circuit 18 enters a standby state without performing its own internal test. At this point, the execution of the internal test on the second test area EB may cause the circuits included in the second test area EB (data processing circuit 12, setting change circuit 14) to output a signal to the first clamp circuit 30 according to the result of the internal test. However, as described above, communication by the first clamp circuit 30 is disabled. Therefore, it is possible to suppress the above output signal from affecting the first test area EA (sensor control circuit 18) and the setting state (initial setting X state) of each sensor 20, 22.

[0035] (After completion of internal testing of the second test area): Figure 3 is an explanatory diagram showing the operation of the sensor system 1 while it is running and after the completion of internal testing of the second test area EB. If no fault is detected during the internal testing of the second test area EB and the internal testing is completed successfully, the scan circuit (data processing circuit 12, setting change circuit 14) of the second test area EB transmits a test completion signal S21 to the test control circuit 16 (see timing t3 in Figure 7). If a fault is detected during the internal testing, the test control circuit 16 receives an error signal from the data processing circuit 12, etc., and performs a notification process, for example, to notify an error communication to the outside of the sensor system 1.

[0036] When the test control circuit 16 receives the test completion signal S21, it sends a completion notification signal S22 to the sensor control circuit 18 to notify it of the completion of the internal test for the second test area EB. When the sensor control circuit 18 receives the completion notification signal S22, it sends a sensing start signal S23 to each of the sensors 20 and 22 to start their sensing operation. The sensing start signal S23 includes a first setting Y for the sensing operation (see "Setting Y" in Figure 7). As a result, each of the sensors 20 and 22 starts a sensing operation according to the first setting Y, provided that its own internal test has been successfully completed, and sends sensor data D1 and D2 according to the result of that sensing operation to the data processing circuit 12.

[0037] The data processing circuit 12 performs data processing corresponding to each of the sensor data D1 and D2, and sends a reception notification signal S24 to the test control circuit 16 indicating that it has successfully received the sensor data D1 and D2 from each of the sensors 20 and 22. As a result, the test control circuit 16 can determine that the internal tests for each of the sensors 20 and 22 have been successfully completed and that each of the sensors 20 and 22 and the data processing circuit 12 are functioning correctly.

[0038] (Sensor data reception in progress): Figure 4 is an explanatory diagram showing the operation of the sensor system 1 after startup and while receiving sensor data D1 and D2. The test control circuit 16 provides a clamp start signal S31 to the second clamp circuit 32. As a result, in addition to communication by the first clamp circuit 30, communication by the second clamp circuit 32 is also disabled.

[0039] The test control circuit 16 sends a test instruction signal S32 to the scan circuit (not shown) of the first test area EA to instruct it to start an internal test (e.g., LBIST) for the first test area EA (see timing t4 in Figure 7). This starts an internal test on the sensor control circuit 18 included in the first test area EA. During this time, each sensor 20, 22 performs a sensing operation that outputs sensor data D1, D2 at a predetermined period with a first setting Y for sensing operation (indicated as "Data Y Output" in Figure 7), and the data processing circuit 12 repeatedly performs data reception processing (indicated as "Data Y Input" in Figure 7) to receive sensor data D1, D2 from each sensor 20, 22, and data processing on the received sensor data D1, D2. In short, the internal test for the first test area EA is performed after the sensor system 1 is started up and while the data processing circuit 12 is receiving and processing data.

[0040] As described above, during the sensing operation of each sensor 20, 22, communication by the first clamp circuit 30 and communication by the second clamp circuit 32 are disabled. Therefore, it is possible to suppress the output signal corresponding to the result of the internal test for the first test area EA from affecting the second test area EB (data processing circuit 12, setting change circuit 14) and the setting state of each sensor 20, 22 (setting state of the first setting Y).

[0041] (Upon completion of internal testing of the first test area): Figure 5 is an explanatory diagram showing the operation of the sensor system 1 after startup and upon completion of internal testing of the first test area EA. If no fault is detected during the internal testing of the first test area EA and the internal testing is completed successfully, the scan circuit (sensor control circuit 18) of the first test area EA transmits a test completion signal S41 to the test control circuit 16. If a fault is detected during the internal testing, the test control circuit 16 receives an error signal from the sensor control circuit 18 and performs a notification process, for example, to notify an error to the outside of the sensor system 1.

[0042] When the test control circuit 16 receives the test completion signal S41, it transmits a clamp release signal S42 to both the first clamp circuit 30 and the second clamp circuit 32. This activates communication by both the first clamp circuit 30 and the second clamp circuit 32. The test control circuit 16 also transmits a completion notification signal S43 to the setting change circuit 14 to notify it of the completion of the internal test for the first test area EA.

[0043] (When changing the setting of the sensing operation): Figure 6 is an explanatory diagram showing the operation of the sensor system when changing the setting of the sensing operation. After the sensor system 1 is activated, during the sensing operation of the sensors 20 and 22, the setting change circuit 14 may change the setting for the sensing operation. The setting change circuit 14 generates a second setting Z for the sensing operation (see "SettingZ" in FIG. 7) based on, for example, feedback of data processing for the sensor data D1 and D2 in the data processing circuit 12, instruction information from an external device, and the like, and transmits a setting change signal S51 instructing the second setting Z to the sensor control circuit 18 (see timing t5 in FIG. 7). The sensor control circuit 18 transmits the received setting change signal S51 to each of the sensors 20 and 22. Each of the sensors 20 and 22 changes the setting for the sensing operation from the first setting Y to the second setting Z based on the received setting change signal S51, and starts a sensing operation for outputting sensor data D21 and D22 corresponding to the second setting Z (see timing t6 in FIG. 7). In this way, the sensor control circuit 18 can also serve the role of delivering the setting change signal S51 from the setting change circuit 14 to each of the sensors 20 and 22.

[0044] A-3. Effects of the present embodiment: As described above, according to the present embodiment, the test time can be shortened by dividing the test area of the integrated circuit 11. That is, in the present embodiment, the integrated circuit 11 is connected to external devices (sensors 20 and 22), and in coordination with the operations (initialization processing and internal test) of these devices, the time for the self-diagnostic test at the time of starting the sensor system 1 can be shortened. Further, according to the present embodiment, by executing an internal test of a part of the circuits of the integrated circuit 11 in parallel with the internal test of the devices, the internal test of the integrated circuit 11 can be started at an early stage.

[0045] According to the present embodiment, when the sensor system 1 is started up, an internal test of the data processing circuit 12 is executed in addition to the device test, which eliminates the need to execute the internal test of the data processing circuit 12 during operation of the device. Therefore, after the sensor system 1 is started up, it is possible to suppress restriction of the device execution time caused by executing the internal test of the integrated circuit 11. Further, according to the present embodiment, the total time required for the internal test of the device and the internal test of the integrated circuit can be shortened.

[0046] B. Modifications: The technology disclosed in the present specification is not limited to the above-described embodiment, and can be modified into various forms without departing from the gist thereof. For example, the following modifications are also possible.

[0047] In the above embodiment, an example in which the sensor system 1 and the sensor data processing apparatus 10 are mounted on a vehicle has been described, but the present invention is not limited thereto, and the sensor system 1 and the sensor data processing apparatus 10 may be mounted on a moving body, an apparatus, a fixed body, or the like other than a vehicle.

[0048] In the above embodiment, the sensors 20 and 22 are exemplified as the devices. However, any device that outputs data and can execute an internal test may be used, and for example, a storage device such as a RAM may be used.

[0049] In the above embodiment, each device and each circuit has a configuration (BIST) in which a circuit for self-diagnosis test (DFT circuit) is provided inside the device. However, a configuration in which the circuit is installed in a test control circuit 16 or the like outside the device for testing (BOST (Build off Self Test)) may be adopted.

[0050] In the above embodiment, the first clamp circuit 30 and the second clamp circuit 32 are exemplified as the first interface and the second interface. However, the present invention is not limited thereto, and for example, a configuration including a switch element capable of connecting and disconnecting a communication line may be adopted.

[0051] This international application claims priority based on Japanese Patent Application No. 2025-040773, which is a Japanese patent application filed on March 14, 2025, and the entire content of the Japanese Patent Application No. 2025-040773 is incorporated herein by reference into this international application.

[0052] The above description of specific embodiments of the present invention is provided for illustrative purposes only. It is not intended to be exhaustive or to limit the invention to the forms described. Numerous modifications and changes are possible in light of the above description, as will be obvious to those skilled in the art.

[0053] 1: Sensor system 10: Sensor data processing unit 11: Integrated circuit 12: Data processing circuit 14: Setting change circuit 16: Test control circuit 18: Sensor control circuit 20, 22: Sensor 30: First clamp circuit 32: Second clamp circuit EA: First test area EB: Second test area L1: First data interface L2: Second data interface L3: First control interface L4: Second control interface

Claims

1. A device system comprising an integrated circuit including a device that outputs data, a device control circuit that controls the device, a data processing circuit that processes the data output by the device, and a test control circuit, wherein the test control circuit performs an internal test of the device and an internal test of the data processing circuit in parallel, and after the completion of the internal test of the device, performs an internal test of the device control circuit.

2. A device system according to claim 1, further comprising a first interface for communication between the device control circuit and the data processing circuit, wherein the test control circuit disables communication via the first interface during the period in which it is performing an internal test of the data processing circuit.

3. A device system according to claim 1, further comprising a second interface for communication between the device and the device control circuit, wherein communication via the second interface is disabled during the execution period of internal testing of the device control circuit.

4. A device system according to claim 1, wherein the test control circuit starts an internal test of the device and an internal test of the data processing circuit based on the startup of the device system, and after the startup of the device system, performs an internal test of the device control circuit while the device is in operation.

5. A device system according to claim 1, wherein the integrated circuit further includes a setting change circuit that outputs an instruction signal for changing the settings of the device, and the device control circuit receives the instruction signal from the setting change circuit and transmits it to the device.

6. A device system according to claim 5, comprising a third interface for communication between the device control circuit and the setting change circuit, wherein communication via the third interface is disabled during the execution period of internal testing of the device control circuit.

7. A data processing device comprising an integrated circuit including a device control circuit for controlling a device that outputs data, a data processing circuit for processing the data output by the device, and a test control circuit, wherein the test control circuit performs an internal test of the device and an internal test of the data processing circuit in parallel, and after the completion of the internal test of the device, performs an internal test of the device control circuit.

8. A method for controlling a device system comprising: an integrated circuit including a device that outputs data; a device control circuit that controls the device; and a data processing circuit that processes the data output by the device, the method comprising: performing an internal test of the device and an internal test of the data processing circuit in parallel; and performing an internal test of the device control circuit after the completion of the internal test of the device.

9. A control program for a device system comprising an integrated circuit including a device that outputs data, a device control circuit that controls the device, and a data processing circuit that processes the data output by the device, which causes the computer to perform an internal test of the device and an internal test of the data processing circuit in parallel, and after the completion of the internal test of the device, to perform an internal test of the device control circuit.

10. A computer-readable recording medium that records a computer program for controlling a device system comprising: an integrated circuit including a device that outputs data; a device control circuit that controls the device; and a data processing circuit that processes the data output by the device, wherein the recording medium records an internal test of the device and an internal test of the data processing circuit in parallel, and after the completion of the internal test of the device, it records an internal test of the device control circuit.

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