Imaging element and imaging device

Abstract

The present invention improves the ability to adjust the sensitivity of a phase difference signal. Provided is an imaging element comprising: a pixel unit including a plurality of pixels each comprising a photoelectric conversion unit and a charge transfer unit, a charge holding unit that holds a charge, an auxiliary charge holding unit, a coupling unit that couples the auxiliary charge holding unit to the charge holding unit, and a pixel signal generation unit; and an analog-to-digital conversion unit that converts a generated pixel signal. The pixel signal generation unit further generates, on the basis of the charge of a plurality of pixels on one side of the pupil division, a high-sensitivity mode phase difference signal, which is a phase difference signal in a high-sensitivity mode among phase difference signals that are pixel signals for detecting an image plane phase difference by pupil division, and further generates, as a low-sensitivity mode phase difference signal which is a phase difference signal in a low-sensitivity mode, a pixel signal based on the charge of, among the plurality of pixels on the one side of the pupil division, a number of pixels equal to or less than the number of pixels used during generation of the high-sensitivity mode phase difference signal. The analog-to-digital conversion unit adjusts a gain when converting the low-sensitivity mode phase difference signal.

Description

Image Sensor and Imaging Apparatus

[0001] The present disclosure relates to an image sensor and an imaging apparatus.

[0002] In image sensors, to support HDR (High Dynamic Range), image sensors that perform imaging by switching the sensitivity of pixels are used. Furthermore, to support autofocus (AF), image sensors including pixels (phase difference pixels) capable of generating phase difference signals for detecting the image plane phase difference of a subject are used. Such a phase difference pixel is configured to include a plurality of photoelectric conversion units such as photodiodes that perform photoelectric conversion on incident light. For such phase difference pixels, image sensors capable of generating phase difference signals with different sensitivities for HDR have been proposed. For example, an image sensor has been proposed that includes a circuit which collectively converts charges generated by photoelectric conversion units included in a plurality of phase difference pixels into an image signal, and adjusts the sensitivity of the phase difference signal by changing the number of image signals of activated pixels (see, for example, Patent Document 1).

[0003] US Patent Application Publication No. 2022 / 0337771 Specification

[0004] However, in the above-described conventional technology, since adjustment is performed on a pixel-by-pixel basis, there is a problem that the sensitivity of the phase difference signal cannot be adjusted sufficiently.

[0005] Accordingly, the present disclosure proposes an image sensor and an imaging apparatus in which the sensitivity adjustment capability of phase difference signals is improved.

[0006] The image sensor according to this disclosure comprises a pixel unit having a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion of incident light from a subject and a charge transfer unit that transfers the charge generated by the photoelectric conversion, a charge holding unit that holds the charge transferred by the charge transfer unit, a reset unit that performs a reset by discharging the held charge, an auxiliary charge holding unit coupled to the charge holding unit, a coupling unit that connects the auxiliary charge holding unit to the charge holding unit by making the connection between the charge holding unit and the auxiliary charge holding unit conductive, and a pixel signal generation unit that generates a pixel signal based on the held charge, and an analog-to-digital conversion unit that converts the generated pixel signal into a digital pixel signal, wherein the pixel signal generation unit generates a high-sensitivity mode image, which is the pixel signal in a high-sensitivity mode, an operating mode in which the auxiliary charge holding unit and the charge holding unit are not coupled. The pixel signal generation unit generates a primary signal and a low-sensitivity mode pixel signal, which is the pixel signal in the low-sensitivity mode, an operating mode in which the auxiliary charge holding unit and the charge holding unit are coupled. The pixel signal generation unit further generates a phase difference signal, which is the pixel signal for detecting the image plane phase difference by dividing the pupil, in both the high-sensitivity mode and the low-sensitivity mode. The pixel signal generation unit generates the high-sensitivity mode phase difference signal, which is the phase difference signal in the high-sensitivity mode, based on the charges of multiple pixels on one side of the pupil division, and generates the low-sensitivity mode phase difference signal, which is the phase difference signal in the low-sensitivity mode, based on the charges of a number of pixels on one side of the pupil division that is less than or equal to the number of pixels in the high-sensitivity mode. The analog-to-digital conversion unit adjusts the gain when converting the low-sensitivity mode phase difference signal.

[0007] This figure shows an example of the configuration of an image sensor according to the first embodiment of this disclosure. This figure shows an example of the configuration of a pixel array section according to the first embodiment of this disclosure. This is a cross-sectional view showing an example of the configuration of a pixel block according to the first embodiment of this disclosure. This figure shows an example of the circuit configuration of a pixel unit according to the first embodiment of this disclosure. This figure shows an example of the configuration of a column signal processing unit according to the first embodiment of this disclosure. This figure shows an example of the configuration of an analog-to-digital conversion section according to the first embodiment of this disclosure. This figure shows an example of the generation of a pixel signal and a phase difference signal according to the first embodiment of this disclosure. This figure shows an example of the generation of a pixel signal and a phase difference signal according to the first embodiment of this disclosure. This figure shows an example of the generation of a pixel signal and a phase difference signal according to the first embodiment of this disclosure. This figure shows an example of the generation of a pixel signal and a phase difference signal according to the first embodiment of this disclosure. This figure shows an example of the control method for an image sensor according to the first embodiment of this disclosure. This figure shows an example of the configuration of a pixel array section according to the second embodiment of this disclosure. This figure shows an example of the generation of a pixel signal and a phase difference signal according to the second embodiment of this disclosure. This figure shows an example of the generation of a pixel signal and a phase difference signal according to the second embodiment of this disclosure. This figure shows an example of the configuration of a pixel array section according to the third embodiment of this disclosure. This is a cross-sectional view showing an example of the configuration of a pixel block according to the third embodiment of this disclosure. This figure shows an example of the circuit configuration of a pixel unit according to the third embodiment of this disclosure. This figure shows an example of the configuration of the analog-to-digital conversion unit according to the fourth embodiment of this disclosure. This figure shows an example of the CDS processing according to the fourth embodiment of this disclosure. This figure shows an example of the configuration of the control unit according to the fifth embodiment of this disclosure. This figure shows an example of the generation of a pixel signal and a phase difference signal according to the fifth embodiment of this disclosure. This figure shows an example of the generation of a pixel signal and a phase difference signal according to the fifth embodiment of this disclosure. This figure shows an example of the configuration of a pixel unit according to the sixth embodiment of this disclosure. This figure shows an example of the configuration of the analog-to-digital conversion unit according to the sixth embodiment of this disclosure. This figure shows an example of the generation of a pixel signal and a phase difference signal according to the sixth embodiment of this disclosure. This figure shows an example of the control method for the image sensor according to the seventh embodiment of this disclosure. This figure shows an example of the configuration of a pixel unit according to the eighth embodiment of this disclosure.This figure shows an example of imaging conditions according to the eighth embodiment of this disclosure. This figure shows another example of the configuration of a pixel unit according to the eighth embodiment of this disclosure. This figure shows another example of imaging conditions according to the eighth embodiment of this disclosure. This is a block diagram showing an example of the configuration of an electronic device.

[0008] The embodiments of this disclosure will be described in detail below with reference to the drawings. The description will be in the following order. In each of the following embodiments, the same parts will be denoted by the same reference numerals, and redundant descriptions will be omitted. 1. First Embodiment 2. Second Embodiment 3. Third Embodiment 4. Fourth Embodiment 5. Fifth Embodiment 6. Sixth Embodiment 7. Seventh Embodiment 8. Eighth Embodiment 9. Configuration of the Electronic Device

[0009] (1. First Embodiment) <Configuration of Image Sensor> Figure 1 is a diagram showing an example configuration of an image sensor according to the first embodiment of the present disclosure. The same figure is a block diagram showing an example configuration of the image sensor 1. The image sensor 1 is a semiconductor element that generates pixel signals that constitute an image of a subject. The image sensor 1 comprises a pixel array unit 10, a vertical drive unit 20, a column signal processing unit 30, and a control unit 40.

[0010] The pixel array section 10 is composed of a plurality of pixel units 200 arranged together. In this pixel array section 10, the plurality of pixel units 200 are arranged in the shape of a two-dimensional matrix. Here, each pixel unit 200 is composed of a plurality of pixels having a photoelectric conversion unit that performs photoelectric conversion of incident light, and a charge holding unit (charge holding unit 103, described later) that holds the charge generated by the photoelectric conversion. For example, a photodiode can be used for the photoelectric conversion unit. In addition, a pixel signal generation unit (pixel signal generation unit 110, described later) is provided for each pixel unit 200. This pixel signal generation unit 110 generates a pixel signal based on the charge held in the charge holding unit 103 of the pixel unit 200.

[0011] Signal lines 11 are wired to each pixel unit 200 and the pixel signal generation unit 110. The pixel units 200 and the pixel signal generation unit 110 are controlled by control signals transmitted via the signal lines 11. Signal lines 12 are also wired to the pixel signal generation unit 110. Pixel signals are output from the pixel signal generation unit 110 via these signal lines 12. The signal lines 11 are arranged in rows of a two-dimensional matrix and are wired in common to multiple pixel units 200 arranged in one row. The signal lines 12 are arranged in columns of a two-dimensional matrix and are wired in common to multiple pixel units 200 arranged in one column.

[0012] The vertical drive unit 20 generates control signals for the pixel unit 200 described above. The vertical drive unit 20 in Figure 1 generates control signals for each row of the two-dimensional matrix of the pixel array unit 10 and outputs them sequentially via the signal line 11.

[0013] The column signal processing unit 30 processes the pixel signals generated by the pixel units 200. The column signal processing unit 30 in Figure 1 simultaneously processes pixel signals from multiple pixel units 200 arranged in one row of the pixel array unit 10, transmitted via the signal line 12. This processing can include, for example, analog-to-digital conversion, which converts the analog pixel signals generated by the pixel units 200 into digital pixel signals, and correlated double sampling (CDS), which removes offset errors in the pixel signals. The processed pixel signals are then output to external circuits or other devices outside the image sensor 1.

[0014] The control unit 40 controls the vertical drive unit 20 and the column signal processing unit 30. In Figure 1, the control unit 40 controls the vertical drive unit 20 and the column signal processing unit 30 by outputting control signals via signal lines 41 and 42, respectively.

[0015] <Configuration of Pixel Array Section> Figure 2 is a diagram showing an example configuration of the pixel array section according to the first embodiment of the present disclosure. The diagram shows an example configuration of the pixel array section 10. As described above, the pixel array section 10 has a plurality of pixel units 200 arranged therein. Pixel units 200a-200d are shown in the diagram. Pixel unit 200a will be used as an example for explanation. Pixel unit 200a includes a pixel block 120. The pixel unit 200a in the diagram shows an example where a plurality of pixel blocks 120 (pixel blocks 120a-120d) are included. In the following explanation, if there is no need to distinguish between pixel units 200a-200d, they will simply be referred to as pixel unit 200. Similarly, if there is no need to distinguish between pixel blocks 120a-120d, they will simply be referred to as pixel block 120.

[0016] Here, the pixel block 120 is composed of a plurality of pixels 100 and an on-chip lens 170 that is commonly arranged for the plurality of pixels 100. To explain using pixel block 120a as an example, the pixel block 120a comprises pixels 100a and 100b. These pixels 100a and 100b each have a photoelectric conversion unit (a photoelectric conversion unit 101 described later), are configured in a rectangular shape, and divide the pixel block 120a into two regions. In the following explanation, when it is not necessary to distinguish between pixels 100a and 100b, they will simply be referred to as pixel 100.

[0017] In the pixel block 120a, when generating a pixel signal corresponding to the subject, the pixel signal is generated based on the sum of the charges generated by pixels 100a and 100b, respectively. Furthermore, the pixel block 120a can generate a phase difference signal for detecting the image plane phase difference by dividing the subject into pupils. Pixels 100a and 100b can be divided into pupils in the left-right direction as shown in Figure 2. That is, the pixel signal based on the charge generated by pixel 100a and the pixel signal based on the charge generated by pixel 100b form a pair of phase difference signals.

[0018] Furthermore, pixel signals and phase difference signals can also be generated using the pixel unit 200 as the unit. Specifically, a pixel signal is generated based on the sum of the charges generated by all the pixels 100 arranged in the pixel unit 200. In addition, the pixel unit 200 generates a pixel signal based on the sum of the charges generated by all the pixels 100a and a pixel signal based on the sum of the charges generated by all the pixels 100b as a pair of phase difference signals. In the image sensor 1 of this disclosure, the number of pixels 100a arranged in the pixel unit 200 that contribute to the generation of phase difference signals is adjusted.

[0019] Furthermore, a color filter (color filter 160, described later) can be placed in each pixel 100. This color filter 160 is an optical filter that transmits incident light of a predetermined wavelength. Three types of color filters can be used for this color filter 160: one that transmits red light, one that transmits green light, and one that transmits blue light. In addition, the same type of color filter 160 can be placed in each pixel 100 in the pixel unit 200. That is, a different color filter 160 can be placed in each pixel unit 200. In Figure 2, the white rectangles represent the arrangement of color filters 160 that transmit green light. The rectangles with hatched diagonal lines sloping downwards to the right represent the arrangement of color filters 160 that transmit blue light. The rectangles with hatched diagonal lines sloping upwards to the right represent the arrangement of color filters 160 that transmit red light. In this way, the pixel unit 200 can be arranged in a Bayer array.

[0020] <Pixel Block Configuration> Figure 3 is a cross-sectional view showing an example of the configuration of a pixel block according to the first embodiment of the present disclosure. The same figure is a cross-sectional view showing an example of the configuration of a pixel block 120. As described above, pixels 100a and pixels 100b are arranged in the pixel block 120. Pixel 100a will be described as an example. Pixel 100a comprises a semiconductor substrate 130, an insulating film 140, a wiring region 150, a separation portion 145, a protective film 146, and a color filter 160. In addition, an on-chip lens 170 is commonly arranged in pixels 100a and 100b.

[0021] The semiconductor substrate 130 is a semiconductor substrate on which the diffusion layer of the semiconductor element of the pixel 100 is arranged. The semiconductor substrate 130 can be made of, for example, silicon (Si). The semiconductor elements are arranged in well regions formed on the semiconductor substrate 130. For convenience, the semiconductor substrate 130 in Figure 3 is assumed to be composed of p-type well regions. Semiconductor elements can be formed by arranging n-type or p-type semiconductor regions in these p-type well regions. In the semiconductor substrate 130 in Figure 3, a photoelectric conversion unit 101 is shown as an example. This photoelectric conversion unit 101 is composed of an n-type semiconductor region 131. Specifically, the photodiode consisting of a pn junction at the interface between the n-type semiconductor region 131 and the surrounding p-type well region corresponds to the photoelectric conversion unit 101.

[0022] The insulating film 140 insulates the surface side of the semiconductor substrate 130. This insulating film 140 contains, for example, silicon oxide (SiO ２ A film of the following type can be applied.

[0023] The wiring region 150 is a region located on the surface side of the semiconductor substrate 130 where the wiring of the element is formed. This wiring region 150 comprises wiring 152, via plugs 153, and an insulating layer 151. The wiring 152 is a conductor that transmits signals to the element on the semiconductor substrate 130. This wiring 152 can be made of a metal such as copper (Cu) or tungsten (W). The via plugs 153 connect wiring 152 located on different layers. This via plug 153 can be made of a columnar metal, for example. The insulating layer 151 insulates the wiring 152, etc. This insulating layer 151 can be made of a metal such as SiO ２ It can be composed of the following.

[0024] The separation portion 145 is positioned at the boundary of the pixels 100 on the semiconductor substrate 130 to electrically and optically separate the pixels 100. This separation portion 145 can be made of an insulator embedded in the semiconductor substrate 130. For example, the separation portion 145 is made of SiO in a groove that penetrates the semiconductor substrate 130 formed at the boundary of the pixels 100. ２ It can be formed by arranging insulating materials such as the above.

[0025] The protective film 146 is a film that protects the back side of the semiconductor substrate 130. This protective film 146 is made of SiO ２ It can be made of insulating materials such as the above. The protective film 146 in Figure 3 can be formed at the same time as the separation portion 145.

[0026] The color filter 160 is an optical filter that transmits incident light of a predetermined wavelength. For example, a color filter that transmits red light, green light, and blue light can be used for this color filter 160. In this case, one color filter 160 corresponding to red light, green light, or blue light is placed in each pixel 100. This pixel 100 generates a pixel signal of incident light of the wavelength corresponding to the color filter 160. As described above, multiple pixels 100 placed in the pixel unit 200 are each placed with the same type of color filter 160. Also, the color filter 160 in Figure 3 is placed on the back side of the semiconductor substrate 130.

[0027] Furthermore, a light-shielding section 169 is positioned adjacent to the color filter 160 at the boundary of the pixel block 120. This light-shielding section 169 blocks incident light. By positioning the light-shielding section 169, it is possible to prevent light from entering from adjacent pixel blocks 120, thereby preventing the occurrence of color mixing.

[0028] The on-chip lens 170 is a lens commonly positioned for multiple pixels 100 that constitute the pixel block 120, as described above. The on-chip lens 170 in Figure 3 has a hemispherical cross-section and focuses incident light onto the photoelectric conversion unit 101. The on-chip lens 170 can be made of an organic material such as acrylic resin or an inorganic material such as silicon nitride (SiN).

[0029] [Circuit Configuration of Pixel Unit] Figure 4 is a diagram showing an example of the circuit configuration of a pixel unit according to the first embodiment of the present disclosure. The figure is a circuit diagram showing an example configuration of the pixel unit 200. The figure further includes the analog-to-digital conversion unit 32, the reference signal generation unit 35, and the arithmetic circuit 37, which are included in the control unit 40 and column signal processing unit 30 described in Figure 1. In the figure, "analog-to-digital conversion" is written as "ADC".

[0030] As described above, the pixel unit 200 comprises pixel blocks 120a-120d. In Figure 4, the description of pixel blocks 120b-120d is omitted. Pixel block 120a comprises pixels 100a and 100b. Pixels 100a and 100b each comprise a photoelectric conversion unit 101 and a charge transfer unit 102, respectively. The pixel unit 200 also comprises a charge holding unit 103, a reset unit 104, an auxiliary charge holding unit 106, a coupling unit 105, an amplification transistor 111, and a selection transistor 112. The circuits of the amplification transistor 111 and the selection transistor 112 constitute the pixel signal generation unit 110.

[0031] The charge transfer unit 102, reset unit 104, coupling unit 105, amplification transistor 111, and selection transistor 112 can be made up of n-channel MOS transistors. The auxiliary charge holding unit 106 can also be made up of a semiconductor region similar to that of the charge holding unit 103.

[0032] As mentioned above, signal lines 11 and 12 are wired to the pixel unit 200. In Figure 4, signal line 11 includes signal lines TG1, TG2, FDG, RST, and SEL. Signal line 12 includes signal line VSL. In addition, a power line Vdd is wired to the pixel unit 200. This power line Vdd is the wiring that supplies power to the pixel unit 200.

[0033] In pixel 100a, the anode of the photoelectric conversion unit 101 is connected to a reference potential line (e.g., GND), and the cathode is connected to the source of the charge transfer unit 102. The drain of the charge transfer unit 102 is commonly connected to one end of the charge holding unit 103. This is also the case in pixel 100b. Furthermore, the gate of the amplification transistor 111, the source of the reset unit 104, and the drain of the coupling unit 105 are connected to one end of the charge holding unit 103. The other end of the charge holding unit 103 is connected to the reference potential line. The drain of the reset unit 104 and the drain of the amplification transistor 111 are connected to the power line Vdd. The source of the amplification transistor 111 is connected to the drain of the selection transistor 112, and the source of the selection transistor 112 is connected to the signal line VSL. One end of the auxiliary charge holding unit 106 is connected to the reference potential line, and the other end is connected to the source of the coupling unit 105.

[0034] The gate of the charge transfer unit 102 of pixel 100a is connected to signal line TG1, and the gate of the charge transfer unit 102 of pixel 100b is connected to signal line TG2. The gate of the reset unit 104 is connected to signal line RST. The gate of the coupling unit 105 is connected to signal line FDG.

[0035] The photoelectric conversion unit 101 performs photoelectric conversion of incident light. The charge holding unit 103 holds the charge generated by the photoelectric conversion. This charge holding unit 103 can be made up of a semiconductor region with a relatively high impurity concentration formed on the semiconductor substrate on which the pixels 100 are formed. Such a semiconductor region is called a floating diffusion region (FD). The charge transfer unit 102 is arranged for each pixel 100 and transfers the charge generated and held by the photoelectric conversion unit 101 to the charge holding unit 103.

[0036] The reset unit 104 resets the charge holding unit 103. This reset can be performed by discharging the charge from the charge holding unit 103 by creating conductivity between the charge holding unit 103 and the power line Vdd. The control signal of the reset unit 104 is transmitted via the signal line RST.

[0037] The amplification transistor 111 amplifies the voltage of the charge holding unit 103. The gate of the amplification transistor 111 is connected to the charge holding unit 103. Therefore, a pixel signal with a voltage corresponding to the charge held in the charge holding unit 103 is generated at the source of the amplification transistor 111. Furthermore, by conducting the selection transistor 112, this pixel signal can be output to the signal line VSL. The control signal of the selection transistor 112 is transmitted via the signal line SEL.

[0038] The auxiliary charge holding unit 106 is a capacitor coupled to the charge holding unit 103. By coupling this auxiliary charge holding unit 106 to the charge holding unit 103, the charge holding capacity of the pixel unit 200 can be adjusted. By coupling the auxiliary charge holding unit 106 to the charge holding unit 103, the charge holding capacity of the pixel unit 200 increases. This makes it possible to reduce the sensitivity of the pixel unit 200. If the auxiliary charge holding unit 106 is not coupled to the charge holding unit 103, the sensitivity of the pixel unit 200 becomes relatively high, but charge saturation is more likely to occur. The operating mode in which the auxiliary charge holding unit 106 is not coupled to the charge holding unit 103 and the operating mode in which the auxiliary charge holding unit 106 is coupled to the charge holding unit 103 are referred to as the high-sensitivity mode and the low-sensitivity mode, respectively.

[0039] The coupling portion 105 connects the auxiliary charge holding portion 106 to the charge holding portion 103. This coupling portion 105 is made up of a MOS transistor and can connect the auxiliary charge holding portion 106 to the charge holding portion 103 by making the connection between the charge holding portion 103 and the auxiliary charge holding portion 106 conductive.

[0040] As described above, the charge transfer unit 102, the reset unit 104, the selection transistor 112, and the coupling unit 105 can be formed of n-channel MOS transistors. In this n-channel MOS transistor, applying a voltage exceeding the threshold of the gate-source voltage Vgs to the gate enables conduction between the drain and the source. Hereinafter, the voltage exceeding the threshold of the gate-source voltage Vgs is referred to as an on-voltage. On the other hand, the voltage that brings the MOS transistor into a non-conductive state is referred to as an off-voltage. A control signal including this on-voltage and off-voltage is transmitted via a signal line TG1 or the like.

[0041] Furthermore, when resetting the charge holding unit 103 by the reset unit 104, the photoelectric conversion unit 101 can also be reset by bringing the charge transfer unit 102 into conduction. Also, by bringing the coupling unit 105 into conduction, the auxiliary charge holding unit 106 can be reset.

[0042] Generation of pixel signals in the pixel unit 200 can be performed as follows. First, the charge holding unit 103 is reset by the reset unit 104. At this time, the charge transfer units 102 and the coupling units 105 of all pixels 100 are brought into conduction, so that all photoelectric conversion units 101 and auxiliary charge holding units 106 are also reset. Next, after a predetermined exposure period has elapsed, the charge holding unit 103 is reset. At this time, the pixel signal generation unit 110 generates a reference signal, which is a pixel signal at a reset level. This reference signal is a signal for the aforementioned CDS, and is referred to as a high-sensitivity mode reference signal. Next, the coupling unit 105 is brought into conduction to reset the auxiliary charge holding unit 106. At this time, the pixel signal generation unit 110 generates a low-sensitivity mode reference signal which is a reference signal in the low-sensitivity mode. Thereafter, the coupling unit 105 returns to the non-conductive state.

[0043] Next, all the charge transfer units 102 are brought into conduction to transfer the charges generated by all the photoelectric conversion units 101 to the charge holding unit 103. Thereafter, the pixel signal generation unit 110 generates a pixel signal corresponding to the charge in the charge holding unit 103. In this case, since the auxiliary charge holding unit 106 is not coupled to the charge holding unit 103, the operation is in the high-sensitivity mode. The generated pixel signal becomes a high-sensitivity mode pixel signal.

[0044] Next, the coupling portion 105 is rendered conductive to couple the auxiliary charge holding portion 106 to the charge holding portion 103. Accordingly, a part of the electric charge held in the charge holding portion 103 moves to the auxiliary charge holding portion 106, and the potential of the charge holding portion 103 decreases. Thereafter, the pixel signal generation section 110 generates a pixel signal corresponding to the charge in the charge holding portion 103. In this case, since the auxiliary charge holding portion 106 is coupled to the charge holding portion 103, the operation enters the low-sensitivity mode. The generated pixel signal serves as a low-sensitivity mode pixel signal.

[0045] The phase difference signal can be generated based on charges of the plurality of pixels 100 on one side in pupil division among the plurality of pixels 100 in the pixel unit 200. Here, pixels 100a are assumed as the plurality of pixels 100 on one side in pupil division. The phase difference signal can be generated as follows. After the above-described exposure period has elapsed, the charge holding portion 103 and the auxiliary charge holding portion 106 are reset. Next, the charge transfer portions 102 of all the pixels 100a are rendered conductive to transfer the charges of all the pixels 100a to the charge holding portions 103. Thereafter, the pixel signal generation section 110 generates a pixel signal. This pixel signal serves as a high-sensitivity mode phase difference signal.

[0046] Note that, in order to detect an image plane phase difference, a phase difference signal based on the plurality of pixels 100 (pixels 100b) on the other side in pupil division among the plurality of pixels 100 is required. This phase difference signal is referred to as a second high-sensitivity mode phase difference signal. The second high-sensitivity mode phase difference signal can be generated by subtracting the high-sensitivity mode phase difference signal from the high-sensitivity mode pixel signal.

[0047] A phase difference signal in low-sensitivity mode can also be generated. This can be done as follows: After the above-mentioned exposure period has elapsed, the charge holding unit 103 and the auxiliary charge holding unit 106 are reset. Next, the charge transfer unit 102 of a selected pixel 100a from all the pixels 100a is made conductive, and the charge of that pixel 100a is transferred to the charge holding unit 103. After that, the pixel signal generation unit 110 generates a pixel signal. This pixel signal is a phase difference signal with gain adjusted for the high-sensitivity mode phase difference signal described above. This phase difference signal is used as the low-sensitivity mode phase difference signal. A second low-sensitivity mode phase difference signal in low-sensitivity mode can be generated by subtracting the low-sensitivity mode phase difference signal from the low-sensitivity mode pixel signal.

[0048] The control unit 40 selects the pixels 100a in the pixel unit 200 when generating the low-sensitivity mode phase difference signal described above. The control unit 40 adjusts the number of pixels 100a selected in the pixel unit 200 so that the signal level of the low-sensitivity mode phase difference signal approximates the signal level of the low-sensitivity mode pixel signal.

[0049] The analog-to-digital conversion unit 32 performs analog-to-digital conversion of the pixel signals generated by the pixel unit 200 to generate digital pixel signals. The analog-to-digital conversion unit 32 in Figure 4 performs analog-to-digital conversion of high-sensitivity mode pixel signals, low-sensitivity mode pixel signals, high-sensitivity mode phase difference signals, low-sensitivity mode phase difference signals, high-sensitivity mode reference signals, and low-sensitivity mode reference signals. The analog-to-digital conversion unit 32 performs single-slope type analog-to-digital conversion.

[0050] The reference signal generation unit 35 generates a reference signal necessary for analog-to-digital conversion in the analog-to-digital conversion unit 32. This reference signal is a signal whose value changes in the form of a ramp function. By adjusting the slope of the ramp function of this reference signal, the gain of analog-to-digital conversion in the analog-to-digital conversion unit 32 can be adjusted. The reference signal generation unit 35 generates the reference signal based on the control of the control unit 40. The control unit 40 adjusts the gain of analog-to-digital conversion in the analog-to-digital conversion unit 32 when generating the low-sensitivity mode phase difference signal described above.

[0051] The calculation circuit 37 performs calculations to generate the second high-sensitivity mode phase difference signal and the second low-sensitivity mode phase difference signal described above.

[0052] The configuration of the column signal processing unit 30, including the analog-to-digital conversion unit 32, will be explained using Figure 5 below.

[0053] <Configuration of Column Signal Processing Unit> Figure 5 is a diagram showing an example configuration of the column signal processing unit according to the first embodiment of the present disclosure. The diagram shows an example configuration of the column signal processing unit 30. The column signal processing unit 30 comprises a constant current circuit 31, an analog-to-digital conversion unit 32, a holding unit 33, a horizontal transfer unit 34, and a reference signal generation unit 35. Of these, the constant current circuit 31, the analog-to-digital conversion unit 32, and the holding unit 33 are arranged for each of the multiple signal lines 12. Note that the calculation circuit 37 described in Figure 4 is omitted in this figure.

[0054] The constant current circuit 31 is a circuit that constitutes the load for the amplification transistor 111, as described in Figure 4. The sink terminal of the constant current circuit 31 is connected to the signal line 12, and the source terminal is connected to the reference potential line. In this way, the constant current circuit 31, together with the amplification transistor 111, constitutes a source follower circuit. The pixel signal is transmitted as a voltage signal corresponding to the incident light to the signal line 12 to which the sink terminal of the constant current circuit 31 is connected.

[0055] The reference signal generation unit 35 generates a reference signal and outputs it to the analog-to-digital conversion unit 32. This reference signal is a signal whose value changes in a ramp-like manner.

[0056] The analog-to-digital conversion unit 32 performs analog-to-digital conversion of the pixel signal. This analog-to-digital conversion unit 32 converts the analog pixel signal generated by the pixel unit 200 into a digital pixel signal. The analog-to-digital conversion unit 32 in Figure 5 converts the analog pixel signal into a digital pixel signal based on the reference signal output from the reference signal generation unit 35. Specifically, the analog-to-digital conversion unit 32 compares the analog pixel signal with the reference signal and detects the period until the analog pixel signal and the reference signal match. Since the reference signal is a voltage signal corresponding to the elapsed time, the period from the start of the reference signal output until it matches the analog pixel signal is the period corresponding to the voltage of the analog pixel signal. By outputting a digital signal corresponding to this period, the analog pixel signal can be converted into a digital pixel signal.

[0057] The holding unit 33 holds the pixel signal that has been converted into a digital signal by the analog-to-digital conversion unit 32.

[0058] The horizontal transfer unit 34 is responsible for transferring pixel signals. The horizontal transfer unit 34 in Figure 5 is connected to the outputs of all the holding units 33, which are arranged for each signal line 12. The horizontal transfer unit 34 sequentially transfers and outputs the pixel signals output from the holding units 33. For example, the horizontal transfer unit 34 can transfer and output the pixel signals starting from the rightmost holding unit 33 among the multiple holding units 33 arranged in the column signal processing unit 30 in Figure 5.

[0059] <Configuration of Analog-to-Digital Conversion Unit> Figure 6 is a diagram showing an example configuration of the analog-to-digital conversion unit according to the first embodiment of the present disclosure. The same figure is a block diagram showing an example configuration of the analog-to-digital conversion unit 32. The analog-to-digital conversion unit 32 includes a comparator 301, a counter 302, and a CDS unit 303.

[0060] The comparator 301 compares the pixel signal and the reference signal. The pixel signal is input to the non-inverting input of the comparator 301, and the reference signal is input to the inverting input. The comparator 301 outputs the comparison result of the pixel signal and the reference signal to the counter 302. Specifically, the comparator 301 outputs a signal to the counter 302 that transitions when the reference signal exceeds the pixel signal.

[0061] The counter 302 performs a counting operation during the period from the start of analog-to-digital conversion in the analog-to-digital conversion unit 32 to the input of the comparison result by the comparator 301, and outputs the count value to the CDS unit 303 as the digital value after analog-to-digital conversion.

[0062] The CDS unit 303 performs CDS processing. Here, CDS processing is a process that removes the offset (noise) by taking the difference between the pixel signal generated by exposure and the pixel signal at the time of reset. Charge that is not discharged during reset remains in the charge holding unit 103 etc. as explained in Figure 4. The signal component based on this residual charge becomes an offset component of the pixel signal and causes noise. Therefore, the pixel signal at the time of reset is held, and the pixel signal at the time of reset (reset level pixel signal) is subtracted from the pixel signal based on the charge generated and transferred during exposure (signal level pixel signal). This makes it possible to remove the offset component.

[0063] The CDS unit 303 performs a process of subtracting the high-sensitivity mode reference signal from the high-sensitivity mode pixel signal and the high-sensitivity mode phase difference signal. The CDS unit 303 also performs a process of subtracting the low-sensitivity mode reference signal from the low-sensitivity mode pixel signal and the low-sensitivity mode phase difference signal. The high-sensitivity mode pixel signal and the like after CDS processing are output to the holding unit 33 as described in Figure 5.

[0064] As mentioned above, the pixel unit 200 can generate pixel signals and phase difference signals. Furthermore, the pixel unit 200 can generate pixel signals and phase difference signals in a single frame period. This will be explained below. After exposure, the pixel unit 200 sequentially generates a high-sensitivity mode reference signal (P1), a low-sensitivity mode reference signal (P2), a phase difference signal (D1), a high-sensitivity mode pixel signal (D2), and a low-sensitivity mode pixel signal (D3). During the period D1, either the high-sensitivity mode phase difference signal or the low-sensitivity mode phase difference signal is selected. At this time, the selection of pixels 100 and the adjustment of the analog-to-digital conversion gain are performed. This will be explained using Figures 7A and 7B.

[0065] <Generation of Pixel Signals and Phase Difference Signals> Figures 7A and 7B show an example of the generation of pixel signals and phase difference signals according to the first embodiment of the present disclosure. Figures 7A and 7B show the conditions for generating pixel signals and phase difference signals. In Figures 7A and 7B, the generation of pixel signals and phase difference signals is performed in the order of P1, P2, D1, D2, and D3. "Signal level" indicates whether it is the reset level or the signal level. "Sensitivity" indicates whether it is the high-sensitivity mode or the low-sensitivity mode. "AD conversion gain" indicates the gain of analog-to-digital conversion. "Readout pixel" indicates a pixel 100 used for generating pixel signals in the pixel unit 200. A rectangle labeled "L" represents a pixel 100a, and a rectangle labeled "R" represents a pixel 100b. Of these, the dot-hatched pixel 100 is used for generating pixel signals. In Figures 7A and 7B, the sensitivity ratio between the low-sensitivity mode and the high-sensitivity mode is assumed to be 1:4. Here, sensitivity represents the conversion efficiency at the pixel. The sensitivity of the low-sensitivity mode and the high-sensitivity mode corresponds to the ratio of the total capacity of the charge holding unit 103 and the auxiliary charge holding unit 106 to the capacity of the charge holding unit 103. "Signal name" represents the name of the generated signal.

[0066] Figure 7A shows the conditions for generating a high-sensitivity mode phase difference signal. The gain of the analog-to-digital conversion is 0 dB for P1, 12 dB for P2, 12 dB for D1, 12 dB for D2, and 0 dB for D3. That is, it is 0 dB in low-sensitivity mode and 12 dB in high-sensitivity mode. Also, in D2 and D3, all pixels 100 are used for pixel signal generation. In contrast, in D1, only pixel 100a is used for pixel signal generation.

[0067] Figure 7B shows the conditions for generating a low-sensitivity mode phase difference signal. The parts that differ from Figure 7A are enclosed in a thick line. At D1, only one pixel, 100a, is read out. In other words, the number of readout pixels is reduced to 1 / 4. Furthermore, the gain of the analog-to-digital conversion at D1 is adjusted to 0 dB.

[0068] The overall gain in D3 is 0 dB. In contrast, the overall gain in D2 is 24 dB because the sensitivity ratio is 1:4, resulting in a pixel sensitivity of 4 times (12 dB), and the analog-to-digital conversion gain is 12 dB. In contrast, the overall gain of D1 in high-sensitivity mode (Figure 7A) is 18 dB because the number of pixels is halved (-6 dB) compared to D2. On the other hand, in low-sensitivity mode (Figure 7B), the number of pixels is 1 / 4 (-12 dB), and the AD conversion gain is 0 dB, so the overall gain of D2 is 24 dB - 12 dB (pixel decimation) - 12 dB (AD conversion gain) = 0 dB. That is, it is equal to the overall gain in D3. For this reason, the phase difference signal generated in high-sensitivity mode can be used as the phase difference signal in low-sensitivity mode.

[0069] Figure 8 is a diagram showing an example of the generation of a pixel signal and a phase difference signal according to the first embodiment of this disclosure. The diagram is a timing diagram showing an example of the generation of a pixel signal and a phase difference signal in the pixel unit 200. The diagram also shows an example of generating the high-sensitivity mode phase difference signal shown in Figure 7A.

[0070] In Figure 8, "SEL" represents the signal on signal line SEL. "RST" represents the signal on signal line RST. "TG1" represents the signal on signal line TG1. "TG2" represents the signal on signal line TG2. "TG3" represents the signal on signal line TG3 (not shown in Figure 4). "TG4" represents the signal on signal line TG4 (not shown in Figure 4). "TG5" represents the signal on signal line TG5 (not shown in Figure 4). "TG6" represents the signal on signal line TG6 (not shown in Figure 4). "TG7" represents the signal on signal line TG7 (not shown in Figure 4). "TG8" represents the signal on signal line TG8 (not shown in Figure 4). "FDG" represents the signal on signal line FDG. "VSL" represents the pixel signal output to signal line VSL. "REF" represents the waveform of the reference signal output from the reference signal generation unit 35, as explained in Figure 4.

[0071] The signals "SEL," "RST," "TG1," etc., and "FDG" have a binarized waveform where the high-level portion represents the on-voltage. For example, a voltage of 3V can be applied to this on-voltage. The low-level portion represents the off-voltage. The dashed line in Figure 8 represents the off-voltage level. For example, a voltage of 0V or a negative voltage (e.g., -1.2V) can be applied to this off-voltage.

[0072] In the initial state, an off voltage is input to signal line SEL and signal lines TG1 to TG8. On voltage is input to signal line RST and signal line FDG. As the reset unit 104 and coupling unit 105 become conductive, the charge holding unit 103 and auxiliary charge holding unit 106 are reset.

[0073] At T1, an ON voltage is input from signal lines TG1-TG8. As a result, the charge transfer unit 102 becomes conductive in addition to the reset unit 104, and the photoelectric conversion unit 101 is reset in addition to the charge holding unit 103 and the auxiliary charge holding unit 106.

[0074] At T2, the ON voltage input to signal lines TG1-TG8 is stopped. This initiates the exposure period. Charge generated by photoelectric conversion is accumulated in the photoelectric conversion unit 101.

[0075] At T3, an ON voltage is input from the signal line SEL. This selects the pixel unit 200. At the same time, the input of an ON voltage to the signal line RST is stopped. This stops the reset of the charge holding unit 103 and the auxiliary charge holding unit 106.

[0076] At T4, the pixel signal generation unit 110 of the pixel unit 200 starts outputting the pixel signal during reset. In Figure 8, "A" on the signal line VSL represents the reset level pixel signal. Since an ON voltage is input to the signal line FDG and the coupling unit 105 is in a conductive state, this "A" becomes the low-sensitivity mode reference signal.

[0077] During the period from T5 to T6, the reference signal generation unit 35 outputs a ramp-like reference signal, and the analog-to-digital conversion unit 32 performs analog-to-digital conversion. The conversion result is a digital low-sensitivity mode reference signal.

[0078] At T7, the input of the ON voltage to the signal line FDG is stopped. As a result, the coupling section 105 becomes non-conductive, and the system switches to high-sensitivity mode. Also, during the period from T7 to T8, the pixel signal generation unit 110 of the pixel unit 200 starts outputting the pixel signal at the time of reset. In Figure 8, the "B" in the signal line VSL represents the high-sensitivity mode reference signal.

[0079] During the period from T8 to T9, the reference signal generation unit 35 outputs a reference signal, and the analog-to-digital conversion unit 32 performs analog-to-digital conversion. Note that because the AD conversion gain is different, the reference signal has a different slope than the low-sensitivity mode T5 to T6. The conversion result becomes a digital high-sensitivity mode reference signal.

[0080] At T10, ON voltages are input from signal lines TG1, TG3, TG5, and TG7, causing the charge transfer units 102 of all pixels 100a to become conductive. As a result, the charge accumulated in the photoelectric conversion units 101 of all pixels 100a is transferred to the charge holding units 103.

[0081] At T11, the input of the ON voltage to the signal line TG1, etc., is stopped, and the charge transfer section 102 of all pixels 100a becomes non-conductive. During the period from T11 to T12, the pixel signal generation unit 110 generates the pixel signal "C" and outputs it to the signal line VSL. This pixel signal corresponds to the high-sensitivity mode phase difference signal.

[0082] During the period from T12 to T13, the reference signal generation unit 35 outputs a reference signal, and the analog-to-digital conversion unit 32 performs analog-to-digital conversion. The conversion result is a high-sensitivity mode phase difference signal.

[0083] At T14, ON voltages are input from signal lines TG2, TG4, TG6, and TG8, causing the charge transfer units 102 of all pixels 100b to become conductive. As a result, the charge accumulated in the photoelectric conversion units 101 of all pixels 100b is transferred to the charge holding units 103.

[0084] At T15, the input of the ON voltage to the signal line TG2, etc., is stopped, and the charge transfer section 102 of all pixels 100b becomes non-conductive. During the period from T15 to T16, the pixel signal generation unit 110 generates the pixel signal "D" and outputs it to the signal line VSL. This pixel signal corresponds to the high-sensitivity mode pixel signal.

[0085] During the period from T16 to T17, the reference signal generation unit 35 outputs a reference signal, and the analog-to-digital conversion unit 32 performs analog-to-digital conversion. The conversion result is a digital high-sensitivity mode pixel signal.

[0086] At T18, an ON voltage is input to the signal line FDG. This causes the coupling unit 105 to become conductive, and the system switches to low-sensitivity mode. Also, during the period from T18 to T19, the pixel signal generation unit 110 generates a pixel signal "E" and outputs it to the signal line VSL. This pixel signal corresponds to the low-sensitivity mode pixel signal.

[0087] During the period from T20 to T21, the reference signal generation unit 35 outputs a reference signal, and the analog-to-digital conversion unit 32 performs analog-to-digital conversion. The conversion result is a digital low-sensitivity mode pixel signal.

[0088] At T21, the application of the ON voltage to the signal line SEL is stopped, and the pixel unit 200 becomes unselected. At the same time, an ON voltage is input to the signal line RST. This returns the system to its initial state, and the reset of the charge holding unit 103 and the auxiliary charge holding unit 106 is resumed.

[0089] By following the above procedure, the pixel unit 200 can generate a pixel signal and a high-sensitivity mode phase difference.

[0090] Figure 9 is a diagram showing an example of the generation of a pixel signal and a phase difference signal according to the first embodiment of this disclosure. Similar to Figure 8, this figure is a timing diagram showing an example of the generation of a pixel signal and a phase difference signal in the pixel unit 200. This figure also shows an example of generating the low-sensitivity mode phase difference signal shown in Figure 7B. The periods T41 to T49 in this figure are the same as T1 to T9 in Figure 8, so their explanation is omitted.

[0091] At T50, an ON voltage is input from the signal line TG1, causing the charge transfer unit 102 of the pixel 100a of the pixel block 120a to become conductive. As a result, the charge accumulated in the photoelectric conversion unit 101 of the pixel 100a of the pixel block 120a is transferred to the charge holding unit 103.

[0092] At T51, the ON voltage input to signal line TG1 is stopped, and the charge transfer unit 102 of pixel 100a of pixel block 120a becomes non-conductive. During the period from T50 to T51, the pixel signal generation unit 110 generates the pixel signal "F" and outputs it to signal line VSL. This pixel signal corresponds to the low-sensitivity mode phase difference signal.

[0093] During the period from T52 to T53, the reference signal generation unit 35 outputs a reference signal, and the analog-to-digital conversion unit 32 performs analog-to-digital conversion. Note that, unlike the reference signal at T12 to T13 in Figure 8, the reference signal has the same slope as in the low-sensitivity mode. The conversion result is a digital low-sensitivity mode phase difference signal.

[0094] At T54, an ON voltage is input from signal lines TG2-TG8, causing the charge transfer units 102 of pixels 100a other than pixel block 120a and all pixels 100b to become conductive. As a result, the charge accumulated in the photoelectric conversion units 101 of pixels 100a other than pixel block 120a and all pixels 100b is transferred to the charge holding unit 103.

[0095] At T55, the ON voltage input to signal lines TG2-TG8 is stopped, and the charge transfer units 102 of pixels 100a other than pixel block 120a and all pixels 100b become non-conductive. The period from T56 to T61 is the same as T16 to T21 in Figure 8, so the explanation is omitted.

[0096] Note that the generation of pixel signals and phase difference signals in the pixel unit 200 is not limited to the example in Figure 9. For example, a step of generating a high-sensitivity mode phase difference signal can be added after "D1" in Figure 9. Specifically, between T53 and T54, an on-voltage can be applied to TG3, TG5, and TG7 to transfer the charge accumulated in the photoelectric conversion unit 101 of each pixel 100a of pixel block 120b, pixel block 120c, and pixel block 120d to the charge holding unit 103, and a step can be added in which the pixel signal generation unit 110 generates a pixel signal. In this case, a low-sensitivity mode phase difference signal and a high-sensitivity mode phase difference signal can be generated continuously within the same frame period.

[0097] <Control Method for Image Sensor> Figure 10 shows an example of a control method for an image sensor according to the first embodiment of this disclosure. The figure shows an example of a control method for generating pixel signals in the image sensor 1. The image sensor 1 performs rolling shutter imaging. That is, exposure and pixel signal generation are performed sequentially for each row of the pixel array 10, and these timings are shifted for each row. The figure shows exposure and pixel signal generation for each frame period. The area with dot hatching in the figure represents the exposure period 401. The dashed line in the figure represents the exposure start (shutter) timing, and the dotted line represents the pixel signal generation timing. The "synchronization signal" in the figure is a signal that represents the division of the frame period. The "I2C" in the figure is a signal line that transmits commands from the host system. Based on the commands from the host system, the pixel decimation and AD conversion gain shown in Figures 7A and 7B are set.

[0098] In the image sensor 1 of this disclosure, since pixel downsampling is performed, the command needs to be transmitted to the image sensor 1 one frame period in advance.

[0099] Thus, the image sensor 1 of the first embodiment of this disclosure adjusts the number of pixels 100 used to generate the phase difference signal in high-sensitivity mode and adjusts the conversion gain in the analog-to-digital conversion unit 32 when generating the phase difference signal used in low-sensitivity mode. This adjusts the level of the phase difference signal generated in high-sensitivity mode and makes it usable as a phase difference signal in low-sensitivity mode. As a result, it becomes possible to detect the image plane phase difference in low-sensitivity mode, improving convenience.

[0100] (2. Second Embodiment) The image sensor 1 of the first embodiment described above used a pixel unit 200 having a pixel block 120 having two pixels 100 (pixel 100a and pixel 100b). In contrast, the image sensor 1 of the second embodiment of this disclosure differs from the first embodiment described above in that it uses a pixel unit 200 having a pixel block 120 having four pixels 100.

[0101] <Configuration of Pixel Array Section> Figure 11 is a diagram showing an example configuration of a pixel array section according to the second embodiment of the present disclosure. This diagram, like Figure 2, shows an example configuration of the pixel array section 10. The pixel unit 200 of the pixel array section 10 in this figure has a pixel block 120 having four pixels 100 (pixels 100a-100d) arranged in two rows and two columns. The pixel block 120 in this figure can be divided into pupils in the left-right and up-down directions in Figure 11. In the pixel unit 200 in this figure, one pixel block 120 is arranged, so the number of pixels on one side in pupil division is 2.

[0102] <Generation of Pixel Signals and Phase Difference Signals> Figures 12A and 12B show an example of the generation of pixel signals and phase difference signals according to the second embodiment of the present disclosure. Figures 12A and 12B show the conditions for generating pixel signals and phase difference signals, similar to Figures 7A and 7B. In Figures 12A and 12B, the readout pixels and AD conversion gain are different from those in Figures 7A and 7B. The ratio of sensitivity between the low-sensitivity mode and the high-sensitivity mode is assumed to be 1:4, similar to Figures 7A and 7B.

[0103] Since the number of readout pixels in D1 in Figure 12A is 2, the number of pixels in D1 in Figure 12B, where the number of readout pixels has been reduced, becomes 1. That is, the decimation rate becomes 1 / 2. Because the amount of gain reduction due to pixel decimation decreases, the AD conversion gain in Figure 12B is adjusted to -6 dB. This makes the overall gain in D2 equal to the overall gain in D3, and the phase difference signal generated in high-sensitivity mode can be used as the phase difference signal in low-sensitivity mode.

[0104] The configuration of the image sensor 1 other than that described above is the same as that of the image sensor 1 in the first embodiment of this disclosure, so a description will be omitted.

[0105] Thus, in the second embodiment of the present disclosure, when using a pixel block 120 having a plurality of pixels 100 arranged in two rows and two columns, the image sensor 1 adjusts the number of pixels 100 used to generate the phase difference signal and adjusts the AD conversion gain. This allows the level of the phase difference signal generated in high-sensitivity mode to be adjusted and used as a low-sensitivity mode phase difference signal.

[0106] (3. Third Embodiment) The image sensor 1 of the first embodiment described above had a different AD conversion gain when generating a low-sensitivity mode phase difference signal (D phase) than when generating a high-sensitivity mode reference signal (P phase). In contrast, the image sensor 1 of the third embodiment of this disclosure differs from the first embodiment described above in that it corrects the error based on the difference in these gains.

[0107] <Configuration of the Pixel Array Section> Figure 13 is a diagram showing an example configuration of the pixel array section according to the third embodiment of the present disclosure. This diagram, like Figure 2, shows an example configuration of the pixel array section 10. The pixel array section 10 in this figure differs from the pixel array section 10 in Figure 2 in that it further comprises a pixel unit 201.

[0108] The pixel unit 201 is a pixel unit having a pixel block 121 equipped with light-shielding pixels 190. The pixel unit 201 in Figure 13 shows an example in which four light-shielding pixels 190 are arranged. Here, a light-shielding pixel 190 is a pixel from which incident light is blocked. These light-shielding pixels 190 can be arranged outside the effective pixel area in the pixel array 10.

[0109] <Pixel Block Configuration> Figure 14 is a cross-sectional view showing an example of the configuration of a pixel block according to the third embodiment of the present disclosure. The same figure is a cross-sectional view showing an example of the configuration of a pixel block 121. As described above, a light-shielding pixel 190 is arranged in the pixel block 121. The light-shielding pixel 190 differs from the pixel 100 in that the color filter 160 and the on-chip lens 170 are omitted.

[0110] As described above, the light-shielding pixel 190 omits the color filter 160, and a light-shielding portion 169 is placed over its entire surface. In addition, a protective film 171 is placed in place of the on-chip lens 170. This light-shielding pixel 190 is used to generate a signal that corrects errors based on the difference between the AD conversion gain of the D phase and the AD conversion gain of the P phase.

[0111] [Pixel Unit Configuration] Figure 15 is a diagram showing an example of the circuit configuration of a pixel unit according to the third embodiment of this disclosure. Similar to Figure 4, this figure is a circuit diagram showing an example configuration of the pixel unit 200. Note that the circuit description of the pixel unit 200 has been simplified in this figure.

[0112] Figure 15 further illustrates the pixel unit 201, the analog-to-digital conversion unit 38, and the correction unit 39. The pixel unit 201 can be configured with the same circuitry as the pixel unit 200. Therefore, the pixel unit 201 can also generate a low-sensitivity mode reference signal and a low-sensitivity mode phase difference signal. The analog-to-digital conversion unit 38 performs analog-to-digital conversion and CDS processing on the high-sensitivity mode reference signal and low-sensitivity mode phase difference signal generated by the pixel unit 201.

[0113] The correction unit 39 corrects errors in the low-sensitivity mode phase difference signal generated by the pixel unit 200. As mentioned above, the AD conversion gain used when generating the low-sensitivity mode phase difference signal is set to a different value than when generating the high-sensitivity mode reference signal used for CDS processing. Therefore, errors may occur in the CDS processing in the analog-to-digital conversion unit 32. Specifically, this may result in a shift in the black level, etc., in the low-sensitivity mode phase difference signal after processing. The correction unit 39 corrects these errors. In the light-shielding pixel 190 described above, a high-sensitivity mode reference signal and a low-sensitivity mode phase difference signal are also generated and converted from analog to digital and subjected to CDS processing in the analog-to-digital conversion unit 38 in Figure 15. Since the signal after this CDS processing contains the above-mentioned errors, this signal is used as a correction signal. Specifically, the correction unit 39 performs the correction by subtracting the correction signal from the low-sensitivity mode phase difference signal from the analog-to-digital conversion unit 32.

[0114] The configuration of the image sensor 1 other than that described above is the same as that of the image sensor 1 in the first embodiment of this disclosure, so a description will be omitted.

[0115] As described above, the image sensor 1 of the third embodiment of this disclosure is equipped with a correction unit 39 to correct the low-sensitivity mode phase difference signal. This reduces the error in the low-sensitivity mode phase difference signal and improves the accuracy of image plane phase difference detection.

[0116] (4. Fourth Embodiment) The image sensor 1 of the first embodiment described above used a different AD conversion gain for generating the low-sensitivity mode phase difference signal (D phase) than for generating the high-sensitivity mode reference signal (P phase). In contrast, the image sensor 1 of the fourth embodiment of this disclosure differs from the first embodiment described above in that it selects and uses either the low-sensitivity mode reference signal or the high-sensitivity mode reference signal as the reference signal used for CDS processing of the low-sensitivity mode phase difference signal.

[0117] <Configuration of Analog-to-Digital Conversion Unit> Figure 16 is a diagram showing an example configuration of the analog-to-digital conversion unit according to the fourth embodiment of this disclosure. Similar to Figure 6, this figure is a block diagram showing an example configuration of the analog-to-digital conversion unit 32. The figure further shows a control unit 40. The control unit 40 includes a selection unit 43.

[0118] The selection unit 43 selects either a low-sensitivity mode reference signal or a high-sensitivity mode reference signal as the reference signal used when performing CDS processing on a low-sensitivity mode phase difference signal. The selection unit 43 selects between the low-sensitivity mode reference signal and the high-sensitivity mode reference signal according to the gain when converting the low-sensitivity mode phase difference signal in the analog-to-digital conversion unit 32. The selection unit 43 outputs the selection result to the CDS unit 303 of the analog-to-digital conversion unit 32.

[0119] The CDS unit 303 in Figure 16 performs CDS processing on the low-sensitivity mode phase difference signal using a reference signal corresponding to the selection result from the selection unit 43.

[0120] Figure 17 shows an example of CDS processing according to the fourth embodiment of this disclosure. The figure shows the waveforms of the reference signals in P1, P2, D1, D2, and D3. Normally, the CDS processing of the low-sensitivity mode phase difference signal generated in D1 uses the high-sensitivity mode reference signal generated in P2. However, if the AD conversion gain in D1 and the AD conversion gain in P2 differ significantly, the error in CDS processing may increase. In such cases, the error in CDS processing can be reduced by performing CDS processing using the low-sensitivity mode reference signal generated in P1. The correction unit 39 in Figure 16 selects either the low-sensitivity mode reference signal or the high-sensitivity mode reference signal according to the AD conversion gain in D1. Specifically, it selects the reference signal that reduces the difference between the AD conversion gain in D1 and the AD conversion gains in P1 and P2. In the example shown in the figure, the low-sensitivity mode reference signal generated in P1 is selected.

[0121] The configuration of the image sensor 1 other than that described above is the same as that of the image sensor 1 in the first embodiment of this disclosure, so a description will be omitted.

[0122] Thus, the image sensor 1 of the fourth embodiment of this disclosure has a selection unit 43 to select a reference signal to be used for CDS processing of the low-sensitivity mode phase difference signal. This makes it possible to reduce errors in CDS processing of the low-sensitivity mode phase difference signal.

[0123] (5. Fifth Embodiment) The image sensor 1 of the first embodiment described above adjusted the number of pixels 100 used to generate the low-sensitivity mode phase difference signal. In contrast, the image sensor 1 of the fifth embodiment of this disclosure differs from the first embodiment described above in that it partially omits the adjustment of the number of pixels 100 used to generate the low-sensitivity mode phase difference signal.

[0124] <Configuration of the control unit> Figure 18 is a diagram showing an example configuration of the control unit according to the fifth embodiment of the present disclosure. The same figure shows an example configuration of the control unit 40 according to the fifth embodiment of the present disclosure. The control unit 40 in the same figure further comprises an adjustment unit 44.

[0125] The adjustment unit 44 adjusts the number of pixels 100 on one side of the pupil division used when generating the low-sensitivity mode phase difference signal. This adjustment unit 44 adjusts the number of pixels 100 on one side of the pupil division according to the signal level of the high-sensitivity mode pixel signal. When the shooting scene becomes dark and the overall gain of the low-sensitivity mode pixel signal exceeds 6 dB, the signal level of the high-sensitivity mode pixel signal also decreases. In such cases, the number of pixels 100 used when generating the low-sensitivity mode phase difference signal can be set to "0", and the level of the low-sensitivity mode phase difference signal can be made equivalent to that of the low-sensitivity mode pixel signal simply by adjusting the AD conversion gain. Pixel decimation prevents deterioration of the signal-to-noise ratio (S / N ratio).

[0126] <Generation of Pixel Signals and Phase Difference Signals> Figures 19A and 19B show an example of the generation of pixel signals and phase difference signals according to the fifth embodiment of the present disclosure. Figures 19A and 19B, like Figures 12A and 12B, show the generation of pixel signals and phase difference signals when using a pixel block 120 having four pixels 100 arranged in two rows and two columns. Figures 19A and 19B further show the number of terminal counts and the required number of bits during analog-to-digital conversion in the analog-to-digital conversion unit 32.

[0127] Figure 19A shows the case where the number of pixels is adjusted. Figure 19B shows the case where the number of pixels is not adjusted, i.e., pixel downsampling is not performed. As shown in Figure 19B, when the minimum AD conversion gain is 3 dB and the AD conversion gain at D3 is 9 dB or more, pixel downsampling is not necessary.

[0128] Figure 20 shows an example of the generation of a pixel signal and a phase difference signal according to the fifth embodiment of this disclosure. The figure shows the conditions for performing pixel decimation. The upper part of the figure shows the case where the sensitivity ratio is 1:4, and the lower part of the figure shows the case where the sensitivity ratio is 1:16. In the figure, "SFHDR" represents the difference between the AD conversion gain of D3 and the AD conversion gain of D2. D1 to D3 in the figure represent the sum of the gain based on the number of pixels (CG) and the AD conversion gain (AG). "Number of pixels" in the figure represents the number of pixels 100 used when generating a low-sensitivity mode phase difference signal. In this way, pixel decimation can be omitted when the AD conversion gain of D3 is 9 dB or more.

[0129] The configuration of the image sensor 1 other than that described above is the same as that of the image sensor 1 in the first embodiment of this disclosure, so a description will be omitted.

[0130] Thus, the image sensor 1 of the fifth embodiment of this disclosure adjusts the number of pixels to be downsampled when generating a low-sensitivity mode phase difference signal according to the environment, such as the shooting scene. This makes it possible to optimize the generation of the low-sensitivity mode phase difference signal.

[0131] (6. Sixth Embodiment) The image sensor 1 of the first embodiment described above generated a high-sensitivity mode pixel signal and a low-sensitivity mode pixel signal. In contrast, the image sensor 1 of the sixth embodiment of this disclosure differs from the first embodiment described above in that it selects and generates either a high-sensitivity mode pixel signal or a low-sensitivity mode pixel signal.

[0132] <Pixel Unit Configuration> Figure 21 is a diagram showing an example configuration of a pixel unit according to the sixth embodiment of the present disclosure. The same figure is a circuit diagram showing an example configuration of a pixel unit 200 according to the sixth embodiment of the present disclosure. The pixel unit 200 in the same figure differs from the pixel unit 200 in Figure 4 in that a switching transistor 107 is arranged in parallel with the coupling unit 105. The switching transistor 107 switches the sensitivity of the pixel unit 200. The signal line FDGV is connected to the gate of the switching transistor 107. The signal of this signal line FDGV is generated by the analog-to-digital conversion unit 32.

[0133] <Configuration of Analog-to-Digital Conversion Unit> Figure 22 is a diagram showing an example configuration of the analog-to-digital conversion unit according to the sixth embodiment of the present disclosure. The analog-to-digital conversion unit 32 in the figure includes an amplification unit 304, a latch circuit 305, a multiplexer 306, and a switching control unit 307 instead of the CDS unit 303. In the figure, "latch circuit" is written as "latch" and "multiplexer" is written as "MUX".

[0134] In addition to comparing the pixel signal and the reference signal, the comparator 301 in Figure 22 can also compare the signal level of the pixel signal with a predetermined threshold.

[0135] The amplifier 304 amplifies the output of the comparator 301 and outputs it to the latch circuit 305 and the multiplexer 306. The latch circuit 305 latches the result of determining the magnitude of the signal level (D-phase level) of the pixel signal. The multiplexer 306 inputs the output of the amplifier 304 and the output of the latch circuit 305 as a single signal to the counter 302.

[0136] The switching control unit 307 switches the signal on the signal line FDGV based on the determination result of the magnitude of the D-phase level of the pixel signal latched by the latch circuit 305. For example, when the D-phase level of the pixel signal in high-sensitivity mode is above the threshold level, the switching control unit 154 conducts the switching transistor 107 of the pixel unit 200 to switch to low-sensitivity mode. On the other hand, when the D-phase level of the pixel signal in high-sensitivity mode is below the threshold level, the switching control unit 307 switches the pixel unit 200 to high-sensitivity mode.

[0137] Figure 23 is a diagram showing an example of the generation of a pixel signal and a phase difference signal according to the sixth embodiment of this disclosure. The diagram is a timing diagram showing an example of the generation of a pixel signal and a phase difference signal in the pixel unit 200. In the diagram, "FDGV" represents the signal of the signal line FDGV. During the "determination" period after D1 in the diagram, the signal level of the pixel signal described above is determined. Based on this determination result, the switching control unit 307 generates a signal and controls the switching transistor 107 of the pixel unit 200 to switch between high-sensitivity mode and low-sensitivity mode. After that, D2 is performed according to each operating mode. Note that in D1 in the diagram, pixel decimation and AD conversion gain adjustment can be performed. Also, in D2, it is necessary to correct the error of the CDS processing.

[0138] The configuration of the image sensor 1 other than that described above is the same as that of the image sensor 1 in the first embodiment of this disclosure, so a description will be omitted.

[0139] Thus, the image sensor 1 of the sixth embodiment of this disclosure switches between a high-sensitivity mode and a low-sensitivity mode based on the signal level of the pixel signal. This makes it possible to shorten the time required for analog-to-digital conversion.

[0140] (7. Seventh Embodiment) The image sensor 1 of the first embodiment described above performed imaging once during the frame period. In contrast, the image sensor 1 of the seventh embodiment of this disclosure differs from the first embodiment described above in that it performs multiple images during the frame period.

[0141] <Control Method for Image Sensor> Figure 24 is a diagram showing an example of a control method for an image sensor according to the seventh embodiment of this disclosure. Similar to Figure 10, this figure shows an example of a control method for generating pixel signals in the image sensor 1. In this figure, the image sensor 1 performs a shortened exposure period 402 after the aforementioned exposure period 401. This enables so-called short exposure imaging, and the sensitivity of pixel signal generation can be adjusted in four stages.

[0142] The configuration of the image sensor 1 other than that described above is the same as that of the image sensor 1 in the first embodiment of this disclosure, so a description will be omitted.

[0143] Thus, the image sensor 1 of the seventh embodiment of this disclosure performs multiple images during the frame period. This improves convenience.

[0144] (8. Eighth Embodiment) A variation of the image sensor 1 of the first embodiment described above will be explained.

[0145] <Pixel Unit Configuration> Figure 25 is a diagram showing an example of the configuration of a pixel unit according to the eighth embodiment of the present disclosure. The figure shows an example of a pixel unit 200 having pixels 100 arranged in 4 rows and 4 columns. The upper part of the figure shows an example where the pixel decimation rate is 4. The middle part of the figure shows an example where the pixel decimation rate is 2. The lower part of the figure shows an example where no pixel decimation is performed.

[0146] Figure 26 shows an example of imaging conditions according to the eighth embodiment of this disclosure. The figure shows the relationship between the sensitivity ratio, pixel decimation, and the AD conversion gain in D1 to D3. When the sensitivity ratio is 1:4, the number of pixels used to generate the low-sensitivity mode phase difference signal is reduced to 1 / 4, thereby producing a low-sensitivity mode phase difference signal equivalent to the low-sensitivity mode pixel signal (D3). When the sensitivity ratio is 1:8, the number of pixels used to generate the low-sensitivity mode phase difference signal is reduced to 1 / 4, and the AD conversion gain of D1 is set to -6 dB. When the sensitivity ratio is 1:16, the number of pixels used to generate the low-sensitivity mode phase difference signal is reduced to 1 / 4, and the AD conversion gain of D1 is set to -12 dB.

[0147] <Other Configurations of the Pixel Unit> Figure 27 is a diagram showing other configuration examples of a pixel unit according to the eighth embodiment of the present disclosure. The figure shows an example of a pixel unit 200 having pixels 100 arranged in 2 rows and 2 columns. The upper part of the figure shows an example where the pixel decimation rate is 2. The lower part of the figure shows an example where no pixel decimation is performed.

[0148] Figure 28 shows another example of imaging conditions according to the eighth embodiment of this disclosure. Similar to Figure 26, this figure shows the relationship between the sensitivity ratio, pixel decimation, and AD conversion gain in D1 to D3.

[0149] The configuration of the image sensor 1 other than that described above is the same as that of the image sensor 1 in the first embodiment of this disclosure, so a description will be omitted.

[0150] (9. Configuration of Electronic Devices) The image sensor 1 described above can be applied to various electronic devices such as imaging systems like digital still cameras and digital video cameras, mobile phones equipped with imaging functions, or other devices equipped with imaging functions.

[0151] Figure 29 is a block diagram showing an example of the configuration of an electronic device. As shown in Figure 29, the electronic device 701 includes an optical system 702, an image sensor 703, and a DSP (Digital Signal Processor) 704. The DSP 704, display device 705, operating system 706, memory 708, recording device 709, and power supply system 710 are connected via a bus 707, and the device is capable of capturing still and moving images.

[0152] The optical system 702 is composed of one or more lenses and guides the image light (incident light) from the subject to the image sensor 703, forming an image on the light-receiving surface (sensor part) of the image sensor 703.

[0153] The image sensor 703 is the image sensor 1 of any of the above-described configuration examples. Electrons are accumulated in the image sensor 703 for a certain period of time in accordance with the image formed on the light-receiving surface via the optical system 702. Then, a signal corresponding to the electrons accumulated in the image sensor 703 is input to the DSP 704.

[0154] The DSP 704 performs various signal processing on the signal from the image sensor 703 to acquire an image, and temporarily stores the image data in the memory 708. The image data stored in the memory 708 is recorded in the recording device 709 or supplied to the display device 705 to display the image. The operation system 706 accepts various operations from the user and supplies operation signals to each block of the electronic device 701, and the power supply system 710 supplies the power necessary to drive each block of the electronic device 701. Note that the DSP 704 is an example of a "processing circuit" in this disclosure.

[0155] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0156] Furthermore, this technology can also take the following configuration: (1) A pixel unit comprising a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion of incident light from a subject and a charge transfer unit that transfers the charge generated by the photoelectric conversion, a charge holding unit that holds the charge transferred by the charge transfer unit, a reset unit that performs a reset by discharging the held charge, an auxiliary charge holding unit coupled to the charge holding unit, a coupling unit that connects the auxiliary charge holding unit to the charge holding unit by making the connection between the charge holding unit and the auxiliary charge holding unit conductive, and a pixel signal generation unit that generates a pixel signal based on the held charge, and an analog-to-digital conversion unit that converts the generated pixel signal into a digital pixel signal, wherein the pixel signal generation unit generates a high-sensitivity mode pixel signal which is the pixel signal in a high-sensitivity mode which is an operating mode in which the auxiliary charge holding unit and the charge holding unit are not coupled, and a low-sensitivity mode pixel signal which is the pixel signal in a low-sensitivity mode which is an operating mode in which the auxiliary charge holding unit and the charge holding unit are coupled, The pixel signal generation unit further generates a high-sensitivity mode phase difference signal, which is the phase difference signal in the high-sensitivity mode, from the phase difference signals that are the pixel signals for detecting the image plane phase difference by dividing the pupil, based on the charges of a plurality of pixels on one side of the pupil division; the pixel signal generation unit further generates a low-sensitivity mode phase difference signal, which is the phase difference signal in the low-sensitivity mode, based on the charges of a number of pixels on one side of the plurality of pixels in the pupil division that are less than or equal to the number of pixels used when generating the high-sensitivity mode phase difference signal; and the analog-to-digital conversion unit adjusts the gain when converting the low-sensitivity mode phase difference signal. (2) The image sensor according to (1), further comprising a calculation circuit that generates a second high-sensitivity mode phase difference signal, which is a phase difference signal based on the charge of the pixel on the other side of the pupil division, by subtracting the high-sensitivity mode phase difference signal from the high-sensitivity mode pixel signal, and generates a second low-sensitivity mode phase difference signal, which is a phase difference signal based on the charge of the pixel on the other side of the pupil division, by subtracting the low-sensitivity mode phase difference signal from the low-sensitivity mode pixel signal.(3) The image sensor according to (1) or (2), wherein the pixel signal generation unit further generates a high-sensitivity mode reference signal, which is the pixel signal at the time of reset in the high-sensitivity mode, and a low-sensitivity mode reference signal, which is the pixel signal at the time of reset in the low-sensitivity mode, and the analog-to-digital conversion unit generates a digital high-sensitivity mode pixel signal obtained by subtracting the high-sensitivity mode reference signal, and a digital low-sensitivity mode pixel signal obtained by subtracting the low-sensitivity mode reference signal. (4) The image sensor according to (3), wherein the analog-to-digital conversion unit further generates a digital low-sensitivity mode phase difference signal obtained by subtracting the low-sensitivity mode reference signal. (5) The image sensor according to (4), further comprising a light-shielding pixel, which is the pixel from which incident light is blocked, and a correction unit that corrects the digital low-sensitivity mode phase difference signal based on the low-sensitivity mode reference signal and the low-sensitivity mode phase difference signal generated based on the light-shielding pixel. (6) The image sensor according to (4), further comprising a selection unit that selects either the low-sensitivity mode reference signal or the high-sensitivity mode reference signal as a reference signal according to the gain when the analog-to-digital conversion unit converts the phase difference signal, wherein the analog-to-digital conversion unit generates the digital low-sensitivity mode phase difference signal obtained by subtracting the selected reference signal. (7) The image sensor according to any one of (1) to (6), further comprising an adjustment unit that adjusts the number of pixels on one side of the pupil division used when the pixel signal generation unit generates the low-sensitivity mode phase difference signal. (8) The image sensor according to any one of (1) to (7), wherein the pixel unit comprises a pixel block having a plurality of pixels and an on-chip lens. (9) The image sensor according to (8), wherein the pixel unit comprises a plurality of pixel blocks. (10) The image sensor according to (8), wherein the pixel block comprises two pixels. (11) The image sensor according to (8), wherein the pixel block comprises four pixels arranged in two rows and two columns.(12) A pixel unit comprising a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion of incident light from a subject and a charge transfer unit that transfers the charge generated by the photoelectric conversion, a charge holding unit that holds the charge transferred by the charge transfer unit, a reset unit that performs a reset by discharging the held charge, an auxiliary charge holding unit coupled to the charge holding unit, a coupling unit that connects the auxiliary charge holding unit to the charge holding unit by making the connection between the charge holding unit and the auxiliary charge holding unit conductive, and a pixel signal generation unit that generates a pixel signal based on the held charge, and an analog-to-digital conversion unit that converts the generated pixel signal into a digital pixel signal, wherein the pixel signal generation unit generates a high-sensitivity mode pixel signal which is the pixel signal in a high-sensitivity mode which is an operating mode in which the auxiliary charge holding unit and the charge holding unit are not coupled, and a low-sensitivity mode pixel signal which is the pixel signal in a low-sensitivity mode which is an operating mode in which the auxiliary charge holding unit and the charge holding unit are coupled, The pixel signal generation unit further generates a high-sensitivity mode phase difference signal, which is the phase difference signal in the high-sensitivity mode, from the phase difference signals which are the pixel signals for detecting the image plane phase difference by dividing the pupil, based on the charges of a plurality of pixels on one side of the pupil division; the pixel signal generation unit further generates a low-sensitivity mode phase difference signal, which is the phase difference signal in the low-sensitivity mode, based on the charges of a number of pixels less than or equal to the number of pixels used when generating the high-sensitivity mode phase difference signal from a plurality of pixels on one side of the pupil division; the imaging device having an image sensor that adjusts the gain when converting the low-sensitivity mode phase difference signal, and a processing circuit that processes the high-sensitivity mode pixel signal and the low-sensitivity mode pixel signal.

[0157] 1 Image sensor 10 Pixel array section 30 Column signal processing section 32, 38 Analog-to-digital conversion section 35 Reference signal generation section 37 Arithmetic circuit 39 Correction section 40 Control section 43 Selection section 44 Adjustment section 100, 100a, 100b Pixel 101 Photoelectric conversion section 102 Charge transfer section 103 Charge holding section 104 Reset section 105 Coupling section 106 Auxiliary charge holding section 110 Pixel signal generation section 120, 120a, 120b, 120c, 120d, 121 Pixel block 170 On-chip lens 190 Light-shielding pixel 200, 200a, 200b, 200c, 200d Pixel unit 303 CDS section 701 Electronic equipment 704 DSP

Claims

1. A pixel unit comprising: a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion of incident light from a subject and a charge transfer unit that transfers the charge generated by the photoelectric conversion; a charge holding unit that holds the charge transferred by the charge transfer unit; a reset unit that performs a reset by discharging the held charge; an auxiliary charge holding unit coupled to the charge holding unit; a coupling unit that connects the auxiliary charge holding unit to the charge holding unit by making the connection between the charge holding unit and the auxiliary charge holding unit conductive; and a pixel signal generation unit that generates a pixel signal based on the held charge; and an analog-to-digital conversion unit that converts the generated pixel signal into a digital pixel signal, wherein the pixel signal generation unit generates a high-sensitivity mode pixel signal, which is the pixel signal in a high-sensitivity mode, which is an operating mode in which the auxiliary charge holding unit and the charge holding unit are not coupled; and a low-sensitivity mode pixel signal, which is the pixel signal in a low-sensitivity mode, which is an operating mode in which the auxiliary charge holding unit and the charge holding unit are coupled. The pixel signal generation unit further generates a high-sensitivity mode phase difference signal, which is the phase difference signal in the high-sensitivity mode, from the phase difference signals that are the pixel signals for detecting the image plane phase difference by dividing the pupil, based on the charges of a plurality of pixels on one side of the pupil division; the pixel signal generation unit further generates a low-sensitivity mode phase difference signal, which is the phase difference signal in the low-sensitivity mode, based on the charges of a number of pixels on one side of the plurality of pixels in the pupil division that are less than or equal to the number of pixels used when generating the high-sensitivity mode phase difference signal; and the analog-to-digital conversion unit adjusts the gain when converting the low-sensitivity mode phase difference signal.

2. The image sensor according to claim 1, further comprising a calculation circuit that generates a second high-sensitivity mode phase difference signal, which is a phase difference signal based on the charge of the pixel on the other side of the pupil division, by subtracting the high-sensitivity mode phase difference signal from the high-sensitivity mode pixel signal, and generates a second low-sensitivity mode phase difference signal, which is a phase difference signal based on the charge of the pixel on the other side of the pupil division, by subtracting the low-sensitivity mode phase difference signal from the low-sensitivity mode pixel signal.

3. The image sensor according to claim 1, wherein the pixel signal generation unit further generates a high-sensitivity mode reference signal, which is the pixel signal at the time of reset in the high-sensitivity mode, and a low-sensitivity mode reference signal, which is the pixel signal at the time of reset in the low-sensitivity mode, and the analog-to-digital conversion unit generates a digital high-sensitivity mode pixel signal obtained by subtracting the high-sensitivity mode reference signal, and a digital low-sensitivity mode pixel signal obtained by subtracting the low-sensitivity mode reference signal.

4. The image sensor according to claim 3, wherein the analog-to-digital conversion unit further generates the digital low-sensitivity mode phase difference signal obtained by subtracting the low-sensitivity mode reference signal.

5. The image sensor according to claim 4, further comprising a light-shielding pixel which is a pixel from which incident light is blocked, and a correction unit which corrects the digital low-sensitivity mode phase difference signal based on a low-sensitivity mode reference signal and a low-sensitivity mode phase difference signal generated based on the light-shielding pixel.

6. The image sensor according to claim 4, further comprising a selection unit that selects either the low-sensitivity mode reference signal or the high-sensitivity mode reference signal as a reference signal according to the gain when the analog-to-digital conversion unit converts the phase difference signal, wherein the analog-to-digital conversion unit generates the digital low-sensitivity mode phase difference signal obtained by subtracting the selected reference signal.

7. The image sensor according to claim 1, further comprising an adjustment unit for adjusting the number of pixels on one side of the pupil division used when the pixel signal generation unit generates the low-sensitivity mode phase difference signal.

8. The image sensor according to claim 1, wherein the pixel unit comprises a pixel block having a plurality of pixels and an on-chip lens.

9. The image sensor according to claim 8, wherein the pixel unit comprises a plurality of the pixel blocks.

10. The image sensor according to claim 8, wherein the pixel block comprises two of the pixels.

11. The image sensor according to claim 8, wherein the pixel block comprises four pixels arranged in two rows and two columns.

12. A pixel unit comprising: a plurality of pixels each having a photoelectric conversion unit that performs photoelectric conversion of incident light from a subject and a charge transfer unit that transfers the charge generated by the photoelectric conversion; a charge holding unit that holds the charge transferred by the charge transfer unit; a reset unit that performs a reset by discharging the held charge; an auxiliary charge holding unit coupled to the charge holding unit; a coupling unit that connects the auxiliary charge holding unit to the charge holding unit by making the connection between the charge holding unit and the auxiliary charge holding unit conductive; and a pixel signal generation unit that generates a pixel signal based on the held charge; and an analog-to-digital conversion unit that converts the generated pixel signal into a digital pixel signal, wherein the pixel signal generation unit generates a high-sensitivity mode pixel signal which is the pixel signal in a high-sensitivity mode, which is an operating mode in which the auxiliary charge holding unit and the charge holding unit are not coupled; and a low-sensitivity mode pixel signal which is the pixel signal in a low-sensitivity mode, which is an operating mode in which the auxiliary charge holding unit and the charge holding unit are coupled. The pixel signal generation unit further generates a high-sensitivity mode phase difference signal, which is the phase difference signal in the high-sensitivity mode, from the phase difference signals which are the pixel signals for detecting the image plane phase difference by dividing the pupil, based on the charges of a plurality of pixels on one side of the pupil division; the pixel signal generation unit further generates a low-sensitivity mode phase difference signal, which is the phase difference signal in the low-sensitivity mode, based on the charges of a number of pixels less than or equal to the number of pixels used when generating the high-sensitivity mode phase difference signal from a plurality of pixels on one side of the pupil division; the imaging device having an image sensor that adjusts the gain when converting the low-sensitivity mode phase difference signal, and a processing circuit that processes the high-sensitivity mode pixel signal and the low-sensitivity mode pixel signal.

Images