Crystal oscillation circuit

Abstract

A crystal oscillation circuit (30) comprises: a crystal oscillator (32); a FET (34b) having a gate (G) connected to one end of the crystal oscillator (32), a drain (D) connected to the other end of the crystal oscillator (32), and a source (S) to which a prescribed first DC potential (AVSS33; ground) is applied; a constant current source (34a) to which a prescribed second DC potential (DC power supply AVDD33) is applied; and a voltage-limiting circuit (34c) which is connected between an output terminal of the constant current source (34a) and the drain (D) and which limits the voltage of a signal appearing in the drain (D) so that the voltage does not exceed a prescribed value.

Description

Crystal Oscillator Circuit

[0001] The present disclosure relates to a crystal oscillator circuit.

[0002] Conventionally, a damping resistor connected in series with a crystal resonator is provided to prevent the excitation level of the crystal resonator constituting the crystal oscillator circuit from exceeding a specified value (see, for example, Patent Document 1).

[0003] In the technology of Patent Document 1, providing a transmission gate that functions as a damping resistor reduces the number of external components provided outside a semiconductor chip including the crystal oscillator circuit.

[0004] Japanese Unexamined Patent Publication No. Hei 5-235640

[0005] However, the technology of Patent Document 1 functionally provides a damping resistor in the crystal oscillator circuit, and has the following problem arising from providing the damping resistor. That is, since the damping resistor is provided in series with the output of the inverting amplifier that constitutes the crystal oscillator circuit, the absolute value of the negative resistance "-R" of the inverting amplifier decreases. As a result, it is necessary to secure a sufficient magnitude of negative resistance compared to a crystal oscillator circuit without a damping resistor, which leads to the problem that the current consumption of the inverting amplifier increases.

[0006] Accordingly, an object of the present disclosure is to provide a crystal oscillator circuit that does not require a damping resistor without increasing the current consumption of an inverting amplifier.

[0007] To achieve the above object, a crystal oscillator circuit according to one aspect of the present disclosure includes: a crystal resonator; a transistor having a gate connected to one end of the crystal resonator, a drain connected to the other end of the crystal resonator, and a source to which a predetermined first DC potential is applied; a constant current source to which a predetermined second DC potential is applied; and a voltage limiting circuit connected between an output terminal of the constant current source and the drain, the voltage limiting circuit limiting the voltage of a signal appearing at the drain so that the voltage does not exceed a predetermined value.

[0008] The present disclosure provides a crystal oscillator circuit that does not require a damping resistor without increasing the current consumption of an inverting amplifier.

[0009] Figure 1 is a circuit diagram illustrating the basic performance required of a crystal oscillator circuit. Figure 2 is a circuit diagram showing the configuration of a crystal oscillator circuit according to a reference example illustrating the problems of the prior art. Figure 3 is a circuit diagram showing the configuration of a crystal oscillator circuit according to an embodiment. Figure 4 is a circuit diagram showing the configuration of a crystal oscillator circuit according to a first modified example of the embodiment. Figure 5 is a circuit diagram showing the configuration of a crystal oscillator circuit according to a second modified example of the embodiment. Figure 6 is a circuit diagram showing the configuration of a crystal oscillator circuit according to a third modified example of the embodiment.

[0010] (The idea that the inventors have come up with) First, in order to explain the embodiments, we will explain the idea that the inventors have come up with.

[0011] Figure 1 is a circuit diagram illustrating the basic performance required of a crystal oscillator circuit. Here, a general crystal oscillator circuit 10 is shown. The crystal oscillator circuit 10 consists of a crystal oscillator 12 and a damping resistor RD connected in series between the input terminal XI and the output terminal XO, and an inverting amplifier 14 and a feedback resistor RF connected in parallel between the input terminal XI and the output terminal XO. Load capacitors CL1 and CL2 are connected between each end of the crystal oscillator 12 and ground.

[0012] The quartz oscillator 12 is an element that provides stable vibration at a specific frequency, and has an equivalent series resistance ESR as an important parameter that dampens the vibration.

[0013] The inverting amplifier 14 is a circuit component that amplifies the signal at input terminal XI and outputs it to output terminal XO in order to start and maintain oscillation, and has a negative resistance "-R" as an important parameter.

[0014] The feedback resistor RF is a resistor element that provides feedback in the inverting amplifier 14 to maintain oscillation.

[0015] The load capacitances CL1 and CL2 prevent excessive vibration of the crystal oscillator 12 and suppress the amplitude of the oscillation signal that appears at the output terminal XO.

[0016] The following two are important indicators for the crystal oscillator circuit 10 having such a configuration.

[0017] (1) Oscillation margin The oscillation margin is a value that indicates the margin for the crystal oscillator 12 to oscillate, and is expressed as follows.

[0018] Oscillation margin = (Absolute value of negative resistance "-R") / (Equivalent series resistance ESR)

[0019] The greater the oscillation margin, the more stable the oscillation in the crystal oscillator circuit 10 will be, and a margin of 5 (times) or more is recommended.

[0020] (2) Excitation level The excitation level is a value that indicates the power consumption of the crystal oscillator 12 when the crystal oscillator 12 is vibrating, and is expressed as follows.

[0021] Excitation level = (Current I flowing through the crystal oscillator 12) ２ × Equivalent series resistance ESR

[0022] Each crystal oscillator 12 has a specified maximum excitation level, and oscillations exceeding this specified level may damage the crystal oscillator 12. For this reason, a damping resistor RD is generally connected in series with the crystal oscillator 12 to suppress the current I flowing through the crystal oscillator 12 and reduce the excitation level.

[0023] Figure 2 is a circuit diagram showing the configuration of a crystal oscillator circuit 20, which is a reference example used to explain the problems of the conventional technology. The crystal oscillator circuit 20 has a configuration in which a comparator 22 that outputs a clock CLKOUT is added to the crystal oscillator circuit 10 shown in Figure 1. The inverting amplifier 14 is configured by connecting a constant current source 14a connected to a 3.3V DC power supply and a source-grounded FET 14b in series.

[0024] In a crystal oscillator circuit 20 using an inverting amplifier 14 that includes a source-grounded FET 14b, the negative resistance "-R" of the inverting amplifier 14 can be easily adjusted by adjusting the output current of the constant current source 14a. The negative resistance "-R" is expressed as follows.

[0025]

[0026] Here, gm is the transconductance of FET 14b, ω is 2 × π × oscillation frequency, and Cin and Cout are the capacitances to ground of the input terminal XI and output terminal XO, respectively.

[0027] Furthermore, the transconductance gm of FET 14b is expressed as follows.

[0028]

[0029] Here, μ is the carrier mobility of FET 14b, and C ｏｘ This is the gate oxide film capacitance per unit area of ​​FET 14b, and I Ｄ is the drain current of FET 14b, and W / L is the gate aspect ratio of FET 14b.

[0030] Furthermore, each type of crystal oscillator 12 has specified equivalent series resistance (ESR) and maximum excitation level, as shown in the table below.

[0031]

[0032] As shown in the table above, oscillator C has a larger equivalent series resistance (ESR) and a smaller maximum excitation bell specification compared to other types of oscillators. Therefore, in a crystal oscillator circuit 20 using such oscillator C, it is necessary to reduce the excitation level by suppressing the current with a damping resistor RD.

[0033] In the crystal oscillator circuit 20 of this example, a damping resistor RD is provided in series with the output of the inverting amplifier 14, which reduces the absolute value of the negative resistance "-R". Therefore, compared to a crystal oscillator circuit without a damping resistor RD, it becomes necessary to ensure a larger negative resistance "-R", which results in the problem of increased current consumption of the inverting amplifier 14.

[0034] Therefore, in order to solve the problems of the prior art described above, the present inventors diligently studied and came up with the following crystal oscillator circuit configuration. Specifically, the crystal oscillator circuit comprises a crystal resonator, a transistor having a gate connected to one end of the crystal resonator, a drain connected to the other end of the crystal resonator, and a source to which a predetermined first DC potential is applied, a constant current source to which a predetermined second DC potential is applied, and a voltage limiting circuit connected between the output terminal of the constant current source and the drain, which limits the voltage so that the voltage of the signal appearing at the drain does not exceed a predetermined value.

[0035] As a result, the voltage limiting circuit suppresses the excitation level of the crystal oscillator to a specified value, ensuring stable oscillation without the need for a damping resistor or increasing the current consumption of the inverting amplifier.

[0036] The embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments described below are all specific examples of this disclosure. The voltages, frequencies, numbers, numerical values, circuit components, connection configurations of circuit components, signal waveforms, etc., shown in the following embodiments are examples and are not intended to limit this disclosure. Furthermore, the figures are not necessarily strictly illustrative. In each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations are omitted or simplified. Also, "connection" refers to an electrical connection, including not only cases where two circuit elements are directly connected, but also cases where two circuit elements are indirectly connected with another circuit element inserted between them.

[0037] Figure 3 is a circuit diagram showing the configuration of a crystal oscillator circuit 30 according to an embodiment. The crystal oscillator circuit 30 consists of a crystal oscillator 32, an inverting amplifier 34, and a feedback resistor RF, which are connected between the input terminal XI and the output terminal XO. Load capacitors CL1 and CL2 are connected between each end of the crystal oscillator 32 and ground.

[0038] The inverting amplifier 34 includes: a source-grounded n-channel FET 34b having a gate G connected to one end of the crystal resonator 32, a drain D connected to the other end of the crystal resonator 32, and a source S connected to a predetermined first DC potential (here, AVSS 33; ground); a constant current source 34a connected to a predetermined second DC potential (here, DC power supply AVDD 33 (i.e., a 3.3 V DC voltage)); and a voltage limiting circuit 34c connected between the output terminal of the constant current source 34a and the drain D of the FET 34b, and configured to limit the voltage so that the voltage of a signal appearing at the drain D of the FET 34b does not exceed a predetermined value.

[0039] The constant current source 34a is configured using, for example, at least one of an FET, a bipolar transistor, a resistor, and a Zener diode.

[0040] In the present embodiment, the voltage limiting circuit 34c is configured by an n-channel FET having a fixed potential BIAS applied to its gate.

[0041] With such a configuration, the voltage limiting circuit 34c is inserted between the constant current source 34a and the source-grounded FET 34b, thereby limiting the upper limit of the amplitude of the oscillation signal appearing at the output terminal XO as shown in FIG. 3 and suppressing the excitation level. That is, according to the present embodiment, the excitation level is suppressed without inserting a series damping resistor into the output of the inverting amplifier 34 (which would reduce the absolute value of the negative resistance "-R"). Therefore, the crystal oscillation circuit 30 that does not require a damping resistor and does not increase the current consumption of the inverting amplifier 34 is implemented.

[0042] FIG. 4 is a circuit diagram showing a configuration of a crystal oscillation circuit 30a according to a first modification of the embodiment. The crystal oscillation circuit 30a according to the present modification basically has the same configuration as the crystal oscillation circuit 30 according to the embodiment shown in FIG. 3, except that the voltage limiting circuit 34c limits the voltage such that the voltage of an oscillation signal appearing at the drain D of the FET 34b does not exceed a predetermined value in accordance with a control signal from a voltage adjustment circuit 40 provided outside the crystal oscillation circuit 30a, which differs from the embodiment.

[0043] The voltage adjustment circuit 40 is a voltage generator that applies a desired voltage to the gate of the FET constituting the voltage limiting circuit 34c. Accordingly, the upper limit of the amplitude of the oscillation signal appearing at the drain D of the FET 34b, that is, the output terminal XO, is limited to a desired voltage as shown in FIG. 4.

[0044] FIG. 5 is a circuit diagram showing a configuration of a crystal oscillation circuit 30b according to a second modification of the embodiment. The crystal oscillation circuit 30b according to the present modification is configured of a crystal resonator 32, an inverting amplifier 44, and a feedback resistor RF connected between an input terminal XI and an output terminal XO. Load capacitances CL1 and CL2 are connected between both ends of the crystal resonator 32 and ground, respectively.

[0045] The inverting amplifier 44 includes a source-grounded p-channel FET 44b having a gate G connected to one end of the crystal resonator 32, a drain D connected to the other end of the crystal resonator 32, and a source S connected to a predetermined first DC potential (here, a DC power supply AVDD33), a voltage limiting circuit 44c connected to the drain of the FET 44b, and a constant current source 44a connected between the voltage limiting circuit 44c and a predetermined second DC potential (here, AVSS33; ground).

[0046] The present modification differs from the embodiment, in which each component is configured of an n-channel FET, in that the source-grounded FET 44b is a p-channel FET and the voltage limiting circuit 44c is configured of a p-channel FET.

[0047] According to the crystal oscillation circuit 30b of the present modification, similarly to the embodiment, a voltage limiting circuit 44c is inserted between the constant current source 44a and the source-grounded FET 44b, whereby the lower limit of the amplitude of the oscillation signal appearing at the output terminal XO is limited as shown in FIG. 5, and the excitation level is suppressed. That is, according to the present modification, the excitation level is suppressed without inserting a damping resistor in series with the output of the inverting amplifier 44 (which would reduce the absolute value of the negative resistance "-R"). Therefore, the crystal oscillation circuit 30b that does not require a damping resistor is realized without increasing the current consumption of the inverting amplifier 44.

[0048] Figure 6 is a circuit diagram showing the configuration of a crystal oscillator circuit 30c according to a third modified example of the embodiment. The crystal oscillator circuit 30c according to this modified example basically has the same configuration as the crystal oscillator circuit 30b according to the second modified example shown in Figure 5, but differs from the embodiment in that the voltage limiting circuit 44c limits the voltage so that the voltage of the signal appearing at the drain D of the FET 44b does not exceed a predetermined value (here, does not fall below a predetermined lower limit) in response to a control signal from a voltage adjustment circuit 40 provided outside the crystal oscillator circuit 30c.

[0049] The voltage adjustment circuit 40 is a voltage generator that applies a desired voltage to the gate of the FET constituting the voltage limiting circuit 44c. As a result, the lower limit of the amplitude of the oscillation signal appearing at the drain D of FET 44b, i.e., the output terminal XO, is limited to the desired voltage, as shown in Figure 6.

[0050] As described above, the crystal oscillator circuit 30 according to this embodiment includes a crystal oscillator 32, an FET 34b having a gate G connected to one end of the crystal oscillator 32, a drain D connected to the other end of the crystal oscillator 32, and a source S connected to a predetermined first DC potential (AVSS 33; ground), a constant current source 34a connected to a predetermined second DC potential (DC power supply AVDD 33), and a voltage limiting circuit 34c connected between the output terminal of the constant current source 34a and the drain D, which limits the voltage so that the voltage of the signal appearing at the drain D does not exceed a predetermined value.

[0051] As a result, a voltage limiting circuit 34c is inserted between the constant current source 34a and the source-grounded FET 34b, limiting the upper limit of the amplitude of the oscillation signal appearing at the output terminal XO and suppressing the excitation level. In other words, according to this embodiment, the excitation level is suppressed without inserting a damping resistor in series with the output of the inverting amplifier 34 (which reduces the absolute value of the negative resistance "-R"). Therefore, a crystal oscillator circuit 30 that does not require a damping resistor is realized without increasing the current consumption of the inverting amplifier 34.

[0052] Here, as in the crystal oscillator circuit 30a according to the first modified example, the voltage limiting circuit 34c may change a predetermined value in response to a signal input from outside the crystal oscillator circuit. This allows the excitation level to be arbitrarily set according to the type of crystal oscillator 32.

[0053] Furthermore, the voltage limiting circuit 34c and FET 34b may both be n-channel FETs, or, as in the second and third modifications, the voltage limiting circuit 44c and FET 44b may both be p-channel FETs.

[0054] The crystal oscillator circuit described above has been explained based on embodiments and modifications, but this disclosure is not limited to these embodiments and modifications. Within the scope of this disclosure, various modifications conceivable by those skilled in the art, as well as other forms constructed by combining some of the components of the embodiments and modifications, are also included, as long as they do not depart from the spirit of this disclosure.

[0055] For example, the above embodiments and modifications may include the comparator 22 shown in Figure 2.

[0056] Furthermore, in the above embodiment and its modifications, the crystal oscillator 32 and the inverting amplifier 34, etc., are connected via input terminal XI and output terminal XO. However, the connection is not limited to this configuration, and the crystal oscillator 32 and the inverting amplifier 34, etc., may be directly connected without going through input terminal XI and output terminal XO.

[0057] Furthermore, although load capacities CL1 and CL2 were connected in the above embodiment and modified example, load capacities CL1 and CL2 may be realized by stray capacities.

[0058] Furthermore, the voltage limiting circuit 34c in the embodiment and the voltage limiting circuit 44c in the second modified example may be composed of diodes instead of FETs.

[0059] Furthermore, although a damping resistor was not provided in the above embodiment and its modifications, a resistor may be connected in series with the crystal oscillator 32, or a resistive component may be provided in series with the crystal oscillator 32.

[0060] Furthermore, although a MOSFET was used as the FET in the above embodiments and modifications, it is not limited to this, and a JFET may also be used. Moreover, the FET may be other types of switching elements such as a bipolar transistor.

[0061] Furthermore, the crystal oscillator circuit may include a configuration that incorporates a voltage adjustment circuit 40.

[0062] This disclosure can be used as a crystal oscillator circuit, particularly as a crystal oscillator circuit that does not require a damping resistor and does not increase the current consumption of the inverting amplifier, for example, as a clock generation circuit that generates the operating clock for various electronic circuits.

[0063] 30, 30a, 30b, 30c Crystal oscillator circuit 32 Crystal oscillator 34, 44 Inverting amplifier 34a, 44a Constant current source 34b, 44b FET 34c, 44c Voltage limiting circuit 40 Voltage regulation circuit CL1, CL2 Load capacitance XI Input terminal XO Output terminal RF Feedback resistor

Claims

1. A crystal oscillator circuit comprising: a crystal oscillator; a transistor having a gate connected to one end of the crystal oscillator, a drain connected to the other end of the crystal oscillator, and a source to which a predetermined first DC potential is applied; a constant current source to which a predetermined second DC potential is applied; and a voltage limiting circuit connected between the output terminal of the constant current source and the drain, which limits the voltage so that the voltage of the signal appearing at the drain does not exceed a predetermined value.

2. The crystal oscillator circuit according to claim 1, wherein the voltage limiting circuit changes the predetermined value in response to a signal input from outside the crystal oscillator circuit.

3. The crystal oscillator circuit according to claim 1 or 2, wherein the voltage limiting circuit and the transistor are n-channel FETs.

4. The crystal oscillator circuit according to claim 1 or 2, wherein the voltage limiting circuit and the transistor are p-channel FETs.

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