Amplifier configured to provide substantially constant gain for wide input common mode range

Abstract

An amplifier, including: an output circuit; input differential NFETs including drains coupled to the output circuit, and gates configured to receive positive and negative components of an input differential signal, respectively; a current source NFET including a drain coupled to sources of the input differential NFETs, respectively, and a gate coupled to the output circuit and configured to receive a first bias voltage; a current source PFET including a gate configured to receive a second bias voltage; input differential PFETs including sources coupled to a drain of the current source PFET, and gates configured to receive the positive and negative components of the input differential signal, respectively; a pair of current source NFETs including drains coupled to the output circuit and to drains of the input differential PFETs, respectively; and a control circuit including an input coupled to the current source PFET and an output coupled to gates of the first pair of current source NFETs.

Description

Qualcomm Ref. No. 2500510WO 1 / 27AMPLIFIER CONFIGURED TO PROVIDE SUBSTANTIALLY CONSTANT GAIN FOR WIDE INPUT COMMON MODE RANGECROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present Application for Patent claims priority to pending U.S. Non-Pro visional Application no. 19 / 076,492, filed March 11, 2025, and assigned to the assignee hereof and hereby expressly incorporated by reference herein as if fully set forth below and for all applicable purposes.FIELD

[0002] This disclosure relates generally to amplifiers, and in particular, to an amplifier configured to provide substantially constant gain for wide input common mode range.BACKGROUND

[0003] A low dropout (LDO) voltage regulator may be configured to provide a regulated supply voltage to a particular load, such as a voltage controlled oscillator (VCO). The load, such as the VCO, may be used in various operating modes that may require significantly different regulated voltages. Accordingly, the regulated supply voltage generated by the LDO voltage regulator may have a wide voltage range. The LDO voltage regulator typically includes an operational amplifier for driving a pass field effect transistor (FET) to generate the regulated supply voltage. The wide voltage range for the regulated supply voltage may impose a wide range common mode voltage associated with an input differential voltage of the operational amplifier.SUMMARY

[0004] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0005] An aspect of the disclosure relates to an amplifier. The amplifier, includes: an output circuit; a pair of input differential n-channel field effect transistors (NFETs) including drains coupled to the output circuit, and gates configured to receive positive and negative components of an input differential signal, respectively; a current source NFET includingQualcomm Ref. No. 250051 OWO 2 / 27a drain coupled to sources of the input differential NFETs, and a gate coupled to the output circuit and configured to receive a first bias voltage; a current source p-channel field effect transistor (PFET) including a gate configured to receive a second bias voltage; a pair of input differential PFETs including sources coupled to a drain of the current source PFET, and gates configured to receive the positive and negative components of the input differential signal, respectively; a first pair of current source NFETs including drains coupled to the output circuit and to drains of the input differential PFETs, respectively; and a control circuit including an input coupled to the current source PFET and an output coupled to gates of the first pair of current source NFETs, respectively.

[0006] Another aspect of the disclosure relates to an amplifier. The amplifier, includes: an output circuit; a current source p-channel field effect transistor (PFET) including a gate coupled to the output circuit and configured to receive a first bias voltage; a pair of input differential PFETs including sources coupled to a drain of the current source PFET, drains coupled to the output circuit, and gates configured to receive positive and negative components of an input differential signal, respectively; a first pair of current source PFETs; a pair of input differential n-channel field effect transistors (NFETs) including drains coupled to drains of the first pair of current source PFETs, respectively, and gates configured to receive the positive and negative components of the input differential signal, respectively; a current source NFET including a gate configured to receive a second bias voltage, and a drain coupled to sources of the pair of input differential NFETs, respectively; and a control circuit including an input coupled to the current source NFET and an output coupled to gates of the first pair of current source PFETs, respectively.

[0007] Another aspect of the disclosure relates to a method. The method includes: amplifying an input differential signal using a first pair of input differential field effect transistor (FETs) to generate an output signal at an output circuit; amplifying the input differential signal using a second pair of input differential FETs to generate the output signal at the output circuit; sensing a current flowing into or out of the second pair of input differential FETs from or to a first current source, respectively; and controlling a pair of currents flowing out of or into the first pair of input differential FETs and into or out of a first pair of current sources based on the sensed current, respectively, to reduce currents flowing through the output circuit to or from the first pair of current sources.

[0008] To the accomplishment of the foregoing and related ends, the one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detailQualcomm Ref. No. 2500510WO 3 / 27certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the description implementations are intended to include all such aspects and their equivalents.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 illustrates a block diagram of an example phase locked loop (PLL) in accordance with an aspect of the disclosure.

[0010] FIG. 2 illustrates a schematic diagram of an example low dropout (LDO) voltage regulator in accordance with another aspect of the disclosure.

[0011] FIG. 3A illustrates a schematic diagram of an example amplifier in accordance with another aspect of the disclosure.

[0012] FIG. 3B illustrates a graph of an example direct current (DC) gain versus input common mode voltage VinCM of an input differential signal associated with the amplifier of FIG.3 A in accordance with another aspect of the disclosure.

[0013] FIG. 3C illustrates a graph of an example drain current (Id) versus drain-to-source voltage (Vds) associated with an output field effect transistor (FET) of the amplifier of FIG. 3A in accordance with another aspect of the disclosure.

[0014] FIG. 4A illustrates a schematic diagram of another example amplifier in accordance with another aspect of the disclosure.

[0015] FIG. 4B illustrates a graph of an example direct current (DC) gain versus input common mode voltage VinCM of an input differential signal associated with the amplifier of FIG.4A in accordance with another aspect of the disclosure.

[0016] FIG. 5 illustrates a schematic diagram of another example amplifier in accordance with another aspect of the disclosure.

[0017] FIG. 6 illustrates a schematic diagram of another example amplifier in accordance with another aspect of the disclosure.

[0018] FIG. 7 illustrates a schematic diagram of another example amplifier in accordance with another aspect of the disclosure.

[0019] FIG. 8 illustrates a schematic diagram of another example amplifier in accordance with another aspect of the disclosure.

[0020] FIG. 9 illustrates a schematic diagram of another example amplifier in accordance with another aspect of the disclosure.Qualcomm Ref. No. 2500510WO 4 / 27

[0021] FIG. 10 illustrates a flow diagram of an example method of amplifying an input differential signal to generate an output signal in accordance with another aspect of the disclosure.DETAILED DESCRIPTION

[0022] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts. The term “substantially” means that the associated parameter may not be exact as indicated but accounts for some variation due to specified tolerances.

[0023] FIG. 1 illustrates a block diagram of an example phase locked loop (PLL) 100 in accordance with an aspect of the disclosure. The PLL 100 serves as an example to which a low dropout (LDO) voltage regulator provides a regulated voltage. The PLL 100 includes a phase detector 110, a charge pump 120, a loop filter 130, a voltage controlled oscillator (VCO) 140, a buffer 150, and a frequency divider 160. Additionally, the PLL 100 includes a low dropout (LDO) voltage regulator 170.

[0024] The phase detector 110 is configured to generate a phase error signal A(|) based on a phase difference between a reference clock signal / REF and a feedback clock signal / FB. The charge pump 120 is configured to generate a current signal ICP based on the phase error signal A(|). The loop filter 130 is configured to filter (e.g., low pass filter) the current signal ICP to generate a frequency-control voltage signal VFC for the VCO 140. The VCO 140 is configured to generate a VCO clock signal fvco whose frequency is controlled by the frequency-control voltage signal VFC. The frequency divider 160 is configured to frequency divide the VCO clock signal fvco to generate the feedback clock signal / FB. The buffer 150 is configured to buffer the VCO clock signal fvco to generate an output clock fpLL of the PLL 100.Qualcomm Ref. No. 2500510WO 5 / 27

[0025] As shown, the LDO voltage regulator 170 is coupled between a power or voltage rail VDD and the VCO 140. The LDO voltage regulator 170 is configured to generate a regulated supply voltage Vvco for supplying power to the VCO 140. The LDO voltage regulator 170 may generate the regulated supply voltage Vvco based on a substantially temperature- stable reference voltage VREF (e.g., a bandgap voltage). The LDO voltage regulator 170 substantially isolates the VCO 140 from noise present on the voltage rail VDD (e.g., due to high speed and current demanding switching circuitry coupled to the voltage rail VDD). As a result, the VCO 140 is able to generate the VCO clock signal fvco with substantially less phase noise.

[0026] The PLL 100 may be used to provide the PLL clock signal fpi.i. for controlling the speed of operation of various circuits, such as one or more cores or sub-cores of a system on chip (SOC). In certain high-performance modes, such circuits may be operated at a relatively high speed, for example, to process data in a relatively fast manner. In certain low-performance modes (e.g., sleep or lower power), such circuits may be operated at a relatively low speed to consume less power while optionally performing some low speed operations. Accordingly, the frequency of the PLL clock signal fpi.i. may vary significantly between such high and low performance modes. And, as a consequence, the VCO supply voltage Vvco may be varied between relatively high voltage to relatively low voltage based on the high to low performance operation of the PLL 100, respectively.

[0027] FIG. 2 illustrates a schematic diagram of an example low dropout (LDO) voltage regulator 200 in accordance with another aspect of the disclosure. The LDO voltage regulator 200 may be an example implementation of the LDO 170 of PLL 100 previously discussed. The LDO voltage regulator 200 includes an amplifier (e.g., operational amplifier) 220 and a pass field effect transistor (FET) M0 (e.g., of a p-channel type, but could also be of an n-channel type).

[0028] The amplifier 220 includes a first (e.g., positive) input configured to receive a reference voltage VREF, a second (e.g., negative) input that may be coupled directly (as shown) (or indirectly via a resistor or voltage divider) to an output of the LDO voltage regulator 200, and an output coupled to a gate of the pass FET M0. The pass FET M0 is coupled between an upper voltage rail VDD and the output of the LDO voltage regulator 200. The VCO 290 (and / or other type of load) may be coupled between the output of the LDO voltage regulator 200 and a lower voltage rail (e.g., ground).

[0029] Via negative feedback, the amplifier 220 generates an output voltage VOUT to control (via the gate voltage of) the pass FET M0 such that the VCO supply voltage Vvco isQualcomm Ref. No. 2500510WO 6 / 27substantially equal to or related (based on the resistor or voltage divider) to the reference voltage VREF. AS previously discussed, the VCO supply voltage Vvco may vary significantly depending on the performance mode of the VCO 290. Accordingly, the input common mode voltage of an input differential signal (e.g., VREF / VVCO) of the amplifier 220 may likewise vary significantly to achieve the desired variation of the VCO supply voltage Vvco.

[0030] FIG. 3A illustrates a schematic diagram of an example amplifier 300 in accordance with another aspect of the disclosure. The amplifier 300 may be an example implementation of the amplifier 220 of the LDO voltage regulator 200. The amplifier 300 includes a folded cascode amplifier configuration including input differential n-channel field effect transistors (NFETs) MNP and MNN, a current source (or sink) NFET MNB, and an output circuit including current mirror p-channel field effect transistors (PFETs) MPOP and MPON, a pair of cascode PFETs MCPP and MCPN, a pair of cascode NFETs MCNP and MCNN, and a pair of current source (or sink) NFETs MNOP and MNON.

[0031] The current mirror PFETs MPOP and MPON include sources coupled to an upper voltage rail VDD, gates coupled together, and drains coupled to drains of the input differential NFETs MNP and MNN, respectively. The input differential NFETs MNP and MNN include gates configured to receive a positive component VINP and a negative component VINN of an input differential signal VINP / VINN, respectively. The input differential NFETs MNP and MNN include sources coupled to a drain of current source NFET MNB. The current source NFET MNB includes a gate configured to receive an NFET current source bias voltage VBIASN for setting / controlling a substantially constant current through the current source NFET MNB, and a source coupled to a lower voltage rail (e.g., ground).

[0032] The cascode PFETs MCPP and MCPN include sources coupled to drains of the current mirror PFETs MPOP and MPON, respectively. The cascode PFETs MCPP and MCPN include gates configured to receive a PFET cascode bias voltage VCASP. The cascode PFETs MCPP and MCPN include drains coupled to drains of the cascode NFETs MCNP and MCNN, respectively. The coupled-together drains of cascode FETs MCPP and MCNP may be coupled to the gates of the current mirror PFETs MPOP and MPON. The output of the amplifier 300 may be taken off the coupled-together drains of the cascode FETs MCPN and MCNN, respectively. The output of the amplifier 300 is configured to produce the output signal VOUT (e.g., for driving the gate of the pass FET M0 of the LDO voltage regulator 200).Qualcomm Ref. No. 2500510WO 7 / 27

[0033] The cascode NFETs MCNP and MCNN include gates configured to receive a NFET cascode bias voltage VCASN. The cascode NFETs MCNP and MCNN include sources coupled to drains of the NFET current source NFETs MNOP and MNON, respectively. The NFET current source NFETs MNOP and MNON include gates coupled to the gate of the current source NFET MNB to also receive the NFET current source bias voltage VBIASN. Similarly, the NFET current source bias voltage VBIASN configures the NFET current source NFETs MNOP and MNON to generate a substantially constant current. The NFET current source NFETs MNOP and MNON include sources coupled to the lower voltage rail (e.g., ground).

[0034] If the input differential signal VINP / VINN has a relatively high common mode voltage level, the input differential NFETs MNP and MNN are significantly turned on (e.g., the voltage drop across them is relatively small) to produce a drain voltage for the current source NFET MNB that is high enough for it operate in the saturation region and serve as an effective current source for the input differential NFETs MNP and MNN. If, on the other hand, the input differential signal VINP / VINN has a relatively low common mode voltage level, the input differential NFETs MNP and MNN are not significantly turned on (e.g., the voltage drop across them is relatively large), which causes the drain voltage for the current source NFET MNB to be relatively low such that it operates in the triode region. In such case, the current source NFET MNB collapses and stops operating as an effective current source; thereby, adversely impacting the operation of the amplifier 300.

[0035] Accordingly, to deal with a wide input common mode voltage swing (e.g., low and high), the amplifier 300 further includes a pair of input differential PFETs Mpp and MPN and related circuitry. More specifically, the amplifier 300 includes a current source PFET MPB, the pair of input differential PFETs Mpp and MPN, and a pair of current source (or sink) NFETs MNPB and MNNB. The current source PFET MPB includes a source coupled to the upper voltage rail VDD, a gate configured to receive a PFET current source bias voltage VBIASP, and a drain coupled to sources of the input differential PFETs Mpp and MPN, respectively. The input differential PFETs Mpp and MPN include gates configured to receive the positive component VINP and the negative component VINN of the input differential signal VINP / VINN, respectively.

[0036] The input differential PFETs Mpp and MPN include drains coupled to drains of the current source NFETs MNPB and MNNB, respectively. The current source NFETs MNPB and MNNB include gates coupled to gates of current source NFETs MNB, MNOP, and MNON to also receive the NFET current source bias voltage VBIASN. Similarly, the NFET current sourceQualcomm Ref. No. 2500510WO 8 / 27bias voltage VBIASN configures each of the current source NFETs MNPB and MNNB to generate a substantially constant current. The current source NFETs MNPB and MNNB include sources coupled to the lower voltage rail (e.g., ground). The sources of the cascode NFETs MCNP and MCNN of the output circuit are also coupled to the drains of the current source NFETs MNPB and MNNB, respectively. The operation of the amplifier 300 is explained as follows.

[0037] FIG. 3B illustrates a graph of an example direct current (DC) gain versus input common mode voltage VinCM of the input differential signal VINP / VINN associated with the amplifier 300 in accordance with another aspect of the disclosure. The horizontal axis of the graph represents the input common mode voltage VinCM in Volt (V) ranging from 0.0V to 0.7V. The vertical axis of the graph represents the DC gain of the amplifier 300 (e.g., DC gain=Voui7VinCM) ranging from zero (0) decibel (dB) to 60dB.

[0038] The graph depicts the DC gain versus input common mode voltage VinCM response of the amplifier 300 (represented as a short-dashed line) if the input differential PFETs Mpp and MPN and related circuitry were not present in the amplifier 300 (e.g., only the input differential NFETs MNP / MNN). AS the graph illustrates, and as previously discussed, if the input common mode voltage VinCM is relatively high (e.g., at or above 0.2V), the amplifier 300 has a relatively high DC gain (e.g., about 45dB to 50dB). This is because the input differential NFETs MNP / MNN are sufficiently turned on to provide a sufficient drain voltage for the current source NFET MNB to allow it to operate in the saturation region and effectively as a current source. If the input common mode voltage VinCM is relatively low (e.g., below 0.2V), the amplifier 300 has a relatively low DC gain (e.g., about lOdB to 40dB). This is because the input differential NFETs MNP / MNN are sufficiently turned off to produce a significant voltage drop across them that results in a lower drain voltage of the current source NFET MNB. This causes the current source NFET MNB to operate in the triode region, where it no longer operates effectively as a current source.

[0039] The graph also depicts the DC gain versus input common mode voltage VinCM response of the amplifier 300 (represented as a long-dashed line) if the input differential PFETs Mpp and MPN and related circuitry were present in the amplifier 300 (e.g., both the input differential NFETs MNP / MNN and PFETs MPP / MPN are present). As the graph illustrates, if the input common mode voltage VinCM is relatively low (e.g., below 0.3V), the amplifier 300 has a relatively high DC gain (e.g., about 50dB to 55dB) due to the input differential PFETs Mpp and MPN being turned on sufficiently to produce a sufficiently lowQualcomm Ref. No. 2500510WO 9 / 27drain voltage for the current source PFET MPB to allow it to operate in the saturation region and effectively as a current source. If the input common mode voltage VinCM is relatively high (e.g., at or above 0.3V), the amplifier 300 has a relatively high DC gain (e.g., about 42dB to 50dB). This is because, as previously discussed, the input differential NFETs MNP / MNN are sufficiently turned on to provide a sufficient drain voltage for the current source NFET MNB to allow it to operate in the saturation region and effectively as a current source.

[0040] However, as the graph also illustrates, the DC gain of the amplifier 300 drops by about lOdB above an input common mode voltage VinCM increases of 0.3V, with a total DC gain variation of 15dB across the input common mode voltage VinCM range of 0.1V to 0.6V. This is due to the effects the input differential PFETs MPP / MPN have on the output circuit when they are effectively turned off due to a high input common mode voltage VinCM. That is, when the input differential PFETs MPP / MPN are effectively turned off due to a relatively high input common mode voltage VinCM, the current through the input differential PFETs MPP / MPN reduces or is substantially nil. The current source NFETs MNPB and MNNB, being biased for sourcing a substantially constant current, pull currents I from the output circuit to maintain the constant current. The current source NFETs MNPB and MNNB pulling current I from the output circuit increases the current or current density through the output cascode FETs MCPP, MCPN, MCNP, and MCNN. AS discussed in more detail as follows, the increase in the current or current density in the output cascode FETs MCPP, MCPN, MCNP, and MCNN reduces the DC gain of the amplifier 300.

[0041] FIG. 3C illustrates a graph of an example drain current (Id) versus drain-to-source voltage (Vds) associated with an output field effect transistor (FET) (e.g., MCPP, MCPN, MCNP, and MCNN) of the amplifier 300 in accordance with another aspect of the disclosure. The horizontal axis of the graph represents the drain-to-source voltage Vds of the output FET, and the vertical axis of the graph represents the drain current Ids of the output FET.

[0042] The graph includes two (2) drain current Id versus drain-to-source voltage Vds responses of the output FET for different drain current or current densities Idi and kb. In the saturation region, where the output FET operates, the output resistance Rout associated with the output FET is inversely related to the slope of the Id-Vds responses. For the lower drain current or current density Idi, the slope of the Id-Vds response in the saturation region is relatively small. For the higher drain current or current density kb, the slope of the Id-Vds response in the saturation region is relatively high. Accordingly, as the output resistance Rout is inversely related to the slope of the Id-Vds response, theQualcomm Ref. No. 2500510WO 10 / 27output resistance Rout2 associated with the higher current density kb is less than the output resistance Routi associated with the lower current density Idi (e.g., Rout2<Routi).

[0043] As the DC gain of the amplifier 300 is related to the transconductance gain gm of the output FET multiplied by its output resistance Rout (e.g., DC gain=gm*Rout), the lower Rout2 associated with the higher current density kb results in a lower DC gain. Accordingly, with reference again to FIG. 3A, the current I pulling by the current source NFETs MNPB and MNNB when the input common mode voltage VinCM is relatively high (e.g., above 0.3V) causes the current density in the output cascode FETs MCPP, MCPN, MCNP, and MCNN to increase, which results in their output resistance Rout to decrease, which, in turn, results in a lowering of the DC gain of the amplifier 300 (e.g., by lOdB as the input common mode voltage VinCM increases from 0.3V to 0.6V, as shown in FIG.3B).

[0044] FIG. 4A illustrates a schematic diagram of another example amplifier 400 in accordance with another aspect of the disclosure. The amplifier 400 may also be an example implementation of the amplifier 220 of the EDO voltage regulator 200. The amplifier 400 is similar to amplifier 300 and includes many of the same / similar elements as indicated by the same reference identifiers.

[0045] The amplifier 400 differs from amplifier 300 in a couple of manners: (1) the gates of the current source NFETs MNPB and MNNB are no longer coupled to the gates of the current source NFETs MNB, MNOP, and MNON; and thereby, do not receive and are not controlled by the NFET current source bias voltage VBIASN; and (2) the amplifier 400 further includes a control circuit 410 including an input coupled to and configured to sense the bias current IBIASP flowing through the current source PFET MPB, and an output coupled to the gates of the current source NFETs MNPB and MNNB.

[0046] The control circuit 410 is configured to control currents Ii and I2 flowing through the current source NFETs MNPB and MNNB (via a control gate voltage Vccs) based on the bias current IBIASP flowing through the current source PFET MPB (e.g., where the currents Ii and I2 flowing through the current source NFETs MNPB and MNNB are substantially equal to each other, and their sum is substantially equal to the bias current IBIASP flowing through the current source PFET MPB (e.g., II=I2=IBIASP / 2->II+I2=IBIASP). In such case, when the input common mode voltage VinCM is relatively high, and the bias current IBIASP flowing through the current source PFET MPB and into the input differential PFETs Mpp fand MPN is relatively small, the control circuit 410 generates the control voltage Vccs so that the currents Ii and I2 flowing through the current source NFETs MNPB and MNNB track theQualcomm Ref. No. 2500510WO 11 / 27bias current IBIASP. AS a result, the current source NFETs MNPB and MNNB do not substantially pull any current from the output FETs MCPP, MCPN, MCNP, and MCNN SO as not to substantially affect the output resistance Rout; and therefore, the DC gain of the amplifier 400.

[0047] FIG. 4B illustrates a graph of an example direct current (DC) gain versus input common mode voltage VinCM of the input differential signal VINP / VINN associated with the amplifier 400 in accordance with another aspect of the disclosure. The graph is substantially the same as the graph depicted in FIG. 3B except that it further includes the DC gain versus VinCM response associated with the amplifier 400 as shown as a solid line. As shown, the DC gain versus VinCM response is substantially constant over a wide range of VinCM (e.g., from less than 0.1V to 0.6V) only varying by about 5dB due to the current source NFETs MNPB and MNNB not drawing substantially any current from the output circuit (e.g., FETs MCPP, MCPN, MCNP, and MCNN).

[0048] FIG. 5 illustrates a schematic diagram of another example amplifier 500 in accordance with another aspect of the disclosure. The amplifier 500 may be another example implementation of the amplifier 220 of the EDO voltage regulator 200. The amplifier 500 is similar to amplifier 400 and includes many of the same / similar elements as indicated by the same reference identifiers. The amplifier 500 provides an example implementation of the control circuit 410 of amplifier 400.

[0049] In particular, the amplifier 500 includes a control circuit 510 including a replica current source PFET MRPB, a replica input PFET MRP, and a replica (diode-connected) current source NFET MRNB coupled in series between the upper voltage rail VDD and the lower voltage rail (e.g., ground). More specifically, the replica current source PFET MRPB includes a source coupled to the upper voltage rail VDD, a gate coupled to the gate of the current source PFET MPB, and a drain coupled to a source of the replica input PFET MRP. The replica input PFET MRP includes a gate configured to receive a replica input voltage VRIN, and a drain coupled to the drain / gate of the replica (diode-connected) current source NFET MRNB. The drain / gate of the replica (diode-connected) current source NFET MRNB is coupled to the gates of the current source NFETs MNPB and MNNB. The replica (diode- connected) current source NFET MRNB includes a source coupled to the lower voltage rail (e.g., ground).

[0050] The current source PFET MPB and replica current source PFET MRPB form a current mirror to generate a replica bias current IBIASRP based on the bias current IBIASP. For example, the channel width to channel length ratio (W / E) of the current source PFET MPBQualcomm Ref. No. 2500510WO 12 / 27may be substantially 2J times larger than the W / L of the replica current source PFET MRPB. In such case, the replica bias current IBIASRP is substantially equal to 1 / 2J*IBIASP (e.g., the current mirror has a current gain of 1 / 2J). The replica input voltage VRIN may be the positive component VINP of the input differential signal VINP / VINN, the negative component VINN of the input differential signal VINP / VINN, or substantially the common mode voltage VinCM associated with the input differential signal VINP / VINN (e.g., VinCM=(ViNP+ViNN) / 2).

[0051] The replica (diode-connected) current source NFET MRNB and the current source NFETs MNPB and MNNB also form a current mirror to generate currents Ii and I2 based on the replica bias current IBIASRP. The W / L of each of the current source NFETs MNPB and MNNB may be substantially J times larger than the W / L of the replica (diode-connected) current source NFET MRNB. In such case, the currents Ii and I2 are each substantially equal to 1 / J*IBIASRP (e.g., the current mirror has a current gain of J). Accordingly, based on the aforementioned current mirror configurations, the currents Ii and I2 are each substantially equal to IBIASP / 2 (e.g., II=I2=J*IBIASRP=J*(1 / 2J*IBIASP)=IBIASP / 2). AS discussed with reference to amplifier 400, the currents Ii and I2 tracking the bias current IBIASP cause the current source NFETs MNPB and MNNB to not substantially pull any current from the output FETs MCPP, MCPN, MCNP, and MCNN SO as not to substantially affect the output resistance Rout; and therefore, the DC gain of the amplifier 500.

[0052] FIG. 6 illustrates a schematic diagram of another example amplifier 600 in accordance with another aspect of the disclosure. The amplifier 600 may be another example implementation of the amplifier 220 of the LDO voltage regulator 200. The amplifier 600 is similar to amplifier 500 and includes many of the same / similar elements as indicated by the same reference identifiers. The amplifier 600 provides another example implementation of the control circuit 410 of amplifier 400.

[0053] In particular, the amplifier 600 includes a control circuit 610 similar to control circuit 510 including the replica current source PFET MRPB, the replica input PFET MRP, and the replica (diode-connected) current source NFET MRN in a similar arrangement. The control circuit 610 differs from control circuit 510 in that it further includes an operational amplifier 620 including a first (e.g., positive) input coupled to the drain of the current source PFET MPB (as well as the sources of the input differential PFETs Mpp and MPN), a second (e.g., negative) input coupled to the drain of the replica current source PFET MRPB (as well as the source of the replica input PFET MRP), and an output coupled to the gate of the replica input PFET MRPB.Qualcomm Ref. No. 2500510WO 13 / 27

[0054] Through negative feedback, the operational amplifier 620 provides a gate voltage for the replica input PFET MRP to substantially force the drain voltage of the replica current source PFET MRPB (as well as the source of the replica input PFET MRP) to be substantially equal to the drain voltage of the current source PFET MPB (as well as the source voltages of the input differential PFETs Mpp and MPN). This ensures that the replica PFETs MRPB and MRP are biased substantially the same as the PFETs MPB and MPP / MPN to achieve a more accurate current generation of the replica current IBIASRP based on the PFET bias current IBIASP. Besides the operational amplifier 620, the operation of the control circuit 610 is substantially the same as the control circuit 510 as previously discussed.

[0055] FIG. 7 illustrates a schematic diagram of another example amplifier 700 in accordance with another aspect of the disclosure. The amplifier 700 may also be an example implementation of the amplifier 220 of the LDO voltage regulator 200. The amplifier 700 is an inverted version (e.g., corresponding PFETs become NFETs, and corresponding NFETs become PFETs) of the amplifier 400.

[0056] In particular, the amplifier 700 includes a current source PFET MPB including a source coupled to the upper voltage rail VDD, a gate configured to receive a PFET current source bias voltage VBIASP, and a drain coupled to sources of a pair of input differential PFETs Mpp and MPN, respectively. The PFET current source bias voltage VBIASP configures the current source PFET MPB to generate a substantially constant current. The input differential PFETs Mpp and MPN include gates configured to receive a positive component VINP and a negative component VINN of an input differential signal VINP / VINN, respectively. The input differential PFETs Mpp and MPN include drains coupled to drains of a pair of current source (or sink) NFETs MNOP and MNON of the output circuit of the amplifier 700, respectively.

[0057] The amplifier 700 includes an output circuit including a pair of current source PFETs MPOP and MPON including respective sources coupled to the upper voltage rail VDD, gates coupled to the gate of current source PFET MPB to also receive the PFET current source bias voltage VBIASP, and drains coupled to sources of a pair of cascode PFETs MCPP and MCPN, respectively. The PFET current source bias voltage VBIASP also configures each of the current source PFETs MPOP and MPON to generate a substantially constant current. The cascode PFETs MCPP and MCPN include gates configured to receive a PFET cascode bias voltage VCASP. The cascode PFETs MCPP and MCPN include drains coupled to drains of a pair of cascode NFETs MCNP and MCNN, respectively. The drains of cascode FETsQualcomm Ref. No. 2500510WO 14 / 27MCPP and MCNP are coupled to gates of the current source NFETs MNOP and MNON. The drains of cascode FETs MCPN and MCNN may serve as the amplifier’s 700 output to generate the output voltage VOUT. The cascode NFETs MCNP and MCNN include gates configured to receive an NFET cascode bias voltage VCASN. The cascode NFETs MCNP and MCNN include sources coupled to the drains of current source NFETs MNOP and MNON, respectively. The current source NFETs MNOP and MNON include sources coupled to a lower voltage rail (e.g., ground).

[0058] The amplifier 700 further includes a pair of current source PFETs MPPB and MPNB including sources coupled to the upper voltage rail VDD, gates coupled to an output of a control circuit 710 to receive a gate control voltage Vccs, and drains coupled to drains of a pair of input differential NFETs MNP and MNN, respectively. The input differential NFETs MNP and MNN include gates configured to receive the positive component VINP and the negative component VINN of the input differential signal VINP / VINN, respectively. The input differential NFETs MNP and MNN include sources coupled to a source of current source NFET MNB. The current source NFET MNB includes a gate configured to receive an NFET current source bias voltage VBIASN, and a source coupled to the lower voltage rail (e.g., ground). The sources of cascode PFETs MCPP and MCPN of output circuit are coupled to the drains of current source PFETs MPPB and MPNB, respectively. The control circuit 710 includes an input coupled to and configured to sense the bias current IBIASN through the NFET current source MNB.

[0059] In the case of amplifier 700, if the control circuit 710 were not present and the gates of the current source PFETs MPPB and MPNB were coupled to the gates of current source PFETs MPB, MPOP, and MPON, the current source PFETs MPPB and MPNB would supply current to the output FETs MCPP, MCPN, MCNP and MCNN when the input common mode voltage VinCM associated with the input differential signal VINP / VINN is relatively low so as to collapse the current source NFET MNB. AS previously discussed, the higher current through the output FETs MCPP, MCPN, MCNP and MCNN causes the output resistance Rout to decrease; and consequently, the DC gain of the amplifier 700 to decrease, as previously discussed.

[0060] Thus, similarly, as discussed with reference to amplifier 400, the control circuit 710 is configured to sense the bias current IBIASN flowing through the current source NFET MNB, and generate the gate control voltage Vccs for the current source PFETs MPPB and MPNB so that it generates currents Ii and I2 that tracks or are based on the bias current IBIASN. Thus, when the input common mode voltage VinCM is relatively low, and consequently,Qualcomm Ref. No. 2500510WO 15 / 27the bias current IBIASN is relatively low, the control circuit 710 is configured to generate the gate control voltage Vccs to cause the current source PFETs MPPB to MPNB to reduce its currents Ii and I2 so that it does not end up flowing to the output circuit of the amplifier 700; and thus, the DC gain of the amplifier 700 remains substantially constant over a wide range of the input common mode voltage VinCM.

[0061] FIG. 8 illustrates a schematic diagram of another example amplifier 800 in accordance with another aspect of the disclosure. The amplifier 800 may be another example implementation of the amplifier 220 of the LDO voltage regulator 200. The amplifier 800 is similar to amplifier 700 and includes many of the same / similar elements as indicated by the same reference identifiers. The amplifier 800 provides an example implementation of the control circuit 710 of amplifier 700.

[0062] In particular, the amplifier 800 includes a control circuit 810 including a replica (diode- connected) current source PFET MRPB, a replica input NFET MRN, and a replica current source NFET MRNB, all coupled in series between the upper voltage rail VDD and the lower voltage rail (e.g., ground). More specifically, the replica (diode-connected) current source PFET MRPB includes a source coupled to the upper voltage rail VDD, a gate and a drain coupled to the gates of the current source PFETs MPPB and MPNB, as well as to a source of the replica input NFET MRN. The replica input NFET MRNB includes a gate configured to receive a replica input voltage VRIN, and a source coupled to a drain of the replica current source NFET MRNB. The replica current source NFET MRNB includes a gate coupled to the gate of the current source NFET MNB to receive the NFET current source bias voltage VBIASN. The replica current source NFET MRNB includes a source coupled to the lower voltage rail (e.g., ground).

[0063] The current source NFET MNB and replica current source NFET MRNB form a current mirror to generate a replica bias current IBIASRN based on the bias current IBIASN. For example, the W / E of the current source NFET MNB may be substantially 2J times larger than the W / E of the replica current source NFET MRNB. In such case, the replica bias current IBIASRN is substantially equal to 1 / 2J*IBIASN (e.g., the current mirror has a current gain of 1 / 2J). The replica input voltage VRIN may be the positive component VINP of the input differential signal VINP / VINN, the negative component VINN of the input differential signal VINP / VINN, or substantially the common mode voltage VinCM associated with the input differential signal VINP / VINN (e.g., VinCM=(ViNP+ViNN) / 2).

[0064] The replica (diode-connected) current source PFET MRPB and the current source PFETs MPPB and MPNB also form a current mirror to generate currents Ii and I2 based on theQualcomm Ref. No. 2500510WO 16 / 27replica bias current IBIASRN. The W / L of each of the current source PFETs MPPB and MPNB may be substantially J times larger than the W / L of the replica (diode-connected) current source PFET MRPB. In such case, the currents Ii and I2 are each substantially equal to 1 / J*IBIASRN (e.g., the current mirror has a current gain of J). Accordingly, based on the aforementioned current mirror configurations, the currents Ii and I2 are each substantially equal to IBIASN / 2 (e.g., II=I2=J*IBIASRN=J*(1 / 2J*IBIASN)=IBIASN / 2). AS discussed with reference to amplifier 700, the currents Ii and I2 tracking the bias current IBIASN causes the current source PFETs MPPB and MPNB to not substantially provide any current to the output FETs MCPP, MCPN, MCNP, and MCNN SO as not to substantially affect the output resistance Rout; and therefore, the DC gain of the amplifier 800.

[0065] FIG. 9 illustrates a schematic diagram of another example amplifier 900 in accordance with another aspect of the disclosure. The amplifier 900 may be another example implementation of the amplifier 220 of the LDO voltage regulator 200. The amplifier 900 is similar to amplifier 800 and includes many of the same / similar elements as indicated by the same reference identifiers. The amplifier 900 provides another example implementation of the control circuit 710 of amplifier 700.

[0066] In particular, the amplifier 900 includes a control circuit 910 similar to control circuit 810 including the replica (diode-connected) current source PFET MRPB, the replica input NFET MRN, and the replica current source NFET MRNB in a similar arrangement. The control circuit 910 differs from control circuit 810 in that it further includes an operational amplifier 920 including a first (e.g., positive) input coupled to the drain of the current source NFET MNB (as well as the sources of the input differential NFETs MNP and MNN), a second (e.g., negative) input coupled to the drain of the replica current source NFET MRNB (as well as the source of the replica input NFET MRN), and an output coupled to the gate of the replica input NFET MRN.

[0067] Through negative feedback, the operational amplifier 920 provides a gate voltage for the replica input NFET MRN to substantially force the drain voltage of the replica current source NFET MRNB (as well as the source voltage of the replica input NFET MRN) to be substantially equal to the drain voltage of the current source NFET MNB (as well as the source voltages of the input differential NFETs MNP and MNN). This ensures that the replica NFETs MRN and MRNB are biased substantially the same as the NFETs MNB and MNP / MNN to achieve a more accurate current generation of the replica current IBIASRN based on the PFET bias current IBIASN. Besides the operational amplifier 920, theQualcomm Ref. No. 2500510WO 17 / 27operation of the control circuit 910 is substantially the same as the control circuit 810 as previously discussed.

[0068] FIG. 10 illustrates a flow diagram of an example method 1000 of amplifying an input differential signal to generate an output signal in accordance with another aspect of the disclosure. The method 1000 includes amplifying an input differential signal using a first pair of input differential field effect transistor (FETs) to generate an output signal at an output circuit (block 1010). Examples of the first pair of input differential FETs include any of the input differential NFETs MNP / MNN of amplifiers 400, 500, and 600 or input differential PFETs MPP / MPN of amplifiers 700, 800, and 900.

[0069] The method 1000 further includes amplifying the input differential signal using a second pair of input differential FETs to generate the output signal at the output circuit (block 1020). Examples of the second pair of input differential FETs include any of the input differential PFETs MPP / MPN of amplifiers 400, 500, and 600 or input differential NFETs MNP / MNN of amplifiers 700, 800, and 900. Additionally, the method 1000 includes sensing a current flowing into or out of the second pair of input differential FETs from or to a first current source, respectively (block 1030). Examples of means for sensing a current flowing into or out of the second pair of input differential FETs from or to a first current source, respectively, include any of the control circuits 410, 510, 610, 710, 810, or 910.

[0070] The method 1000 also includes controlling a pair of currents flowing out of or into the first pair of input differential FETs and into or out of a first pair of current sources based on the sensed current, respectively, to reduce currents flowing through the output circuit to or from the first pair of current sources. Examples of means for controlling a pair of currents flowing out of or into the first pair of input differential FETs and into or out of a first pair of current sources based on the sensed current include any of the control circuits 410, 510, 610, 710, 810, or 910.

[0071] The following provides an overview of aspects of the present disclosure:

[0072] Aspect 1: An amplifier, comprising: an output circuit; a pair of input differential n- channel field effect transistors (NFETs) including drains coupled to the output circuit, and gates configured to receive positive and negative components of an input differential signal, respectively; a current source NFET including a drain coupled to sources of the input differential NFETs, and a gate coupled to the output circuit and configured to receive a first bias voltage; a current source p-channel field effect transistor (PFET) including a gate configured to receive a second bias voltage; a pair of input differentialQualcomm Ref. No. 2500510WO 18 / 27PFETs including sources coupled to a drain of the current source PFET, and gates configured to receive the positive and negative components of the input differential signal, respectively; a first pair of current source NFETs including drains coupled to the output circuit and to drains of the input differential PFETs, respectively; and a control circuit including an input coupled to the current source PFET and an output coupled to gates of the first pair of current source NFETs, respectively.

[0073] Aspect 2: The amplifier of aspect 1, wherein the control circuit includes: a replica current source PFET including a gate coupled to the gate of the current source PFET; a replica input PFET including a source coupled to a drain of the replica current source PFET, a gate configured to receive a replica input signal; and a replica current source NFET including a drain and a gate coupled to a drain of the replica input PFET and to gates of the first pair of current source NFETs.

[0074] Aspect 3: The amplifier of aspect 2, wherein the replica input PFET includes a gate configured to receive a replica input signal, the replica input signal being substantially the same as the positive component of the input differential signal, the negative component of the input differential signal, or a common mode voltage associated with the input differential signal.

[0075] Aspect 4: The amplifier of aspect 2 or 3, wherein: a channel width to channel length ratio (W / E) of the current source PFET is substantially J times greater than a W / L of the replica current source PFET; and a W / L of each of the first pair of the current source NFETs is substantially J times greater than a W / L of the replica current source NFET.

[0076] Aspect 5: The amplifier of any one of aspects 2-4, wherein the control circuit further comprises an operational amplifier including a first input coupled to the drain of the current source PFET, a second input coupled to the drain of the replica current source PFET, and an output coupled to a gate of the replica input PFET.

[0077] Aspect 6: The amplifier of any one of aspects 1-5, wherein the output circuit comprises:a pair of cascode PFETs including sources coupled to the drains of the pair of input differential NFETs, respectively, wherein the pair of cascode PFETs include gates configured to receive a first cascode bias voltage; and a pair of cascode NFETs including drains coupled to drains of the pair of cascode PFETs, wherein the pair of cascode NFETs include gates configured to receive a second cascode bias voltage, and wherein the pair of cascode NFETs include sources coupled to the drains of the first pair of current source NFETs, respectively.Qualcomm Ref. No. 2500510WO 19 / 27

[0078] Aspect 7: The amplifier of aspect 6, wherein the output circuit further comprises: a pair of current mirror PFETs including drains coupled to sources of the pair of cascode PFETs, respectively, wherein the pair of current mirror PFETs include gates coupled to the drains of one of the pair of cascode PFETs and one of the pair of cascode NFETs, respectively, wherein the drains of another of the pair of cascode PFETs and another of the pair of cascode NFETs serve as an output of the amplifier; and a second pair of current source NFETs including gates coupled to the gate of the current source NFET, wherein the second pair of current source NFETs include drains coupled to sources of the pair of cascode NFETs, respectively.

[0079] Aspect 8: An amplifier, comprising: an output circuit; a current source p-channel field effect transistor (PFET) including a gate coupled to the output circuit and configured to receive a first bias voltage; a pair of input differential PFETs including sources coupled to a drain of the current source PFET, drains coupled to the output circuit, and gates configured to receive positive and negative components of an input differential signal, respectively; a first pair of current source PFETs; a pair of input differential n-channel field effect transistors (NFETs) including drains coupled to the output circuit and to drains of the first pair of current source PFETs, respectively, and gates configured to receive the positive and negative components of the input differential signal, respectively; a current source NFET including a gate configured to receive a second bias voltage, and a drain coupled to sources of the pair of input differential NFETs, respectively; and a control circuit including an input coupled to the current source NFET and an output coupled to gates of the first pair of current source PFETs, respectively.

[0080] Aspect 9: The amplifier of aspect 8, wherein the control circuit includes: a replica current source PFET including a gate and a drain coupled to the gates of the first pair of current source PFETs; a replica input NFET including a drain coupled to the drain and the gate of the replica current source PFET; and a replica current source NFET including a drain coupled to a source of the replica input NFET and to a gate coupled to the gate of the current source NFET.

[0081] Aspect 10: The amplifier of aspect 9, wherein the replica input NFET includes a gate configured to receive a replica input signal, the replica input signal being substantially the same as the positive component of the input differential signal, the negative component of the input differential signal, or a common mode voltage associated with the input differential signal.Qualcomm Ref. No. 2500510WO 20 / 27

[0082] Aspect 11: The amplifier of aspect 9 or 10, wherein: a channel width to channel length ratio (W / L) of the current source NFET is substantially J times greater than a W / L of the replica current source NFET; and a W / L of each of the first pair of the current source PFETs is substantially J times greater than a W / L of the replica current source PFET.

[0083] Aspect 12: The amplifier of any one of aspects 9-11, wherein the control circuit further comprises an operational amplifier including a first input coupled to the drain of the current source NFET, a second input coupled to the drain of the replica current source NFET, and an output coupled to a gate of the replica input NFET.

[0084] Aspect 13: The amplifier of any one of aspects 8-12, wherein the output circuit comprises:a pair of cascode PFETs including sources coupled to the drains of the first pair of current source PFETs, respectively, wherein the pair of cascode PFETs include gates configured to receive a first cascode bias voltage; and a pair of cascode NFETs including drains coupled to drains of the pair of cascode PFETs, wherein the pair of cascode NFETs include gates configured to receive a second cascode bias voltage, and wherein the pair of cascode NFETs include sources coupled to the drains of the pair of input differential NFETs, respectively.

[0085] Aspect 14: The amplifier of aspect 13, wherein the output circuit further comprises: a second pair of current source PFETs including gates coupled to the gate of the current source PFET, wherein the second pair of current source PFETs include drains coupled to sources of the pair of cascode PFETs, respectively; and a pair of current mirror NFETs including drains coupled to sources of the pair of cascode NFETs, respectively, wherein the pair of current mirror NFETs include gates coupled to the drains of one of the pair of cascode PFETs and one of the pair of cascode NFETs, respectively, wherein the drains of another of the pair of cascode PFETs and another of the pair of cascode NFETs serve as an output of the amplifier.

[0086] Aspect 15: A method, comprising: amplifying an input differential signal using a first pair of input differential field effect transistor (FETs) to generate an output signal at an output circuit; amplifying the input differential signal using a second pair of input differential FETs to generate the output signal at the output circuit; sensing a current flowing into or out of the second pair of input differential FETs from or to a first current source, respectively; and controlling a pair of currents flowing out of or into the first pair of input differential FETs and into or out of a first pair of current sources based on the sensed current, respectively, to reduce currents flowing through the output circuit to or from the first pair of current sources.Qualcomm Ref. No. 2500510WO 21 / 27

[0087] Aspect 16: The method of aspect 15, wherein sensing the current flowing into or out of the second pair of input differential FETs comprises: generating a replica current based on the current; and generating a gate control voltage for the first pair of current sources based on the replica current.

[0088] Aspect 17: The method of aspect 16, wherein: the current is substantially 2J times greater than the replica current; and each of the pair of currents is substantially J times greater than the replica current.

[0089] Aspect 18: The method of aspect 16 or 17, further comprising: routing the replica current through a replica input FET; and providing a replica input signal to a gate of the replica input FET, wherein the replica input signal is substantially the same as a positive component of the input differential signal, a negative component of the input differential signal, or a common mode voltage associated with the input differential signal.

[0090] Aspect 19: The method of aspect 16 or 17, further comprising: routing the replica current through a replica input FET; and generating a gate voltage for the replica input FET based on a first voltage at sources of the second pair of input differential FETs and a second voltage at a source of the replica input FET.

[0091] Aspect 20: The method of any one of aspects 15-19, further comprising providing a substantially constant current from or to the output circuit.

[0092] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

Qualcomm Ref. No. 2500510WO 22 / 27CLAIMS WHAT IS CLAIMED:

1. An amplifier, comprising:an output circuit;a pair of input differential n-channel field effect transistors (NFETs) including drains coupled to the output circuit, and gates configured to receive positive and negative components of an input differential signal, respectively;a current source NFET including a drain coupled to sources of the input differential NFETs, and a gate coupled to the output circuit and configured to receive a first bias voltage;a current source p-channel field effect transistor (PFET) including a gate configured to receive a second bias voltage;a pair of input differential PFETs including sources coupled to a drain of the current source PFET, and gates configured to receive the positive and negative components of the input differential signal, respectively;a first pair of current source NFETs including drains coupled to the output circuit and to drains of the input differential PFETs, respectively; anda control circuit including an input coupled to the current source PFET and an output coupled to gates of the first pair of current source NFETs.

2. The amplifier of claim 1, wherein the control circuit includes:a replica current source PFET including a gate coupled to the gate of the current source PFET;a replica input PFET including a source coupled to a drain of the replica current source PFET; anda replica current source NFET including a drain and a gate coupled to a drain of the replica input PFET and to gates of the first pair of current source NFETs.

3. The amplifier of claim 2, wherein the replica input PFET includes a gate configured to receive a replica input signal, the replica input signal being substantially the same as the positive component of the input differential signal, the negative component of the input differential signal, or a common mode voltage associated with the input differential signal.Qualcomm Ref. No. 2500510WO 23 / 274. The amplifier of claim 2, wherein:a channel width to channel length ratio (W / L) of the current source PFET is substantially 2 J times greater than a W / L of the replica current source PFET; anda W / L of each of the first pair of the current source NFETs is substantially J times greater than a W / L of the replica current source NFET.

5. The amplifier of claim 2, wherein the control circuit further comprises an operational amplifier including a first input coupled to the drain of the current source PFET, a second input coupled to the drain of the replica current source PFET, and an output coupled to a gate of the replica input PFET.

6. The amplifier of claim 1, wherein the output circuit comprises:a pair of cascode PFETs including sources coupled to the drains of the pair of input differential NFETs, respectively, wherein the pair of cascode PFETs include gates configured to receive a first cascode bias voltage; anda pair of cascode NFETs including drains coupled to drains of the pair of cascode PFETs, wherein the pair of cascode NFETs include gates configured to receive a second cascode bias voltage, and wherein the pair of cascode NFETs include sources coupled to the drains of the first pair of current source NFETs, respectively.

7. The amplifier of claim 6, wherein the output circuit further comprises: a pair of current mirror PFETs including drains coupled to sources of the pair of cascode PFETs, respectively, wherein the pair of current mirror PFETs include gates coupled to the drains of one of the pair of cascode PFETs and one of the pair of cascode NFETs, respectively, wherein the drains of another of the pair of cascode PFETs and another of the pair of cascode NFETs serve as an output of the amplifier; anda second pair of current source NFETs including gates coupled to the gate of the current source NFET, wherein the second pair of current source NFETs include drains coupled to sources of the pair of cascode NFETs, respectively.

8. An amplifier, comprising:an output circuit;Qualcomm Ref. No. 2500510WO 24 / 27a current source p-channel field effect transistor (PFET) including a gate coupled to the output circuit and configured to receive a first bias voltage;a pair of input differential PFETs including sources coupled to a drain of the current source PFET, drains coupled to the output circuit, and gates configured to receive positive and negative components of an input differential signal, respectively;a first pair of current source PFETs;a pair of input differential n-channel field effect transistors (NFETs) including drains coupled to the output circuit and to drains of the first pair of current source PFETs, respectively, and gates configured to receive the positive and negative components of the input differential signal, respectively;a current source NFET including a gate configured to receive a second bias voltage, and a drain coupled to sources of the pair of input differential NFETs, respectively; anda control circuit including an input coupled to the current source NFET and an output coupled to gates of the first pair of current source PFETs, respectively.

9. The amplifier of claim 8, wherein the control circuit includes:a replica current source PFET including a gate and a drain coupled to the gates of the first pair of current source PFETs;a replica input NFET including a drain coupled to the drain and the gate of the replica current source PFET; anda replica current source NFET including a drain coupled to a source of the replica input NFET and to a gate coupled to the gate of the current source NFET.

10. The amplifier of claim 9, wherein the replica input NFET includes a gate configured to receive a replica input signal, the replica input signal being substantially the same as the positive component of the input differential signal, the negative component of the input differential signal, or a common mode voltage associated with the input differential signal.

11. The amplifier of claim 9, wherein:a channel width to channel length ratio (W / L) of the current source NFET is substantially 2 J times greater than a W / L of the replica current source NFET; andQualcomm Ref. No. 2500510WO 25 / 27a W / L of each of the first pair of the current source PFETs is substantially J times greater than a W / L of the replica current source PFET.

12. The amplifier of claim 9, wherein the control circuit further comprises an operational amplifier including a first input coupled to the drain of the current source NFET, a second input coupled to the drain of the replica current source NFET, and an output coupled to a gate of the replica input NFET.

13. The amplifier of claim 8, wherein the output circuit comprises:a pair of cascode PFETs including sources coupled to the drains of the first pair of current source PFETs, respectively, wherein the pair of cascode PFETs include gates configured to receive a first cascode bias voltage; anda pair of cascode NFETs including drains coupled to drains of the pair of cascode PFETs, wherein the pair of cascode NFETs include gates configured to receive a second cascode bias voltage, and wherein the pair of cascode NFETs include sources coupled to the drains of the pair of input differential NFETs, respectively.

14. The amplifier of claim 13, wherein the output circuit further comprises: a second pair of current source PFETs including gates coupled to the gate of the current source PFET, wherein the second pair of current source PFETs include drains coupled to sources of the pair of cascode PFETs, respectively; anda pair of current mirror NFETs including drains coupled to sources of the pair of cascode NFETs, respectively, wherein the pair of current mirror NFETs include gates coupled to the drains of one of the pair of cascode PFETs and one of the pair of cascode NFETs, respectively, wherein the drains of another of the pair of cascode PFETs and another of the pair of cascode NFETs serve as an output of the amplifier.

15. A method, comprising:amplifying an input differential signal using a first pair of input differential field effect transistor (FETs) to generate an output signal at an output circuit;amplifying the input differential signal using a second pair of input differential FETs to generate the output signal at the output circuit;sensing a current flowing into or out of the second pair of input differential FETs from or to a first current source, respectively; andQualcomm Ref. No. 2500510WO 26 / 27controlling a pair of currents flowing out of or into the first pair of input differential FETs and into or out of a first pair of current sources based on the sensed current, respectively, to reduce currents flowing through the output circuit to or from the first pair of current sources.

16. The method of claim 15, wherein sensing the current flowing into or out of the second pair of input differential FETs comprises:generating a replica current based on the current; andgenerating a gate control voltage for the first pair of current sources based on the replica current.

17. The method of claim 16, wherein:the current is substantially 2J times greater than the replica current; and each of the pair of currents is substantially J times greater than the replica current.

18. The method of claim 16, further comprising:routing the replica current through a replica input FET; andproviding a replica input signal to a gate of the replica input FET, wherein the replica input signal is substantially the same as a positive component of the input differential signal, a negative component of the input differential signal, or a common mode voltage associated with the input differential signal.

19. The method of claim 16, further comprising:routing the replica current through a replica input FET; andgenerating a gate voltage for the replica input FET based on a first voltage at sources of the second pair of input differential FETs and a second voltage at a source of the replica input FET.

20. The method of claim 15, further comprising providing a substantially constant current from or to the output circuit.

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