A method to improve interconnect reliability for a microelectric device

Abstract

Embodiments described herein relate to methods of forming interconnect structures in microelectronic devices, and more particularly to methods for selectively forming barrier and liner materials within high-aspect-ratio features to improve electrical performance and reliability of interconnects. In one or more embodiments, a method of forming a microelectronic device includes forming a dielectric layer on a substrate. The dielectric layer includes at least one feature defining a gap including sidewalls and a bottom. The method further includes selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and forming a barrier layer in the gap. The method further includes selectively depositing a metal liner on the barrier layer.

Description

PATENTAtty Docket No.44026119WO01A METHOD TO IMPROVE INTERCONNECT RELIABILITY FOR A MICROELECTRIC DEVICEBACKGROUNDField

[0001] Embodiments described herein relate to methods of forming interconnect structures in microelectronic devices, and more particularly to methods for selectively forming barrier and liner materials within high-aspect-ratio features to improve electrical performance and reliability of interconnects.Description of the Related Art

[0002] Continued scaling of semiconductor devices to advanced technology nodes presents increasing challenges for interconnect structures. Interconnects include conductive lines that transfer current within a device layer and conductive vias that transfer current between device layers. As feature sizes decrease and interconnect pitch is reduced, the dimensions of these lines and vias also decrease. Reduced dimensions can increase electrical resistance within the interconnect structure, which may result in increased voltage drop, reduced circuit speed, and increased power consumption.

[0003] Interconnect structures are commonly formed in dielectric materials by creating features such as vias and trenches and filling the features with a conductive material. In many implementations, one or more intermediate layers may be formed within the features prior to deposition of the conductive fill material. For example, barrier layers and liner layers may be used to promote adhesion between materials and to inhibit diffusion of conductive materials into surrounding dielectric layers. As feature dimensions continue to shrink, however, these intermediate layers may occupy an increasing fraction of the feature volume and may contribute to increased electrical resistance.

[0004] In addition, deposition of material layers within high-aspect-ratio features can present integration challenges. Achieving desired material coverage and properties along feature sidewalls and bottoms may become increasingly difficult as device dimensions decrease and aspect ratios increase.PATENTAtty Docket No.44026119WO01

[0005] Accordingly, improved methods of forming interconnect structures are desirable. In particular, there remains a need for methods of depositing barrier and liner materials in microelectronic features that reduce electrical resistance and improve reliability of interconnect structures.SUMMARY

[0006] Embodiments described herein relate to methods of forming interconnect structures in microelectronic devices, and more particularly to methods for selectively forming barrier and liner materials within high-aspect-ratio features to improve electrical performance and reliability of interconnects.

[0007] In one or more embodiments, a method of forming a microelectronic device includes forming a dielectric layer on a substrate. The dielectric layer includes at least one feature defining a gap including sidewalls and a bottom. The method further includes selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and forming a barrier layer in the gap. The method further includes selectively depositing a metal liner on the barrier layer. The metal liner is deposited at a thickness on the sidewalls that is greater than a thickness of the metal liner deposited on the bottom. The method further includes removing the SAM after selectively depositing the metal liner and performing a gap fill process over the metal liner.

[0008] In one or more embodiments, a microelectronic device includes a substrate. A dielectric layer is disposed on the substrate. The dielectric layer includes at least one feature defining a gap including sidewalls and a bottom. A barrier layer is disposed along the sidewalls of the gap. A metal liner is disposed on the barrier layer. The metal liner has a thickness on the sidewalls that is greater than a thickness of the metal liner on the bottom of the gap.

[0009] In one or more embodiments, an interconnect structure of a microelectronic device includes a dielectric layer disposed on a substrate. The dielectric layer includes a gap including sidewalls and a bottom. A barrier layer is disposed along the sidewalls of the gap. A metal liner is disposed on the barrier layer along the sidewalls of the gap. A second metal liner is disposed on the bottom of the gap and over at least a portion of the metal liner. A conductive fill material is disposed in the gap.PATENTAtty Docket No.44026119WO01BRIEF DESCRIPTION OF THE DRAWINGS

[0010] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

[0011] FIG. 1A illustrates a portion of a microelectronic device during a stage of manufacture and having a passivation layer formed on a bottom of a gap, according to one or more embodiments.

[0012] FIG. 1 B illustrates a barrier layer formed after formation of the passivation layer shown in FIG. 1 A, according to one or more embodiments.

[0013] FIG. 1C illustrates a liner layer formed on the barrier layer formed in FIG.1 B, according to one or more embodiments.

[0014] FIG. 1 D illustrates removal of the passivation layer formed in FIG. 1A, according to one or more embodiments.

[0015] FIG. 1 E illustrates a second liner layer formed on the liner layer formed in FIG. 1C, according to one or more embodiments.

[0016] FIG. 1 F illustrates a third liner layer formed on the liner layer formed in FIG.1 E, according to one or more embodiments.

[0017] FIG. 2 illustrates a process flow diagram of a method of manufacturing a microelectronic device in accordance with one or more embodiments of the disclosure.

[0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.PATENTAtty Docket No.44026119WO01DETAILED DESCRIPTION

[0019] Embodiments described herein relate to methods of forming interconnect structures in microelectronic devices, and more particularly to methods for selectively forming barrier and liner materials within high-aspect-ratio features to improve electrical performance and reliability of interconnects.

[0020] In various embodiments, a dielectric layer includes one or more features defining gaps such as vias or trenches having sidewalls and a bottom surface. A selfassembled monolayer (SAM) may be selectively formed on the bottom surface of the gap to suppress nucleation of subsequently deposited barrier and liner materials at the via bottom while permitting selective growth along the sidewalls. A barrier layer and a metal liner may then be selectively deposited along the sidewalls of the gap while deposition at the bottom surface is reduced or suppressed. After formation of the selective liner, the SAM may be removed to expose the bottom of the gap (e.g., a via bottom or a trench bottom, depending on the feature), and additional liner materials may be deposited to improve adhesion and coverage for subsequently deposited conductive fill materials. In some embodiments, a cobalt liner stack including a physical vapor deposition (PVD) cobalt layer and a chemical vapor deposition (CVD) cobalt layer is formed after removal of the SAM. The PVD cobalt layer may improve adhesion and surface uniformity while the CVD cobalt layer provides additional coverage and thickness. These configurations can reduce via resistance, improve adhesion of conductive fill materials, enhance interconnect reliability, and improve manufacturability of advanced semiconductor interconnect structures.

[0021] Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.

[0022] As used in this specification and the appended claims, the term “substrate” and “wafer” are used interchangeably, both referring to a surface, or portion of a surface, upon which a process acts. It will also be understood by those skilled in the art that reference to a substrate can also refer to only a portion of the substrate, unless the context clearly indicates otherwise. Additionally, reference to depositing on aPATENTAtty Docket No.44026119WO01substrate can mean both a bare substrate and a substrate with one or more films or features deposited or formed thereon.

[0023] A “substrate” as used herein, refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. For example, a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate (or otherwise generate or graft target chemical moieties to impart chemical functionality), anneal and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed may also be performed on an underlayer formed on the substrate as disclosed in more detail below, and the term “substrate surface” is intended to include such underlayer as the context indicates. Thus, for example, where a film / layer or partial film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface comprises will depend on what films are to be deposited, as well as the particular chemistry used.

[0024] As used in this specification and the appended claims, the terms “reactive gas”, “precursor”, “reactant”, and the like, are used interchangeably to mean a gas that includes a species which is reactive with a substrate surface. For example, a first “reactive gas” may simply adsorb onto the surface of a substrate and be available for further chemical reaction with a second reactive gas.

[0025] Some embodiments of the disclosure provide methods for improving performance of interconnects. Interconnects comprise metal lines that transfer current within the same device layer, and metal vias that transfer current between layers. These lines and vias are formed with conductive metal such as copper or cobalt in gaps formed within the device. In one or more embodiments, a dielectric layerPATENTAtty Docket No.44026119WO01comprises at least one feature defining a gap including sidewalls and a bottom. In one or more embodiments, the gap comprises the metal lines and the metal vias. In one or more embodiments, the metal lines have a sidewall and a bottom. In one or more embodiments, the metal vias have a sidewall and a bottom. As used in this specification and the appended claims, unless specified otherwise, reference to the “bottom of the gap” is intended to mean the bottom of the metal via, which is nearest the substrate.

[0026] Embodiments of the disclosure provide methods of forming interconnect structures in the manufacture of microelectronic devices. In one or more embodiments, microelectronic devices described herein comprise at least one top interconnect structure that is interconnected to at least one bottom interconnect structure. Embodiments of the disclosure provide microelectronic devices and methods of manufacturing microelectronic devices that improve performance of interconnects, for example, reducing via resistance.

[0027] Methods of forming microelectronic devices are described herein with reference to FIGS. 1 A-1 F. FIG. 2 is a flow chart of an exemplary method of forming microelectronic devices corresponding to the stages shown in FIGS. 1A-1 F, according to one or more embodiments.

[0028] Referring to FIGS. 1A-1 F, a portion of a microelectronic device 100 is shown during stages of manufacture. In FIG. 1A, the microelectronic device 100 comprises, for example, a substrate 110, a barrier layer 120 on the substrate 110, a metal layer 130 on the barrier layer 120, a conductive filled gap 140, an aluminum oxide etch stop layer 142, and a dielectric layer 145 on the aluminum oxide etch stop layer 142. The dielectric layer 145 comprising at least one feature defining a gap 146 including sidewalls 148 and a bottom 149. According to one or more embodiments, a passivation layer (e.g., a self-assembled monolayer (SAM)) 150 is formed on the bottom 149 of the gap. It will be appreciated that in one or more embodiments, the conductive filled gap 140 forms a metal line that transfers current within the same device layer.

[0029] In one or more embodiments, the substrate 110 is a wafer, for example a semiconductor substrate. In one or more embodiments, the substrate 110 is an etchPATENTAtty Docket No.44026119WO01stop layer on a wafer. In one or more embodiments, the substrate 110 is an aluminum oxide etch stop layer on a wafer. In one or more embodiments, the barrier layer 120 comprises tantalum nitride (TaN). In one or more embodiments, the barrier layer 120 comprises tantalum nitride (TaN) formed by ALD. In one or more embodiments, the metal layer 130 comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta). In one or more embodiments, the metal layer 130 comprises one or more of a single layer of ruthenium (Ru) or a single layer of cobalt (Co). In one or more embodiments, a portion of the metal layer 130 is etched. In one or more embodiments, the SAM 150 is deposited on the portion of the metal layer 130 that is etched. In one or more embodiments, the conductive filled gap 140 comprises one or more of copper (Cu) or cobalt (Co). In one or more embodiments, the etch stop layer 142 comprises one or more of aluminum oxide, silicon nitride, or aluminum nitride.

[0030] In one or more embodiments, the dielectric layer 145 is a low-k dielectric layer. In certain embodiments, the dielectric layer 145 comprises silicon oxide (SiOx). In one or more embodiments, the dielectric layer 145 comprises SiOxHy(CHz). Further embodiments provide that the dielectric layer 145 comprises porous or carbon-doped SiOx. In some embodiments, the dielectric layer 145 is a porous or carbon-doped SiOx layer with a k value less than about 5. In other embodiments, the dielectric layer 145 is a multilayer structure. For example, in one or more embodiments, the dielectric layer 145 comprises a multilayer structure having one or more of a dielectric layer, an etch stop layer, or a hard mask layer.

[0031] In one or more embodiments, the dielectric layer 145 comprises at least one feature defining the gap 146 including the sidewalls 148 and the bottom 149. The Figures show substrates having a single feature for illustrative purposes; however, those skilled in the art will understand that there can be more than one feature. The shape of the feature can be any suitable shape including, but not limited to, trenches, cylindrical vias that, when filled with metal, transfer current between layers, and lines that transfer current within the same device layer. In some embodiments, the feature defines the gap 146 in the dielectric layer 145. The gap 146 in some embodiments defines a via portion 146V and a line portion 146L, but the embodiments shown are not intended to be limiting. As used herein, the term “feature” means any intentional surface irregularity. Suitable examples of features include but are not limited toPATENTAtty Docket No.44026119WO01trenches which have a top, two sidewalls and a bottom, peaks which have a top and two sidewalls. Features can have any suitable aspect ratio (ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is greater than or equal to about 5:1 , 10:1 , 15:1 , 20:1 , 25:1 , 30:1 , 35:1 , or 40:1.

[0032] In one or more embodiments, the SAM 150 is formed on the metal layer 130. In one or more embodiments, the SAM 150 is deposited by exposing the bottom 149 of the gap 146 to a hydrocarbon carried in argon (Ar) gas. In one or more embodiments, the SAM 150 comprises an unsaturated hydrocarbon.

[0033] It was discovered that use of an unsaturated hydrocarbon SAM 150 improved Cu interconnect via resistance by minimizing via bottom metal liner growth with selective deposition of a metal liner on via sidewall rather than via bottom. Embodiments of the disclosure provide methods to selectively grow a metal liner such a Ru liner on the via sidewall versus the via bottom with high selectivity (e.g., the ratio of the sidewall liner thickness to bottom liner thickness is greater than 3, greater than 4, greater than 5, greater than 6, greater than 7, greater than 8, greater than 9 or greater than 10). Selection of SAM chemistry and a process enables metal (e.g., Ru) nucleation and growth only at the via sidewall, not on the via bottom. Thinner or no metal (e.g., Ru) growth on the via bottom reduces via resistance and Cu corrosion. Other liner materials include cobalt (Co), molybdenum (Mo), and tantalum (Ta). In specific embodiments, a SAM chemist ry / process which can suppress metal liner growth at the via bottom (for example, less than 10 Angstroms, less than 5 Angstroms, less than 4 Angstroms, less than 3 Angstroms, less than 2 Angstroms or less than 1 Angstrom) and maintain metal liner growth at via sidewall (for example, 5 Angstroms or greater or 10 Angstroms or greater). The SAM chemistry facilitates achievement of selectivity on the via bottom (e.g., Cu, Co, W) versus the via sidewall (e.g., TaN).

[0034] According to one or more embodiments, selectively depositing the SAM comprises exposing the bottom 149 of the gap 146 to a hydrocarbon having a formula of H — C=C — R, wherein R is a linear alkyl chain or an aryl group comprising from 1 to 20 carbon atoms or a formula of R'C=CR", wherein R' and R" independently include a linear alkyl chain or an aryl group comprising from 1 to 20 carbon atoms.PATENTAtty Docket No.44026119WO01

[0035] In some embodiments, the substrate is soaked in a vapor of the unsaturated hydrocarbon. In some embodiments, the processing conditions for exposing the substrate to the unsaturated hydrocarbon may be controlled.

[0036] In some embodiments, the pressure of the processing chamber is controlled. The pressure of the processing chamber may be any suitable pressure for forming the blocking layer. In some embodiments, the pressure of the processing chamber is maintained at less than or equal to about 80 Torr, less than or equal to about 70 Torr, less than or equal to about 60 Torr, less than or equal to about 50 Torr, less than or equal to about 40 Torr, less than or equal to about 30 Torr, less than or equal to about 20 Torr, less than or equal to about 15 Torr, less than or equal to about 10 Torr, or less than or equal to about 5 Torr. In some embodiments, the pressure of the processing chamber is maintained at about 10 Torr, about 20 Torr, about 30 Torr, about 40 Torr, or about 50 Torr.

[0037] In one or more embodiments, a flow of argon (Ar) gas is configured to carry the unsaturated hydrocarbon from a container to the processing chamber. In some embodiments, the flow rate of the argon (Ar) gas that is configured to carry the unsaturated hydrocarbon into the processing chamber is controlled. The flow rate of the argon (Ar) gas may be any suitable flow rate for forming the passivation layer. In some embodiments, the flow rate of the argon (Ar) gas is in a range of about 50 seem to about 100 seem, or in a range of about 75 seem to about 100 seem. In one or more embodiments, the flow rate of the argon (Ar) gas is about 600 seem. In some embodiments, the flow rate of the argon (Ar) gas is less than or equal to about 600 seem, less than or equal to about 500 seem, less than or equal to about 400 seem, less than or equal to about 300 seem, less than or equal to about 250 seem, less than or equal to about 200 seem, less than or equal to about 150 seem, less than or equal to about 100 seem, less than or equal to about 75 seem, or less than or equal to about 50 seem.

[0038] In some embodiments, the soak period, during which the unsaturated hydrocarbon is exposed to the substrate, is controlled. The soak period may be any suitable period for forming the blocking layer. In some embodiments, the soak period is from 1 to 200 s, for example from 1 to 10 s, greater than or equal to about 10 s,PATENTAtty Docket No.44026119WO01greater than or equal to about 20 s, greater than or equal to about 30 s, greater than or equal to about 45 s, greater than or equal to about 60 s, greater than or equal to about 80 s, greater than or equal to about 120 s, greater than or equal to about 150 s, or greater than or equal to about 200 s. In some embodiments, the soak period is about 60 s. In some embodiments, the soak period is about 200 s.

[0039] In one or more embodiments, the unsaturated hydrocarbon is in a liquid phase when the unsaturated hydrocarbon is in a container, such as an ampoule or a cylinder, from which the unsaturated hydrocarbon is delivered to the chamber in a carrier gas. In some embodiments, the unsaturated hydrocarbon is in a saturated vapor phase in the container when the container has a pressure of about 0.1 torr. In one or more embodiments, a temperature of the container is lower than the temperature in the processing chamber. In one or more embodiments, a carrier gas such as argon (Ar) gas carries the saturated vapor phase unsaturated hydrocarbon from the container to the processing chamber. In some embodiments, a temperature of the processing chamber is controlled during exposure to the unsaturated hydrocarbon. The temperature of the processing chamber may also be referred to as the operating temperature. In some embodiments, the temperature of the processing chamber is in a range of about 150° C. to about 400° C., for example, 200° C. to about 300° C. In some embodiments, the temperature of the processing chamber is less than or equal to about 300° C., less than or equal to about 275° C., less than or equal to about 250° C., less than or equal to about 225° C., or less than or equal to about 200° C.

[0040] Referring to FIG. 1 B, a barrier layer 160 is selectively formed along the sidewalls 148, and deposition on the SAM -cove red bottom 149 is reduced or suppressed. In one or more embodiments, the barrier layer 160 has the same properties as the barrier layer 120. In one or more embodiments, the barrier layer 160 does not form on the bottom 149 of the gap 146. In one or more embodiments, when the SAM 150 is not present, the deposition of the barrier layer 160 is substantially conformal. In one or more embodiments where the SAM 150 is not present, the barrier layer 160 forms on the sidewalls 148, and the bottom 149 of the gap 146. As used herein, a layer which is “substantially conformal” refers to a layer where the thickness is about the same throughout (e.g., on the top, middle and bottom of sidewalls 148PATENTAtty Docket No.44026119WO01and on the bottom 149 of the gap 146). A layer which is substantially conformal varies in thickness by less than or equal to about 5%, 2%, 1% or 0.5%. In one or more embodiments, the barrier layer 160 is selectively deposited on at least a portion of the sidewalls 148. In one or more unillustrated embodiments, the barrier layer 160 is selectively deposited on at least a portion of the bottom 149. In one or more embodiments, the barrier layer 160 may cover the entirety of the sidewalls 148. In one or more embodiments, the barrier layer 160 includes tantalum (Ta) and / or tantalum nitride (TaN).

[0041] In one or more embodiments, the barrier layer 160 is selectively deposited by atomic layer deposition (ALD), and has a thickness in a range of from about 2 A to about 10 A. In some embodiments, the barrier layer 160 is deposited in a single ALD cycle. In other embodiments, the barrier layer 160 is deposited in from 1 to 20 ALD cycles. In one or more embodiments, each cycle of the 1 to 20 ALD cycles is configured to deposit a thickness of about 0.5 A of the barrier layer 160.

[0042] In one or more embodiments, when the barrier layer 160 formed on the bottom 149 and the sidewalls 148, there is a ratio of the thickness of the barrier layer 160 thickness on the sidewalls 148 to the thickness of the barrier layer 160 thickness on the bottom 149, the ratio being greater than 6. In one or more, the ratio is greater than 5, greater than 4, greater than 3, greater than 2, or greater than 1. In one or more embodiments, when the SAM 150 is present, the barrier layer 160 has a thickness in a range of from 5 Angstroms to 20 Angstroms on the sidewalls 148. In one or more embodiments, the barrier layer 160 has a thickness of less than or equal to 5 Angstroms on the bottom 149. In one or more embodiments, the barrier layer 160 has a thickness of less than or equal to 4 Angstroms, less than or equal to 3 Angstroms, less than or equal to 2 Angstroms, or less than or equal to 1 Angstrom on the bottom 149. In one or more embodiments, the barrier layer 160 does not form on the bottom 149.

[0043] Referring to FIG. 1C, a metal liner 170 is shown on the barrier layer 160 shown in FIG. 1B. In one or more embodiments, the metal liner 170 has the same properties as the metal layer 130. In one or more embodiments, the metal liner 170 is selectively deposited on the sidewalls 148 of the microelectronic device. In one orPATENTAtty Docket No.44026119WO01more embodiments, the metal liner 170 comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta). In one or more embodiments, the metal liner 170 comprises one or more of a single layer of ruthenium (Ru) or a single layer of cobalt (Co). In one or more embodiments, the metal liner 170 comprises a single layer of ruthenium (Ru). In one or more embodiments, the metal liner 170 comprises the single layer of ruthenium (Ru) selectively deposited on the sidewall. In one or more embodiments, the metal liner 170 comprises a multilayer film having a first liner film comprised of a first metal M1 and a second liner film comprised of a second metal M2. In one or more embodiments, the metal liner 170 comprises the first metal M1 comprising ruthenium (Ru) and the second metal M2 comprising cobalt (Co).

[0044] Embodiments of the disclosure advantageously provide methods of forming microelectronic devices that reduce a resistance of a via by at least 20% as compared to a resistance of a via in a microelectronic device where a metal liner is not selectively deposited. In one or more embodiments, the resistance of the vias of microelectronic devices described herein is reduced by at least 15%, at least 10% or at least 5% as compared to a resistance of a via in a microelectronic device where a metal liner is not selectively deposited.

[0045] Using typical deposition processes, ruthenium (Ru) is deposited on a sidewall and a bottom. It has been discovered that, when using known deposition processes for a time period of 40 seconds, a ruthenium (Ru) layer deposited on a sidewall has a thickness of 10 Angstroms, and a ruthenium (Ru) layer deposited on the bottom has a thickness of about 3.87 Angstroms. In one or more embodiments, a ratio of the thickness of the ruthenium (Ru) layer thickness on the sidewalls to the thickness of the ruthenium (Ru) layer thickness on the bottom is about 2.6.

[0046] It has been discovered that selectively depositing a single layer of ruthenium (Ru) according to embodiments of the methods described herein increases a ratio of the thickness of the metal liner thickness on the sidewalls to the thickness of the metal liner thickness on the bottom. In one or more embodiments, the thickness of the metal liner thickness on the sidewalls is greater than the thickness of the metal liner on the bottom.PATENTAtty Docket No.44026119WO01

[0047] In one or more embodiments, when the metal liner 170 comprises a single layer of ruthenium (Ru) selectively deposited on the sidewall 148, there is a ratio of the thickness of the metal liner thickness on the sidewalls 148 to the thickness of the metal liner 170 thickness on the bottom 149, the ratio being greater than 3. In one or more embodiments, the ratio of the thickness of the metal liner thickness on the sidewalls 148 to the thickness of the metal liner thickness on the bottom 149 is greater than 4, greater than 5, greater than 6 or greater than 7. In one or more embodiments, the metal liner 170 does not form on the bottom 149.

[0048] In one or more embodiments, when the metal liner 170 comprises a single layer of selectively deposited ruthenium (Ru), the metal liner 170 has a thickness in a range of from 5 Angstroms to 20 Angstroms on the sidewalls 148. In one or more embodiments, when the metal liner 170 comprises a single layer of selectively deposited ruthenium (Ru), the metal liner 170 has a thickness of less than or equal to 5 Angstroms on the bottom 149. In one or more embodiments, when the metal liner 170 comprises a single layer of selectively deposited ruthenium (Ru), the metal liner 170 has a thickness of less than or equal to 4 Angstroms, less than or equal to 3 Angstroms, less than or equal to 2 Angstroms, or less than or equal to 1 Angstrom on the bottom 149.

[0049] In one or more embodiments, the metal liner 170 comprising ruthenium (Ru) is selectively deposited by a selective ruthenium (Ru) deposition process. The selective ruthenium (Ru) deposition on the sidewall comprises a cyclic deposition process that includes ruthenium deposition using a ruthenium (Ru) precursor carried by a carrier gas such as an argon (Ar) gas. In one or more embodiments, the selective ruthenium (Ru) deposition further comprises an annealing or treatment that is performed while flowing hydrogen (H2) and optionally a second gas, for example, argon (Ar). In one or more embodiments, the selective ruthenium (Ru) deposition is performed in a substrate processing chamber in which the deposition is performed while the chamber is at a first pressure, and the annealing is performed while the substrate processing chamber is at a second pressure that is greater than the first pressure. In one or more embodiments, the first pressure is in a range of from 1 torr to 5 torr. In some embodiments, the first pressure is in a range of from 1 torr to 4 torr, or a range of from 1 torr to 3 torr. In one or more embodiments, the second pressurePATENTAtty Docket No.44026119WO01is in a range of from 10 torr to 150 torr. In some embodiments, the second pressure is in a range of from 10 torr to 40 torr, or in a range of from 10 torr to 30 torr. Thus, according to one or more embodiments, a cyclic deposition process includes deposition and annealing / treatment. In the deposition, a ruthenium precursor (e.g., any suitable metalorganic precursor, for example, Cyclohexadienyl ruthenium tricarbonyl, Ru3(CO)g) is flowed in carrier gas and reactant gas (e.g., Ar and / or H2) for 2-10 seconds, e.g., 3-6 seconds to form a deposited ruthenium layer. In the annealing or treatment, the deposited ruthenium layer is annealed or treated in the presence of a flowing gas (e.g., >90% H2 and a second gas such as Ar) for 30-90 seconds, for examples 40-70 seconds. This cyclic deposition processes comprising cycles of deposition and annealing or treatment is repeated multiple times to obtain a desired film thickness.

[0050] Referring to FIG. 1 D, in one or more embodiments, the SAM 150 has been removed from the structure shown in FIG. 1 C. In one or more embodiments, removing the SAM 150 comprises a plasma treatment process including flowing one or more of hydrogen (H2) or argon (Ar). Removal of the SAM 150 exposes the bottom 149 of the gap 146 while the selectively deposited liner remains on the sidewalls 148. In some embodiments, the plasma treatment process may also treat a surface of the barrier layer 160. After removal of the SAM 150, a portion of the metal layer 130 is exposed at the bottom of the gap 146. In some embodiments, selective liner deposition improves via resistance but reduced liner coverage at the bottom 149 of the gap 146 may adversely affect adhesion of subsequently deposited conductive fill material; accordingly, embodiments further include formation of a PVD cobalt layer after SAM removal to improve adhesion and interconnect reliability. In some embodiments, after removal of the SAM, an annealing or treatment may be performed prior to deposition of the cobalt liner.

[0051] Referring to FIG. 1E, a second metal liner 180 is formed on the metal liner 170 formed in FIG. 1C according to one or more embodiments. The second metal liner 180 is deposited after removal of the SAM 150 and is formed on the exposed bottom 149 of the gap 146 and over at least a portion of the metal liner 170 disposed on the sidewalls 148. In one or more embodiments, the second metal liner 180 is deposited using a physical vapor deposition (PVD) process. In some embodiments,PATENTAtty Docket No.44026119WO01the second metal liner 180 comprises cobalt (Co). The second metal liner 180 may improve adhesion between the underlying structure and subsequently deposited liner layers or conductive fill materials. In one or more embodiments, the second metal liner 180 has a thickness in a range of from about 1 A to about 20 A, such as about 5 A.

[0052] Referring to FIG. 1 F, a third metal liner 190 is formed on the second metal liner 180 formed in FIG. 1 E according to one or more embodiments. In one or more embodiments, the third metal liner 190 comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta). In some embodiments, the third metal liner 190 comprises a cobalt liner deposited over the second metal liner 180. In one or more embodiments, the third metal liner 190 is deposited using a chemical vapor deposition (CVD) process. The third metal liner 190 may form along the sidewalls 148 and over the second metal liner 180 at the bottom 149 of the gap 146. In one or more embodiments, the third metal liner 190 has a thickness in a range of from about 5 A to about 20 A. In some embodiments, the combination of the PVD-deposited cobalt liner 180 and the CVD-deposited cobalt liner 190 improves adhesion of subsequently deposited conductive fill materials and improves interconnect reliability.

[0053] In one or more embodiments, the barrier layer and / or metal film may be deposited via ALD. In a typical ALD process, alternating pulses or flows of “A” precursor and “B” precursor can be used to deposit a film. The alternating exposure of the surface to reactants “A” and “B” is continued until the desired thickness film is reached. However, instead of pulsing the reactants, the gases can flow simultaneously from one or more gas delivery head or nozzle and the substrate and / or gas delivery head can be moved such that the substrate is sequentially exposed to each of the reactive gases. Of course, the aforementioned ALD cycles are merely exemplary of a wide variety of ALD process cycles in which a deposited layer is formed by alternating layers of precursors and co-reactants.

[0054] In one or more embodiments, the co-reactants are in vapor or gas form. The reactants may be delivered with a carrier gas. A carrier gas, a purge gas, a deposition gas, or other process gas may contain nitrogen, hydrogen, argon, neon, helium, or combinations thereof. The various plasmas described herein, such as thePATENTAtty Docket No.44026119WO01nitrogen plasma or the inert gas plasma, may be ignited from and / or contain a plasma co-reactant gas.

[0055] In one or more embodiments, the various gases for the process may be pulsed into an inlet, through a gas channel, from various holes or outlets, and into a central channel. In one or more embodiments, the deposition gases may be sequentially pulsed to and through a showerhead. Alternatively, as described above, the gases can flow simultaneously through gas supply nozzle or head and the substrate and / or the gas supply head can be moved so that the substrate is sequentially exposed to the gases.

[0056] In one or more embodiments, the barrier layer material and liner film are deposited using a multi-chamber process with separation of the barrier layer material (e.g., tantalum nitride (TaN)) and the metal liner film. In other embodiments, a single chamber approach is used, with all processes occurring within one chamber and the different layers / films separated in processing by gas purges.

[0057] Some embodiments of the disclosure are directed to barrier applications, e.g., copper barrier applications. The barrier layer formed by one or more embodiments may be used as a copper barrier. Suitable barrier layers for copper barrier applications include, but are not limited to, TaN and MnN. For copper barrier applications, suitable dopants include, but are not limited to, Ru, Cu, Co, Mn, Al, Ta, Mo, Nb, V, or combinations thereof. A plasma treatment can be used after doping to promote the intermetallic compound formation between the matrix and dopant, as well as removing film impurities and improving the density of the barrier layer. In other embodiments, post treatment can include, but is not limited to, physical vapor deposition (PVD) treatment, thermal anneal, chemical enhancement, or the like. In some copper barrier applications, a high frequency plasma (defined as greater than about 14 MHz or about 40 MHz or greater) can be used with any inert gas, including, but not limited to, one or more of neon (Ne), hydrogen (H2), and argon (Ar) gas. In one or more embodiments, to prevent low-k damage, a higher plasma frequency can be used (higher than 13.56 MHz). In some embodiments, the barrier layer is a copper barrier and comprises TaN doped with Ru.PATENTAtty Docket No.44026119WO01

[0058] Suitable precursors for depositing a liner layer include metal-containing precursors such as carbonyl-containing and cyclopentadiene-containing precursors. In a non-limiting example, if the liner layer is RuCo, the Ru-containing precursor may be triruthenium dodecacarbonyl Ru3(CO)i2 and the Go-containing precursor may be dicobalt hexacarbonyl tertbutylacetylene (CCTBA). If the liner layer is TaRu, the Ta-containing precursor may be pentakis(dimethlamino) tantalum (PDMAT). Other suitable precursors are known to those skilled in the art. Organic species in organic-containing precursors for liner layers may get partially incorporated into the underlying layer (such as a barrier or dielectric layer), which may increase the adhesion at the liner layer-underlying layer interface.

[0059] As used herein, “chemical vapor deposition” refers to a process in which a substrate surface is exposed to precursors and / or co-reagents simultaneous or substantially simultaneously. As used herein, “substantially simultaneously” refers to either co-flow or where there is overlap for a majority of exposures of the precursors.

[0060] FIG. 2 illustrates a process flow diagram of a method 200 for forming a microelectronic device. The method 200 may be used to form any of the microelectronic devices of one or more embodiments shown in FIGS. 1A-1 F. Referring to FIG. 2, the method 200 comprises, at operation 210, forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. At operation 220, the method 200 comprises selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. At operation 230, the method 200 comprises forming a barrier layer on the SAM. At operation 240, the method 200 comprises selectively depositing a metal liner on the barrier layer, wherein in some embodiments the metal liner is deposited at a thickness on the sidewalls that is greater than a thickness of the metal liner deposited on the bottom, and in some embodiments the metal liner is selectively deposited on the sidewalls and not deposited on the bottom.

[0061] At operation 250, the method 200 comprises removing the SAM after selectively depositing the metal liner on the barrier layer. In some embodiments, after operation 250 the method further comprises operations 252 and 254. At operation 252, a second metal liner is deposited over the metal liner and the bottom of the gap,PATENTAtty Docket No.44026119WO01wherein the second metal liner is deposited using a physical vapor deposition (PVD) process. In some embodiments, the second metal liner comprises cobalt (Co) and has a thickness from about 1 A to about 20 A, such as about 5 A. At operation 254, a third metal liner is deposited over the second metal liner, wherein the third metal liner is deposited using a chemical vapor deposition (CVD) process. In some embodiments, the third metal liner comprises cobalt (Co) and has a thickness from about 1 A to about 20 A, such as about 10 A to about 15 A. In some embodiments, the combination of the second metal liner deposited by PVD and the third metal liner deposited by CVD improves adhesion and interconnect reliability. At operation 260, the method 200 comprises performing a gap fill process over the liner stack. The gap fill process can include forming one or more of a via and a line to form an interconnect in the device. In some embodiments, the CVD cobalt layer has a thickness greater than the thickness of the PVD cobalt layer. In some embodiments, inclusion of the PVD cobalt layer improves surface uniformity and reduces particle generation compared to liners formed without the PVD cobalt layer. In some embodiments, the gap fill process comprises depositing copper (Cu) or cobalt (Co).

[0062] In one or more embodiments, the methods described herein comprise an optional post-processing operation. The optional post-processing operation can be, for example, a process to modify film properties (e.g., annealing) or a further film deposition process (e.g., additional ALD or CVD processes) to grow additional films. In some embodiments, the optional post-processing operation can be a process that modifies a property of the deposited film. In some embodiments, the optional postprocessing operation comprises annealing the as-deposited film. In some embodiments, annealing is done at temperatures in the range of about 300° C., 400° C., 500° C., 600° C., 700° C., 800° C., 900° C. or 1000° C. The annealing environment of some embodiments comprises one or more of an inert gas (e.g., molecular nitrogen (N2), argon (Ar)) or a reducing gas (e.g., molecular hydrogen (H2) or ammonia (NH3)) or an oxidant, such as, but not limited to, oxygen (02), ozone (03), or peroxides. Annealing can be performed for any suitable length of time. In some embodiments, the film is annealed for a predetermined time in the range of about 15 seconds to about 90 minutes, or in the range of about 1 minute to about 60 minutes. In somePATENTAtty Docket No.44026119WO01embodiments, annealing the as-deposited film increases the density, decreases the resistivity and / or increases the purity of the metal liner layers.

[0063] In some embodiments, the substrate is moved from a first chamber to a separate, next chamber for further processing. The substrate can be moved directly from the first chamber to the separate processing chamber, or the substrate can be moved from the first chamber to one or more transfer chambers, and then moved to the separate processing chamber. In some embodiments, the deposition of the barrier layer and the dopant film can be done in a single chamber, and then the postprocessing can be performed in a separate chamber. Accordingly, the processing apparatus may comprise multiple chambers in communication with a transfer station. An apparatus of this sort may be referred to as a “cluster tool” or “clustered system”, and the like.

[0064] Generally, a cluster tool is a modular system comprising multiple chambers which perform various functions including substrate center-finding and orientation, degassing, annealing, deposition and / or etching. According to one or more embodiments, a cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber may house a robot that can shuttle substrates between and among processing chambers and load lock chambers. The transfer chamber is typically maintained at a vacuum condition and provides an intermediate stage for shuttling substrates from one chamber to another and / or to a load lock chamber positioned at a front end of the cluster tool. However, the exact arrangement and combination of chambers may be altered for purposes of performing specific steps of a process as described herein. By carrying out processes in a chamber on a cluster tool, surface contamination of the substrate with atmospheric impurities can be avoided without oxidation prior to depositing a subsequent film.

[0065] According to one or more embodiments, the substrate is continuously under vacuum or “load lock” conditions and is not exposed to ambient air when being moved from one chamber to the next. The transfer chambers are thus under vacuum and are “pumped down” under vacuum pressure. Inert gases may be present in the processing chambers or the transfer chambers. In some embodiments, an inert gas is used as a purge gas to remove some or all of the reactants (e.g., reactant). According to one orPATENTAtty Docket No.44026119WO01more embodiments, a purge gas is injected at the exit of the deposition chamber to prevent reactants (e.g., reactant) from moving from the deposition chamber to the transfer chamber and / or additional processing chamber. Thus, the flow of inert gas forms a curtain at the exit of the chamber.

[0066] The substrate can be processed in single substrate deposition chambers, where a single substrate is loaded, processed and unloaded before another substrate is processed. The substrate can also be processed in a continuous manner, similar to a conveyer system, in which multiple substrates are individually loaded into a first part of the chamber, move through the chamber and are unloaded from a second part of the chamber. The shape of the chamber and associated conveyer system can form a straight path or curved path. Additionally, the processing chamber may be a carousel in which multiple substrates are moved about a central axis and are exposed to deposition, etch, annealing, cleaning, etc. processes throughout the carousel path.

[0067] During processing, the substrate can be heated or cooled. Such heating or cooling can be accomplished by any suitable means including, but not limited to, changing the temperature of the substrate support and flowing heated or cooled gases to the substrate surface. In some embodiments, the substrate support includes a heater / cooler which can be controlled to change the substrate temperature conductively. In one or more embodiments, the gases (either reactive gases or inert gases) being employed are heated or cooled to locally change the substrate temperature. In some embodiments, a heater / cooler is positioned within the chamber adjacent the substrate surface to convectively change the substrate temperature.

[0068] The substrate can also be stationary or rotated during processing. A rotating substrate can be rotated (about the substrate axis) continuously or in discrete steps. For example, a substrate may be rotated throughout the entire process, or the substrate can be rotated by a small amount between exposures to different reactive or purge gases. Rotating the substrate during processing (either continuously or in steps) may help produce a more uniform deposition or etch by minimizing the effect of, for example, local variability in gas flow geometries.

[0069] Another aspect of the disclosure pertains to a non-transitory computer readable medium including instructions, that, when executed by a controller of aPATENTAtty Docket No.44026119WO01processing system, causes the processing system to perform operations of the methods described herein. In one embodiment, a non-transitory computer readable medium including instructions, that, when executed by a controller of a processing system, causes the processing system to perform operations of the methods described herein with respect to FIGS. 1 A-1 F and 2.

[0070] Benefits of the present disclosure include methods of forming interconnect structures that reduce via resistance and improve interconnect reliability by enabling selective deposition of barrier and liner materials within high aspect ratio features. In one or more embodiments, the present disclosure provides improved electrical performance by forming a self-assembled monolayer (SAM) on the bottom of a gap to suppress metal nucleation and growth at the via bottom while permitting selective deposition of a barrier layer and a metal liner layer along via sidewalls. Such selective sidewall liner formation may reduce resistance associated with via bottom overgrowth and may reduce corrosion of conductive fill materials. Benefits of the present disclosure further include improved adhesion and reliability of subsequently deposited conductive fill materials by removing the SAM and forming a cobalt liner stack that includes a PVD-deposited cobalt layer followed by a CVD-deposited cobalt layer. In some embodiments, the PVD cobalt layer improves adhesion and / or surface uniformity and reduces particle generation, while the subsequent CVD cobalt layer provides desired liner thickness and coverage. Collectively, these features can yield reduced via resistance, improved adhesion, improved interconnect reliability, improved manufacturability, and improved process robustness for advanced interconnect integration.

[0071] Reference throughout this specification to “one embodiment,” “certain embodiments,” “one or more embodiments” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases such as “in one or more embodiments,” “in certain embodiments,” “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.PATENTAtty Docket No.44026119WO01

[0072] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the method and apparatus of the present disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure include modifications and variations that are within the scope of the appended claims and their equivalents.

Claims

1. PATENTAtty Docket No.44026119WO01What is claimed is:

1. A method of forming a microelectronic device comprising:forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom;selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap;forming a barrier layer in the gap;selectively depositing a metal liner on the barrier layer, wherein the metal liner is deposited at a thickness on the sidewalls that is greater than a thickness of the metal liner deposited on the bottom;removing the SAM after selectively depositing the metal liner; and performing a gap fill process over the metal liner.

2. The method of claim 1 , wherein selectively depositing the SAM comprises exposing the bottom of the gap to a hydrocarbon.

3. The method of claim 2, wherein the hydrocarbon comprises an unsaturated hydrocarbon.

4. The method of claim 2, wherein the hydrocarbon has a formula of H — C=C — R, wherein R is a linear alkyl chain or an aryl group comprising from 1 to 20 carbon atoms.

5. The method of claim 1 , wherein the barrier layer comprises tantalum nitride (TaN).

6. The method of claim 1 , wherein the metal liner comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta).

7. The method of claim 1 , wherein removing the SAM comprises a plasma treatment process including flowing hydrogen (H2) or argon (Ar).PATENTAtty Docket No.44026119WO018. The method of claim 1 , further comprising depositing a second metal liner over the metal liner and the bottom of the gap using a physical vapor deposition (PVD) process.

9. The method of claim 8, further comprising depositing a third metal liner over the second metal liner using a chemical vapor deposition (CVD) process.

10. The method of claim 9, wherein the second metal liner and the third metal liner comprise cobalt.

11. The method of claim 1, wherein the gap fill process comprises depositing copper (Cu) or cobalt (Co).

12. The method of claim 1 , wherein a ratio of a thickness of the metal liner on the sidewalls to a thickness of the metal liner on the bottom of the gap is greater than 3.

13. A microelectronic device comprising:a substrate;a dielectric layer disposed on the substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom;a barrier layer disposed along the sidewalls of the gap; anda metal liner disposed on the barrier layer, wherein the metal liner has a thickness on the sidewalls that is greater than a thickness of the metal liner on the bottom of the gap.

14. The microelectronic device of claim 13, wherein the barrier layer comprises tantalum nitride (TaN).

15. The microelectronic device of claim 13, wherein the metal liner comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta).PATENTAtty Docket No.44026119WO0116. The microelectronic device of claim 13, wherein a ratio of the thickness of the metal liner on the sidewalls to the thickness of the metal liner on the bottom of the gap is greater than 3.

17. The microelectronic device of claim 13, further comprising a second metal liner disposed on the metal liner and on the bottom of the gap, the second metal liner comprising cobalt (Co).

18. The microelectronic device of claim 17, further comprising a third metal liner disposed on the second metal liner, the third metal liner comprising cobalt (Co).

19. An interconnect structure of a microelectronic device comprising:a dielectric layer disposed on a substrate, the dielectric layer comprising a gap including sidewalls and a bottom;a barrier layer disposed along the sidewalls of the gap;a metal liner disposed on the barrier layer along the sidewalls of the gap; a second metal liner disposed on the bottom of the gap and over at least a portion of the metal liner; anda conductive fill material disposed in the gap.

20. The interconnect structure of claim 19, wherein the second metal liner comprises cobalt.

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