Semiconductor device and manufacturing method therefor

Abstract

The present disclosure provides a semiconductor device and a manufacturing method therefor. The semiconductor device may comprise a silicon carbide body, a gate trench, two shielding regions, and a conductive connection portion, wherein the silicon carbide body comprises a first surface and a second surface arranged opposite to each other; the gate trench extends from the first surface into the silicon carbide body, and a conductive gate electrode is arranged in the gate trench; the two shielding regions extend from the first surface into the silicon carbide body, are spaced apart in a first direction, and are arranged on two sides of the gate trench, and two cells adjacent in the first direction share one shielding region; and the conductive connection portion is arranged on the side of the shielding regions distant from the second surface, and conductive gate electrodes in gate trenches of two cells adjacent in a second direction are electrically connected by means of the conductive connection portion, the first direction being perpendicular to the second direction.

Description

A semiconductor device and its manufacturing method Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more particularly to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Power devices, as core components of modern electronic power systems, play an irreplaceable role in power management, energy conversion, and power processing. As electronic power technology advances towards higher frequencies, higher densities, and higher reliability, traditional silicon (Si)-based power devices, limited by their material properties, are struggling to meet increasingly stringent performance requirements. In contrast, wide-bandgap semiconductors, due to their larger bandgap width, typically exhibit advantages such as high frequency, high power density, high breakdown voltage, and strong radiation resistance. Among these wide-bandgap semiconductors, silicon carbide (SiC) stands out for its high critical breakdown electric field, high thermal conductivity, and high saturated electron drift velocity. Compared to the widely used silicon (Si) insulated-gate bipolar transistors (IGBTs), SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) exhibit lower switching losses and higher operating frequencies due to their unipolar conductivity and high saturated electron drift velocity.

[0003] In particular, trench-gate SiC MOSFETs have gained attention due to their superior electrical characteristics, including high cell density, low conduction loss, and excellent switching performance. However, the limitations of existing SiC MOSFET device structures in terms of electric field shielding, process compatibility, and high-temperature characteristics lead to problems such as complex processes, poor high-temperature conduction characteristics, large cell size, and high requirements for high-energy ion implantation processes. Summary of the Invention

[0004] This disclosure aims to provide a semiconductor device and a method for manufacturing the same.

[0005] The technical solution of this disclosure embodiment is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a semiconductor device comprising a plurality of cells arranged in an array, the cells comprising:

[0007] The silicon carbide body includes a first surface and a second surface disposed opposite to the first surface;

[0008] A gate trench extends from the first surface into the silicon carbide body, and a conductive gate electrode is disposed in the gate trench.

[0009] Two shielding regions extend from the first surface into the silicon carbide body, are spaced apart on both sides of the gate trench along a first direction, and two adjacent cells in the first direction share one shielding region.

[0010] A conductive connection portion is disposed on the side of the shielding area away from the second surface, and the conductive gate electrodes in the gate trenches of two adjacent cells in the second direction are electrically connected through the conductive connection portion, wherein the first direction is perpendicular to the second direction.

[0011] Secondly, embodiments of this disclosure provide a method for manufacturing a semiconductor device, the semiconductor device comprising a plurality of cells arranged in an array, wherein forming the cells comprises:

[0012] A silicon carbide body is provided, the silicon carbide body including a first surface and a second surface disposed opposite to the first surface;

[0013] A gate trench is formed extending from the first surface of the silicon carbide body into the silicon carbide body;

[0014] Two shielding regions are formed extending from the first surface of the silicon carbide body into the silicon carbide body. The two shielding regions are spaced apart on both sides of the gate trench along a first direction, and two adjacent cells in the first direction share one shielding region.

[0015] A conductive connection is formed on the side of the shielding area away from the second surface, and the conductive gate electrodes in the gate trenches of two adjacent cells in the second direction are electrically connected through the conductive connection, wherein the first direction is perpendicular to the second direction.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description.

[0017] It is understood that before using the technical solutions disclosed in the various embodiments of this disclosure, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this disclosure in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained. Brief description of the attached figures

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 is a schematic diagram of a semiconductor device provided in an embodiment of this disclosure.

[0020] Figure 2 is a cross-sectional view along line AA in Figure 1 provided by an embodiment of this disclosure.

[0021] Figure 3 is a cross-sectional view along line BB in Figure 1 provided by an embodiment of this disclosure.

[0022] Figure 4 is a schematic diagram of a silicon carbide body provided in an embodiment of this disclosure.

[0023] Figure 5 is a schematic diagram of a semiconductor device after a gate trench has been formed, according to an embodiment of this disclosure.

[0024] Figure 6 is a schematic diagram of a semiconductor device after a gate structure has been formed, according to an embodiment of this disclosure.

[0025] Figure 7 is a schematic diagram of a semiconductor device after a shielding region has been formed, according to an embodiment of this disclosure.

[0026] Figure 8 is a schematic diagram of another semiconductor device after forming a shielding region according to an embodiment of this disclosure.

[0027] Figure 9 is a schematic diagram of another semiconductor device provided in an embodiment of this disclosure.

[0028] Figure 10 is a cross-sectional view along line AA in Figure 9 provided by an embodiment of this disclosure.

[0029] Figure 11 is a cross-sectional view along line BB in Figure 9 provided by an embodiment of this disclosure.

[0030] Figure 12 is a schematic diagram of two cells in a first direction provided by an embodiment of this disclosure.

[0031] Figure 13 is a schematic diagram of a semiconductor device after the formation of the body region and the source region according to an embodiment of the present disclosure.

[0032] Figure 14 is a schematic diagram of a semiconductor device after a conductive connection has been formed, according to an embodiment of this disclosure.

[0033] Figure 15 is a schematic diagram of a semiconductor device after the formation of an interlayer dielectric layer according to an embodiment of the present disclosure.

[0034] Figure 16 is a schematic diagram of a semiconductor device after the formation of a source interconnect layer according to an embodiment of the present disclosure.

[0035] Figure 17 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this disclosure.

[0036] Explanation of reference numerals in the attached figures:

[0037] 1. Silicon carbide body; 10. Cell; 11. Gate trench; 111. Gate structure; 12. Shielding region; 13. Body region; 14. Source region; 15. First surface; 16. Second surface; 2. Conductive connection; 3. Source connection; 4. Interlayer dielectric layer; 5. Metal electrode; P1, First direction; P2, Second direction.

[0038] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0039] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0040] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0041] The terms “having,” “containing,” “including,” and “comprising” are open-ended and indicate the presence of the stated structure, element, or feature but do not exclude the presence of additional elements or features. The quantifiers and pronouns “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0042] The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a lower doping concentration than the "n" doped region, while "n+" doped regions have a higher doping concentration than the "n" doped region. Doped regions with the same doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doped regions can have the same or different absolute doping concentrations. Two adjacent doped regions with the same conductivity type but different dopant concentrations form a unipolar junction, for example, an n / n+ or p / p+ junction along the boundary surface between the two doped regions. At the unipolar junction, the dopant concentration profile orthogonal to the unipolar junction can show steps or inflection points where the dopant concentration profile changes from concave to convex, or vice versa.

[0043] The main components of a layer or structure derived from a chemical compound or alloy are elements whose atoms form the chemical compound or alloy. For example, nickel and silicon are the main components of nickel silicide layers, and copper and aluminum are the main components of copper-aluminum alloys.

[0044] Trench gate MOSFETs are a relatively new device structure. Compared to traditional planar MOSFETs, the trench gate design changes the conductive channel from lateral to vertical, effectively reducing cell size, lowering on-resistance, and eliminating the junction field-effect transistor (JFET) effect. However, trench gate technology is limited by current process technology and gate oxide reliability issues. Specifically, the electric field concentration at the bottom of the gate trench leads to lower long-term reliability of the semiconductor device.

[0045] However, due to the inherent electrical properties of SiC materials, the gate oxide layer at the bottom and sidewalls of the trench cannot withstand the high electric field intensity when the device is blocked, thus making it impossible to continue using the traditional Si-based trench-gate MOSFET device structure. The key technical challenge of existing traditional SiC MOSFET device structures lies in how to effectively shield the electric field of the gate oxide layer at these locations. Current mainstream trench-gate SiC MOSFET structures address this key challenge by primarily using p+ injection regions to suppress the gate oxide layer electric field.

[0046] The shortcomings in electric field shielding, process compatibility and high temperature characteristics lead to problems such as complex processes, poor high temperature conductivity, large cell size and high requirements for high-energy ion implantation processes.

[0047] Based on this, the present disclosure first provides a novel semiconductor device. Referring to FIG1, the semiconductor device includes a plurality of cells 10 arranged in an array. Referring to FIGS. 2 and 3, each cell 10 may include a silicon carbide body 1, a gate trench 11, two shielding regions 12, and a conductive connection portion 2. Referring to FIG4, the silicon carbide body 1 includes a first surface 15 and a second surface 16 disposed opposite to the first surface 15. The gate trench 11 extends from the first surface 15 into the silicon carbide body 1, and a conductive gate electrode is disposed in the gate trench 11. The two shielding regions 12 extend from the first surface 15 into the silicon carbide body 1, and are disposed at intervals on both sides of the gate trench 11 along a first direction P1, and two adjacent cells 10 in the first direction P1 share a shielding region 12. The conductive connection portion 2 is disposed on the side of the shielding region 12 away from the second surface 16, and the conductive gate electrodes in the gate trench 11 of two adjacent cells 10 in the second direction P2 are electrically connected through the conductive connection portion 2. The first direction P1 is perpendicular to the second direction P2.

[0048] It should be noted that Figure 1 contains multiple cells 10 as shown in the dashed box. A cell 10 may include the structure shown in Figure 2, namely the silicon carbide body 1 completely enclosed by the dashed box, a gate trench 11, two shielding areas 12, and two conductive connection parts 2.

[0049] By setting shielding regions 12 on both sides of the gate trench 11 and having adjacent cells 10 share a single shielding region 12, a staggered arrangement structure is formed. This design can simultaneously exert a shielding effect in two dimensions (first direction P1 and second direction P2), effectively suppressing the high electric field intensity at the bottom and sidewalls of the gate trench 11, thereby significantly reducing the electric field stress in the gate oxide layer, extending its lifespan, and improving the device's withstand voltage performance and reliability. The staggered arrangement structure allows adjacent cells 10 to share the shielding region 12, reducing the redundancy of the shielding region 12 and achieving higher cell 10 integration density without increasing additional area. Simultaneously, this design allows for further reduction of the cell 10 size, optimizing the device's area utilization, increasing the current density per unit area, and thus improving the overall device performance. Due to the reduction in cell 10 size and the optimized layout of the shielding region 12, the device structure is more compact, and the on-resistance is reduced. Furthermore, the optimized layout of the shielding region 12 allows for a shallower depth, reducing reliance on high-energy ion implantation and further optimizing the device's conduction characteristics. The reduction in on-resistance is particularly noticeable under high-temperature conditions, improving device efficiency. This structural design eliminates the need for complex secondary epitaxy or multiple trench etching processes, simplifying the overall process flow. Due to the dual shielding effect of the shielding region 12, the device exhibits better stability under extreme operating conditions such as high voltage, high current, and high temperature. This structure effectively prevents breakdown caused by electric field concentration, enhancing the device's robustness and making it more suitable for high-efficiency power applications, such as electric vehicles and industrial converters.

[0050] In some examples, referring to FIG4, the silicon carbide body 1 includes a first surface 15 and a second surface 16 disposed opposite each other. By way of example, the silicon carbide body 1 can be polytype 15R-SiC, 2H-SiC, 4H-SiC, or 6H-SiC. In addition to the main components silicon and carbon, the silicon carbide body 1 may also include dopant atoms such as nitrogen (N), phosphorus (P), beryllium (Be), boron (B), aluminum (Al), and / or gallium (Ga). Furthermore, the silicon carbide body 1 may include unwanted impurities such as hydrogen and / or oxygen. The silicon carbide body 1 may include a first surface 15 on the front side and an opposing second surface 16 on the rear side.

[0051] It should be noted that the conductivity type of the silicon carbide body 1 can be the first conductivity type, which can be n-type or p-type. Here and below, the conductivity type of the silicon carbide body 1 is named the first conductivity type, i.e., n-type.

[0052] It should be noted that the first conductivity type and the second conductivity type in this disclosure are used to distinguish between n-type and p-type. When the first conductivity type is n-type, the second conductivity type is p-type, and when the first conductivity type is p-type, the second conductivity type is n-type.

[0053] In some examples, referring to FIG5, the shielding area extends from the first surface 15 into the silicon carbide body 1 and is spaced apart in the first direction P1.

[0054] In some examples, referring to FIG6, the gate trench 11 extends from the first surface 15 into the silicon carbide body 1. Optionally, the gate trench 11 extending from the first surface 15 into the silicon carbide body 1 can be formed on the silicon carbide body 1. When forming the gate trench 11, a mask etching process can be used to etch the gate trench 11 on the silicon carbide body 1. The formed gate trench 11 has sidewalls and a bottom. The gate trench 11 can be disposed between the two shielding regions 12 in the first direction P1.

[0055] Optionally, referring to FIG7, a gate structure 111 may be provided in the gate trench 11. The gate structure 111 may include a conductive gate electrode of a first conductivity type and a gate dielectric at least between the body region 13 and the conductive gate electrode. The conductive gate electrode is used to wrap the conductive gate electrode (such as a polysilicon gate), and the gate dielectric is in contact with the sidewall of the gate trench 11.

[0056] In some examples, referring to FIG7, the shielding region 12 is spaced apart from the gate trench 11, and the bottom of the shielding region 12 is closer to the second surface 16 than the bottom of the gate trench 11. The conductivity type of the shielding region 12 is the second conductivity type. Specifically, when the second conductivity type is p-type, a p-type body mask can be fabricated first using photolithography, and then p-type impurity boron or aluminum can be implanted based on the p-type body mask to form the p-type shielding region 12.

[0057] In some examples, as shown in Figure 7, the two shielding regions 12 are symmetrically arranged with respect to the gate trench 11. This symmetrical structure effectively balances the electric field distribution, thereby improving the electrical performance and reliability of the device. In other examples, as shown in Figure 8, one of the shielding regions 12 extends from the first surface 15 into the interior of the silicon carbide body 1 and along the first direction P1, such that the shielding region 12 simultaneously contacts the sidewalls and bottom of the gate trench 11. This asymmetrical design further enhances the electric field shielding effect of the shielding region 12 on the gate trench 11, especially under high voltage and high electric field strength operating conditions, significantly reducing the electric field stress in the gate oxide layer and extending the device's lifespan.

[0058] Referring to Figures 9, 10 and 11, when the two shielding regions 12 extend from the first surface 15 to the silicon carbide body 1 and extend in the first direction P1, the shielding regions 12 can also optimize the electric field at the bottom of the gate trench 11.

[0059] In some examples, referring to FIG12, two adjacent cells 10 in the first direction P1 share a shielding area 12, which can increase the cell density 10 in the semiconductor device.

[0060] In some examples, referring to Figure 13, the cell 10 further includes a body region 13 and a source region 14, which are doped in opposite directions to form a pn junction. The source region 14 has a first conductivity type, and the body region 13 has a second conductivity type. The body region 13 is in contact with the sidewall of the gate trench 11, and the source region 14 is in contact with the sidewall of the gate trench 11. The source region 14 is located between the body region 13 and the first surface 15. The body region 13 has a second conductivity type, and the source region 14 has a first conductivity type. Since the source region 14 is located between the body region 13 and the first surface 15, when the first conductivity type is n-type, n-type impurity implantation can be used to form an n-type source region 14. The doping concentration of the shielding region 12 is greater than the doping concentration of the body region 13.

[0061] In some examples, as shown in Figure 14, the conductive connection portion 2 is disposed on the side of the shielding region 12 away from the second surface 16. This allows the conductive gate electrodes in the gate trenches 11 of two adjacent cells 10 in the second direction P2 to be reliably electrically connected through the conductive connection portion 2. It is worth noting that the second direction P2 is perpendicular to the first direction P1. This layout not only optimizes the electrical performance of the device but also achieves efficient integrated design in terms of structure. Through this unique connection method, the device can further improve the overall current distribution uniformity and signal transmission efficiency while ensuring low-resistance connection. Furthermore, the placement of the conductive connection portion 2 also provides important technical support for further miniaturization and high-performance of the device.

[0062] Optionally, the conductive connection portion 2 can be made of polysilicon. This polysilicon conductive connection portion 2 partially covers the conductive gate electrode in the gate trench 11 of its adjacent cell 10 in the second direction P2. With this design, reliable electrical connections can be achieved between multiple cells 10, thereby optimizing the overall electrical performance and integration of the device.

[0063] In some examples, referring to Figure 15, cell 10 may also include an interlayer dielectric (ILD) layer 4, which is disposed on the side of silicon carbide body 1 away from the second surface 16, covering the source region 14, body region 13, gate structure 111 in gate trench 11, and conductive connection portion 2. This design further optimizes the electrical performance and reliability of the device. The interlayer dielectric layer 4 covers the source region 14, body region 13, gate structure 111, and conductive connection portion 2, effectively isolating electric field interference between different functional regions, reducing leakage current and parasitic effects, thereby improving the electrical performance of the device. The coverage of the interlayer dielectric layer 4 provides additional protection for the device, preventing the influence of external environments (such as humidity, impurities, etc.) on the device, and enhancing the stability of the device in complex operating environments.

[0064] In some examples, referring to Figures 2 and 16, cell 10 may further include a metal electrode 5 disposed on the side of interlayer dielectric layer 4 away from the first surface 15. Interlayer dielectric layer 4 serves to insulate the metal electrode 5 from the silicon carbide body 1 and the conductive connection portion 2. Multiple connection holes can be formed on the interlayer dielectric layer 4 by etching, including source connection holes and shielding region connection holes. These connection holes penetrate the interlayer dielectric layer 4. Source connection portions 3 can then be formed inside the source connection holes and shielding region connection holes, connecting the source connection portions 3 between the shielding region 12 and the metal electrode 5, and between the source region 14 and the metal electrode 5. This completes the connection between the metal electrode 5 and the source of the semiconductor device.

[0065] The interlayer dielectric layer 4 provides reliable insulation between the metal electrode 5, the silicon carbide body 1, and the conductive connection portion 2, effectively preventing leakage current and parasitic effects, thereby significantly improving the electrical performance and reliability of the device. Through the insulation layer, the electric field distribution is more uniform, reducing electric field concentration and further enhancing the device's withstand voltage. The source connection portion 3 penetrates the interlayer dielectric layer 4, directly connecting the shielding region 12, the source region 14, and the metal electrode 5, forming a low-resistance current path. This significantly reduces the source contact resistance and improves the device's conduction efficiency. The design of the source connection portion 3 makes the current distribution more uniform, reducing local current density concentration, thereby improving the device's stability and reliability under high current conditions.

[0066] In some examples, the conductive connection 2 is an annular conductive connection 2 that surrounds the source connection 3 connecting the shielding region 12 and the metal electrode 5, and the annular conductive connection 2 and the source connection 3 are spaced apart. By surrounding the source connection 3, the annular conductive connection 2 provides a compact and efficient electrical connection path. This surrounding structure enables multi-point contact within a limited space, thereby reducing contact resistance and improving current transmission efficiency.

[0067] In some exemplary embodiments of this disclosure, continuing to refer to FIG1, a plurality of cells 10 are staggered, and the projection of a cell 10 on the first direction P1 and the projection of its adjacent cell 10 on the first direction P1 partially overlap. Specifically, the silicon carbide body 1 is provided with staggered rectangular gate trenches 11 and shielding regions 12. The width of each gate trench 11 can be any value greater than or equal to 0.2 μm and less than or equal to 1.5 μm, and the depth can be greater than or equal to 0.5 μm. The depth of the gate trench 11 is any value less than or equal to 1.5 μm, and any value greater than or equal to 0.1 μm and less than or equal to 0.5 μm deeper than the body region. The gate oxide layer is attached to the sidewall and bottom surface of the trench, and the thickness range can be greater than or equal to 30 nm and less than or equal to 200 nm. The remaining part is filled with polysilicon. The gate polysilicon in adjacent trenches on the second direction P2 is interconnected by conductive connection part 2. The beginning and end ends of the gate trench 11 on the second direction P2 partially overlap with the adjacent shielding region 12. The depth of the shielding region 12 is any value greater than or equal to 0.1 μm and less than or equal to 1 μm deeper than the depth of the gate trench 11. The source connection part 3 in each shielding region 12 is short-circuited with the source metal electrode 5.

[0068] The semiconductor device in this embodiment of the disclosure forms a staggered structure by providing shielding regions 12 on both sides of the gate trench 11 and having adjacent cells 10 share a single shielding region 12. This design can simultaneously exert a shielding effect in two dimensions (first direction P1 and second direction P2), effectively suppressing the high electric field intensity at the bottom and sidewalls of the gate trench 11, thereby significantly reducing the electric field stress in the gate oxide layer, extending its lifespan, and improving the device's withstand voltage performance and reliability. The staggered structure allows adjacent cells 10 to share the shielding region 12, reducing the redundancy of the shielding region 12 and achieving higher cell 10 integration density without increasing additional area. Simultaneously, this design allows for further reduction of the cell 10 size, optimizing the device's area utilization, increasing the current density per unit area, and thus improving the overall performance of the device. Due to the reduction in cell 10 size and the optimized layout of the shielding region 12, the device structure is more compact, and the on-resistance is reduced. Furthermore, the optimized layout of the shielding region 12 allows for a shallower depth, reducing reliance on high-energy ion implantation and further optimizing the device's conduction characteristics. The reduction in on-resistance is particularly noticeable under high-temperature conditions, improving device efficiency. This structural design eliminates the need for complex secondary epitaxy or multiple trench etching processes, simplifying the overall process flow. Due to the dual shielding effect of the shielding region 12, the device exhibits better stability under extreme operating conditions such as high voltage, high current, and high temperature. This structure effectively prevents breakdown caused by electric field concentration, enhancing the device's robustness and making it more suitable for high-efficiency power applications, such as electric vehicles and industrial converters.

[0069] Furthermore, this disclosure also provides a method for manufacturing a semiconductor device, the semiconductor device including a plurality of cells 10 arranged in an array. Referring to FIG17, the process of forming cells 10 may include steps S1710 to S1740.

[0070] In step S1710, a silicon carbide body is provided, the silicon carbide body including a first surface and a second surface disposed opposite to the first surface.

[0071] The specific details of the silicon carbide body have been described in detail in the section on semiconductor devices, and can be found in the description of Figure 4. Therefore, they will not be repeated here.

[0072] In step S1720, two shielding regions are formed extending from the first surface of the silicon carbide body into the silicon carbide body. The two shielding regions are spaced apart along the first direction P1, and two adjacent cells 10 in the first direction P1 share a shielding region.

[0073] In one example embodiment of this disclosure, referring to FIG5, two shielding regions 12 spaced apart in the first direction P1 can be formed on the silicon carbide body 1. The shielding regions 12 extend from the body region 13 toward the silicon carbide body 1. The shielding regions 12 can protect the gate trench 11 and thereby reduce the electric field of the gate structure 111.

[0074] In step S1730, a gate trench is formed extending from the first surface of the silicon carbide body into the silicon carbide body, and the gate trench is disposed between two shielding regions in the first direction P1.

[0075] In one exemplary embodiment of this disclosure, referring to Figures 6 and 7, when forming the gate trench 11, a mask etching process can be used to etch the gate trench 11 onto the silicon carbide body 1. The formed gate trench 11 has sidewalls and a bottom. The specific location of the gate trench 11 can be customized based on user requirements, and will not be elaborated in this exemplary embodiment.

[0076] Optionally, the two shielding regions 12 are arranged symmetrically with respect to the gate trench 11.

[0077] In step S1740, a conductive connection portion is formed on the side of the shielding region away from the second surface, and the conductive gate electrodes in the gate trenches of two adjacent cells 10 in the second direction P2 are electrically connected through the conductive connection portion, wherein the first direction P1 is perpendicular to the second direction P2.

[0078] In some exemplary embodiments of this disclosure, referring to FIG14, after the shielding region 12 is formed, a conductive connection portion 2 may be formed on the side of the shielding region away from the second surface 16. The conductive connection portion 2 may be formed by deposition. Optionally, the conductive connection portion 2 may be polysilicon, i.e., the same material as the gate electrode. The conductive connection portion 2 is used to electrically connect the conductive gate electrodes in the gate trench 11 of two adjacent cells 10 in the second direction P2, so that the conductive gate electrodes in the plurality of cells 10 are connected.

[0079] In some examples, a shielding region 12 can be formed first on the silicon carbide body 1, which can be achieved by ion implantation. Specifically, when the second conductivity type is p-type, a p-type body mask can be fabricated first using photolithography, and then p-type impurities boron or aluminum can be implanted onto the p-type body mask to form the p-type shielding region 12. The doping concentration of the shielding region 12 is greater than the doping concentration of the body region 13.

[0080] After the shielding region 12 is formed, a gate trench 11 can be formed on the silicon carbide body 1, and a gate structure 111 can be formed in the gate trench 11. The gate structure 111 includes a conductive gate electrode. The formation of the gate trench 11 and the gate structure 111 can be referred to the introduction of semiconductor devices, and will not be elaborated here.

[0081] Optionally, the gate trench 11 is formed after the shielding region 12 is formed, and then the gate structure 111 is formed inside the gate trench 11. During the formation of the gate trench 11, the gate trench 11 may also be formed in part of the shielding region 12.

[0082] In some examples, referring to FIG13, the manufacturing method of the above-described semiconductor device may further include forming a body region 13 and a source region 14. Specifically, the body region 13 may first be formed on the silicon carbide body 1, and then the source region 14 may be formed between the body region 13 and the first surface 15. The body region 13 and the source region 14 are doped in opposite directions to form a pn junction. The conductivity type of the source region 14 is a first conductivity type, and the conductivity type of the body region 13 is a second conductivity type.

[0083] In some examples, the body region 13 contacts the sidewall of the gate trench 11, and the source region 14 contacts the sidewall of the gate trench 11, with the source region 14 located between the body region 13 and the first surface 15. The body region 13 has a second conductivity type, and the source region 14 has a first conductivity type.

[0084] Specifically, when the second conductivity type is p-type, a p-type body region mask can be fabricated first using photolithography, and then p-type impurity aluminum can be injected based on the p-type body region mask to form the p-type body region 13.

[0085] The process of forming the body region 13 and the source region 14 can be carried out before forming the gate trench 11, that is, firstly, dopants are introduced on the silicon carbide body 1 to form the body region 13 and the source region 14. Then, the gate trench 11 is formed on the silicon carbide body 1 by etching, and the gate structure 111 is formed in the gate trench 11.

[0086] The process for forming the body region 13 and the source region 14 can also occur after at least a portion of the gate trench 11 structure has been formed. The specific process flow can be customized based on requirements and will not be elaborated upon in this example embodiment.

[0087] After the formation of the body region 13 and the source region 14 is completed, referring to FIG14, a conductive connection portion 2 can be formed on the shielding region 12. The conductive connection portion 2 can be made of polysilicon and can be formed by deposition. The conductive connection portion 2 is disposed on the side of the shielding region 12 away from the second surface 16. This allows the conductive gate electrodes in the gate trenches 11 of two adjacent cells 10 in the second direction P2 to be reliably electrically connected through the conductive connection portion 2. The conductive connection portion 2 can be made of polysilicon and partially covers the conductive gate electrodes in the gate trenches 11 of the adjacent cells 10 in the second direction P2, thereby enabling electrical connection between multiple cells 10. That is, the gates of the cells 10 of the semiconductor device are connected through the conductive connection portion 2, and the sources are connected through the aforementioned source connection portion 3 and the aforementioned metal electrode 5. Multiple cells 10 are configured with a common drain.

[0088] In some examples, when manufacturing the aforementioned semiconductor device, the shielding region 12 and the body region 13 can first be formed on the silicon carbide body 1 by boron or aluminum ion implantation. The junction depth of the shielding region 12 and the body region 13 can be greater than or equal to 0.6 μm and less than or equal to 2.5 μm, and greater than or equal to 0.4 μm and less than or equal to 1 μm, respectively. Then, the source region 14 can be formed by nitrogen or phosphorus ion implantation. The junction depth can be any value greater than or equal to 0.1 μm and less than or equal to 0.5 μm. Subsequently, high-temperature activation annealing is performed, and the temperature range can be greater than or equal to 1600°C and less than or equal to 1900°C.

[0089] Optionally, the gate trench 11 is formed by reactive ion etching (RIE) process, and the depth can be any value greater than or equal to 0.5 μm and less than or equal to 1.5 μm. Optionally, a rounding process can be further used to improve the bottom morphology.

[0090] When forming the gate structure 111, a gate oxide layer can first be formed on the sidewalls and bottom using thermal oxidation, chemical vapor deposition, or a combination of both. The thickness can be greater than or equal to 30 nm and less than or equal to 200 nm. Then, the remaining trench is filled by chemical vapor deposition of the gate polysilicon, i.e., the conductive gate electrode. Excess polysilicon on the wafer surface can be removed by processes such as chemical mechanical polishing, leaving a thickness greater than or equal to 0.1 μm and less than or equal to 1.5 μm. Alternatively, polysilicon patterns can be formed using RIE (Reverse Engineering).

[0091] Before forming the interlayer dielectric layer 4, as shown in FIG14, a conductive connection portion 2 is formed on the side of the shielding region 12 away from the second surface. The conductive connection portion 2 can also be formed by chemical vapor deposition or by etching process to form the required shape. The material of the conductive connection portion 2 can be polysilicon, which is the same as the material of the conductive gate electrode in the gate structure described above.

[0092] When forming the interlayer dielectric layer 4, referring to Figure 15, the interlayer dielectric layer 4 can be formed by chemical vapor deposition and reflow, with a thickness ranging from greater than or equal to 0.2 μm to less than or equal to 1.5 μm. A portion of the interlayer dielectric layer is selectively removed by reactive ion etching to form interconnecting vias.

[0093] Metal is deposited using a sputtering process, with the main materials including but not limited to Al, AlCu, AlSi, and AlSiCu. The thickness can be greater than or equal to 2 μm and less than or equal to 6 μm. Then, a gate metal and source metal pattern is formed to form the metal electrode 5 through a wet etching process, a RIE etching process, or a combination of both. Alternatively, Cu metal can be formed as the metal electrode 5 through an electroplating process, with a thickness greater than or equal to 3 μm and less than or equal to 10 μm. The formation method of the metal electrode 5 can also be customized according to user requirements, which will not be elaborated in this example embodiment.

[0094] In some examples, metal W can be deposited first by CVD process and the source connection 3 can be formed by etching back, and then metal electrode 5 can be formed by sputtering or electroplating.

[0095] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0096] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention applied herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not claimed herein.

[0097] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes a plurality of cells (10) arranged in an array, each cell (10) comprising: The silicon carbide body (1) includes a first surface (15) and a second surface (16) disposed opposite to the first surface (15). A gate trench (11) extends from the first surface (15) into the silicon carbide body (1), and a conductive gate electrode is disposed in the gate trench (11); Two shielding regions (12) extend from the first surface (15) into the silicon carbide body (1) and are spaced apart on both sides of the gate trench (11) along the first direction (P1), and two adjacent cells (10) in the first direction (P1) share one shielding region (12). A conductive connection portion (2) is disposed on the side of the shielding area (12) away from the second surface (16). The conductive gate electrodes in the gate trenches (11) of two adjacent cells (10) in the second direction (P2) are electrically connected through the conductive connection portion (2), wherein the first direction (P1) is perpendicular to the second direction (P2).

2. The semiconductor device according to claim 1, characterized in that, The conductive connection portion (2) of the cell (10) partially covers the conductive gate electrode in the gate trench (11) of the cell (10) adjacent to it in the second direction (P2).

3. The semiconductor device according to claim 1, characterized in that, Multiple cells (10) are staggered, and the projection of the same cell (10) in the first direction (P1) and the projection of the cell (10) adjacent to it in the second direction (P2) in the first direction (P1) partially overlap.

4. The semiconductor device according to claim 1, characterized in that, Each of the cells (10) further includes: Body region (13) and source region (14), the body region (13) and the source region (14) are in contact with the sidewall of the gate trench (11), and the body region (13) is located between the source region (14) and the silicon carbide body (1).

5. The semiconductor device according to claim 4, characterized in that, Each of the cells (10) further includes: An interlayer dielectric layer (4) is disposed on the side of the silicon carbide body (1) away from the second surface (16) and covers the gate trench (11), the shielding area (12) and the conductive connection portion (2). A metal electrode (5) is disposed on the side of the interlayer dielectric layer (4) away from the first surface (15); The source connection portion (3) penetrates the interlayer dielectric layer (4) and is connected between the shielding region (12) and the metal electrode (5), as well as between the source region (14) and the metal electrode (5).

6. The semiconductor device according to claim 5, characterized in that, The conductive connection part (2) is an annular conductive connection part (2), which surrounds the source connection part (3) connected between the shielding area (12) and the metal electrode (5), and the annular conductive connection part (2) and the source connection part (3) are spaced apart.

7. A method for manufacturing a semiconductor device, said semiconductor device comprising a plurality of cells (10) arranged in an array, characterized in that, Forming each of the cells (10) includes: A silicon carbide body (1) is provided, the silicon carbide body (1) including a first surface (15) and a second surface (16) disposed opposite to the first surface (15); Two shielding regions (12) are formed extending from the first surface (15) of the silicon carbide body (1) into the silicon carbide body (1), the two shielding regions (12) are spaced apart along a first direction (P1), and two adjacent cells (10) in the first direction (P1) share one shielding region (12). A gate trench (11) is formed extending from the first surface (15) of the silicon carbide body (1) into the silicon carbide body (1), and the gate trench (11) is disposed between the two shielding regions (12) in a first direction (P1); A conductive connection portion (2) is formed on the side of the shielding area (12) away from the second surface (16), and the conductive gate electrodes in the gate trenches (11) of two adjacent cells (10) in the second direction (P2) are electrically connected through the conductive connection portion (2), wherein the first direction (P1) is perpendicular to the second direction (P2).

8. The method according to claim 7, characterized in that, The conductive connection part (2) includes polycrystalline silicon; The conductive connection portion (2) of the cell (10) partially covers the conductive gate electrode in the gate trench (11) of the cell (10) adjacent to it in the second direction (P2).

9. The method according to claim 7, characterized in that, Multiple cells (10) are staggered, and the projection of a cell (10) in the first direction (P1) and the projection of the cell (10) adjacent to it in the second direction (P2) in the first direction (P1) partially overlap.

10. The method according to claim 7, characterized in that, The method further includes: A body region (13) and a source region (14) are formed, the body region (13) and the source region (14) are in contact with the sidewall of the gate trench (11), and the body region (13) is located between the source region (14) and the silicon carbide body (1).

11. The method according to claim 10, characterized in that, The method further includes: An interlayer dielectric layer (4) is formed, which is disposed on the side of the silicon carbide body (1) away from the second surface (16) and covers the gate trench (11), the shielding area (12) and the conductive connection portion (2). A source connection portion (3) and a metal electrode (5) are formed. The metal electrode (5) is disposed on the side of the interlayer dielectric layer (4) away from the first surface (15). The source connection portion (3) penetrates the interlayer dielectric layer (4) and is connected between the shielding region (12) and the metal electrode (5), as well as between the source region (14) and the metal electrode (5).

12. The method according to claim 11, characterized in that, The conductive connection part (2) is an annular conductive connection part (2), which surrounds the source connection part (3) connected between the shielding area (12) and the metal electrode (5), and the annular conductive connection part (2) and the source connection part (3) are spaced apart.

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