Three-terminal type triple-junction tandem solar cell and manufacturing method therefor
Patent Information
- Application Number
- PCT/CN2025/114886
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-18
- Filing Date
- 2025-08-15
- Publication Date
- 2026-09-24
Smart Images
Figure CN2025114886_24092026_PF_FP_ABST
Abstract
Description
A three-terminal triple-junction tandem solar cell and its fabrication method Technical Field
[0001] This invention relates to the field of photovoltaics, and more particularly to a three-terminal triple-junction tandem solar cell and its preparation method. Background Technology
[0002] Tandem solar cells are a type of solar cell that has been developed in recent years. Tandem solar cells typically use two types of cells connected in series at the top and bottom (e.g., the perovskite-crystalline silicon cell in CN118414005A) to obtain a higher open-circuit voltage, which serves as the basis for achieving higher conversion efficiency.
[0003] Conventional tandem solar cells typically employ a double PN junction structure (referred to as "double junction"), resulting in the current mainstream "two-terminal" or "four-terminal" structures. To improve the efficiency of tandem solar cells, using a more efficient back-contact cell as the bottom cell, thus forming a unique "three-terminal" tandem solar cell structure, has become a new technological breakthrough. However, whether it's a "two-terminal," "four-terminal," or "three-terminal" structure, they are all further structural or process optimizations based on the conventional double junction structure, unable to achieve higher open-circuit voltages, severely hindering the further development of "three-terminal" tandem solar cells. Summary of the Invention
[0004] To address the aforementioned technical problems, this invention provides a three-terminal, three-junction tandem solar cell and its fabrication method. This invention further improves the conversion efficiency by optimizing the structure of the tandem solar cell.
[0005] The specific technical solution of the present invention is as follows: In a first aspect, the present invention provides a three-terminal triple-junction tandem solar cell, comprising: an N-type silicon substrate; the front side of the N-type silicon substrate is sequentially provided with a boron diffusion layer, a phosphorus diffusion layer, an interconnect layer, a hole transport layer, a perovskite layer, an electron transport layer, and a transparent conductive film; the back side of the N-type silicon substrate is provided with staggered p-regions and n-regions, the p-regions being boron diffusion layers and the n-regions being N-type silicon substrates, the back sides of the p-regions and n-regions being provided with passivation antireflection films, and the back sides of the p-regions and n-regions being provided with positive and negative electrodes, respectively. Conventional tandem solar cells consist of perovskite cells and HJT cells, while the tandem solar cell of this invention uses a BC cell with higher efficiency as the bottom cell. The BC cell of this invention has a double-junction structure, and its preparation process is very similar to that of conventional single-junction BC cells, without adding too many extra steps, resulting in lower process complexity and a higher degree of mass production capability. Conventional tandem solar cell structures consist of two-terminal perovskite cells and crystalline silicon cells to form a double-junction cell. By connecting the top cell in series with the bottom cell, a higher open-circuit voltage can be obtained compared to a single-junction cell (conventional cell open-circuit voltage ~0.7V, double-junction tandem cell open-circuit voltage >1V). The triple-junction cell constructed in this invention, through the series connection of three PN junctions, is expected to obtain an even higher open-circuit voltage than the double-junction cell.
[0006] Preferably, on the back side of the N-type silicon substrate, the boron diffusion layer is higher than the N-type silicon substrate.
[0007] Secondly, the present invention provides a method for fabricating the above-mentioned three-terminal triple-junction tandem solar cell, comprising the following steps: S1, polishing and oxidizing the back side of an N-type silicon substrate. After oxidation, an oxide layer (SiO2) is formed on the back side. x (A layer) can protect the back from corrosion during subsequent front texturing.
[0008] S2. Texturing the front side and acid etching to remove part of the oxide layer on the back side. Since the oxide layer effectively protects the back and sides of the silicon wafer from corrosion during alkaline texturing, maintaining the polished surface morphology, a pyramidal textured surface is formed on the front side. Furthermore, considering subsequent diffusion (under the same diffusion conditions), the front side has a textured structure (larger specific surface area), while the back side has a polished structure (smaller specific surface area). Therefore, the front side requires more boron diffusion sources, while the back side requires fewer. Thus, if a small portion of the oxide layer remains on the back side after texturing, during subsequent boron diffusion, the presence of this small oxide layer on the back side can prevent a large number of boron atoms from entering the back side of the silicon wafer, while the front side can allow relatively more boron atoms to enter, perfectly satisfying the purpose of this invention.
[0009] S3, double-sided boron diffusion; transforms both the front and back oxide layers of the N-type silicon substrate into a boron diffusion layer and a BSG layer.
[0010] S4. The laser sequentially loosens the BSG layer in the preset n-area on the back, the BSG layer on the front, and the BSG layer around the side.
[0011] During boron or phosphorus diffusion, conventional BSG and PSG layers can effectively block the inward diffusion of boron or phosphorus atoms. Therefore, this invention first uses laser processing to loosen the BSG layer in a predetermined n-region on the back side of the silicon wafer. This allows phosphorus atoms to further diffuse inward into the boron diffusion layer at the bottom of the BSG layer during subsequent phosphorus diffusion, transforming its surface into a phosphorus diffusion layer, while the BSG layer essentially transforms into a PSG layer simultaneously. Subsequently, laser processing is used again to loosen the BSG layer on the front side of the silicon wafer. It is important to note that compared to the back-side laser processing method, the specific surface area of the textured surface on the front side of the silicon wafer is larger, resulting in a correspondingly larger phosphorus doping concentration compared to the back side. Therefore, the degree to which the BSG layer is loosened by laser processing is greater, which facilitates the inward diffusion of phosphorus atoms during subsequent phosphorus diffusion, allowing the front-side BSG layer to also simultaneously transform into a PSG layer during the subsequent phosphorus diffusion process (this process saves the wet cleaning step compared to the conventional method of first removing the layer with laser and then wet cleaning). Finally, the BSG layer on the side is treated synchronously under the same frontal laser parameters to loosen the BSG layer on the side. This allows the BSG layer on the side to be basically transformed into a PSG layer during the subsequent phosphorus diffusion process. Therefore, the difference in the dissolution rate of different oxide layers in HF can be utilized in the subsequent chain wet deoxide removal step.
[0012] S5, double-sided phosphorus diffusion; transforms the surface of the front boron diffusion layer into a phosphorus diffusion layer and a PSG layer, while transforming the BSG layer in the preset n region on the back into a PSG layer and the surface of the bottom boron diffusion layer into a phosphorus diffusion layer.
[0013] S6, the back side undergoes chain-like acid cleaning, alkaline cleaning, and acid cleaning in sequence.
[0014] Conventional HF solutions can remove oxide layers, but the dissolution rates of different doped oxide layers in HF solutions vary, i.e., PSG layer dissolution rate > BPSG layer > BSG layer. This is because phosphorus-doped oxide layers have a larger number of electrons. When reacting with HF solution, the oxide layer with more electrons is more prone to electron gain and loss reactions, resulting in higher solubility. Therefore, after the aforementioned S4 laser treatment + S5 phosphorus diffusion, the BSG layer deposited on the surface and sides of the preset n-region on the back of the silicon wafer is essentially transformed into a PSG layer (the initial BSG layer has been completely loosened by the laser). However, the surface BSG layer of the boron diffusion layer on the back of the silicon wafer is not treated by the laser; during the phosphorus diffusion process, only a small portion of phosphorus atoms enter the BSG layer, forming the so-called BPSG layer (boron-phosphorus co-doped oxide layer). Therefore, this difference can be utilized to control the reaction conditions during acid cleaning to remove the PSG layer deposited on the surface and sides of the preset n-region first, while the BPSG layer on the surface of the boron diffusion layer can still be partially retained. The diffusion layer at the bottom of the pre-defined n-region surface on the back of the silicon wafer is then removed via a subsequent chain-type alkaline polishing bath until the N-type silicon substrate is exposed. Since some BPSG layer remains on the surface of the boron diffusion layer on the back of the wafer, this portion is protected from damage during the chain-type alkaline polishing process. Furthermore, for the side-mounted areas of the silicon wafer, since the side PSG layer has been removed, this portion can also be removed simultaneously during the chain-type alkaline polishing process, thus preventing edge leakage. For the front of the silicon wafer, the chain-type "floating on water" alkaline polishing method protects the diffusion layers on the front side from damage due to both the water film and the presence of the PSG layer. Finally, a second acid cleaning step removes all remaining BSG, BPSG, and PSG layers from both the front and back of the silicon wafer.
[0015] S7, back coating.
[0016] S8, positive and negative electrodes are formed on the back side.
[0017] S9. Remove the front oxide layer.
[0018] S10, an interconnect layer, a hole transport layer, a perovskite layer, an electron transport layer, and a transparent conductive film are sequentially deposited on the front side.
[0019] S11, the front side forms the negative electrode.
[0020] Preferably, in S1, a wet chain acid bath is used to polish and oxidize the back side of the N-type silicon substrate, wherein the concentration of HNO3 in the acid bath is 30-70 wt%, the concentration of H2SO4 is 2-5 wt%, and the concentration of H3PO4 is 5-20 wt%.
[0021] The purpose of the oxidation process is to form an oxide layer on the back side (single side) of the silicon wafer. However, considering the subsequent diffusion process (under the same diffusion conditions), since the front side has a textured structure (larger specific surface area) and the back side has a polished structure (smaller specific surface area), the front side requires more boron diffusion sources, while the back side requires fewer. If the oxide layer formed by oxidation is denser and thicker, and a small portion of the oxide layer remains on the back side after the texturing process in step S2, then during the subsequent boron diffusion process, the presence of this small portion of oxide layer on the back side can prevent a large number of boron atoms from entering the back side of the silicon wafer, while the front side can allow relatively more boron atoms to enter, which perfectly satisfies the purpose of this invention. Therefore, in order to make the oxide layer formed by oxidation of silicon wafers denser and thicker, the wet solution of the chain oxidation tank uses a mixture of multiple acids such as HNO3, H2SO4, and H3PO4. Among them, HNO3 plays a strong oxidizing role; H2SO4 partly plays a strong oxidizing role, and on the other hand, H2SO4 is an oily and viscous substance that can improve the surface tension of silicon wafers, so that the oxidation of the entire back side of the silicon wafer is sufficient and uniform. Since HNO3 and H2SO4 are volatile, and their strong oxidizing properties require a large number of H ions, adding H3PO4 can act as a stabilizer for the solution, providing sufficient H ions to the solution, and H3PO4 is not easily volatile.
[0022] Preferably, in S2, the acid washing conditions are: HF solution concentration 2-10 wt%, time 20-60 s.
[0023] In order to preserve the oxide layer formed during the oxidation process on the back of the silicon wafer in step S1, the acid concentration and cleaning time need to be further reduced compared to conventional pickling processes.
[0024] Preferably, in S3, the boron diffusion conditions are: diffusion temperature 900–950℃, time 20–80 min, BCl3 flow rate 100–300 sccm, O2 flow rate 500–3000 sccm; oxidation propagation temperature 1000–1050℃, O2 flow rate 1000–20000 sccm, time 60–120 min; the resulting BSG layer thickness is 30–80 nm; and the boron atom surface doping concentration is 1E18–7E18 cm⁻¹. -3 The doping depth is 0.7–1.5 μm.
[0025] Preferably, in S4, the laser conditions for the BSG layer in the pre-defined n-region on the back side are: using an ultraviolet nanosecond laser, wavelength 200–400 nm, power 1–5 W, time 1–3 s, and frequency 50–100 kHz; the laser conditions for the BSG layer on the front side are: using an ultraviolet nanosecond laser, wavelength 200–400 nm, power 5–20 W, time 5–10 s, and frequency 10–20 kHz. Compared to the back side laser treatment method, because the specific surface area of the textured surface on the front side of the silicon wafer is larger, the corresponding subsequent phosphorus doping amount is also larger than that on the back side. Therefore, the laser loosening of the BSG layer is more significant, which helps the phosphorus atoms to diffuse inward during the subsequent phosphorus diffusion process. As a result, the front side BSG layer is basically transformed into a PSG layer during the subsequent phosphorus diffusion (compared to the conventional method of first removing with laser and then wet cleaning, this process can save the wet cleaning step). Since the laser loosening energy is higher than that of the laser treatment on the back side of the silicon wafer, the boron doped atoms in the BSG layer can be pushed into the front side boron diffusion layer, further compensating for the slightly larger requirement of the front side boron diffusion source in S3.
[0026] Since the side-coated portion needs to be removed simultaneously during the subsequent chain cleaning process, the laser conditions for the side-coated BSG layer are (similar to the front laser treatment conditions): using an ultraviolet nanosecond laser with a wavelength of 200–400 nm, a power of 5–20 W, a time of 5–10 s, and a frequency of 10–20 kHz.
[0027] The purpose of employing the aforementioned laser conditions in this invention is as follows: First, ultraviolet lasers penetrate silicon wafers much shallower than green and infrared lasers, allowing for more effective treatment of the BSG layer on the silicon wafer surface without causing significant laser damage to the underlying boron diffusion layer. Second, higher laser power results in higher energy per laser beam, which more effectively loosens the surface BSG layer, allowing for the introduction of more dopant sources. Third, the laser processing time follows a similar principle to power; longer processing times result in greater luminous flux injected by the laser, making it easier to loosen the BSG layer on the silicon wafer surface. Finally, different laser frequencies significantly affect the energy of a single laser beam. When the laser output power is constant, lower frequencies generally result in higher energy per laser beam, and vice versa. This is because the energy of a single laser beam is related to the repetition frequency of the laser, while the output power is the product of the energy of a single laser beam and the repetition frequency. Specifically, the repetition frequency refers to the number of laser pulses emitted per unit time. With a fixed output power, the repetition frequency affects the energy of a single pulse. Increasing the repetition frequency leads to a decrease in the energy of a single pulse because the output power is fixed, and more pulses mean less energy carried by each pulse. Conversely, if the frequency increases, the energy of a single pulse will decrease accordingly to maintain a constant output power. This is because the output power is the product of the energy of a single pulse and the repetition frequency; increasing the frequency inevitably leads to a decrease in the energy of a single pulse. By limiting the laser parameters within a reasonable range, the required doping levels on the front and back sides of the silicon wafer (the front side requires a higher doping level than the back side) can be controlled during the subsequent phosphorus diffusion process.
[0028] Preferably, in S5, the phosphorus diffusion conditions are: diffusion temperature 750–850℃, time 5–30 min, POCl3 flow rate 500–2500 sccm, O2 flow rate 500–3000 sccm; oxidation propagation temperature 850–950℃, time 5–60 min, O2 flow rate 1000–10000 sccm; the resulting PSG layer thickness is 30–70 nm; and the phosphorus atom surface doping concentration is 1E19–8E19 cm⁻¹. -3 The doping depth is 0.2–0.4 μm.
[0029] Preferably, in S6, the conditions for the first acid cleaning are: HF solution concentration 10-40 wt%, belt speed 1-3 m / min; the conditions for the alkaline cleaning are: KOH solution concentration 1.7-2.2 wt%, belt speed 1-6 m / min; the second acid cleaning is performed by spraying with HF solution, with an HF solution concentration of 20-60 wt%. Preferably, in S10, the material of the hole transport layer is 2,2',7,7'-tetra(N,N-di-p-toluidine)spirofluorene, poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine], nickel oxide, cuprous iodide, or copper thiocyanate; the material of the perovskite layer is methylamine lead iodide, formamidinium lead iodide, or cesium lead halide; and the material of the electron transport layer is TiO2, ZnO, or SnO2.
[0030] Thirdly, the present invention provides another method for fabricating a three-terminal triple-junction tandem solar cell, comprising: S1, polishing and oxidizing the back side of an N-type silicon substrate; S2, texturing the front side and acid washing to remove part of the oxide layer on the back side; S3, primary boron diffusion; removal of the front side BSG layer; secondary boron diffusion; S4, sequentially loosening the BSG layer in the predetermined n-region on the back side, the BSG layer on the front side, and the BSG layer coated around the side using laser; S5, phosphorus diffusion; primary phosphorus diffusion; removal of the front side PSG layer; secondary phosphorus diffusion; S6, sequentially performing chain-like acid cleaning, alkaline cleaning, and acid cleaning on the back side; S7, coating the back side; S8, forming positive and negative electrodes on the back side; S9, removing the oxide layer on the front side; S10, sequentially depositing an interconnect layer, a hole transport layer, a perovskite layer, an electron transport layer, and a transparent conductive film on the front side; S11, forming the negative electrode on the front side.
[0031] This invention discovers that in the first preparation method provided by this invention, during boron and phosphorus diffusion, the specific surface area of the front side (pyramidal textured surface) of the silicon wafer is larger than that of the back side (polished surface), making it impossible to simultaneously meet the boron or phosphorus atom doping requirements of both the front and back sides under the same diffusion conditions (the doping concentration and depth of the front side are often lower than that of the back side). To further meet the front diffusion requirements, the second method provided by this invention performs secondary diffusion processes for both boron and phosphorus diffusion, thereby satisfying the performance requirements.
[0032] Preferably, in S3, the primary boron diffusion conditions are: diffusion temperature 900–950℃, time 20–80 min, BCl3 flow rate 100–300 sccm, O2 flow rate 500–3000 sccm; oxidation propagation temperature 1000–1050℃, O2 flow rate 1000–20000 sccm, time 60–120 min; the resulting BSG layer thickness is 30–80 nm; and the boron atom surface doping concentration is 1E18–7E18 cm⁻¹. -3The doping depth was 0.7–1.5 μm; the secondary boron diffusion conditions were: diffusion temperature 900–950 °C, time 10–30 min, BCl3 flow rate 20–100 sccm, O2 flow rate 200–1000 sccm; oxidation propagation temperature 1000–1050 °C, O2 flow rate 1000–20000 sccm, time 10–50 min; the resulting BSG layer thickness was 30–70 nm; and the boron atom surface doping concentration was 5E18–2E19 cm⁻¹. -3 The doping depth is 1.0–2.0 μm. Preferably, in S5, the primary phosphorus diffusion conditions are: diffusion temperature 750–850 °C, time 5–30 min, POCl3 flow rate 500–2500 sccm, O2 flow rate 500–3000 sccm; oxidation propagation temperature 850–950 °C, time 5–60 min, O2 flow rate 1000–10000 sccm; the resulting PSG layer thickness is 30–70 nm; and the phosphorus atom surface doping concentration is 1E19–8E19 cm⁻¹. -3 The doping depth was 0.2–0.4 μm; the secondary phosphorus diffusion conditions were: diffusion temperature 750–850 °C, time 2–10 min, POCl3 flow rate 200–1000 sccm, O2 flow rate 300–2000 sccm; oxidation propagation temperature 850–950 °C, time 2–10 min, O2 flow rate 300–2000 sccm; the resulting PSG layer thickness was 20–60 nm; and the phosphorus atom surface doping concentration was 5E19–3E20 cm⁻¹. -3 The doping depth is 0.3–0.5 μm.
[0033] Compared with the prior art, the beneficial effects of the present invention are: (1) The present invention provides a three-terminal triple junction tandem solar cell, and the present invention further improves the conversion efficiency by optimizing the structure of the tandem solar cell.
[0034] (2) This invention provides two different preparation methods for fabricating the above-described three-terminal triple-junction tandem solar cell. The second method can further meet the requirements for boron or phosphorus atom doping on the front / back side, thereby improving the cell performance. Attached Figure Description
[0035] Figure 1 is a schematic diagram of the structure of a silicon wafer after single-sided polishing.
[0036] Figure 2 is a schematic diagram of the structure of the back side of the silicon wafer after oxidation.
[0037] Figure 3 is a schematic diagram of the structure of the silicon wafer after texturing the front side.
[0038] Figure 4 is a schematic diagram of the structure of the silicon wafer after boron diffusion (the back oxide layer is not shown in the figure due to its thinness).
[0039] Figure 5 is a schematic diagram of the structure of a silicon wafer after phosphorus diffusion.
[0040] Figure 6 is a schematic diagram of the structure after the silicon wafer chain cleaning.
[0041] Figure 7 is a schematic diagram of the structure after a passivation antireflective film is deposited on one side of the back of a silicon wafer and a high-temperature paste is screen-printed.
[0042] Figure 8 is a schematic diagram of the structure after a perovskite layer is deposited on the surface of a silicon wafer.
[0043] Figure 9 is a schematic diagram of a three-terminal triple-junction tandem solar cell.
[0044] The attached figures are labeled as follows: 1. N-type silicon substrate; 2. Oxide layer; 3. Pyramidal textured surface; 4. Boron diffusion layer; 5. BSG layer; 6. Phosphorus diffusion layer; 7. PSG layer; 8. Passivation antireflection film; 9. Interconnect layer; 10. Hole transport layer; 11. Perovskite layer; 12. Electron transport layer; 13. Transparent conductive film; 14. Positive electrode; 15. Negative electrode. Detailed Implementation
[0045] The present invention will be further described below with reference to embodiments.
[0046] In a first aspect of the general embodiments, the present invention provides a three-terminal triple-junction tandem solar cell, comprising: an N-type silicon substrate; the front side of the N-type silicon substrate is sequentially provided with a boron diffusion layer, a phosphorus diffusion layer, an interconnect layer, a hole transport layer, a perovskite layer, an electron transport layer, and a transparent conductive film; the back side of the N-type silicon substrate is provided with staggered p-regions and n-regions, the p-regions being boron diffusion layers and the n-regions being N-type silicon substrates, the back sides of the p-regions and n-regions being provided with passivation antireflection films, and the back sides of the p-regions and n-regions being respectively provided with a positive electrode and a negative electrode.
[0047] In some preferred embodiments, the boron diffusion layer is higher than the N-type silicon substrate on the back side.
[0048] Secondly, the present invention provides a method for preparing the above-mentioned three-terminal triple-junction tandem solar cell, which includes the following steps: S1, polishing and oxidizing the back side of an N-type silicon substrate.
[0049] In some preferred embodiments, S1 includes: selecting an N-type silicon substrate cut by diamond wire, and performing back-side polishing and oxidation treatment through a wet chain acid bath, wherein the concentration of HNO3 in the acid bath is 30-70 wt%, the concentration of H2SO4 is 2-5 wt%, and the concentration of H3PO4 is 5-20 wt%; the temperature is room temperature, and the belt speed is 1-10 m / min.
[0050] S2, front side is lined, and acid pickling removes part of the oxide layer on the back side.
[0051] In some preferred embodiments, S2 includes: placing a silicon wafer with oxide layers on its back and sides into an alkaline texturing bath for single-sided texturing, wherein the alkaline concentration is 1.5–2.2 wt%, the temperature is 75–85°C, and the time is 6–8 min. Since the oxide layer effectively protects the back and sides of the silicon wafer from corrosion during the alkaline texturing process, it maintains the polished surface morphology, while reducing the thinning amount required for single-sided texturing. Subsequently, the acid cleaning tank (HF) integrated into the chain machine further removes some of the oxide layer present on the surface. The acid cleaning conditions are: HF solution concentration 2–10 wt%, time 20–60 s.
[0052] S3, double-sided boron diffusion; transforms both the front and back oxide layers of the N-type silicon substrate into a boron diffusion layer and a BSG layer.
[0053] In some preferred embodiments, in S3, the boron diffusion conditions are: diffusion temperature 900–950℃, time 20–80 min, BCl3 flow rate 100–300 sccm, O2 flow rate 500–3000 sccm; oxidation propagation temperature 1000–1050℃, O2 flow rate 1000–20000 sccm, time 60–120 min, resulting in a BSG layer thickness of 30–80 nm and a boron atom surface doping concentration of 1E18–7E18 cm⁻¹. -3 The doping depth is 0.7–1.5 μm.
[0054] S4. The laser sequentially loosens the BSG layer in the preset n-area on the back, the BSG layer on the front, and the BSG layer around the side.
[0055] In some preferred embodiments, in S4, the laser conditions for the BSG layer in the pre-defined n-region on the back side are: using an ultraviolet nanosecond laser with a wavelength of 200–400 nm, a power of 1–5 W, a duration of 1–3 s, and a frequency of 50–100 kHz; the laser conditions for the BSG layer on the front side and the BSG layer coated around the side side are: using an ultraviolet nanosecond laser with a wavelength of 200–400 nm, a power of 5–20 W, a duration of 5–10 s, and a frequency of 10–20 kHz.
[0056] S5, double-sided phosphorus diffusion; transforms the surface of the front boron diffusion layer into a phosphorus diffusion layer and a PSG layer, while transforming the BSG layer in the preset n region on the back into a PSG layer and the surface of the bottom boron diffusion layer into a phosphorus diffusion layer.
[0057] In some preferred embodiments, in S5: the phosphorus diffusion conditions are as follows: phosphorus diffusion temperature 750–850℃, diffusion time 5–30 min, POCl3 carried by nitrogen gas at a flow rate of 500–2500 sccm, and O2 flow rate of 500–3000 sccm; followed by oxidation propagation at a temperature of 850–950℃, a propagation time of 5–60 min, and an O2 flow rate of 1000–10000 sccm, resulting in a PSG layer thickness of 30–70 nm and a phosphorus atom surface doping concentration of 1E19–8E19 cm⁻¹. -3 The doping depth is 0.2–0.4 μm.
[0058] S6. The back side undergoes a chain of acid cleaning, alkali cleaning, and acid cleaning in sequence. Conventional HF solution can remove the oxide layer, but the dissolution rate of different doped oxide layers in HF solution varies, i.e., PSG layer dissolution rate > BPSG layer > BSG layer. This is because the phosphorus-doped oxide layer has a larger number of electrons. When reacting with HF solution, the oxide layer with more electrons is more prone to electron gain and loss reactions, resulting in higher solubility. Therefore, after the above S4 laser treatment + S5 phosphorus diffusion, the BSG layer deposited on the surface and sides of the preset n-region on the back of the silicon wafer is basically transformed into a PSG layer (the initial BSG layer has been completely loosened by the laser). However, the surface BSG layer of the boron diffusion layer area on the back of the silicon wafer is not laser treated. During the phosphorus diffusion process, only a small portion of phosphorus atoms enter the BSG layer, forming the so-called BPSG layer (boron and phosphorus co-doped oxide layer). Therefore, this difference can be utilized to control the reaction conditions during acid cleaning to remove the PSG layer deposited on the surface and sides of the preset n-region first, while the BPSG layer on the surface of the boron diffusion layer can still be partially retained. The diffusion layer at the bottom of the pre-defined n-region surface on the back of the silicon wafer is then removed via a subsequent chain-type alkaline polishing bath until the N-type silicon substrate is exposed. Since some BPSG layer remains on the surface of the boron diffusion layer on the back of the wafer, this portion is protected from damage during the chain-type alkaline polishing process. Furthermore, for the side-mounted areas of the silicon wafer, since the side PSG layer has been removed, this portion can also be removed simultaneously during the chain-type alkaline polishing process, thus preventing edge leakage. For the front of the silicon wafer, the chain-type "floating on water" alkaline polishing method protects the diffusion layers on the front side from damage due to both the water film and the presence of the PSG layer. Finally, a second acid cleaning step removes all remaining PSG, BPSG, and other layers from both the front and back of the silicon wafer.
[0059] In some preferred embodiments, the conditions for the first acid cleaning are: HF solution concentration of 10-40 wt% and belt speed of 1-3 m / min; the conditions for the alkaline cleaning are: KOH solution concentration of 1.7-2.2 wt% and belt speed of 1-6 m / min; the second acid cleaning is carried out by acid spraying with an HF solution concentration of 20-60 wt%.
[0060] S7, with passivation and anti-reflective coating on the back.
[0061] In some preferred embodiments, S7 includes: depositing AlO on the back side of the processed silicon wafer using a plate-type ALD deposition method. x The thin film, formed by the reaction of Al(CH3)3 with water vapor, has a thickness of 8–10 nm, and the process temperature is controlled at 220–280 °C. Subsequently, SiN is deposited on the back side of a silicon wafer using a plate-type PECVD equipment. x Film, in which SiN x The film thickness is 80–120 nm, and the refractive index is 1.9–2.1. The reactant gases in the tubular cavity are SiH4 and NH3. The operating pressure is 1500–1700 mTorr, the power is 10000–15000 W, the temperature is 400–600 °C, the SiH4 gas flow rate is 900–2000 sccm, the NH3 gas flow rate is 7000–12000 sccm, and the deposition time is 5–20 min. Because a perovskite portion needs to be deposited on the front side of the subsequent battery, AlO2 cannot be covered on the front side. x and SiN x Related insulating dielectric films.
[0062] S8, positive and negative electrodes are formed on the back side.
[0063] In some preferred embodiments, S8 includes: screen printing a high-temperature paste, sintering; subsequently, screen printing a high-temperature paste on one side of the back of the silicon wafer, wherein the negative electrode is printed on the n-region surface on the back of the N-type silicon substrate, the positive electrode is printed on the boron diffusion layer, and then sintering at 700-800°C to form an ohmic contact.
[0064] S9. Remove the front oxide layer.
[0065] In some preferred embodiments, S9 includes: since an oxide layer inevitably forms on the front side of the silicon wafer during the high-temperature sintering process, a chain acid (HF) cleaning machine is required to remove the surface oxide layer after the subsequent deposition of the perovskite layer, wherein the concentration of the HF solution in the chain machine is 20-80 wt% and the belt speed is 0.5-5 m / min.
[0066] S10, an interconnect layer, a hole transport layer, a perovskite layer, an electron transport layer, and a transparent conductive film are sequentially deposited on the front side.
[0067] In some preferred embodiments, S10 includes: depositing perovskite on the front side of the silicon wafer: first, depositing an intermediate interconnect layer, for example, depositing a transparent conductive film (TCO layer) using PVD; then, depositing a hole transport layer on the TCO layer using a coating-like method, the material of which can be 2,2',7,7'-tetratetra(N,N-di-p-toluidine)spirofluorene, poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine], nickel oxide, cuprous iodide, or copper thiocyanate, etc., followed by S10... Annealing and crystallization are performed at 0–300℃; then, a perovskite layer is deposited on the hole transport layer using a coating-like method. The material of this layer can be lead methylamine iodine, lead formamidinium iodine, cesium lead halide, etc., followed by annealing and crystallization at 100–300℃; an electron transport layer is further deposited on the perovskite layer using PVD or other methods. The material of this layer can be TiO2, ZnO, SnO2, etc., followed by annealing and crystallization at 100–300℃; finally, a TCO layer is deposited on the electron transport layer using PVD or other methods.
[0068] S11, the front side forms the negative electrode.
[0069] In some preferred embodiments, S11 includes: screen printing a low-temperature paste and sintering; screen printing a low-temperature paste on the tandem battery to print a negative electrode on the front side (on the transparent conductive film layer on the surface of the electron transport layer), and then sintering at a low temperature of 200-300°C to form an ohmic contact, thereby obtaining the final "three-terminal" (one positive electrode and two negative electrodes) triple-junction battery structure.
[0070] Thirdly, the present invention provides another method for fabricating a three-terminal triple-junction tandem solar cell, comprising: S1, polishing and oxidizing the back side of an N-type silicon substrate; S2, texturing the front side and acid washing to remove part of the oxide layer on the back side; S3, primary boron diffusion; removal of the front side BSG layer; secondary boron diffusion; S4, sequentially loosening the BSG layer in the predetermined n-region on the back side, the BSG layer on the front side, and the BSG layer coated around the side using laser; S5, phosphorus diffusion; primary phosphorus diffusion; removal of the front side PSG layer; secondary phosphorus diffusion; S6, sequentially performing chain-like acid cleaning, alkaline cleaning, and acid cleaning on the back side; S7, coating the back side; S8, forming positive and negative electrodes on the back side; S9, removing the oxide layer on the front side; S10, sequentially depositing an interconnect layer, a hole transport layer, a perovskite layer, an electron transport layer, and a transparent conductive film on the front side; S11, forming the negative electrode on the front side.
[0071] In some preferred embodiments, in S3, the primary boron diffusion conditions are: diffusion temperature 900–950℃, time 20–80 min, BCl3 flow rate 100–300 sccm, O2 flow rate 500–3000 sccm; oxidation propagation temperature 1000–1050℃, O2 flow rate 1000–20000 sccm, time 60–120 min, resulting in a BSG layer thickness of 30–80 nm and a boron atom surface doping concentration of 1E18–7E18 cm⁻¹. -3 The doping depth was 0.7–1.5 μm; the secondary boron diffusion conditions were: diffusion temperature 900–950 °C, time 10–30 min, BCl3 flow rate 20–100 sccm, O2 flow rate 200–1000 sccm; oxidation propagation temperature 1000–1050 °C, O2 flow rate 1000–20000 sccm, time 10–50 min; the resulting BSG layer thickness was 30–70 nm; and the boron atom surface doping concentration was 5E18–2E19 cm⁻¹. -3 The doping depth is 1.0–2.0 μm. In some preferred embodiments, in S5, the primary phosphorus diffusion conditions are: diffusion temperature 750–850 °C, time 5–30 min, POCl3 flow rate 500–2500 sccm, O2 flow rate 500–3000 sccm; oxidation propagation temperature 850–950 °C, time 5–60 min, O2 flow rate 1000–10000 sccm, resulting in a PSG layer thickness of 30–70 nm and a phosphorus atom surface doping concentration of 1E19–8E19 cm⁻¹. -3 The doping depth was 0.2–0.4 μm; the secondary phosphorus diffusion conditions were: diffusion temperature 750–850 °C, time 2–10 min, POCl3 flow rate 200–1000 sccm, O2 flow rate 300–2000 sccm; oxidation propagation temperature 850–950 °C, time 2–10 min, O2 flow rate 300–2000 sccm; the resulting PSG layer thickness was 20–60 nm; and the phosphorus atom surface doping concentration was 5E19–3E20 cm⁻¹. -3 The doping depth is 0.3–0.5 μm.
[0072] Specific Embodiment and Comparative Example 1: A three-terminal triple-junction tandem solar cell, as shown in Figure 9, includes: an N-type silicon substrate 1; the front side of the N-type silicon substrate is sequentially provided with a boron diffusion layer 4, a phosphorus diffusion layer 6, an interconnect layer 9, a hole transport layer 10, a perovskite layer 11, an electron transport layer 12, and a transparent conductive film 13; the back side of the N-type silicon substrate is provided with staggered p-regions and n-regions, the p-regions being boron diffusion layers and the n-regions being N-type silicon substrates, the back sides of the p-regions and n-regions are provided with passivation antireflection films 8, and the back sides of the p-regions and n-regions are respectively provided with a positive electrode 14 and a negative electrode 15. Wherein, on the back side of the N-type silicon substrate, the boron diffusion layer is higher than the N-type silicon substrate.
[0073] The fabrication method of the above-mentioned three-terminal triple-junction tandem solar cell includes the following steps: S1, back-side polishing and oxidation of N-type silicon substrate: An N-type silicon substrate 1, cut with diamond wire, is selected and back-side polished and oxidized using a wet chain acid bath. The acid bath contains 60 wt% HNO3, 3 wt% H2SO4 solution, and 8 wt% H3PO4 solution; the temperature is room temperature, and the belt speed is 5 m / min. During the process, a water film covers the front side of the silicon wafer, preventing corrosion during acid polishing, as shown in Figure 1. Immediately afterward, the acid-polished silicon wafer undergoes a chain wet oxidation process, which forms an oxide layer 2 (SiO2) on the back and sides of the silicon wafer. x The silicon wafer is coated with a water film on the front side (as shown in Figure 2), while the front side is still covered with a water film to prevent oxidation. These two steps can be completed in a single chain conveyor, reducing process complexity.
[0074] S2. Front-side texturing: Silicon wafers with oxide layers on the back and sides are placed in an alkaline texturing bath for single-sided texturing, forming a pyramidal textured surface 3 on the front side. The alkaline concentration is 1.7wt%, the temperature is 80℃, and the time is 7 minutes. Because the oxide layer effectively protects the back and sides of the silicon wafer from corrosion during the alkaline texturing process, it maintains the polished surface morphology and reduces the thinning amount required for single-sided texturing. Subsequently, the chain-type machine's built-in acid cleaning tank (HF) further removes the oxide layer on the surface, as shown in Figure 3. The acid cleaning conditions are: HF concentration 5wt%, time 50 seconds.
[0075] S3. Double-sided boron diffusion: This transforms both the front and back oxide layers of the N-type silicon substrate into a boron diffusion layer 4 and a BSG layer 5, as shown in Figure 4. The boron diffusion conditions are: diffusion temperature 930℃, time 60 min, BCl3 flow rate 200 sccm, O2 flow rate 1200 sccm; oxidation propagation temperature 1050℃, O2 flow rate 8000 sccm, time 80 min. The resulting BSG layer thickness is approximately 50 nm, and the boron atom surface doping concentration is approximately 5E18 cm⁻¹. -3 The doping depth is approximately 1.2 μm.
[0076] S4. The laser sequentially loosens the BSG layer in the pre-defined n-region on the back, the BSG layer on the front, and the BSG layer coated around the side. Specifically: the laser conditions for the BSG layer in the pre-defined n-region on the back are: using an ultraviolet nanosecond laser, wavelength 266nm, power 3W, time 2.5s, frequency 70kHz; the laser conditions for the BSG layer on the front and the BSG layer coated around the side are: using an ultraviolet nanosecond laser, wavelength 266nm, power 9W, time 7s, frequency 12kHz.
[0077] S5. Phosphorus doping of silicon wafers is performed using phosphorus diffusion. First, the BSG layers on the front and sides of the silicon wafer have been largely loosened by laser diffusion. During phosphorus diffusion, the front and side portions can be transformed into phosphorus diffusion layer 6 and PSG layer 7, respectively. It should be noted that because the boron diffusion layer on the front is relatively thick, the shallow diffusion depth during phosphorus diffusion can cause the surface of the boron diffusion layer to transform into a phosphorus diffusion layer, thus forming a layered structure. For the BSG layer in the pre-defined n-region on the back of the silicon wafer, the degree of laser loosening is less, and the amount of phosphorus diffused into the pre-defined n-region is less than that on the front, which perfectly meets the experimental objective, as shown in Figure 5.
[0078] The phosphorus diffusion conditions were as follows: phosphorus diffusion temperature 790℃, diffusion time 15 min, POCl3 carried by nitrogen gas at a flow rate of 1200 sccm, and O2 flow rate of 2000 sccm; followed by oxidation propagation at 890℃ for 20 min, with an O2 flow rate of 5000 sccm. The resulting PSG layer thickness was approximately 20 nm, and the phosphorus atom surface doping concentration was approximately 7E19 cm⁻¹. -3 The doping depth is approximately 0.25 μm.
[0079] S6. The back side sequentially undergoes chain-type acid cleaning, alkali cleaning, and acid cleaning, as shown in Figure 6. The conditions for the first acid cleaning are: HF solution concentration of 15wt% and belt speed of 3m / min. The conditions for the alkali cleaning are: KOH solution concentration of 2.0wt% and belt speed of 2m / min. The second acid cleaning is carried out by acid spraying, with the condition that the HF solution concentration is 50wt%.
[0080] S7, Backside passivation and antireflection coating 8: AlO₂ is deposited on the backside of the processed silicon wafer using a plate-type ALD deposition method. x The thin film, approximately 8 nm thick, was formed by the reaction of Al(CH3)3 with water vapor, and the process temperature was controlled at 250°C. Subsequently, SiN was deposited on the back side of the silicon wafer using a plate-type PECVD equipment. x Film, in which SiN x The film thickness is approximately 85 nm, with a refractive index of 2.0. The reactant gases within the tubular cavity are SiH4 and NH3. The operating pressure is 1600 mTorr, the power is 12000 W, the temperature is 440 °C, the SiH4 gas flow rate is 1200 sccm, the NH3 gas flow rate is 9000 sccm, and the deposition time is 12 min. Because a perovskite portion needs to be deposited on the front side of the subsequent battery, AlO2 cannot be covered on the front side. x and SiN x Related insulating dielectric films.
[0081] S8. Forming positive and negative electrodes on the back side: screen printing high-temperature paste and sintering; then screen printing high-temperature paste on one side of the back of the silicon wafer, wherein the negative electrode 15 is printed in the n-region on the back of the silicon wafer and the positive electrode 14 is printed in the boron diffusion layer, and then sintering at 770°C to form an ohmic contact, as shown in Figure 7.
[0082] S9. Removal of front oxide layer: During the high-temperature sintering process, an oxide layer will inevitably form on the front side of the silicon wafer. Therefore, after the subsequent deposition of the perovskite layer, a chain acid (HF) cleaning machine is required to remove the surface oxide layer. The concentration of the HF solution in the chain machine is 40wt%, and the belt speed is 3m / min.
[0083] S10. Sequential deposition of interconnect layer 9, hole transport layer 10, perovskite layer 11, electron transport layer 12, and transparent conductive film 13 on the front side: Perovskite is deposited on the front side of the silicon wafer: First, the intermediate interconnect layer is deposited, specifically a transparent conductive film (TCO layer) is deposited using PVD, which is ITO; then, a hole transport layer is deposited on the TCO layer using a coating method, which is nickel oxide, and then annealed and crystallized at 180°C; next, a perovskite layer is deposited on the hole transport layer using a coating method, which is methylamine lead iodine, and then annealed and crystallized at 200°C; an electron transport layer is further deposited on the perovskite layer using PVD, which is TiO2, and then annealed and crystallized at 180°C; finally, a TCO layer is deposited on the electron transport layer using PVD, which is ITO, as shown in Figure 8.
[0084] S11. Forming the negative electrode on the front side: Screen printing low-temperature paste and sintering; Screen printing low-temperature paste on the tandem battery to print the negative electrode 15 on the front side (on the transparent conductive film layer on the surface of the electron transport layer), and then sintering at 220℃ to form an ohmic contact, resulting in the final "three-terminal" (one positive electrode, two negative electrodes) triple junction battery structure, as shown in Figure 9.
[0085] Example 2 The preparation method of Example 2 differs from that of Example 1 only in the following steps: S3, Double-sided primary boron diffusion; converting both the front and back oxide layers of the N-type silicon substrate into a boron diffusion layer and a BSG layer; Removing the BSG layer on the front surface of the silicon wafer using a chain machine, wherein the concentration of HF solution in the chain machine is 60wt% and the belt speed is 2m / min; Secondary boron diffusion. Wherein: The primary boron diffusion conditions are: diffusion temperature 930℃, time 60min, BCl3 flow rate 200sccm, O2 flow rate 1200sccm; Oxidation propulsion temperature 1050℃, O2 flow rate 8000sccm, time 80min, resulting in a BSG layer thickness of approximately 50nm and a boron atom surface doping concentration of approximately 5E18cm. -3 The doping depth is approximately 1.2 μm.
[0086] The secondary boron diffusion conditions were: boron diffusion temperature 930℃, time 12 min, BCl3 flow rate 40 sccm, O2 flow rate 500 sccm; oxidation propagation temperature 1050℃, O2 flow rate 3000 sccm, time 20 min. The resulting BSG layer thickness was approximately 35 nm, and the boron atom surface doping concentration was 1E19cm. -3 The doping depth is approximately 1.5 μm.
[0087] S5. Double-sided primary phosphorus diffusion: The surface layer of the boron diffusion layer on the front side is transformed into a phosphorus diffusion layer and a PSG layer. Simultaneously, the BSG layer in the pre-defined n-region on the back side is transformed into a PSG layer, and the surface layer of the bottom boron diffusion layer is transformed into a phosphorus diffusion layer. The PSG layer on the front surface of the silicon wafer is removed using a chain conveyor, where the concentration of the HF solution in the chain conveyor is 30wt%, and the belt speed is 3m / min. Secondary phosphorus diffusion: The primary phosphorus diffusion conditions are: phosphorus diffusion temperature 790℃, diffusion time 15min, POCl3 carried by nitrogen at a flow rate of 1200 sccm, and O2 flow rate 2000 sccm. Afterwards, oxidation propagation is performed at a temperature of 890℃ for 20min, with an O2 flow rate of 5000 sccm. The resulting PSG layer thickness is approximately 20nm, and the phosphorus atom surface doping concentration is approximately 7E19cm. -3 The doping depth is approximately 0.25 μm.
[0088] The secondary phosphorus diffusion conditions were: phosphorus diffusion temperature 790℃, time 5 min, POCl3 flow rate 300 sccm, O2 flow rate 1000 sccm; oxidation propagation temperature 890℃, time 8 min, O2 flow rate 1500 sccm. The resulting PSG layer thickness was approximately 25 nm, and the phosphorus atom surface doping concentration was 2E20cm⁻¹. -3 The doping depth is approximately 0.32 μm.
[0089] Comparative Example 1 (Conventional tandem cell structure, non-back contact cell structure) S1, Preparation of crystalline silicon cells.
[0090] S1.1 Texturing the front side of N-type silicon wafers. Select N-type silicon wafers cut with diamond wire and perform alkaline texturing treatment on the N-type silicon wafers to form a light-trapping pyramidal textured surface on their front side; the alkaline texturing conditions are: KOH solution concentration of 1.7wt%, temperature of 80℃, and time of 7min.
[0091] S1.2. Front-side boron diffusion transforms the front surface of the N-type silicon wafer into a boron-doped layer and a BSG layer, while the back surface becomes a phosphorus-doped layer (the N-type silicon wafer is phosphorus-doped silicon). The boron diffusion conditions are: diffusion temperature 930℃, time 20 min, BCl3 flow rate 50 sccm, O2 flow rate 800 sccm; oxidation propagation temperature 1050℃, O2 flow rate 7000 sccm, time 60 min, resulting in a BSG layer thickness of approximately 50 nm.
[0092] S1.3. A chain machine is used to remove the BSG layer on the back and sides of the silicon wafer. The concentration of the HF solution in the chain machine is 40wt%, and the belt speed is 3m / min.
[0093] S1.4 Alkali Cleaning to Remove Boron Doping Layer: The silicon wafer is placed in an alkaline polishing tank to remove the boron doped layer that has spread on the back and sides of the wafer. The alkaline polishing conditions are: KOH solution concentration of 2.0 wt%, temperature of 75℃, and time of 5 min.
[0094] S1.5, Backside Passivation Film Deposition: To prevent the deposition of an insulating passivation film on the front side of the silicon wafer, which would affect carrier transport between the perovskite and crystalline silicon cells, a plate-type ALD and PECVD system can be used to sequentially deposit AlO2 on the back side (single side) of the silicon wafer. x and SiN x Passivation film. AlO x and SiN x The passivation film thicknesses are approximately 8 nm and 82 nm, respectively.
[0095] S1.6. The negative electrode paste is printed on the back of the silicon wafer using screen printing, and then sintered at 750°C to form an ohmic contact, thus forming the negative electrode.
[0096] S2. Using crystalline silicon solar cells as a substrate, an interconnect layer (ITO layer) is deposited on the front side using methods such as magnetron sputtering. The thickness of the ITO layer is 55 nm and the refractive index is 1.7.
[0097] S3. Dissolve tetrabutyl titanate in a suitable solvent (isopropanol) to prepare an electron transport layer precursor solution, and then uniformly coat this solution onto the interconnect layer using a coating technique. After coating, anneal and crystallize the entire sample to remove residual solvent from each layer at a temperature of 160°C.
[0098] S4. Subsequently, a wide-bandgap perovskite layer is deposited on the electron transport layer. The preparation formula is as follows: methylammonium bromide (MABr, CH3NH3Br), methylammonium chloride (MACl, CH3NH3Cl), lead bromide (PbBr2), and lead chloride (PbCl2). N,N-dimethylformamide (DMF) and dimethyl sulfoxide (DMSO) are thoroughly mixed as solvents. MABr and MACl are dissolved in DMF:DMSO and stirred thoroughly until transparent. For the lead salt solution: PbBr2 and PbCl2 are dissolved in DMF:DMSO and heated at 60°C with stirring until dissolved. The two solutions are mixed at a 1:1 volume ratio to obtain the precursor solution. The precursor solution is then uniformly applied to the surface of the hole transport layer using a coating technique. Afterward, in an environment isolated from water vapor and oxygen, a first drying is performed at 65°C, followed by a second annealing and crystallization at 105°C in an air environment with 5% RH to form the final perovskite layer with the chemical formula MAPb(BrCl)3.
[0099] S5. Next, prepare the hole transport layer precursor solution (nano NiO). x The particulate ink is then coated onto the perovskite layer and annealed at 180°C for 12 min to form a hole transport layer.
[0100] S6. A transparent conductive film (ITO layer) with a thickness of 55 nm and a refractive index of 1.7 is deposited on the hole transport layer by magnetron sputtering.
[0101] S7. Low-temperature paste (positive electrode) is deposited on the transparent conductive film on the front side of the perovskite cell using screen printing, and then contact is formed at 200°C. Since there is already a negative electrode on the back side (N-type silicon wafer) of the crystalline silicon cell, the entire cell forms a conventional two-end perovskite cell + crystalline silicon stacked cell structure.
[0102] The electrical performance of the solar cells obtained in each embodiment and comparative example was tested, and the results are shown in Table 1.
[0103] Table 1 Firstly, regarding Example 1, due to the adoption of a three-terminal triple-junction tandem cell structure, compared to the conventional double-junction tandem cell structure in Comparative Example 1, the cell has the highest open-circuit voltage, making it easier to obtain higher electrical performance data. Regarding Example 2, because the textured surface area on the front of the silicon wafer is larger, a greater amount of diffusion source is required compared to the back. Through secondary boron and phosphorus diffusion design, the diffusion requirements on both the front and back sides can be fully matched, resulting in optimal cell performance. Finally, regarding Comparative Example 1, because the cell uses a conventional double-junction structure, the bottom cell performance is weaker than the double-junction bottom cells in Examples 1 and 2, resulting in the lowest overall cell performance.
[0104] Unless otherwise specified, the raw materials and equipment used in this invention are all commonly used in the field; unless otherwise specified, the methods used in this invention are all conventional methods in the field.
[0105] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications, alterations, and equivalent transformations made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.
Claims
1. A three-terminal triple-junction tandem solar cell, characterized in that... include: N-type silicon substrate; The front side of the N-type silicon substrate is sequentially provided with a boron diffusion layer, a phosphorus diffusion layer, an interconnect layer, a hole transport layer, a perovskite layer, an electron transport layer, and a transparent conductive film. The back of the N-type silicon substrate has staggered p-regions and n-regions. The p-regions are boron diffusion layers, and the n-regions are N-type silicon substrates. The back of the p-regions and n-regions are provided with passivation antireflection films, and the back of the p-regions and n-regions are respectively provided with positive and negative electrodes.
2. The three-terminal triple-junction tandem solar cell according to claim 1, characterized in that: On the back side of the N-type silicon substrate, the boron diffusion layer is higher than the N-type silicon substrate.
3. A method for preparing a three-terminal triple-junction tandem solar cell according to claim 1 or 2, characterized in that... include: S1 and N-type silicon substrates are polished and oxidized on the back side; S2. Front side is texturized, and acid pickling removes part of the oxide layer on the back side; S3, boron diffusion; S4. The laser sequentially loosens the BSG layer in the preset n area on the back, the BSG layer on the front, and the BSG layer around the side. S5, phosphorus diffusion; S6. The back side undergoes chain-like acid cleaning, alkaline cleaning, and acid cleaning in sequence. S7, back coating; S8, positive and negative electrodes are formed on the back side; S9. Remove the front oxide layer; S10, an interconnect layer, a hole transport layer, a perovskite layer, an electron transport layer, and a transparent conductive film are sequentially deposited on the front side; S11, the front side forms the negative electrode.
4. The preparation method according to claim 3, characterized in that: In S1, a wet chain acid bath is used to polish and oxidize the back side of the N-type silicon substrate. The concentration of HNO3 in the acid bath is 30-70 wt%, the concentration of H2SO4 is 2-5 wt%, and the concentration of H3PO4 is 5-20 wt%.
5. The preparation method according to claim 3, characterized in that: In S2, the acid washing conditions are: HF solution concentration 2-10wt%, time 20-60s.
6. The preparation method according to claim 3, characterized in that: In S4, The laser conditions for the BSG layer in the pre-defined n-region on the back side are as follows: an ultraviolet nanosecond laser is used, with a wavelength of 200-400nm, a power of 1-5W, a duration of 1-3s, and a frequency of 50-100kHz. The laser conditions for the front BSG layer and the side-coated BSG layer are as follows: use an ultraviolet nanosecond laser with a wavelength of 200-400nm, a power of 5-20W, a duration of 5-10s, and a frequency of 10-20kHz.
7. The preparation method according to claim 3, characterized in that: In S6, The conditions for the first acid cleaning are: HF solution concentration 10-40 wt%, belt speed 1-3 m / min; The alkaline cleaning conditions are: KOH solution concentration 1.7–2.2 wt%, belt speed 1–6 m / min; The second acid cleaning was performed by spraying with an HF solution, with a concentration of 20–60 wt%.
8. The preparation method according to claim 3, characterized in that: In S14, The hole transport layer is made of 2,2',7,7'-tetratetra(N,N-di-p-toluidine)spirofluorene, poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine], nickel oxide, cuprous iodide, or copper thiocyanate; The material of the perovskite layer is methylamine lead iodine, formamidinium lead iodine, or cesium lead halide; The electron transport layer is made of TiO2, ZnO, or SnO2.
9. A method for fabricating a three-terminal triple-junction tandem solar cell according to claim 1 or 2, characterized in that... include: S1 and N-type silicon substrates are polished and oxidized on the back side; S2. Front side is texturized, and acid pickling removes part of the oxide layer on the back side; S3, primary boron diffusion; Removal of the front-side BSG layer; secondary boron diffusion; S4. The laser sequentially loosens the BSG layer in the preset n area on the back, the BSG layer on the front, and the BSG layer around the side. S5, primary phosphorus diffusion; removal of the front PSG layer; secondary phosphorus diffusion; S6. The back side undergoes chain-like acid cleaning, alkaline cleaning, and acid cleaning in sequence. S7, back coating; S8, positive and negative electrodes are formed on the back side; S9. Remove the front oxide layer; S10, an interconnect layer, a hole transport layer, a perovskite layer, an electron transport layer, and a transparent conductive film are sequentially deposited on the front side; S11, the front side forms the negative electrode.
10. The preparation method according to claim 9, characterized in that: In S3, The primary boron diffusion conditions were: diffusion temperature 900–950℃, time 20–80 min, BCl3 flow rate 100–300 sccm, and O2 flow rate 500–3000 sccm; oxidation propagation temperature 1000–1050℃, O2 flow rate 1000–20000 sccm, time 60–120 min; the resulting BSG layer thickness was 30–80 nm; and the boron atom surface doping concentration was 1E18–7E18 cm⁻¹. -3 The doping depth is 0.7–1.5 μm; The secondary boron diffusion conditions were as follows: diffusion temperature 900–950℃, time 10–30 min, BCl3 flow rate 20–100 sccm, O2 flow rate 200–1000 sccm; oxidation propagation temperature 1000–1050℃, O2 flow rate 1000–20000 sccm, time 10–50 min; the resulting BSG layer thickness was 30–70 nm; and the boron atom surface doping concentration was 5E18–2E19 cm⁻¹. -3 The doping depth is 1.0–2.0 μm; In S5, The primary phosphorus diffusion conditions were: diffusion temperature 750–850℃, time 5–30 min, POCl3 flow rate 500–2500 sccm, O2 flow rate 500–3000 sccm; oxidation propagation temperature 850–950℃, time 5–60 min, O2 flow rate 1000–10000 sccm; resulting PSG layer thickness 30–70 nm; and phosphorus atom surface doping concentration 1E19–8E19 cm⁻¹. -3 The doping depth is 0.2–0.4 μm; The secondary phosphorus diffusion conditions were as follows: diffusion temperature 750–850℃, time 2–10 min, POCl3 flow rate 200–1000 sccm, O2 flow rate 300–2000 sccm; oxidation propagation temperature 850–950℃, time 2–10 min, O2 flow rate 300–2000 sccm; resulting PSG layer thickness 20–60 nm; and phosphorus atom surface doping concentration 5E19–3E20 cm⁻¹. -3 The doping depth is 0.3–0.5 μm.