Semiconductor device structure and manufacturing method therefor, and chip
Patent Information
- Application Number
- PCT/CN2025/128954
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-19
- Filing Date
- 2025-10-21
- Publication Date
- 2026-09-24
Smart Images
Figure CN2025128954_24092026_PF_FP_ABST
Abstract
Description
A semiconductor device structure, its fabrication method, and a chip Technical Field
[0001] This invention belongs to the field of semiconductor device technology, and relates to a semiconductor device structure, its fabrication method, and a chip. Background Technology
[0002] Flip chip technology is mainly divided into two categories. One is reflow solder, including tin, tin-lead alloys, tin-silver alloys, and gold-tin alloys. Although lead-free soldering technology is mature, the solder is liquid at high temperatures, which can lead to bridging between adjacent solder bumps under pressure, making it unsuitable for fine-pitch flip chip applications. The other is bonding using pure gold bumps, where gold bumps are electrically connected to the substrate via thermoforming soldering or anisotropic conductive adhesive. Although gold bumps have excellent reliability and no bridging issues between adjacent gold bumps, the material cost of gold is very high. With the rising price of gold, developing new materials to replace gold is currently a hot research topic. Considering the excellent properties of gold bumps, such as oxidation resistance, sulfidation resistance, hardness, roughness, and solderability, there are few solutions that can replace gold. Among them, gold-silver alloys are one of the most promising solutions for replacing gold bumps.
[0003] TWI469288B discloses electroplated gold and silver bumps, addressing the issue of preventing silver oxidation. This involves electroplating or electroless plating of gold, palladium, copper, or nickel on the top or sides of the gold and silver bumps to prevent silver oxidation, with copper or nickel being more prone to oxidation than silver. TW201044527A discloses electroplated gold and silver bumps containing at least 80% silver, then forming a protective layer on the gold and silver surface through replacement or reduction of gold to prevent silver oxidation. TW201019440A discloses silver bumps made from pure silver or silver alloys, where the silver alloy contains at least 80% silver, and then plating a layer of pure gold or a gold alloy on the silver alloy surface to address the oxidation problem.
[0004] CN117542818B addresses the issue of oxidation and sulfidation resistance in gold and silver bumps by increasing the gold content to over 60%. This is achieved by first preparing a gold-silver alloy body with a gold content of 20%–50% as a bonding layer in the same electroplating bath using a low current density, followed by preparing a thin protective layer with a gold content of over 60% on the bump surface under a high current density. CN118398588B, to address potential welding defects caused by silver oxidation, utilizes electrochemical etching to selectively remove metallic silver from the bump surface, forming a nanoporous gold structure. This approach does not affect the bump's hardness and effectively solves the oxidation and sulfidation resistance problems of gold and silver bumps.
[0005] Although the above solutions address issues such as the hardness of gold and silver bumps, oxidation resistance, or poor welding caused by sulfidation, none of them address the bonding strength between gold and silver bumps and different metal layers during the manufacturing process. After the bump is fabricated, it needs to undergo various reliability tests, such as TCT (Temperature Cycle Test): -65℃ (15min) ~150℃ (15min), more than 700 cycles; PCT (Pressure Cooker Test): 121℃, 100% RH, 2atm, 168 hrs; THT (Temperature Humidity Test): 85℃ / 85% RH, 1000 hrs; HTST (High Temperature Storage Life Test): 150℃, 1000 hrs; LTST (Low Temperature Storage Life Test): -65℃, 1000 hrs, etc., to check the bonding strength between the bump and the underlying Bump Metal (UBM). Specifically, a thrust shear test can be performed on the bump that has undergone reliability testing to check whether the underlying UBM layer is exposed.
[0006] Most reliability failures occur due to poor adhesion between the bump and the UBM layer; therefore, the choice of UBM material metal has a significant impact on adhesion strength. CN105895604B mentions the preparation of bumps, wherein the material of the electroplated conductive bump is selected from gold, copper, nickel, silver, or their alloys, while the UBM material is selected from titanium / copper, titanium-tungsten / gold, or silver-containing alloys. CN116564916A mentions that the UBM layer used for gold bumps consists of a titanium layer, a titanium-tungsten layer, and a gold layer, from near to far from the electrode pad. By changing the UBM layer structure, increasing the titanium layer and decreasing the thickness of the titanium-tungsten layer, the adhesion strength of the bump is increased. US20230369270A1, in order to solve the reliability problem of bump-bonded IC devices at high temperatures, uses gold, copper, or non-conductive materials for the bump material, and the UBM layer is formed by a titanium / gold stack. US20190214357A1 mentions that a technical problem encountered in the process of creating bumps on the chip to connect to the substrate in flip chip technology is the low manufacturing yield of the bump structure. The yield is improved by developing additional etching processes. The bump material used is gold, and the UBM material is a titanium-tungsten alloy. US10629444B2 describes a novel bump structure, which is considered an alternative to gold bumps in display driver IC packages. The bump material used is a copper-nickel-gold trilayer, and the UBM layer includes a Ti layer and a Cu layer on the Ti layer, or a TiW layer and a Cu layer on the TiW layer. TW200633093A provides a method for manufacturing metal bumps, which are made of gold (Au), and the metal layer consists of a titanium-tungsten alloy (TiW) metal layer and a gold (Au) metal layer. US6664128B2 provides a bump manufacturing process in which the material forming the conductive layer is selected from aluminum, titanium, titanium-tungsten alloy, chromium, gold, silver and copper, wherein the UBM layer includes layers selected from the group consisting of aluminum / nickel-vanadium / copper layers, titanium / nickel-vanadium / copper layers, titanium-tungsten / nickel-vanadium / copper layers and chromium / nickel-vanadium / copper layers.
[0007] To address the issue of gold-silver alloy bumps failing high- and low-temperature cycling reliability testing with existing UBM layers, CN119340299A proposes a thermal expansion coefficient difference of less than 9 ppm / K between the gold-silver alloy bumps and the adhesion layer. This can resolve the bonding strength problem encountered by semiconductor devices during high- and low-temperature cycling (350 cycles) reliability testing. However, for some high-end DDIC (Display Driver IC) chips, the applied high- and low-temperature cycling tests are more stringent, with cycle counts reaching 700 or even 1000 cycles or more, making it difficult to completely eliminate the possibility of interface bonding failure. Technical issues
[0008] There is an urgent need to improve the bonding reliability between gold-silver alloy bumps and UBM layers, so as to ensure that semiconductor devices based on gold-silver alloy bumps can pass high-end chip reliability tests, and lay the foundation for the fabrication of flip chips using gold-silver alloys instead of gold. Technical solutions
[0009] The purpose of this invention is to provide a semiconductor device structure, its fabrication method, and a chip. By improving the UBM layer, the bonding reliability between the gold-silver alloy bumps and the UBM layer is enhanced. The resulting semiconductor device structure can pass high-end chip reliability testing, enabling the use of gold-silver alloys to replace pure gold in flip chip fabrication. Through dedicated research, the inventors discovered that the failure mechanism of gold-silver alloys is as follows: during reliability testing, silver atoms in the gold-silver alloy migrate through the gold seed layer to the adhesion layer (titanium or titanium-tungsten alloy) under high-temperature conditions. However, the bonding force between silver and titanium or titanium-tungsten alloy is poor, and separation occurs at the interface even without applying a pushing force.
[0010] According to diffusion theory, diffusion between metals is explained by vacancy or interstitial mechanisms. Diffusion is also influenced by crystal structure. When two metals have similar crystal structures and lattice constants, their interfacial energies are relatively low, resulting in high interfacial bonding forces, and diffusion is more likely to occur. Conversely, if their crystal structures differ significantly, their lattice constants differ considerably, resulting in higher interfacial energies and weaker interfacial bonding forces, diffusion becomes more difficult. As shown in Table 1, both gold and silver have face-centered cubic structures. Silver has an atomic radius of 1.44 Å and a lattice constant of 4.086 Å, while gold has an atomic radius of 1.44 Å and a lattice constant of 4.078 Å. Therefore, gold has a greater chance of diffusion, which explains why gold-silver alloys are prone to interfacial failure at high temperatures. To prevent silver in the bumps from diffusing through the gold seed layer to the adhesion layer, leading to a decrease in bonding forces, a diffusion layer material is needed to prevent silver diffusion into the adhesion layer. This diffusion layer material should also possess the properties of noble metals to avoid a decrease in interfacial bonding forces due to oxidation during material preparation.
[0011] Table 1. Crystal structures, lattice constants, and atomic radii of different noble metals
[0012]
[0013] The inventors found that platinum group metals were a good choice. As shown in Table 1, the lattice constants of platinum group elements are close to those of gold and silver. They have low interfacial bonding energy and strong bonding force. When diffusion occurs, since the atomic radius of silver atoms is larger than that of platinum group elements, these metals diffuse towards silver, thus blocking the diffusion of silver atoms to the adhesion layer.
[0014] Based on this important discovery, the present invention proposes a corresponding solution, as follows:
[0015] A primary aspect of this invention is to provide a semiconductor device structure comprising a gold-silver alloy bump and a UBM layer, wherein the UBM layer is composed of a seed layer, a diffusion barrier layer, and an adhesion layer, or is composed of a diffusion barrier layer and an adhesion layer; the diffusion barrier layer is composed of a platinum group element and / or an alloy containing a platinum group element; the device structure, from top to bottom, is as follows: the bottom of the gold-silver alloy bump is connected to the seed layer, the seed layer is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode; or the bottom of the gold-silver alloy bump is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the seed layer, the seed layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode; or the bottom of the gold-silver alloy bump is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode. By adding a diffusion barrier layer between the gold-silver bump and the adhesion layer, silver atoms are prevented from migrating to the adhesion layer interface, thereby solving the problem of interface failure caused by silver diffusion from the bump to the adhesion layer. The advantages of this approach are that UBM materials can be prepared simultaneously using magnetron sputtering or evaporation deposition, resulting in better interfacial bonding. Compared to preparing barrier layers using electroplating or other methods, it reduces equipment investment and avoids cross-contamination between different plating solutions. The thickness of the metal diffusion layer film prepared using magnetron sputtering or evaporation deposition is more uniform and controllable, which can shorten the subsequent etching time and increase yield and chip yield.
[0016] Preferably, the diffusion barrier layer is composed of one or more of platinum, rhodium, iridium, and their alloys.
[0017] Furthermore, the thickness of the seed layer is 0~500 nm (0 nm means the seed layer is removed), the thickness of the adhesion layer is 10~1000 nm, and the thickness of the diffusion barrier layer is 10~1000 nm.
[0018] Furthermore, the seed layer is gold or a gold alloy.
[0019] Furthermore, the adhesive layer is titanium or a titanium alloy, preferably titanium-tungsten or titanium-nitrogen alloy.
[0020] Furthermore, the thickness of the gold-silver alloy bump is 5~20 μm.
[0021] Furthermore, the gold content in the gold-silver alloy bump is 10~60wt%. If the gold content is too low, the hardness, roughness, and resistance to oxidation and sulfidation of the gold-silver alloy bump will differ significantly from those of a gold bump; if the gold content is too high, firstly, the hardness will be too high, and defects such as gold nodules will easily occur, and secondly, it will be difficult to reduce costs.
[0022] Another aspect of the present invention is to provide a method for fabricating the above-described semiconductor device structure, comprising the following steps:
[0023] S1. An adhesion layer, a diffusion barrier layer, and a seed layer are sequentially prepared on a chip wafer using physical vapor deposition (e.g., evaporation or magnetron sputtering) to obtain a UBM layer; or an adhesion layer and a diffusion barrier layer are sequentially prepared on a chip wafer using physical vapor deposition (e.g., evaporation or magnetron sputtering) to obtain a UBM layer; or an adhesion layer and a diffusion barrier layer are sequentially prepared on a chip wafer using physical vapor deposition (e.g., evaporation or magnetron sputtering) to obtain a UBM layer.
[0024] S2 Coating photoresist and exposing the area to be electroplated;
[0025] S3 uses a gold and silver plating solution to prepare gold and silver alloy bumps by electroplating.
[0026] S4 Removes excess photoresist and UBM layer.
[0027] The key to the preparation method provided by this invention lies in adding a diffusion barrier layer on top of the adhesion layer. The diffusion barrier layer can be located above or below the gold seed layer. Specific operations include physical vapor deposition to prepare the adhesion layer, diffusion barrier layer, and seed layer; coating with photoresist; and electroplating to prepare gold-silver alloy bumps, all of which can employ existing technical solutions.
[0028] Another aspect of the present invention is to provide a chip, said chip comprising the semiconductor device structure provided by the present invention.
[0029] Furthermore, the chip can be a liquid crystal driver chip, a memory chip, a logic chip, or a radio frequency power chip. Beneficial effects
[0030] The technical solution provided by this invention, and the resulting semiconductor device structure, solves the technical problem that gold-silver alloy bumps and existing UBM layers cannot pass high and low temperature cycle reliability tests. The obtained semiconductor device structure and corresponding chip can pass various reliability tests, making it feasible to replace pure gold bumps with gold-silver alloys, thereby significantly reducing the production cost of flip chips. Attached Figure Description
[0031] Figure 1 shows the interface FIB-SEM (Focused Ion Beam Scanning Electron Microscopy) image of semiconductor devices constructed with gold-silver alloy bumps of different gold contents after annealing at 280°C for 8 hours.
[0032] Figure 2 shows the interface FIB-SEM images of a semiconductor device constructed with gold-silver alloy bumps containing 45% gold, after annealing at 280°C for different times.
[0033] Figure 3 is a schematic diagram of the semiconductor device structure provided by the present invention.
[0034] Figure 4 is a FIB-SEM interface diagram of the semiconductor device structures of Example 1 and Comparative Example 1 after annealing at 280°C for 12 hours.
[0035] Reference numerals: 101-Wafer substrate, 102-Electrode, 103-Passivation layer, 104-Adhesion layer, 105-Diffusion barrier layer or seed layer, 106-Seed layer or diffusion barrier layer, 107-Gold-silver alloy bump. Embodiments of the present invention
[0036] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.
[0037] In their previous work, the inventors discovered that existing semiconductor devices constructed with gold-silver alloy bumps are difficult to pass high-end chip reliability tests, such as DDIC. In order to reveal the failure mechanism of existing semiconductor devices constructed with gold-silver alloy bumps, the inventors conducted the following research.
[0038] DDIC reliability testing is time-consuming, such as TCT (-65℃ (15min) ~ 150℃ (15min), 700 cycles or even more than 1000 cycles) and HTST (150℃, 1000 hrs). In order to accelerate the development of materials, the inventors developed a new method that simulates device failure by shortening the time under high temperature conditions based on the time-temperature equivalence effect.
[0039] Semiconductor devices were constructed using gold-silver alloy bumps with different gold contents. The semiconductor devices consisted of gold-silver alloy bumps and a UBM layer, with gold contents of 20%, 45%, and 100% (pure gold) in the gold-silver alloys, respectively. The UBM layer included an adhesion layer and a seed layer. The adhesion layer was a TiW alloy with a thickness of 320 nm, and the seed layer was pure gold with a thickness of 80 nm. These three types of semiconductor devices were annealed at 280℃ for 8 hours, and the interface morphology between the gold-silver alloy bumps and the UBM layer was observed using FIB-SEM. The results are shown in Figure 1. Figure 1 shows that the interface between the gold-silver alloy bumps with a gold content of 20% and the UBM layer had separated, while the interfaces between the gold-silver alloy bumps with a gold content of 45% and the pure gold layer had not separated.
[0040] Semiconductor devices were constructed using gold-silver alloy bumps with a gold content of 45%. The semiconductor device consisted of gold-silver alloy bumps and a UBM layer. The UBM layer included an adhesion layer and a seed layer. The adhesion layer was a TiW alloy with a thickness of 320 nm; the seed layer was pure gold with a thickness of 80 nm. Annealing was performed at 280℃ for 4 h, 8 h, and 12 h, respectively. The failure mechanism was investigated by studying the changes in the interface structure during the annealing process, and the results are shown in Figure 2. In Figure 2, after 4 h of annealing, no interface separation occurred, but a discontinuous layered structure (indicated by the white arrow) was present at the interface. This layered structure gradually disappeared with increasing annealing time. After 12 h of annealing at 280℃, the edge interfaces all separated. Since the layered structure was located above the adhesion layer and was very thin, it could be identified as a gold seed layer. With increasing annealing time, silver gradually diffused into gold, eventually forming a uniform gold-silver alloy. Due to the weak bonding between silver and TiW, interface failure occurred after 12 h of annealing.
[0041] To verify the diffusion of silver atoms in gold, the inventors designed an experiment. First, an 8μm thick gold-silver alloy with a 20% gold content was electroplated onto a wafer, followed by a 1μm thick pure gold plating. EDX was used to detect the gold and silver content in the original pure gold plating after silver diffused into the pure gold plating under different annealing conditions, starting from the top of the plating. The detection voltage was 20KV, resulting in a detection depth of approximately 400-500 nm. The results are shown in Table 2.
[0042] Table 2. Gold and silver content in the original pure gold plating after silver diffusion under different annealing conditions.
[0043]
[0044] Table 2 shows that without annealing, no silver atoms were detected in the gold plating. As the annealing time increased from 8 h to 24 h, the detectable silver atoms in the gold plating increased from 8.55% to 15.4%. This experiment demonstrates that silver diffuses rapidly in gold at 280℃. In summary, the gold atoms and the TiW interface in the adhesion layer have strong bonding, and the interface does not separate after annealing at 280℃. However, the silver atoms and the TiW layer in the adhesion layer have weak bonding. As more silver atoms diffuse through the gold seed layer to the adhesion layer interface, it ultimately leads to interface failure of the device.
[0045] The following describes the fabrication of a semiconductor device with a diffusion barrier layer added to the UBM layer, followed by reliability testing. Example 1
[0046] A semiconductor device structure, as shown in Figure 3, has the following layers: a silicon-based wafer substrate 101 at the bottom, on which transistors are deployed; external interconnects of the transistors are aluminum or copper electrodes 102; passivation layers 103 are located on both sides of the electrodes, and the passivation layer material can be silicon dioxide or silicon nitride, etc., whose main function is to protect and isolate the circuit, and is prepared by vapor deposition or magnetron sputtering; above the electrodes is a UBM layer, and from bottom to top are an adhesion layer 104, a diffusion barrier layer 105, and a seed layer 106. The adhesion layer 104 is made of titanium and has a thickness of 250 nm; the diffusion barrier layer 105 is made of platinum and has a thickness of 50 nm; the seed layer 106 is made of gold and has a thickness of 50 nm; the gold-silver alloy bump 107 has a gold content of 20 wt% and a thickness of 9 μm.
[0047] The specific fabrication process is as follows. On the completed 12-inch LCD driver chip wafer, a Ti adhesion layer was first sputtered using magnetron sputtering. The sputtering conditions were: vacuum level of 2.3 mTorr, bias voltage of 90 V, power of 5 kW, and sputtering time of 200 s. Then, in the same cavity, a Pt target was switched to sputter a Pt diffusion barrier layer. The sputtering conditions were: vacuum level of 2.1 mTorr, bias voltage of 60 V, power of 2 kW, and sputtering time of 120 s. Finally, in the same cavity, an Au target was switched to sputter an Au seed layer. The sputtering conditions were: vacuum level of 2.7 mTorr, bias voltage of 60 V, power of 2 kW, and sputtering time of 150 s. Nitrogen gas was introduced to cool the wafer, and it was then removed. JSR 121 photoresist was spin-coated onto the wafer to expose the area to be electroplated. The photoresist height was 20 μm. After plasma cleaning, a gold-silver conductive metal layer was prepared using a gold-silver alloy electroplating solution. The plating solution temperature was 30℃, pH was 9.0, current density was 0.5 ASD, and electroplating time was 36 min. The height of the bumps after electroplating was approximately 9 μm, and the gold weight content of the bumps was 20%. Finally, the photoresist and UBM layer were removed. Reliability testing: Annealing at 280℃ for 12 h, and the interface morphology was observed using FIB-SEM. Example 2
[0048] A semiconductor device structure is provided, with the overall structure being the same as in Example 1, except that: the UBM structure, from bottom to top, consists of a 320 nm TiW adhesion layer, an 80 nm Au seed layer, and a 100 nm Pt diffusion barrier layer; the gold-silver alloy bumps contain 60 wt% gold and have a thickness of 5 μm. The fabrication process is generally similar to that in Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly based on the UBM structure. Example 3
[0049] A semiconductor device structure is provided, with the overall structure being the same as in Example 1, except that: the UBM structure, from bottom to top, consists of a 320 nm TiW adhesion layer, an 80 nm Au seed layer, and a 100 nm platinum-rhodium alloy diffusion barrier layer; the gold-silver alloy bumps contain 10 wt% gold and have a thickness of 20 μm. The fabrication process is generally similar to that in Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly based on the UBM structure. Example 4
[0050] A semiconductor device structure is provided, with the overall structure being the same as in Example 1, except that the UBM structure, from bottom to top, consists of a 320 nm TiW adhesion layer, a 100 nm platinum-iridium alloy diffusion barrier layer, and a 50 nm Au seed layer. The fabrication process is generally similar to that in Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly based on the UBM structure. Example 5
[0051] A semiconductor device structure is provided, with the overall structure being the same as in Example 1, except that the UBM structure consists of a 100 nm Ti adhesion layer, a 100 nm Ir diffusion barrier layer, and a 50 nm Au seed layer from bottom to top. The fabrication process is generally similar to that in Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly based on the UBM structure. Example 6
[0052] A semiconductor device structure is provided, with the overall structure being the same as in Example 1, except that the UBM structure consists of a 1000 nm Ti adhesion layer, a 500 nm Au seed layer, and a 50 nm Ir diffusion barrier layer from bottom to top. The fabrication process is generally similar to that in Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly based on the UBM structure. Example 7
[0053] A semiconductor device structure is provided, with the overall structure being the same as in Example 1, except that the UBM structure consists of a 100 nm Ti adhesion layer, an 80 nm Au seed layer, and a 100 nm Rh diffusion barrier layer from bottom to top. The fabrication process is generally similar to that in Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly based on the UBM structure. Example 8
[0054] A semiconductor device structure is provided, with the overall structure being the same as in Example 1, except that the UBM structure consists of a 100 nm Ti adhesion layer, a 50 nm Rh diffusion barrier layer, and a 500 nm Au seed layer from bottom to top. The fabrication process is generally similar to that in Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly based on the UBM structure. Example 9
[0055] A semiconductor device structure is provided, with the overall structure being the same as in Example 1, except that the UBM structure consists of a 100 nm Ti adhesion layer and a 100 nm Rh diffusion barrier layer from bottom to top. The fabrication process is generally similar to that in Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly based on the UBM structure. Example 10
[0056] A semiconductor device structure is provided, with the overall structure being the same as in Example 1, except that the UBM structure consists of a 10 nm Ti adhesion layer and a 1000 nm Pd diffusion barrier layer from bottom to top. The fabrication process is generally similar to that in Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly based on the UBM structure. Example 11
[0057] A semiconductor device structure is provided, with the overall structure being the same as in Example 1, except that the UBM structure consists of a 100 nm TiN adhesion layer and a 10 nm Pt diffusion barrier layer from bottom to top. The fabrication process is generally similar to that in Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly based on the UBM structure. Example 12
[0058] A semiconductor device structure is provided, with the overall structure being the same as in Example 1, except that the UBM structure consists of a 100 nm TiW adhesion layer and a 100 nm Ir diffusion barrier layer from bottom to top. The fabrication process is generally similar to that in Example 1, with the magnetron sputtering target and sputtering parameters varying accordingly based on the UBM structure.
[0059] The results show that the devices prepared in the above embodiments do not undergo interface separation even after annealing at 280°C for 12 hours. Therefore, forming a diffusion barrier layer from platinum group elements or alloys can solve the problem of poor adhesion caused by the diffusion of silver to the UBM adhesion layer after reliability testing.
[0060] Comparative Example 1
[0061] A semiconductor device structure is the same as that in Example 1, except that the UBM layer consists of an adhesion layer 104 and a seed layer 106 from bottom to top. Compared with Example 1, the UBM layer does not have a diffusion barrier layer 105. After annealing at 280°C for 12 hours, the interface separated, as shown in Figure 4.
[0062] Although embodiments of the present invention have been shown and described above, it is understood that these embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and alterations to the above embodiments within the scope of the present invention without departing from its principles and spirit. The scope of protection of the present invention is defined by the claims and their equivalents. Industrial applicability
[0063] The technical solution provided by this invention, and the resulting semiconductor device structure, solves the technical problem that gold-silver alloy bumps and existing UBM layers cannot pass high and low temperature cycle reliability tests. The obtained semiconductor device structure and corresponding chip can pass various reliability tests and have broad application prospects in the field of semiconductor devices.
Claims
1. A semiconductor device structure comprising gold-silver alloy bumps and a UBM layer, characterized in that, The semiconductor device structure is used for bump bonding of flip chips, wherein the gold content in the gold-silver alloy bump is 10~45wt%; wherein the UBM layer consists of a seed layer, a diffusion barrier layer, and an adhesion layer, or consists of a diffusion barrier layer and an adhesion layer; the diffusion barrier layer is composed of platinum group elements and / or alloys containing platinum group elements, preventing silver atoms in the gold-silver alloy bump from migrating to the adhesion layer interface; the device structure, from top to bottom, is as follows: the bottom of the gold-silver alloy bump is connected to the seed layer, the seed layer is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode; or the bottom of the gold-silver alloy bump is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the seed layer, the seed layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode; or the bottom of the gold-silver alloy bump is connected to the diffusion barrier layer, the diffusion barrier layer is connected to the adhesion layer, and the adhesion layer is connected to the chip electrode.
2. The semiconductor device structure according to claim 1, characterized in that, The diffusion barrier layer is composed of one or more of platinum, rhodium, iridium, or alloys thereof.
3. The semiconductor device structure according to claim 1, characterized in that, The thickness of the seed layer is 0~500nm, the thickness of the adhesion layer is 10~1000nm, and the thickness of the diffusion barrier layer is 10~1000nm.
4. The semiconductor device structure according to claim 1, characterized in that, The seed layer material is gold or a gold alloy.
5. The semiconductor device structure according to claim 1, characterized in that, The adhesive layer material is titanium or a titanium alloy.
6. The semiconductor device structure according to claim 5, characterized in that, The adhesive layer material is titanium, titanium-tungsten, or a titanium-nitrogen alloy.
7. The semiconductor device structure according to claim 1, characterized in that, The thickness of the gold-silver alloy bump is 5~20 μm.
8. The method for fabricating a semiconductor device structure according to any one of claims 1-7, characterized in that, Includes the following steps: S1. An adhesion layer, a diffusion barrier layer, and a seed layer are sequentially prepared on a chip wafer using physical vapor deposition to obtain a UBM layer; or an adhesion layer, a seed layer, and a diffusion barrier layer are sequentially prepared on a chip wafer using physical vapor deposition to obtain a UBM layer; or an adhesion layer and a diffusion barrier layer are sequentially prepared on a chip wafer using physical vapor deposition to obtain a UBM layer. S2 Coating photoresist and exposing the area to be electroplated; S3 uses a gold and silver plating solution to prepare gold and silver alloy bumps by electroplating. S4 Removes excess photoresist and UBM layer.
9. A chip, characterized in that, The chip includes the semiconductor device structure according to any one of claims 1-7.
10. The chip according to claim 9, characterized in that, The chip is a liquid crystal driver chip, a memory chip, a logic chip, or a radio frequency power chip.