LED backlight driver chip and data transmission direction adaptive circuit thereof

Abstract

The present application discloses an LED backlight driver chip. The LED backlight driver chip comprises a first input / output (I / O) port, a second I / O port, and a data transmission direction adaptive circuit. The data transmission direction adaptive circuit comprises: a first switching unit, a first clamping unit, a second switching unit, and a second clamping unit. By means of the data transmission direction adaptive circuit, when data is inputted from any data I / O port on the LED backlight driver chip, it can be ensured that the data is adaptively outputted from the other data I / O port to a following LED backlight driver chip, and it can also be ensured that when data is inputted from any data I / O port, data that needs to be outputted obtained after computation by the LED backlight driver chip can be outputted from the other data I / O port to a following LED backlight driver chip on a communication link.

Description

LED backlight driver chip and its data transmission direction adaptive circuit Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a data transmission direction adaptive circuit for an LED backlight driver chip. Background Technology

[0002] Figure 1 shows a schematic diagram of a prior art LED backlight panel structure. Multiple LED driver ICs are arranged in series. Each LED driver IC has a data input terminal and a data output terminal. In the communication link of the multiple LED driver ICs in series, the data input terminal of the preceding LED driver IC is connected to the data input terminal of the following LED driver IC. Simultaneously, each LED driver IC has an LED driving channel connected to an LED string, with each LED driving channel connected to one LED string. In the prior art, to arrange LED strings more tightly, the LED driver IC needs to be able to connect to both the LED strings arranged above and below on a single series communication link. However, the pin arrangement of the LED driver IC itself is fixed and unique. This leads to the arrangement of LED driver ICs and LED strings as shown in Figure 1, where LED driver ICs 1-5 are connected to the LED strings below, while ICs 6-9 are connected to the LED strings above. However, this arrangement requires precise placement of ICs 1-9, ensuring that ICs 6-9 are placed within the interval between ICs 1-5 and are placed inverted positions. This undoubtedly greatly increases the complexity of manufacturing the entire LED backlight panel, and the wiring is also more complicated.

[0003] Therefore, it is evident that a new adaptive circuit for data transmission direction is needed in existing LED backlight driver chips. Compared to traditional methods, this can overcome the limitation of fixed pin arrangement on LED driver ICs, which restricts the flexible placement of LED driver ICs. Summary of the Invention

[0004] The technical objective of this invention is to provide a data transmission direction adaptive circuit suitable for LED backlight driver chips. By setting this adaptive circuit in the LED backlight driver chip, the data input and data output terminals of the LED backlight driver chip can be adaptively matched. This ensures that when data is input from any data input / output port on the LED backlight driver chip, the data is adaptively output to the next LED backlight driver chip from the other data input / output port. Furthermore, it ensures that when data is input from any data input / output port, the data that the LED backlight driver chip needs to output after calculation can be output to the next LED backlight driver chip from the other data input / output port.

[0005] Based on the above technical objectives, the present invention provides an LED backlight driver chip, the LED backlight driver chip including a first IO port, a second IO port and a data transmission direction adaptive circuit.

[0006] The data transmission direction adaptive circuit includes: a first switching unit, a first clamping unit, a second switching unit, a second clamping unit, and an adaptive control unit; the adaptive control unit includes a first control unit and a second control unit.

[0007] When the first I / O port and the second I / O port are in an idle state, their potentials are clamped to a fixed level by the first clamping unit and the second clamping unit, respectively.

[0008] The first I / O port is connected to the output terminal of the first switch unit, and the input terminal of the first switch unit receives a fixed level; the second I / O port is connected to the output terminal of the second switch unit, and the input terminal of the second switch unit receives a fixed level.

[0009] The output terminal of the first switch unit is connected to the input terminal of the first control unit in the adaptive control unit. The output terminal of the first control unit is connected to the control terminal of the second switch unit to control the opening and closing of the second switch unit. The input terminal of the first control unit is also connected to the input terminal of the second control unit, and the input terminal of the second switch unit is connected to the input terminal of the second control unit. The output terminal of the second control unit is connected to the input terminal of the first control unit, and the output terminal of the second control unit is also connected to the control terminal of the first switch unit to control the opening and closing of the first switch unit.

[0010] In one embodiment, the first clamping unit includes a first clamping resistor R1, one end of which is connected to the first IO port and the other end is grounded; the first switching unit is a first OD gate circuit, the input terminal of which receives a high-level signal; the first control unit includes a first AND gate and a first NOT gate, and the output terminal of the first OD gate circuit is connected to the first input terminal of the first AND gate.

[0011] In one embodiment, the second clamping unit includes a second clamping resistor R2, one end of which is connected to the first I / O port, and the other end is grounded. The second switching unit is a second OD gate circuit, the input of which receives a high-level signal. The second control unit includes a second AND gate and a second NOT gate, and the output of the second OD gate circuit is connected to the first input of the second AND gate.

[0012] In one embodiment, the output of the second AND gate is input to the second input of the first AND gate via a first NOT gate, and the output of the first AND gate is input to the second input of the second AND gate via a second NOT gate; the output of the first AND gate is connected to the control terminal of the second OD gate, and the output of the second AND gate is connected to the control terminal of the first OD gate.

[0013] In one embodiment, the first control unit includes a first NOR gate and a first NOT gate, and the second control unit includes a second NOR gate and a second NOT gate; the first switching unit is a first OD gate circuit; the second switching unit is a second OD gate circuit; the output terminal of the first OD gate circuit is input to the first input terminal of the first NOR gate through the first NOT gate, and the output terminal of the first NOR gate is connected to the control terminal of the second OD gate circuit; the output terminal of the second OD gate circuit is connected to the first input terminal of the second NOR gate through the second NOT gate; the output terminal of the second NOR gate is connected to the control terminal of the first OD gate circuit; the output terminal of the first NOR gate is connected to the second output terminal of the second NOR gate, and the output terminal of the second NOR gate is connected to the second input terminal of the first NOR gate.

[0014] In one embodiment, the first control unit includes a first NOR gate, and the second control unit includes a second NOR gate; the output of the first OD gate circuit is input to the first input of the first NOR gate, the output of the first NOR gate is input to the first input of the second NOR gate, the output of the second NOR gate is input to the second input of the first NOR gate, and the output of the second OD gate circuit is input to the second input of the second NOR gate.

[0015] In one embodiment, the data transmission direction adaptive circuit further includes a first data selector. The first data input port of the first data selector is connected to a fixed signal, and the second data input port is connected to a signal generated by the LED driver IC. The control terminal of the first data selector is controlled by a drive signal switching signal to determine whether to transmit the fixed level or the signal generated by the LED driver IC to the input terminals of the first OD gate circuit and the second OD gate circuit.

[0016] Based on the above circuit structure, the LED backlight driver chip of the present invention can realize that as long as there is data input in one of the first IO port and the second IO port, the input drive signal can be immediately transmitted from the other IO port to the next LED driver chip, thereby enabling the drive signal to be transmitted smoothly in the entire serial communication link.

[0017] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0019] Figure 1 is a schematic diagram of the structure of an LED backlight panel in the prior art;

[0020] Figure 2 is a schematic diagram of the LED backlight panel structure of the present invention;

[0021] Figure 3 is a schematic diagram of the data transmission direction adaptive circuit structure in the LED driver chip of the first embodiment of the present invention;

[0022] Figure 4 is a circuit structure diagram of the data transmission direction adaptive circuit based on AND gate logic elements according to the first embodiment of the present invention;

[0023] Figure 5 is a circuit structure diagram of the data transmission direction adaptive circuit based on AND gate logic elements according to the second embodiment of the present invention;

[0024] Figure 6 is a circuit structure diagram of the data transmission direction adaptive circuit based on AND gate logic elements according to the third embodiment of the present invention;

[0025] Figure 7 is a circuit structure diagram of the data transmission direction adaptive circuit based on AND gate logic elements according to the fourth embodiment of the present invention;

[0026] Figure 8 is a circuit structure diagram of the data transmission direction adaptive circuit based on AND gate logic elements according to the fifth embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And when a second element, component, area, layer, or portion is discussed, it does not imply that the first element, component, area, layer, or portion necessarily exists in this invention.

[0029] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] Example 1

[0032] As shown in Figures 2-4, the LED driver chip in this embodiment includes a first I / O port, a second I / O port, and a data transmission direction adaptive circuit. The data transmission direction adaptive circuit includes a first switching unit, a first clamping unit, a second switching unit, a second clamping unit, and an adaptive control unit. The adaptive control unit includes a first control unit and a second control unit.

[0033] When the first IO port and the second IO port are in an idle state without signal input, the first clamping unit and the second clamping unit respectively clamp their potentials to a fixed level, so that the first IO port and the second IO port present a high impedance state and wait for signal input.

[0034] The first IO port is connected to the output terminal of the first switching unit, the input terminal of the first switching unit receives a fixed level, and the first clamping unit is connected to the output terminal of the first switching unit to clamp the voltage of the output terminal of the first switching unit.

[0035] The second IO port is connected to the output terminal of the second switching unit, the input terminal of the second switching unit is input with a fixed level, and the second clamping unit is connected to the output terminal of the second switching unit to clamp the voltage of the output terminal of the second switching unit.

[0036] The output terminal of the first switching unit is connected to the input terminal of the first control unit in the adaptive control unit. The output terminal of the first control unit is connected to the control terminal of the second switching unit to control the opening and closing of the second switching unit. The input terminal of the first control unit is also connected to the input terminal of the second control unit, and the input terminal of the second switching unit is connected to the input terminal of the second control unit. The output terminal of the second control unit is connected to the input terminal of the first control unit, and the output terminal of the second control unit is also connected to the control terminal of the first switching unit to control the opening and closing of the first switching unit.

[0037] As shown in Figure 4, the first clamping unit includes a first clamping resistor R1, one end of which is connected to the first IO port, and the other end is grounded. The first switching unit is a first OD gate circuit, with a high-level signal 1 input to its input terminal. The first control unit includes a first AND gate and a first NOT gate, and the output terminal of the first OD gate circuit is connected to the first input terminal of the first AND gate.

[0038] Meanwhile, the second clamping unit includes a second clamping resistor R2, one end of which is connected to the first IO port, and the other end is grounded. The second switching unit is a second OD gate circuit, with a high-level signal 1 input to its input terminal. The second control unit includes a second AND gate and a second NOT gate, and the output terminal of the second OD gate circuit is connected to the first input terminal of the second AND gate.

[0039] The output of the second AND gate is input to the second input of the first AND gate through the first NOT gate, and the output of the first AND gate is input to the second input of the second AND gate through the second NOT gate.

[0040] Meanwhile, the output of the first AND gate is connected to the control terminal of the second OD gate, and the output of the second AND gate is connected to the control terminal of the first OD gate.

[0041] In this embodiment, when the first I / O port and the second I / O port are in an idle state with no signal input, the first I / O port and the second I / O port are clamped to a low level. At this time, the low-level signal is input to the first input terminal of the first AND gate, causing the output terminal of the first AND gate to output a low-level signal. This, in turn, causes the control terminal of the second OD gate circuit to be at a low level, preventing the high-level signal at the input terminal of the second OD gate circuit from being transmitted to the output terminal. Similarly, the control terminal of the first OD gate circuit is also at a low level, preventing the high-level signal at the input terminal of the first OD gate circuit from being transmitted to the output terminal.

[0042] Assuming that when a high-level signal is transmitted into the first I / O port, the output of the first AND gate becomes high, thus closing the second OD gate circuit and outputting a high-level signal from its input to the second I / O port. At this time, the two inputs of the second AND gate remain high and low, respectively, so its output remains low, and the first OD gate circuit remains open. When a low-level signal is transmitted into the first I / O port, the output of the first AND gate becomes low, thus opening the second OD gate circuit and pulling the level of the second I / O port back to low by the second clamping resistor R2.

[0043] When data is input through the second I / O port, the same process described above can be used to output data through the first I / O port.

[0044] Based on the aforementioned adaptive circuit, as long as one of the first and second I / O ports has data input, the input drive signal can be immediately transmitted from the other I / O port to the next LED driver chip. This ensures that the drive signal can be smoothly transmitted throughout the entire serial communication link.

[0045] Example 2

[0046] As shown in Figure 5, based on the aforementioned Embodiment 1, but different from the aforementioned Embodiment 1, the first control unit includes a first NOR gate and a first NOT gate, and the second control unit includes a second NOR gate and a second NOT gate.

[0047] The output of the first OD gate circuit is connected to the first input of the first NOR gate via a first NOT gate. The output of the first NOR gate is connected to the control terminal of the second OD gate circuit. The output of the second OD gate circuit is connected to the first input of the second NOR gate via a second NOT gate. The output of the second NOR gate is connected to the control terminal of the first OD gate circuit. Simultaneously, the output of the first NOR gate is connected to the second output of the second NOR gate, and the output of the second NOR gate is connected to the second input of the first NOR gate.

[0048] In this embodiment, the other circuit structures are consistent with those in Embodiment 1. Based on the aforementioned description of the level changes in Embodiment 1, this embodiment can also achieve the same result: as long as one of the first IO port and the second IO port has data input, the input drive signal can be immediately transmitted from the other IO port to the next LED driver chip. This ensures that the drive signal can be smoothly transmitted throughout the entire serial communication link.

[0049] Example 3

[0050] As shown in Figure 6, based on the aforementioned Embodiment 1, and differing from the aforementioned Embodiment 1, the first control unit includes a first AND gate, a first NOT gate, and a second NOT gate, and the second control unit includes a second AND gate, a third NOT gate, and a fourth NOT gate.

[0051] The first clamping unit includes a first clamping resistor, one end of which is connected to a first I / O port, and the other end of which is connected to the drive voltage VCC. The second clamping unit includes a second clamping resistor, one end of which is connected to the first I / O port, and the other end of which is connected to the drive voltage VCC.

[0052] The output of the first OD gate circuit is input to the first input of the first AND gate via a second NOT gate. The output of the first AND gate is input to the first input of the second AND gate via a third NOT gate. The output of the second AND gate is input to the second input of the first AND gate via a first NOT gate. The output of the second OD gate circuit is input to the second input of the second AND gate via a fourth NOT gate.

[0053] The input terminals of the first and second OD gate circuits are both low level (0).

[0054] In this embodiment, the other circuit structures are consistent with those in Embodiment 1. Based on the aforementioned description of the level changes in Embodiment 1, this embodiment can also achieve the same result: as long as one of the first IO port and the second IO port has data input, the input drive signal can be immediately transmitted from the other IO port to the next LED driver chip. This ensures that the drive signal can be smoothly transmitted throughout the entire serial communication link.

[0055] Example 4

[0056] As shown in Figure 7, based on the aforementioned embodiment 3, and differing from the aforementioned embodiment 3 in that the first control unit includes a first NOR gate, and the second control unit includes a second NOR gate.

[0057] The output of the first OD gate is input to the first input of the first NOR gate, the output of the first NOR gate is input to the first input of the second NOR gate, and the output of the second NOR gate is input to the second input of the first NOR gate. The output of the second OD gate is input to the second input of the second NOR gate.

[0058] In this embodiment, the other circuit structures are consistent with those in Embodiment 3. Based on the aforementioned description of the level changes in Embodiment 3, this embodiment can also achieve the same result: as long as one of the first IO port and the second IO port has data input, the input drive signal can be immediately transmitted from the other IO port to the next LED driver chip. This ensures that the drive signal can be smoothly transmitted throughout the entire serial communication link.

[0059] Example 5

[0060] As shown in Figure 8, based on the aforementioned Embodiment 4, and differing from Embodiment 3, this embodiment adds a first data selector to the adaptive circuit. The first data input port of the first data selector is connected to a low level (0), and the second data input port is connected to a signal generated by the LED driver IC. This signal needs to be transmitted to the next-level LED driver IC. The control terminal of the first data selector is controlled by a drive signal switching signal. When it is necessary to transmit the signal generated by the LED driver IC to the next-level LED driver IC, the drive signal switching signal controls the first data selector to select the signal generated by the LED driver IC at the second data input port to be transmitted to the input terminals of the first and second OD gate circuits. In other states, the first data input port is connected to a low level (0) to transmit the signal to the input terminals of the first and second OD gate circuits.

[0061] The first data selector in this embodiment can be referenced in the aforementioned embodiments 1-3 to enable the LED driver IC to take over the signal content output by the data output terminal.

[0062] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An LED backlight driver chip, the LED backlight driver chip comprising at least: First I / O port, second I / O port, and adaptive circuit for data transmission direction; The data transmission direction adaptive circuit includes: a first switching unit, a first clamping unit, a second switching unit, a second clamping unit, and an adaptive control unit; the adaptive control unit includes a first control unit and a second control unit. When the first I / O port and the second I / O port are in an idle state, their potentials are clamped to a fixed level by the first clamping unit and the second clamping unit, respectively. The first I / O port is connected to the output terminal of the first switch unit, and the input terminal of the first switch unit receives a fixed level; the second I / O port is connected to the output terminal of the second switch unit, and the input terminal of the second switch unit receives a fixed level. The output terminal of the first switch unit is connected to the input terminal of the first control unit in the adaptive control unit. The output terminal of the first control unit is connected to the control terminal of the second switch unit to control the opening and closing of the second switch unit. The input terminal of the first control unit is also connected to the input terminal of the second control unit, and the input terminal of the second switch unit is connected to the input terminal of the second control unit. The output terminal of the second control unit is connected to the input terminal of the first control unit, and the output terminal of the second control unit is also connected to the control terminal of the first switch unit to control the opening and closing of the first switch unit.

2. The LED backlight driver chip according to claim 1, characterized in that, The first clamping unit includes a first clamping resistor R1, one end of which is connected to the first IO port and the other end is grounded; the first switching unit is a first OD gate circuit, the input terminal of which receives a high-level signal; the first control unit includes a first AND gate and a first NOT gate, and the output terminal of the first OD gate circuit is connected to the first input terminal of the first AND gate.

3. The LED backlight driver chip according to claim 2, characterized in that, The second clamping unit includes a second clamping resistor R2, one end of which is connected to the first IO port, and the other end is grounded. The second switching unit is a second OD gate circuit, with a high-level signal input to its input terminal. The second control unit includes a second AND gate and a second NOT gate, and the output terminal of the second OD gate circuit is connected to the first input terminal of the second AND gate.

4. The LED backlight driver chip according to claim 3, characterized in that, The output of the second AND gate is input to the second input of the first AND gate via the first NOT gate, and the output of the first AND gate is input to the second input of the second AND gate via the second NOT gate; the output of the first AND gate is connected to the control terminal of the second OD gate, and the output of the second AND gate is connected to the control terminal of the first OD gate.

5. The LED backlight driver chip according to claim 1, characterized in that, The first control unit includes a first NOR gate and a first NOT gate, and the second control unit includes a second NOR gate and a second NOT gate; the first switching unit is a first OD gate circuit; the second switching unit is a second OD gate circuit; the output terminal of the first OD gate circuit is input to the first input terminal of the first NOR gate through the first NOT gate, and the output terminal of the first NOR gate is connected to the control terminal of the second OD gate circuit; the output terminal of the second OD gate circuit is connected to the first input terminal of the second NOR gate through the second NOT gate; the output terminal of the second NOR gate is connected to the control terminal of the first OD gate circuit; the output terminal of the first NOR gate is connected to the second output terminal of the second NOR gate, and the output terminal of the second NOR gate is connected to the second input terminal of the first NOR gate.

6. The LED backlight driver chip according to claim 1, characterized in that, The first control unit includes a first NOR gate, and the second control unit includes a second NOR gate; the output of the first OD gate circuit is input to the first input of the first NOR gate, the output of the first NOR gate is input to the first input of the second NOR gate, the output of the second NOR gate is input to the second input of the first NOR gate, and the output of the second OD gate circuit is input to the second input of the second NOR gate; the output of the second OD gate circuit is input to the second input of the second NOR gate.

7. The LED backlight driver chip according to claim 1, characterized in that, The data transmission direction adaptive circuit also includes a first data selector. The first data input port of the first data selector is connected to a fixed signal, and the second data input port is connected to a signal generated by the LED driver IC. The control terminal of the first data selector is controlled by a drive signal switching signal to determine whether to transmit the fixed level or the signal generated by the LED driver IC to the input terminals of the first OD gate circuit and the second OD gate circuit.

8. An LED backlight panel, characterized in that the LED light-emitting elements of the LED backlight panel are driven to emit light using an LED backlight driver chip as described in any one of claims 1-7.

9. A display device, characterized in that, The display device uses the LED backlight panel as described in claim 9 for backlighting.

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