Display substrate and display panel

Abstract

A display substrate and a display panel. The display substrate comprises a plurality of pixel circuits provided on a substrate (SUB), each of the pixel circuits comprising a driving transistor (T3), a first light-emitting control transistor (T5), a first reset transistor (T1) and a third reset transistor (T8), a gate electrode of the first light-emitting control transistor (T5) being connected to a light-emitting control signal line (EM), and a first electrode of the third reset transistor (T8) being connected to a third initialization signal line (Vinit3). First electrodes of the two first reset transistors (T1) in the same pixel circuit group are connected as an integrated structure, the integrated structure being connected to a first initialization signal line (Vinit1), and the first initialization signal line (Vinit1) being electrically connected to a first auxiliary signal line (Vinit1'). A second reset control signal line (Reset_H(n)) and the light-emitting control signal line (EM) both extend in a first direction and are arranged in the same layer, and the first auxiliary signal line (Vinit1') extends in a second direction, the second direction intersecting with the first direction. The third initialization signal line (Vinit3) extends in the first direction. The orthographic projection of the third initialization signal line (Vinit3) on the substrate (SUB) does not overlap with the orthographic projection of the light-emitting control signal line (EM) on the substrate (SUB).

Description

Display substrate and display panel Technical Field

[0001] This disclosure relates to the field of display technology, specifically to a display substrate and a display panel. Background Technology

[0002] With the continuous development of display technology, display devices have gradually become ubiquitous in people's lives. Among them, organic light-emitting diode (OLED) display panels are widely used in smart products such as mobile phones, televisions, and laptops due to their advantages such as self-illumination, low power consumption, wide viewing angle, fast response speed, and high contrast. Summary of the Invention

[0003] This disclosure aims to solve at least one of the technical problems existing in the prior art, and proposes a display substrate and a display panel.

[0004] To achieve the above objectives, this disclosure provides a display substrate, comprising:

[0005] Substrate;

[0006] Multiple rows of pixel circuits extending along a first direction are arranged along a second direction, which intersects the first direction. Each pixel circuit row includes multiple pixel circuit groups arranged along the first direction. Each pixel circuit group includes two pixel circuits arranged along the first direction. Each pixel circuit includes a driving transistor, a first light-emitting control transistor, a first reset transistor, and a third reset transistor. The gate of the first light-emitting control transistor is connected to a light-emitting control signal line, and the first electrode of the first light-emitting control transistor is connected to a first voltage signal line. The gate of the third reset transistor is connected to a second reset control signal line, and the first electrode of the third reset transistor is connected to a third initialization signal line. The second electrode of the third reset transistor is electrically connected to the first electrode of the driving transistor and the second electrode of the first light-emitting control transistor. The gate of the first reset transistor is connected to the first reset control signal line. The first electrodes of two first reset transistors in the same pixel circuit group are connected to a single structure, which is connected to the first initialization signal line. The second electrode of the first reset transistor is connected to the second electrode of the driving transistor.

[0007] The second reset control signal line and the light emission control signal line both extend along the first direction and are disposed on the same layer. The first auxiliary signal line extends along the second direction and is disposed on a different layer from the first initialization signal line. The first initialization signal line is electrically connected to the first auxiliary signal line. The third initialization signal line is located on the side of the layer where the second reset control signal line is located away from the substrate and extends along the first direction. The orthographic projection of the third initialization signal line on the substrate does not overlap with the orthographic projection of the light emission control signal line on the substrate.

[0008] In some embodiments, the pixel circuit further includes: a second reset transistor, the gate of the second reset transistor being connected to a second reset control signal line, the first terminal of the second reset transistor being connected to the second reset control signal line, the second terminal of the second reset transistor being connected to a light-emitting device, and the first initialization signal line and the second initialization signal line both extending along the first direction;

[0009] Wherein, at least two of the first initialization signal line, the second initialization signal line and the third initialization signal line are located on different layers.

[0010] In some embodiments, the orthogonal projection of the first electrode of the third reset transistor on the substrate is located on the side of the orthogonal projection of the first initialization signal line on the substrate that is away from the light emission control signal line, and the orthogonal projection of the third initialization signal line on the substrate is located on the side of the orthogonal projection of the third initialization signal line on the substrate that is away from the light emission control signal line.

[0011] In some embodiments, at least one of the third initialization signal line and the second initialization signal line is located on a different layer from the first initialization signal line, and the orthographic projection of at least one of the third initialization signal line and the second initialization signal line on the substrate does not overlap with the orthographic projection of the first initialization signal line on the substrate.

[0012] And / or, the orthographic projection of the first reset control signal line on the substrate does not overlap with the orthographic projection of the second initialization signal line on the substrate.

[0013] In some embodiments, the light emission control signal line, the first reset control signal line, and the second reset control signal line are located in the first gate metal layer;

[0014] The third initialization signal line is located in the second gate metal layer;

[0015] The first initialization signal line and the second initialization signal line are located in the third gate metal layer;

[0016] The first gate metal layer, the second gate metal layer, and the third gate metal layer are arranged sequentially in a direction away from the substrate.

[0017] In some embodiments, the orthographic projection of the third initialization signal line on the substrate is located between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the second initialization signal line on the substrate;

[0018] The display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate. The first source / drain metal layer includes a first transition portion. The orthographic projection of the first transition portion on the substrate overlaps with the orthographic projection of either the third initialization signal line or the first electrode of the third reset transistor on the substrate. The first transition portion is electrically connected to the third initialization signal line and the first electrode of the third reset transistor respectively through vias. The orthographic projection of the first transition portion on the substrate is located between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the second initialization signal line on the substrate, and does not overlap with the orthographic projection of the first initialization signal line on the substrate.

[0019] In some embodiments, the display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate, the first source / drain metal layer including at least one third auxiliary signal line extending along a second direction and at least one second transition portion;

[0020] The orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the third auxiliary signal line on the substrate overlap with the orthographic projection of the second adapter on the substrate. The second adapter is electrically connected to the third auxiliary signal line and is also electrically connected to the third initialization signal line through a via.

[0021] Furthermore, the orthographic projection of the second adapter on the substrate does not overlap with the orthographic projection of the first initialization signal line on the substrate, and / or the orthographic projection of the second adapter on the substrate does not overlap with the orthographic projection of the second initialization signal line on the substrate.

[0022] In some embodiments, the first source / drain metal layer further includes at least one first auxiliary signal line extending along the second direction and at least one second auxiliary signal line extending along the second direction;

[0023] The first source / drain metal layer further includes:

[0024] At least one first redundant adapter, the orthographic projection of the first redundant adapter on the substrate overlaps with the orthographic projection of the third initialization signal line on the substrate, and the direction from the first redundant adapter to the first auxiliary signal line is the same as the direction from the second adapter to the third auxiliary signal line. The first redundant adapter is electrically insulated from the first auxiliary signal line, and the first redundant adapter is electrically connected to the third initialization signal line through a via.

[0025] And / or, at least one second redundant adapter, the orthographic projection of the second redundant adapter on the substrate overlapping the orthographic projection of the third initialization signal line on the substrate, and the direction from the second redundant adapter to the second auxiliary signal line being the same as the direction from the second adapter to the third auxiliary signal line, the second redundant adapter being electrically insulated from the second auxiliary signal line, and the second redundant adapter being electrically connected to the third initialization signal line through a via.

[0026] In some embodiments, the distance between the edge of the second adapter portion away from the third auxiliary signal line and the third auxiliary signal line is a first distance;

[0027] The first source / drain metal layer includes at least one first redundant transition section and at least one second redundant transition section;

[0028] The distance between the edge of the first redundant adapter that is away from the first auxiliary signal line and the first auxiliary signal line is the second distance;

[0029] The distance between the edge of the second redundant adapter that is away from the second auxiliary signal line and the second auxiliary signal line is the third distance;

[0030] The ratio of either the second distance or the third distance to the first distance is 0.5 to 1.5.

[0031] In some embodiments, the orthogonal projection of the second electrode of the second reset transistor onto the substrate is located on the side of the orthogonal projection of the third initialization signal line onto the substrate that is away from the first initialization signal line;

[0032] The display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate. The first source / drain metal layer includes a third transition portion. Either the orthographic projection of the second electrode of the second reset transistor on the substrate and the orthographic projection of the second reset control signal line on the substrate overlap with the orthographic projection of the third transition portion on the substrate. The third transition portion is electrically connected to the second electrode of the second reset transistor and the second reset control signal line respectively through vias. The orthographic projection of the third transition portion on the substrate also overlaps with the orthographic projection of the third reset control signal line on the substrate.

[0033] In some embodiments, the light emission control signal line, the first reset control signal line, and the second reset control signal line are located in the first gate metal layer;

[0034] The second initialization signal line is located in the second gate metal layer;

[0035] The first initialization signal line and the third initialization signal line are located in the third gate metal layer;

[0036] The first gate metal layer, the second gate metal layer, and the third gate metal layer are arranged sequentially in a direction away from the substrate.

[0037] In some embodiments, the orthographic projection of the second initialization signal line on the substrate is located between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the third initialization signal line on the substrate, and the orthographic projection of the first reset control signal line on the substrate is located on the side of the orthographic projection of the second initialization signal line on the substrate that is away from the orthographic projection of the first initialization signal line on the substrate.

[0038] In some embodiments, the display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate. The first source / drain metal layer includes a first transition portion. Either the orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the first electrode of the third reset transistor on the substrate overlaps with the orthographic projection of the first transition portion on the substrate. The first transition portion is electrically connected to the third initialization signal line and the first electrode of the third reset transistor respectively through vias. The orthographic projection of the first transition portion on the substrate also overlaps with the orthographic projection of the second initialization signal line on the substrate. The orthographic projection of the first transition portion on the substrate does not overlap with the orthographic projection of the first initialization signal line on the substrate.

[0039] In some embodiments, the display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate. The first source / drain metal layer includes a third transition portion. Either the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the second electrode of the second reset transistor on the substrate overlaps with the orthographic projection of the third transition portion on the substrate. The third transition portion is electrically connected to the second initialization signal line and the second electrode of the second reset transistor respectively through vias. The orthographic projection of the third transition portion on the substrate does not overlap with the orthographic projection of the first reset control signal line on the substrate.

[0040] In some embodiments, the first source / drain metal layer further includes at least one second auxiliary signal line extending along a second direction and at least one first connection portion, wherein the first connection portion is electrically connected to the second auxiliary signal line and the third adapter portion, respectively.

[0041] In some embodiments, the display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate, the first source / drain metal layer including at least one third auxiliary signal line extending along a second direction;

[0042] The orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the third auxiliary signal line on the substrate have a first overlap area. The third auxiliary signal line is electrically connected to the third initialization signal line through a via. The orthographic projection of the via on the substrate is located within the orthographic projection range of the first overlap area on the substrate. The first overlap area overlaps with the orthographic projection of the first reset control signal line on the substrate.

[0043] In some embodiments, the first electrode of the first reset transistor is located in the first semiconductor layer, and the first semiconductor layer is located between the first gate metal layer and the substrate;

[0044] The display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate. The first source / drain metal layer also includes a fourth transition portion, which is electrically connected to the first initialization signal line and the integrated structure through vias.

[0045] In some embodiments, the shape of the orthographic projection of the integral structure onto the substrate is an asymmetrical shape.

[0046] In some embodiments, the first auxiliary signal line is located in a first source-drain metal layer, and the first source-drain metal layer further includes at least one second connection portion, which is electrically connected to the first auxiliary signal line and the fourth adapter portion, respectively.

[0047] This disclosure also provides a display panel, characterized in that it includes a display substrate as described in any one of the above descriptions. Attached Figure Description

[0048] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0049] Figure 1 is a schematic diagram of the equivalent circuit of the pixel circuit in some embodiments;

[0050] Figure 2A is a schematic diagram of the planar structure of multiple pixel circuits in the display substrate in some embodiments;

[0051] Figures 2B, 2C, 2D, 2E, 2F, and 2G are schematic diagrams of the planar structure of each monolayer film in Figure 2A.

[0052] Figure 2H is a schematic diagram of the cross-sectional structure along the cutting line AA' in Figure 2A;

[0053] Figure 3A is a schematic diagram of the planar structure of multiple pixel circuits in the display substrate in some embodiments of this disclosure;

[0054] Figures 3B, 3C, 3D, 3E, 3F and 3G are schematic diagrams of the planar structure of each single-layer film in Figure 3A.

[0055] Figure 3H is a schematic cross-sectional view of the display substrate along the cutting line BB' shown in Figure 3A;

[0056] Figure 3I is a schematic diagram of a partial cross-sectional structure of the display substrate shown in Figure 3A;

[0057] Figure 4A is a schematic diagram of the planar structure of multiple pixel circuits in the display substrate in some other embodiments of this disclosure;

[0058] Figures 4B, 4C, 4D, 4E, 4F and 4G are schematic diagrams of the planar structure of each single-layer film in Figure 4A.

[0059] Figure 4H is a schematic cross-sectional view of the display substrate shown in Figure 4A along the cutting line CC'. Detailed Implementation

[0060] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0061] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0062] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0063] As used herein, “parallel” and “perpendicular” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°.

[0064] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0065] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0066] In related technologies, an OLED display substrate generally includes a substrate, a driving circuit layer located on one side of the substrate, and a light-emitting device layer located on the side of the driving circuit layer away from the substrate. The driving circuit layer includes multiple pixel circuits, and the light-emitting device layer includes multiple light-emitting devices. The pixel circuits are electrically connected to the light-emitting devices and can provide driving signals to the light-emitting devices to make them emit light.

[0067] Figure 1 is a schematic diagram of the equivalent circuit of the pixel circuit in some embodiments.

[0068] Specifically, as shown in Figure 1, the pixel circuit includes eight transistors and one storage capacitor Cst. The eight transistors are a first reset transistor T1, a threshold compensation transistor T2, a drive transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, and a third reset transistor T8.

[0069] It should be noted that each of these eight transistors can be either a P-type transistor or an N-type transistor, and this disclosure does not limit this. In this embodiment, the threshold compensation transistor T2 is an N-type transistor, and the first reset transistor T1, the third reset transistor T8, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the second reset transistor T7 are P-type transistors.

[0070] Optionally, some of the eight transistors can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), while the rest can be oxide (OPS) thin-film transistors (OTPs). More preferably, the active layer of the LTPS TFTs is made of low-temperature polycrystalline silicon (LTPS), and the active layer of the OPS TFTs is made of oxide semiconductor. LTPS TFTs have advantages such as high mobility and fast charging, while OPS TFTs have advantages such as low leakage current. Integrating LTPS TFTs and OPS TFTs onto a single pixel circuit forms a low-temperature polycrystalline oxide (LTPO) display panel. This allows for switching the refresh rate of the display panel to achieve low-frequency driving, which helps reduce power consumption and improve display quality.

[0071] As shown in Figure 1, the pixel circuit may further include a first node N1, a second node N2, a third node N3, and a fourth node N4. It should be noted that in the pixel circuit 9a provided in this embodiment, the nodes do not represent actual components, but rather the junction points of related electrical connections in the equivalent circuit diagram of the pixel circuit. In other words, these nodes are equivalent to the junction points of related electrical connections in the equivalent circuit diagram of the pixel circuit.

[0072] Specifically, the first node N1 is connected to the gate of the driving transistor T3, the first plate of the storage capacitor Cst, and the first terminal of the threshold compensation transistor T2, respectively. The second node N2 is connected to the first terminal of the driving transistor T3, the second terminal of the first light-emitting control transistor T5, the second terminal of the data writing transistor T4, and the second terminal of the third reset transistor T8, respectively. The third node N3 is connected to the second terminal of the first reset transistor T1, the second terminal of the threshold compensation transistor T2, the first terminal of the second light-emitting control transistor T6, and the second terminal of the driving transistor T3, respectively. The fourth node N4 is connected to the second terminal of the second light-emitting control transistor T6, the second terminal of the second reset transistor T7, and the light-emitting device L, respectively.

[0073] It should be noted that in the embodiments of this disclosure, the first terminal of the transistor can be either the source or the drain, and correspondingly, the second terminal can be either the drain or the source. For example, in one example, the first terminal of the threshold compensation transistor T2 is the source of the threshold compensation transistor T2, and the second terminal of the threshold compensation transistor T2 is the drain of the threshold compensation transistor T2. In another example, the first terminal of the driving transistor T3 is the second terminal of the driving transistor T3, and the second terminal of the driving transistor T3 is the first terminal of the driving transistor T3.

[0074] The second plate of the storage capacitor Cst is electrically connected to the first voltage signal line VDD, and the first plate of the storage capacitor Cst is connected to the first node N1, that is, the first plate of the storage capacitor Cst is connected to the gate of the driving transistor T3.

[0075] The first terminal of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1 and is configured to receive the first initialization signal. The second terminal of the first reset transistor T1 is electrically connected to the second terminal of the driving transistor T3. The gate of the first reset transistor T1 is electrically connected to the first reset control signal line Reset_P(n) and is configured to receive the first reset control signal.

[0076] The first terminal of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, the second terminal of the threshold compensation transistor T2 is electrically connected to the second terminal of the driving transistor T3, and the gate of the threshold compensation transistor T2 is electrically connected to the first scan signal line Gate_N(n), and is configured to receive a compensation control signal.

[0077] The gate of driving transistor T3 is connected to the first plate of storage capacitor Cst, the first terminal of driving transistor T3 is connected to the second node N2, and the second terminal of driving transistor T3 is connected to the third node N3. Driving transistor T3 determines the magnitude of the driving current flowing between the first voltage signal line VDD and the second voltage signal line VSS based on the potential difference between its gate and the first terminal.

[0078] The second terminal of the data writing transistor T4 is electrically connected to the first terminal of the driving transistor T3. The first terminal of the data writing transistor T4 is electrically connected to the data signal line Data and is configured to receive data signals. The gate of the data writing transistor T4 is electrically connected to the second scan signal line Gate_P(n) and is configured to receive scan signals.

[0079] The first terminal of the first light-emitting control transistor T5 is electrically connected to the first voltage signal line VDD, the second terminal of the first light-emitting control transistor T5 is electrically connected to the first terminal of the driving transistor T3, and the gate of the first light-emitting control transistor T5 is electrically connected to the light-emitting control signal line EM, and is configured to receive a light-emitting control signal.

[0080] The first electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T3. The second electrode of the second light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting device L. The gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control signal line EM and is configured to receive the light-emitting control signal.

[0081] The first electrode of the second reset transistor T7 is configured to be electrically connected to the second initialization signal line Vinit2 and to receive the second initialization signal. The second electrode of the second reset transistor T7 is electrically connected to the first electrode of the light-emitting device L. The gate of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Reset_H(n) to receive the reset control signal.

[0082] The first terminal of the third reset transistor T8 is electrically connected to the third initialization signal line Vinit3 and is configured to receive the third initialization signal. The second terminal of the third reset transistor T8 is electrically connected to the first terminal of the driving transistor T3. The gate of the third reset transistor T8 is electrically connected to the second reset control signal line Reset_H(n) and is configured to receive the second reset control signal.

[0083] The second electrode of the light-emitting device L is electrically connected to the second voltage signal line VSS.

[0084] The first voltage signal transmitted by the first voltage signal line VDD is, for example, a high-voltage DC signal, and the second voltage signal transmitted by the second voltage signal line VSS is, for example, a low-voltage DC signal.

[0085] Specifically, the driving process of the pixel circuit driving the light-emitting device L to emit light as shown in Figure 1 may include a first reset stage t1, a data refresh and compensation stage t2, a second reset stage t3, and a light-emitting stage t4.

[0086] In the first reset phase t1, the threshold compensation transistor T2 is turned on under the control of the first scan signal transmitted by the first scan signal line Gate_N(n), and the first reset transistor T1 is turned on under the control of the first reset control signal transmitted by the first reset control signal line Reset_P(n), so that the first initialization signal transmitted by the first initialization signal line Vinit1 is written to the first node N1, thereby resetting the first node N1.

[0087] At this time, the driving transistor T3 is turned on, while the writing transistor T4, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are all turned off, and the light-emitting device L does not emit light.

[0088] During the data refresh and compensation phase t2, the first reset transistor T1 is turned off under the control of the first reset control signal transmitted via the first reset control signal line Reset_P(n), the threshold compensation transistor T2 remains on, the write transistor T4 is turned on under the control of the second scan signal transmitted via the second scan signal line Gate_P(n), and the drive transistor T3 remains on during the first reset phase t1. Therefore, the data signal transmitted via the data signal line Data can be transmitted sequentially through the write transistor T4, the drive transistor T3, and the threshold compensation transistor T2 to the first node N1, causing a change in the voltage of the first node N1 until the voltage of the first node N1 reaches the sum of the threshold voltage of the drive transistor T3 and the voltage of the data signal line Data, causing the drive transistor T3 to turn off. During the data refresh and compensation phase t2, the threshold voltage of the drive transistor T3 can be written to the first node N1 to compensate for the threshold voltage drift of the drive transistor T3, preventing changes in the drive signal generated by the drive transistor T3 and avoiding any impact on the luminous intensity of the light-emitting device L. During this stage, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are in an off state under the control of the light-emitting control signal transmitted by the light-emitting control signal line EM.

[0089] In the second reset phase t3, the threshold compensation transistor T2 is turned off under the control of the first scan signal transmitted by the first scan signal line Gate_N(n), the write transistor T4 is turned off under the control of the second scan signal transmitted by the second scan signal line Gate_P(n), and the second reset transistor T7 and the third reset transistor T8 are turned on under the control of the second reset control signal transmitted by the second reset control signal line Reset_H(n). This causes the third initialization signal transmitted by the third initialization signal line Vinit3 to be written to the second node N2 and the second initialization signal transmitted by the second initialization signal line Vinit2 to be written to the fourth node N4, that is, to be written to the first electrode (e.g., specifically the anode) of the light-emitting device L, thereby resetting the second node N2 and the anode of the light-emitting device L.

[0090] During the light-emitting stage t4, the second reset transistor T7 and the third reset transistor T8 are disconnected under the control of the second reset control signal transmitted on the second reset control signal line Reset_H(n). The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control signal transmitted on the light-emitting control signal line EM. This causes the first voltage signal transmitted on the first voltage signal line VDD to be written into the first pole region of the driving transistor T3. The anode voltage of the light-emitting device L can be written into the second pole region of the driving transistor T3, thereby turning on the driving transistor T3. This forms a path between the first voltage signal line VDD and the light-emitting device L, causing the light-emitting device L to emit light.

[0091] In some display substrates, to meet the ever-increasing demand for high PPI (pixels per inch), the design of the pixel circuit planar structure is limited by the pixel space size, leading to some technical problems in the related display substrates. Specifically, Figure 2A is a schematic diagram of the planar structure of multiple pixel circuits in a display substrate in some embodiments. Figures 2B, 2C, 2D, 2E, 2F, and 2G are schematic diagrams of the planar structure of each single-layer film in Figure 2A. Figure 2H is a schematic diagram of the cross-sectional structure along the cutting line AA' in Figure 2A.

[0092] Figure 2A shows only a partial planar structural diagram of the film layers, specifically including a first semiconductor layer Poly1, a first gate metal layer Gate1, a second gate metal layer Gate2, a third gate metal layer Gate3, and a first source / drain metal layer SD1, which are sequentially stacked along the direction away from the substrate. More specifically, Figures 2B, 2C, 2D, 2E, and 2F are respectively planar structural diagrams of the first semiconductor layer Poly1, the first gate metal layer Gate1, the second gate metal layer Gate2, the third gate metal layer Gate3, and the first source / drain metal layer SD1.

[0093] Furthermore, those skilled in the art will understand that the embodiment shown in FIG2A also includes a second semiconductor layer Poly2 (not shown), a second source-drain metal layer SD2, etc. For example, as shown in FIG2G, the first and second terminals of the threshold compensation transistor T2 are located in the second semiconductor layer Poly2. For example, the data signal line Data and the first voltage signal line VDD may be located in the second source-drain metal layer SD2 (not shown in the embodiments of this disclosure).

[0094] As shown in Figure 2A, and in conjunction with Figures 2B, 2C, 2D, 2E, and 2F, the light-emitting control signal line EM, the second scan signal line Gate_P(n), the first reset control signal line Reset_P(n), the second reset control signal line Reset_H(n), and the first plate C1 of the storage capacitor Cst are located on the first gate metal layer Gate1. The first gate metal layer Gate1 also includes the gate of the first reset transistor T1, the gate of the data writing transistor T4, the gate of the first light-emitting control transistor T5, the gate of the second light-emitting control transistor T6, the gate of the second reset transistor T7, and the gate of the third reset transistor T8. Specifically, the gate of the first reset transistor T1 is connected to the first reset control signal line Reset_P(n) in a single structure; the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control signal line EM in a single structure; and the gates of the second reset transistor T7 and the third reset transistor T8 are connected to the second reset control signal line Reset_H(n) in a single structure.

[0095] The first initialization signal line Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vinit3 are located in the third gate metal layer Gate3. The third gate metal layer also includes the gate of the threshold compensation transistor T2.

[0096] The first scan signal line Gate_N(n) and the second plate C2 of the storage capacitor Cst are located on the second gate metal layer Gate2.

[0097] Among them, the light emission control signal line EM, the second scan signal line Gate_P(n), the first reset control signal line Reset_P(n), the second reset control signal line Reset_H(n), the first initialization signal line Vinit1, the second initialization signal line Vinit2, the third initialization signal line Vinit3, and the first scan signal line Gate_N(n) all extend along the first direction. The first plate C1 of the storage capacitor Cst also serves as the gate of the driving transistor T3.

[0098] As shown in Figure 2B, the active layers of the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the second reset transistor T7, and the third reset transistor T8 are located in the first semiconductor layer Poly1. In addition, the active layers on both sides of each transistor are made conductive, thereby forming the first and second electrodes of each transistor. That is, the first and second electrodes of each transistor can be formed into an integral structure with the active layer.

[0099] Obviously, in the embodiment shown in Figure 2A, the orthographic projection of the light emission control signal line EM on the substrate and the orthographic projection of the third initialization signal line Vinit3 on the substrate largely overlap. Therefore, in the display area of ​​the display substrate, the parasitic capacitance between the light emission control signal line EM and the third initialization signal line Vinit3 is large, which will cause the power consumption of the display substrate to be large when the drive signal with a frequency of 1Hz is used.

[0100] As shown in Figure 2F, the first source / drain metal layer SD1 includes multiple transition sections for realizing electrical connections between various gate metal layers, the first semiconductor layer Poly1, etc. Specifically, the first source / drain metal layer SD1 includes a first transition section 10, a third transition section 30, a fourth transition section 40, a fifth transition section 70, a sixth transition section 80, a seventh transition section 90, an eighth transition section 100, a ninth transition section 110, and a tenth transition section 120.

[0101] As shown in Figures 2A and 2H, the orthographic projection of the first transition portion 10 on the substrate overlaps with both the first electrode of the third reset transistor T8 and the third initialization signal line Vinit3. It is electrically connected to the first electrode of the third reset transistor T8 and the third initialization signal line Vinit3 via vias, thereby achieving the electrical connection between the first electrode of the third reset transistor T8 and the third initialization signal line Vinit3. It is understood that in this embodiment, a via refers to a via that penetrates an insulating layer located between two metal layers. For example, if the display substrate also includes an interlayer dielectric layer located between the third gate metal layer Gate3 and the first source / drain metal layer SD1, then when achieving the electrical connection between the first transition portion 10 located in the first source / drain metal layer SD1 and the third initialization signal line Vinit3 located in the third gate metal layer Gate3, the via refers to a via that penetrates the interlayer dielectric layer; that is, the first transition portion 10 is electrically connected to the third initialization signal line Vinit3 through a via that penetrates the interlayer dielectric layer.

[0102] For example, as shown in FIG2H, the display substrate further includes a first gate insulating layer GI1 located between the first semiconductor layer Poly1 and the first gate metal layer Gate1, a second gate insulating layer GI2 located between the first gate metal layer Gate1 and the second gate metal layer Gate2, a third gate insulating layer GI3 located between the second gate metal layer Gate2 and the third metal layer, and an interlayer dielectric layer ILD located between the third gate metal layer Gate3 and the first source / drain metal layer SD1. The first transition portion 10 is electrically connected to the first electrode of the third reset transistor through a via penetrating the first gate insulating layer GI1, the second gate insulating layer GI2, the third gate metal layer Gate3 and the interlayer dielectric layer ILD.

[0103] Furthermore, the multiple pixel circuits include multiple rows of pixel circuits, each row comprising multiple groups of pixel circuits arranged along a first direction. Each pixel circuit group includes two pixel circuits arranged along the first direction. The first terminals of two adjacent third reset transistors T8 in different pixel circuit groups are connected to form a first integrated structure. Additionally, the first junction portion 10 corresponding to the first terminals of these two third reset transistors T8 is connected to form a second integrated structure. The second integrated structure is electrically connected to the first integrated structure through a via penetrating the first gate insulating layer GI1, the second gate insulating layer GI2, the third gate metal layer Gate3, and the interlayer dielectric layer ILD.

[0104] The orthographic projection of the third transition portion 30 on the substrate SUB overlaps with the orthographic projection of either the first terminal of the second reset transistor T7 or the second initialization signal line Vinit2 on the substrate SUB. The third transition portion 30 is electrically connected to the first terminal of the second reset transistor T7 and the second initialization signal line Vinit2 respectively via vias. Specifically, the third transition portion 30 is electrically connected to the second initialization signal line Vinit2 via a via penetrating the interlayer dielectric layer ILD. The third transition portion 30 is electrically connected to the first terminal of the second reset transistor T7 via a via penetrating the first gate insulating layer GI1, the second gate insulating layer GI2, the third gate insulating layer GI3, and the interlayer dielectric layer ILD.

[0105] The orthographic projection of the fourth transition section 40 on the substrate SUB overlaps with the orthographic projection of either the first terminal of the first reset transistor T1 or the first initialization signal line Vinit1 on the substrate SUB. The fourth transition section 40 is electrically connected to the first terminal of the first reset transistor T1 and the first initialization signal line Vinit1 respectively via vias. Specifically, the fourth transition section 40 is electrically connected to the first initialization signal line Vinit1 via a via penetrating the interlayer dielectric layer ILD. The fourth transition section 40 is electrically connected to the first terminal of the first reset transistor T1 via a via penetrating the first gate insulating layer GI1, the second gate insulating layer GI2, the third gate metal layer Gate3, and the interlayer dielectric layer ILD.

[0106] The orthographic projection of the fifth adapter 70 on the substrate SUB overlaps with the orthographic projection of either the first electrode of the write transistor T4 or the data signal line Data on the substrate SUB. The fifth adapter 70 is electrically connected to the first electrode of the write transistor T4 and the data signal line Data respectively via vias. For example, the fifth adapter 70 is electrically connected to the first electrode of the write transistor T4 via a via penetrating the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1. In one example, the data signal line Data is located in the second source / drain metal layer, and the display substrate also includes a passivation layer located between the first source / drain metal layer SD1 and the second source / drain metal layer. In this case, the data signal line Data is electrically connected to the fifth adapter 70 via a via penetrating the passivation layer.

[0107] The orthographic projection of the sixth adapter 80 on the substrate SUB overlaps with the orthographic projections of any one of the following on the substrate SUB: the first electrode of the first light-emitting control transistor T5, the second electrode C2 of the storage capacitor Cst, and the first voltage signal line VDD. The sixth adapter 80 is electrically connected to the first electrode of the first light-emitting control transistor T5, the second electrode C2 of the storage capacitor Cst, and the first voltage signal line VDD via vias, respectively. For example, the sixth adapter 80 is electrically connected to the first electrode of the write transistor T4 of the first light-emitting control transistor T5 via a via penetrating the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1. The sixth adapter 80 is electrically connected to the second electrode C2 of the storage capacitor Cst via a via penetrating the interlayer dielectric layer ILD and the third gate insulating layer GI3. In one example, the first voltage signal line VDD is located in the second source-drain metal layer, and the first voltage signal line VDD is electrically connected to the sixth adapter 80 via a via penetrating the passivation layer.

[0108] The orthographic projection of the seventh adapter 90 on the substrate SUB overlaps with the orthographic projections of either the second terminal of the first light-emitting control transistor T5 or the second terminal of the third reset transistor T8 on the substrate SUB. The seventh adapter 90 is electrically connected to the second terminals of both the first light-emitting control transistor T5 and the third reset transistor T8 via vias. For example, the seventh adapter 90 is electrically connected to the second terminal of the first light-emitting control transistor T5 via a via penetrating the interlayer dielectric layer (ILD), the third gate insulating layer (GI3), the second gate insulating layer (GI2), and the first gate insulating layer (GI1). The seventh adapter 90 is also electrically connected to the second terminal of the third reset transistor T8 via a via penetrating the interlayer dielectric layer (ILD), the third gate insulating layer (GI3), the second gate insulating layer (GI2), and the first gate insulating layer (GI1). As shown in FIG2B, the second terminal of the data writing transistor T4, the first terminal of the driving transistor T3, and the second terminal of the first light-emitting control transistor T5 are connected as a single structure.

[0109] The orthographic projection of the eighth adapter 100 on the substrate SUB overlaps with the orthographic projections of the second terminal of the first light-emitting control transistor T5, the second terminal of the driving transistor T3, and the first terminal of the second light-emitting control transistor T6 on the substrate SUB. Furthermore, the eighth adapter 100 is electrically connected to the second terminal of the first light-emitting control transistor T5, the second terminal of the driving transistor T3, and the first terminal of the second light-emitting control transistor T6 via vias. For example, the eighth adapter 100 is electrically connected to the second terminal of the first light-emitting control transistor T5, the second terminal of the driving transistor T3, and the first terminal of the second light-emitting control transistor T6 via different vias penetrating the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1, respectively.

[0110] The orthographic projection of the ninth transition section 110 on the substrate SUB overlaps with the orthographic projection of either the first electrode of the threshold compensation transistor T2 or the first plate C1 (gate of the driving transistor T3) of the storage capacitor Cst. The ninth transition section 110 is electrically connected to the gate of the driving transistor T3, the first electrode of the threshold compensation transistor T2, and the first plate C1 of the storage capacitor C through vias, respectively. For example, the ninth transition section 110 is electrically connected to the first plate C1 (gate of the driving transistor T3) of the storage capacitor C through a via penetrating the interlayer dielectric layer ILD, the third gate insulating layer GI3, and the second gate insulating layer GI2. In one example, the second semiconductor layer is located between the second gate metal layer Gate2 and the third gate metal layer Gate3. The third gate insulating layer GI3 includes a first sub-gate insulating layer located between the second semiconductor layer and the second gate metal layer Gate2 and a second sub-gate insulating layer located between the second semiconductor layer and the third gate metal layer Gate3. The ninth transition portion 110 is electrically connected to the first electrode of the threshold compensation transistor T2 through a via penetrating the interlayer dielectric layer ILD and the second sub-gate insulating layer.

[0111] The orthographic projection of the tenth adapter 120 on the substrate SUB overlaps with the orthographic projections of either the first terminal of the second light-emitting control transistor T6 or the second terminal of the second reset transistor T7 on the substrate SUB. The tenth adapter 120 is electrically connected to the first terminal of the second light-emitting control transistor T6 and the second terminal of the second reset transistor T7 via vias, respectively. For example, the tenth adapter 120 is connected to the first terminal of the second light-emitting control transistor T6 and the second terminal of the second reset transistor T7 via vias penetrating the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1, respectively.

[0112] In addition, the first source / drain metal layer SD1 also includes at least one first auxiliary signal line Vinit1' extending along the second direction, at least one second auxiliary signal line Vinit2' extending along the second direction, and at least one third auxiliary signal line Vinit3' extending along the second direction.

[0113] Part of the fourth adapter 40 is electrically connected to the first auxiliary signal line Vinit1'. For example, the first source / drain metal layer SD1 also includes a second connection part 2. The fourth adapter 40 is electrically connected to the first auxiliary signal line Vinit1' via the second connection part 2.

[0114] Simultaneously, the orthographic projection of this fourth adapter portion 40 on the substrate SUB overlaps with the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB and is electrically connected through a via. For example, the fourth adapter portion 40 is electrically connected to the first initialization signal line Vinit1 through a via penetrating the interlayer dielectric layer (ILD). Clearly, the first auxiliary signal line Vinit1' and the first initialization signal line Vinit1 are electrically connected through a portion of the fourth adapter portion 40.

[0115] The orthographic projection of the second auxiliary signal line Vinit2' onto the substrate SUB overlaps with the orthographic projection of the second initialization signal line Vinit2 onto the substrate SUB. The second auxiliary signal line Vinit2' is electrically connected to the second initialization signal line Vinit2 through a via. For example, the second auxiliary signal line Vinit2' is electrically connected to the second initialization signal line Vinit2 through a via that penetrates the interlayer dielectric layer ILD. Specifically, the specific location of the via is located at the corresponding position of the line frame a in Figures 2E and 2F.

[0116] The orthographic projection of the third auxiliary signal line Vinit3' onto the substrate SUB overlaps with the orthographic projection of the third initialization signal line Vinit3 onto the substrate SUB. Furthermore, the third auxiliary signal line Vinit3' is electrically connected to the third initialization signal line Vinit3 through a via. For example, the third auxiliary signal line Vinit3' is electrically connected to the third initialization signal line Vinit3 through a via that penetrates the interlayer dielectric layer (ILD).

[0117] In some embodiments, the electrical connection between the third auxiliary signal line Vinit3' and the third initialization signal line Vinit3 can be similar to the electrical connection between the second auxiliary signal line Vinit2' and the second initialization signal line Vinit2, by providing an additional connection portion electrically connected to a portion of the first adapter 10. In other embodiments, the electrical connection between the third auxiliary signal line Vinit3' and the third initialization signal line Vinit3 can be similar to the electrical connection between the first auxiliary signal line Vinit1' and the first initialization signal line Vinit1, where the first auxiliary signal line Vinit1' is directly electrically connected to the first initialization signal line Vinit1 through a via penetrating the interlayer dielectric layer (ILD).

[0118] Clearly, the first initialization signal line Vinit1 extending along the first direction and the first auxiliary signal line Vinit1' extending along the second direction intersect to form a "grid"-shaped signal transmission line, the second initialization signal line Vinit2 extending along the first direction and the second auxiliary signal line Vinit2' extending along the second direction intersect to form a "grid"-shaped signal transmission line, and the third initialization signal line Vinit3 extending along the first direction and the third auxiliary signal line Vinit3' extending along the second direction intersect to form a "grid"-shaped signal transmission line.

[0119] As shown in the structural diagrams in Figures 2A, 2E, and 2F, the orthogonal projection of the first adapter 10 onto the substrate SUB overlaps with the first initialization signal line Vinit1. The voltage difference between the third initialization signal transmitted by the first adapter 10 and the first initialization signal line Vinit1 is relatively large. For example, in one instance, the third initialization signal transmitted in the first adapter 10 is a positive potential, typically 4.5V to 7V, while the first initialization signal transmitted in the first initialization signal line Vinit1 is a negative potential, typically -2.5V to -5V. With continued use, the large voltage difference between the first initialization signal line Vinit1 and the signal transmitted by the first adapter 10 can easily lead to problems such as burning of the display substrate.

[0120] In order to at least alleviate or solve one of the aforementioned technical problems, this disclosure provides a display substrate and a display panel.

[0121] Figure 3A is a schematic planar structure diagram of multiple pixel circuits in a display substrate according to some embodiments of this disclosure. Figure 3A only shows a portion of the film layers, specifically including a first semiconductor layer Poly1, a first gate metal layer Gate1, a second gate metal layer Gate2, a third gate metal layer Gate3, and a first source / drain metal layer SD1, stacked sequentially along the direction away from the substrate SUB. Figures 3B, 3C, 3D, 3E, 3F, and 3G are schematic planar structures of each single film layer in Figure 3A. Specifically, Figures 3B, 3C, 3D, and 3E are, respectively, schematic planar structures of the first semiconductor layer Poly1, the first gate metal layer Gate1, the second gate metal layer Gate2, the third gate metal layer Gate3, and the first source / drain metal layer SD1. Figures 3F and 3G are schematic planar structures of the first source / drain metal layer SD1. Figure 3H is a cross-sectional structure diagram along the cutting line BB' in the display substrate shown in Figure 3A. Figure 3I is a partial cross-sectional structure diagram of the display substrate shown in Figure 3A.

[0122] As shown in Figures 3A, 3C, 3D and 3H, in some embodiments, a display substrate of the present disclosure has a third initialization signal line Vinit3 whose orthogonal projection on the substrate SUB does not overlap with the orthogonal projection of the light emission control signal line EM on the substrate SUB.

[0123] In this embodiment of the disclosure, the non-overlapping projection of the third initialization signal line Vinit3 onto the substrate SUB and the non-overlapping projection of the light emission control signal line EM onto the substrate SUB can avoid excessive total capacitance of the light emission control signal line EM in the display area, thereby reducing the power consumption of the display substrate.

[0124] As shown in Figures 3A, 3D and 3E, in some embodiments, at least two of the first initialization signal line Vinit1, the second initialization signal line Vinit2 and the third initialization signal line Vinit3 are located on different layers.

[0125] Compared to the display substrate in Figure 2A, the first initialization signal line Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vinit3 are all disposed on the third gate metal layer Gate3. Due to the connection relationship of each transistor, the spatial distribution of the third gate metal layer Gate3 is limited, resulting in the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB and the orthographic projection of the light emission control signal line EM on the substrate SUB largely overlapping. In this embodiment, at least two of the first initialization signal line Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vinit3 are located on different layers. For example, the first initialization signal line Vinit1 and the second initialization signal line Vinit2 can both be located on the third gate metal layer Gate3, and the third initialization signal line Vinit3 can be located on the first gate metal layer Gate1 or the second gate metal layer Gate2. Alternatively, the first initialization signal line Vinit1 and the third initialization signal line Vinit3 can both be located on the third gate metal layer Gate3, and the second initialization signal line Vinit2 can be located on the first gate metal layer Gate1 or the second gate metal layer Gate2.

[0126] In other words, this embodiment of the present disclosure places the first initialization signal line Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vinit3 on at least two layers. This avoids overlap between the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB and the orthographic projection of the light emission control signal line EM on the substrate SUB, thereby preventing excessive power consumption. It also avoids problems such as burn-in caused by the overlap between the orthographic projection of the first adapter 10 on the substrate SUB and the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB, which would occur when connecting the third reset transistor.

[0127] As shown in Figures 3A, 3D, 3E and 3H, the orthographic projections of the first initialization signal line Vinit1 on the substrate SUB and the third initialization signal line Vinit3 on the substrate SUB do not overlap.

[0128] In this embodiment of the disclosure, since the first initialization signal line Vinit1 and the third initialization signal line Vinit3 can be located on different layers, further ensuring that the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB and the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB do not overlap can prevent the display area from burning due to excessive voltage.

[0129] As shown in Figures 3A, 3D, 3E, and 3H, specifically, the third initialization signal line Vinit3 is located on the second gate metal layer Gate2. The first initialization signal line Vinit1 and the second initialization signal line Vinit2 are located on the third gate metal layer Gate3.

[0130] Considering the high PPI requirement, compared to the pixel circuit shown in Figure 2A, in order to at least not increase the planar space occupied by the pixel circuit, the embodiment of this disclosure sets the third initialization signal line Vinit3 in the second gate metal layer Gate2, and sets the first initialization signal line Vinit1 and the second initialization signal line Vinit2 in the third gate metal layer Gate3. This can ensure that the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB does not overlap with the orthographic projection of the light emission control signal line EM on the substrate SUB, and at the same time, it can also ensure that the orthographic projection of the first adapter 10 on the substrate SUB does not overlap with the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB.

[0131] Specifically, as shown in Figures 3A, 3D, 3E, and 3H, the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB is located between the orthographic projections of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the substrate SUB. As shown in Figures 3A, 3F, and 3G, in this embodiment of the present disclosure, the orthographic projection of the first adapter 10 on the substrate SUB overlaps with the orthographic projections of either the third initialization signal line Vinit3 or the first electrode of the third reset transistor on the substrate SUB. Furthermore, the first adapter 10 is electrically connected to both the third initialization signal line Vinit3 and the first electrode of the third reset transistor via vias. The orthographic projection of the first adapter 10 on the substrate SUB is located between the orthographic projections of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the substrate SUB, and does not overlap with the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB.

[0132] Compared to the display substrate in Figure 2A, where the orthographic projection of the first transition portion 10 on the substrate SUB overlaps with the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB, this embodiment of the present disclosure, by moving the film layer where the third initialization signal line Vinit3 is located and setting the specific position of the third initialization signal line Vinit3 on that film layer, can ensure that the orthographic projection of the light emission control signal line EM on the substrate SUB and the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB do not overlap, while also achieving that the orthographic projection of the first transition portion 10 on the substrate SUB and the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB do not overlap.

[0133] As shown in Figures 3G and 3H, the first source / drain metal layer SD1 includes at least one third auxiliary signal line Vinit3' extending along a second direction and at least one second transition portion 20, wherein the second direction intersects the first direction. For example, the second direction may be perpendicular to the first direction.

[0134] The orthographic projection of the third initialization signal line Vinit3 on the substrate SUB and the orthographic projection of the third auxiliary signal line Vinit3' on the substrate SUB overlap with the orthographic projection of the second adapter 20 on the substrate SUB. The second adapter 20 is electrically connected to the third auxiliary signal line Vinit3'. For example, specifically, as shown in Figures 2H and 2H, the first source / drain metal layer SD1 includes at least one third connection portion 3, which is electrically connected to the third auxiliary signal line Vinit3' and the second adapter 20, respectively.

[0135] Furthermore, the second adapter 20 is electrically connected to the third initialization signal line Vinit3 via a via. For example, the second adapter 20 is electrically connected to the third initialization signal line Vinit3 via a via that penetrates the interlayer dielectric layer (ILD).

[0136] In this embodiment, the third auxiliary signal line Vinit3' and the third initialization signal line Vinit3 are electrically connected via the second adapter 20. This allows the third initialization signal to be transmitted from the third auxiliary signal line Vinit3' to the third initialization signal line Vinit3, and then to the driving circuit via the third initialization signal line Vinit3. Clearly, the third initialization signal line Vinit3 extending along the first direction and the third auxiliary signal line Vinit3' extending along the second direction form a "grid" pattern, ensuring the uniformity of the third initialization signal across the entire display area, thereby guaranteeing the uniformity of the light emission effect of the entire display substrate.

[0137] Furthermore, the orthographic projection of the second adapter 20 on the substrate SUB does not overlap with the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB, and / or, the orthographic projection of the second adapter 20 on the substrate SUB does not overlap with the orthographic projection of the second initialization signal line Vinit2 on the substrate SUB.

[0138] In this embodiment of the present disclosure, the specific position of the second transition section 20 is set according to the position of the third initialization signal line Vinit3 in the first source-drain metal layer SD1. This avoids the second transition section 20's orthogonal projection on the substrate SUB from not overlapping with the orthogonal projection of at least one of the first initialization signal line Vinit1 and the second initialization signal line Vinit2 on the substrate SUB. This prevents the third initialization signal transmitted in the second transition section 20 from overlapping with the first initialization signal and the second initialization signal in the display area, thereby avoiding mutual interference between them.

[0139] As shown in Figures 3A, 3F, 3G, and 3H, the first source / drain metal layer SD1 further includes at least one first auxiliary signal line Vinit1' extending along the second direction and at least one second auxiliary signal line Vinit2' extending along the second direction. In addition, the first source / drain metal layer SD1 further includes at least one first redundancy transition section 50, and / or at least one second redundancy transition section 60.

[0140] In this configuration, the orthographic projection of the first redundant transition section 50 onto the substrate SUB overlaps with the orthographic projection of the third initialization signal line Vinit3 onto the substrate SUB. Furthermore, the direction from the first redundant transition section 50 to the first auxiliary signal line Vinit1' is the same as the direction from the second transition section 20 to the third auxiliary signal line Vinit3'. The first redundant transition section 50 is electrically insulated from the first auxiliary signal line Vinit1'. The first redundant transition section 50 is electrically connected to the third initialization signal line Vinit3 via a via. For example, similar to the second transition section 20, the first redundant transition section 50 is electrically connected to the third initialization signal line Vinit3 via a via penetrating the interlayer dielectric layer (ILD).

[0141] The orthographic projection of the second redundant transition section 60 on the substrate SUB overlaps with the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB. Furthermore, the direction from the second redundant transition section 60 to the second auxiliary signal line Vinit2' is the same as the direction from the second transition section 20 to the third auxiliary signal line Vinit3'. The second redundant transition section 60 is electrically insulated from the second auxiliary signal line Vinit2'. The second redundant transition section 60 is electrically connected to the third initialization signal line Vinit3 via a via. Similarly, the second redundant transition section 60 can also be electrically connected to the third initialization signal line Vinit3 via a via penetrating the interlayer dielectric layer (ILD).

[0142] This embodiment of the disclosure further ensures that vertical stripe-related defects are avoided by providing a first redundant transition section 50 and a second redundant transition section 60, which are located similarly to the second transition section 20, next to the first auxiliary signal line Vinit1' and the second auxiliary signal line Vinit2'.

[0143] As shown in Figures 3G and 3H, the distance between the edge of the second transition section 20 away from the third auxiliary signal line Vinit3' and the third auxiliary signal line Vinit3' is the first distance D1; the distance between the edge of the first redundant transition section 50 away from the first auxiliary signal line Vinit1' and the first auxiliary signal line Vinit1' is the second distance D2; the distance between the edge of the second redundant transition section 60 away from the second auxiliary signal line Vinit2' and the second auxiliary signal line Vinit2' is the third distance D3; wherein, the ratio of either the second distance D2 or the third distance D3 to the first distance D1 is 0.5 to 1.5.

[0144] For example, in one instance, the ratio of either the second distance D2 or the third distance D3 to the first distance D1 is 1. That is, in this case, the first distance D1, the second distance D2, and the third distance D3 are all equal.

[0145] It is understandable that the positions of the first redundant transition unit 50 relative to the first auxiliary signal line Vinit1', the second redundant transition unit 60 relative to the second auxiliary signal line Vinit2', and the second transition unit 20 relative to the third auxiliary signal line Vinit3' are the same.

[0146] In other words, in this embodiment of the present disclosure, a first redundant transition section 50, a second redundant transition section 60, and a second transition section 20 are respectively provided at the same positions of the first auxiliary signal line Vinit1', the second auxiliary signal line Vinit2', and the third auxiliary signal line Vinit3'. Based on this design, this embodiment of the present disclosure can further ensure that vertical stripe-related defects are avoided.

[0147] As shown in Figures 3A, 3B and 3D, the orthogonal projection of the second electrode of the second reset transistor onto the substrate SUB is located on the side of the orthogonal projection of the third initialization signal line Vinit3 onto the substrate SUB that is far from the first initialization signal line Vinit1.

[0148] As shown in Figures 3F and 3G, the first source / drain metal layer SD1 includes a third transition portion 30. Referring to Figure 3A, it can be seen that either the orthographic projection of the second electrode of the second reset transistor on the substrate SUB and the orthographic projection of the second reset control signal line Reset_H(n) on the substrate SUB overlaps with the orthographic projection of the third transition portion 30 on the substrate SUB. The third transition portion 30 is electrically connected to the second electrode of the second reset transistor and the second reset control signal line Reset_H(n) through vias. For example, the third transition portion 30 is electrically connected to the second electrode of the second reset transistor through a via penetrating the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1. The third transition portion 30 is also electrically connected to the second reset control signal line Reset_H(n) through a via penetrating the interlayer dielectric layer ILD, the third gate insulating layer GI3, and the second gate insulating layer GI2.

[0149] The orthographic projection of the third adapter 30 on the substrate SUB overlaps with the orthographic projection of the third reset control signal line on the substrate SUB.

[0150] Figure 4A is a planar structural schematic diagram of multiple pixel circuits within a display substrate in some other embodiments of this disclosure. Figure 4A only shows a portion of the film layers, specifically including a first semiconductor layer Poly1, a first gate metal layer Gate1, a second gate metal layer Gate2, a third gate metal layer Gate3, and a first source / drain metal layer SD1, sequentially stacked along the direction away from the substrate SUB. Figures 4B, 4C, 4D, 4E, 4F, and 4G are planar structural schematic diagrams of each single film layer in Figure 4A. Specifically, Figures 4B, 4C, 4D, and 4E are, respectively, planar structural schematic diagrams of the first semiconductor layer Poly1, the first gate metal layer Gate1, the second gate metal layer Gate2, the third gate metal layer Gate3, and the first source / drain metal layer SD1. Figures 4F and 4G are planar structural schematic diagrams of the first source / drain metal layer SD1. Figure 4H is a cross-sectional structural schematic diagram along the cutting line CC' in the display substrate shown in Figure 4A.

[0151] As shown in Figures 4A, 4D, and 4E, in some embodiments, the second initialization signal line Vinit2 is located on the second gate metal layer Gate2. The first initialization signal line Vinit1 and the third initialization signal line Vinit3 are located on the third gate metal layer Gate3.

[0152] Similarly, considering the high PPI requirement, compared to the pixel circuit shown in FIG2A, in order to at least not increase the planar space occupied by the pixel circuit, this disclosure provides another possible embodiment. Specifically, the second initialization signal line Vinit2 is set in the second gate metal layer Gate2, and the first initialization signal line Vinit1 and the third initialization signal line Vinit3 are set in the third gate metal layer Gate3. This enables the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB to not overlap with the orthographic projection of the light emission control signal line EM on the substrate SUB. At the same time, it also enables the orthographic projection of the first adapter 10 on the substrate SUB to not overlap with the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB.

[0153] As shown in Figures 4A, 4D, 4E and 4H, the orthographic projection of the first reset control signal line Reset_P(n) on the substrate SUB does not overlap with the orthographic projection of the second initialization signal line Vinit2 on the substrate SUB.

[0154] In this embodiment, the orthographic projection of the first reset control signal line Reset_P(n) on the substrate SUB does not overlap with the orthographic projection of the second initialization signal line Vinit2 on the substrate SUB, which can significantly reduce the total capacitance of the second initialization signal line Vinit2 in the display area and help avoid the three-screen problem.

[0155] Specifically, as shown in Figures 4A, 4D, and 4E, the orthographic projection of the second initialization signal line Vinit2 on the substrate SUB is located between the orthographic projections of the first initialization signal line Vinit1 and the third initialization signal line Vinit3 on the substrate SUB, and the orthographic projection of the first reset control signal line Reset_P(n) on the substrate SUB is located on the side of the second initialization signal line Vinit2 on the substrate SUB that is far from the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB.

[0156] As shown in Figures 4A, 4F, 4G and 4H, the orthographic projection of the first adapter 10 on the substrate SUB overlaps with the orthographic projection of the second initialization signal line Vinit2 on the substrate SUB, but the orthographic projection of the first adapter 10 on the substrate SUB does not overlap with the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB.

[0157] Similarly, the embodiments of this disclosure can also ensure that the orthographic projection of the light emission control signal line EM on the substrate SUB and the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB do not overlap, while ensuring that the orthographic projection of the first adapter 10 on the substrate SUB and the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB do not overlap, by moving the film layer where the third initialization signal line Vinit3 is located and setting the specific position of the third initialization signal line Vinit3 on the film layer.

[0158] As shown in Figures 4A, 4F, and 4G, the first source / drain metal layer SD1 includes a third transition section 30. The orthographic projection of the second initialization signal line Vinit2 on the substrate SUB and the orthographic projection of the second electrode of the second reset transistor on the substrate SUB overlap with the orthographic projection of the third transition section 30 on the substrate SUB. The third transition section 30 is electrically connected to the second initialization signal line Vinit2 and is electrically connected to the second electrode of the second reset transistor through a via. The orthographic projection of the third transition section 30 on the substrate SUB does not overlap with the orthographic projection of the first reset control signal line Reset_P(n) on the substrate SUB.

[0159] As shown in Figures 4F and 4G, the first source / drain metal layer SD1 also includes at least one first connection portion 1. As shown in Figure 4A, the first connection portion 1 is electrically connected to the second auxiliary signal line Vinit2' and the third adapter portion 30, respectively.

[0160] For example, in the display substrate shown in Figure 4A, multiple pixel circuits are arranged in multiple columns, and each column of pixel circuits includes multiple pixel circuits arranged along a second direction. An auxiliary signal line can be provided every two columns of pixel circuits. The auxiliary signal line can be a first auxiliary signal line Vinit1', a first auxiliary signal line Vinit2', and a first auxiliary signal line Vinit3'. Generally, to ensure the uniformity of signal transmission, the first auxiliary signal lines Vinit1', Vinit2', and Vinit3' are arranged alternately in sequence. Therefore, it can be understood that when the auxiliary signal line closest to the third adapter 30 is the second auxiliary signal line Vinit2', the third adapter 30 is electrically connected to the second auxiliary signal line Vinit2' through the first connecting part 1. When the auxiliary signal line closest to the third adapter 30 is either the first auxiliary signal line Vinit1' or the third auxiliary signal line Vinit3', the third adapter 30 is electrically insulated from either the first auxiliary signal line Vinit1' or the third auxiliary signal line Vinit3'.

[0161] In this embodiment, the third adapter 30 is electrically connected to the second signal line Vinit2' via the first connecting part 1. Since the third adapter 30 is electrically connected to the second initialization signal line Vinit2, the second auxiliary signal line Vinit2' is also electrically connected to the second initialization signal line Vinit2. This connection allows the second initialization signal to be transmitted from the second auxiliary signal line Vinit2' to the second initialization signal line Vinit2, and then to the pixel circuit via the second initialization signal line Vinit2. Clearly, the second initialization signal line Vinit2 extending along the first direction and the second auxiliary signal line Vinit2' extending along the second direction form a "grid" structure for transmitting the second initialization signal, ensuring the uniformity of the second initialization signal across the entire display area, thereby ensuring the uniformity of the light emission effect of the entire display substrate. Furthermore, this design helps reduce pixel size, facilitating the fulfillment of high PPI requirements.

[0162] As shown in Figures 4A and 4G, the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB and the orthographic projection of the third auxiliary signal line Vinit3' on the substrate SUB have a first overlap region, which is located within the frame b in Figure 4G. The third auxiliary signal line Vinit3' is electrically connected to the third initialization signal line Vinit3 through a via, and the orthographic projection of the via on the substrate SUB is located within the first overlap region. For example, the third auxiliary signal line Vinit3' is electrically connected to the third initialization signal line Vinit3 through a via penetrating the interlayer dielectric layer ILD, and the first overlap region overlaps with the orthographic projection of the first reset control signal line Reset_P(n) on the substrate SUB.

[0163] Optionally, in this embodiment of the present disclosure, the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB overlaps with the orthographic projection of the first reset control signal line Reset_P(n) on the substrate SUB.

[0164] Because the position of the third initialization signal line Vinit3 has changed, the electrical connection position between the third initialization signal line Vinit3 and the third auxiliary signal line Vinit3' in this embodiment of the present disclosure has changed compared to the electrical connection position between the third initialization signal line Vinit3 and the third auxiliary signal line Vinit3' in the embodiment shown in FIG2A.

[0165] As shown in Figures 3A and 3B, or Figures 4A and 4B, the multiple pixel circuits include multiple rows of pixel circuits, each row of pixel circuits includes multiple groups of pixel circuits arranged along a first direction, and each group of pixel circuits includes two pixel circuits arranged along the first direction. The first terminals of the two first reset transistors in the same pixel circuit group are connected to form a third integrated structure.

[0166] The first source / drain metal layer SD1 also includes a fourth transition section 40, which is electrically connected to the first initialization signal line Vinit1 and the third integrated structure via vias. For example, the fourth transition section 40 is electrically connected to the first initialization signal line Vinit1 via vias penetrating the interlayer dielectric layer ILD, the third gate insulating layer GI3, and the second gate insulating layer GI2, and is electrically connected to the integrated structure via vias penetrating the interlayer dielectric layer ILD, the third gate insulating layer GI3, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0167] In this embodiment, connecting the first terminals of two first reset transistors in the same pixel circuit group into a single structure, and electrically connecting the fourth adapter 40 to the first initialization signal line Vinit1 and the single structure via vias, reduces the planar space occupied by the fourth adapter 40, avoids overlap with other signals such as the first initialization signal and the second reset control signal, and improves the flexibility of signal arrangement. It is understood that, based on solving the aforementioned technical problems, this disclosure reduces pixel size by connecting two first reset transistors in the same pixel circuit group into a single structure, designing the fourth adapter 40, and using a "grid" design for the auxiliary signal lines and initialization signal lines, thereby meeting the requirements for high PPI.

[0168] As shown in Figures 3A and 3B, or Figures 4A and 4B, the shape of the orthographic projection of the third integral structure onto the substrate SUB is an asymmetrical shape.

[0169] Obviously, in the embodiments of this disclosure, the first reset transistor is an asymmetrical design, and the integrated structure formed by connecting two first reset transistors in the same pixel circuit group is also an asymmetrical design. Based on this design, the embodiments of this disclosure can ensure that the first initialization signal is connected to each pixel circuit even when the pixel space is insufficient.

[0170] As shown in Figures 3A, 3F, and 3G, or as shown in Figures 4A and 4B, the first source / drain metal layer SD1 further includes at least one second connection portion 2, which is electrically connected to the first auxiliary signal line Vinit1' and the fourth adapter portion 40, respectively.

[0171] For example, in the display substrate shown in FIG3A, when the auxiliary signal line closest to the fourth adapter 40 is the first auxiliary signal line Vinit2', the fourth adapter 40 is electrically connected to the first auxiliary signal line Vinit2' through the second connection 2. When the auxiliary signal line closest to the fourth adapter 40 is the second auxiliary signal line Vinit1' or the third auxiliary signal line Vinit3', the fourth adapter 40 is electrically insulated from the second auxiliary signal line Vinit2' or the third auxiliary signal line Vinit3'.

[0172] In this embodiment, the fourth adapter 40 is electrically connected to the first auxiliary line via the second connecting part 2. Since the fourth adapter 40 is electrically connected to the first initialization signal line Vinit1, the first auxiliary signal line Vinit1' is also electrically connected to the first initialization signal line Vinit1. This electrical connection allows the first initialization signal to be transmitted from the first auxiliary signal line Vinit1' to the first initialization signal line Vinit1, and then to the pixel circuit via the first initialization signal line Vinit1. Clearly, the first initialization signal line Vinit1 extending along the first direction and the first auxiliary signal line Vinit1' extending along the second direction form a "grid" structure for transmitting the first initialization signal, ensuring the uniformity of the first initialization signal across the entire display area, thereby ensuring the uniformity of the light emission effect of the entire display substrate. Furthermore, this design helps reduce pixel size, facilitating the fulfillment of high PPI requirements.

[0173] As can be seen from the above, compared with the display substrate shown in Figure 3A, the display substrate shown in Figure 4A no longer needs to set redundant transition parts in the first source / drain metal layer SD1 or other layers. Therefore, the design shown in Figure 4A can effectively improve the light transmittance of the display substrate.

[0174] As shown in Figures 3A, 3D, and 3E, or Figures 4A, 4D, and 4E, the orthogonal projection of the first electrode of the third reset transistor on the substrate SUB is located on the side of the orthogonal projection of the first initialization signal Vinit1 on the substrate SUB that is away from the light emission control signal line, and the orthogonal projection of the third initialization signal line Vinit3 on the substrate SUB is located on the side of the orthogonal projection of the first initialization signal Vinit1 on the substrate SUB that is away from the light emission control signal line.

[0175] Obviously, in this embodiment of the present disclosure, the orthographic projection of the first electrode of the third reset transistor on the substrate SUB and the orthographic projection of the third initialization signal line Vinit3 on the substrate SUB are located on the same side of the orthographic projection of the first initialization signal Vinit1 on the substrate SUB along the second direction. Therefore, when realizing the electrical connection between the first electrode of the third reset transistor and the third initialization signal line Vinit3, the first adapter 10 no longer needs to cross the first initialization signal line Vinit1. That is, the orthographic projection of the first adapter 10 on the substrate SUB and the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB do not overlap, thereby avoiding the problem of burning caused by a large voltage difference between the first initialization signal Vinit1 and the third initialization signal Vinit3.

[0176] Furthermore, as shown in Figures 3A, 3E, and 3G, or Figures 4A, 4E, and 4G, the orthographic projection of the first initialization signal line Vinit1 on the substrate SUB overlaps with the projection of the first auxiliary signal line Vinit1' on the substrate SUB. The first auxiliary signal line Vinit1' is electrically connected to the first initialization signal line Vinit1 through a via, for example, through a via penetrating the interlayer dielectric layer (ILD). Similarly, the first initialization signal line Vinit1 extending along the first direction and the first auxiliary signal line Vinit1' extending along the second direction form a "grid" pattern for transmitting the first initialization signal, ensuring the uniformity of the first initialization signal throughout the display area, thereby ensuring the uniformity of the light emission effect of the entire display substrate. This design also helps to reduce pixel size, facilitating the fulfillment of high PPI requirements.

[0177] It is understandable that, compared to the display substrate shown in Figure 2A, the position of the first initialization signal line Vinit1 in the display substrates shown in Figures 3A and 4A has not been changed. Therefore, in the display substrates shown in Figures 2A, 3A and 4A, the specific positions where the first auxiliary signal line Vinit1' and the first initialization signal line Vinit1 are electrically connected can be the same.

[0178] As shown in Figures 3A and 3H, and as shown in Figures 4A and 4H, the orthographic projections of any two of the third initialization signal line Vinit3, the second initialization signal line Vinit2, and the first initialization signal line Vinit1 onto the substrate SUB do not overlap. Therefore, the embodiments of this disclosure can avoid the problem of display defects caused by the overlap of initialization signals during the driving process.

[0179] This disclosure also provides a display panel, including a display substrate as described in any embodiment of this disclosure.

[0180] In summary, the display substrate, display panel, and display device disclosed herein can achieve a new pixel circuit structure design with initialization signal lines (first initialization signal line Vinit1, second initialization signal line Vinit2, and third initialization signal line Vinit3) under the premise of high PPI and small pixel size. This not only improves product yield but also meets the strong demand from the market and customers for low power consumption and high PPI of the panel.

[0181] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display substrate, characterized in that, include: Substrate; Multiple rows of pixel circuits extending along a first direction are arranged along a second direction, which intersects the first direction. Each pixel circuit row includes multiple pixel circuit groups arranged along the first direction. Each pixel circuit group includes two pixel circuits arranged along the first direction. Each pixel circuit includes a driving transistor, a first light-emitting control transistor, a first reset transistor, and a third reset transistor. The gate of the first light-emitting control transistor is connected to a light-emitting control signal line, and the first electrode of the first light-emitting control transistor is connected to a first voltage signal line. The gate of the third reset transistor is connected to a second reset control signal line, and the first electrode of the third reset transistor is connected to a third initialization signal line. The second electrode of the third reset transistor is electrically connected to the first electrode of the driving transistor and the second electrode of the first light-emitting control transistor. The gate of the first reset transistor is connected to the first reset control signal line. The first electrodes of two first reset transistors in the same pixel circuit group are connected to a single structure, which is connected to the first initialization signal line. The second electrode of the first reset transistor is connected to the second electrode of the driving transistor. The second reset control signal line and the light emission control signal line both extend along the first direction and are disposed on the same layer. The first auxiliary signal line extends along the second direction and is disposed on a different layer from the first initialization signal line. The first initialization signal line is electrically connected to the first auxiliary signal line. The third initialization signal line is located on the side of the layer where the second reset control signal line is located away from the substrate and extends along the first direction. The orthographic projection of the third initialization signal line on the substrate does not overlap with the orthographic projection of the light emission control signal line on the substrate.

2. The display substrate according to claim 1, characterized in that, The pixel circuit further includes: a second reset transistor, the gate of the second reset transistor is connected to a second reset control signal line, the first terminal of the second reset transistor is connected to the second reset control signal line, the second terminal of the second reset transistor is connected to a light-emitting device, and the first initialization signal line and the second initialization signal line both extend along the first direction; Wherein, at least two of the first initialization signal line, the second initialization signal line and the third initialization signal line are located on different layers.

3. The display substrate according to claim 2, characterized in that, The orthographic projection of the first electrode of the third reset transistor on the substrate is located on the side of the first initialization signal line on the substrate away from the light emission control signal line, and the orthographic projection of the third initialization signal line on the substrate is located on the side of the third initialization signal line on the substrate away from the light emission control signal line.

4. The display substrate according to claim 2, characterized in that, At least one of the third initialization signal line and the second initialization signal line is located on a different layer from the first initialization signal line, and the orthographic projection of the third initialization signal line and the second initialization signal line on the substrate does not overlap with the orthographic projection of the first initialization signal line on the substrate; And / or, the orthographic projection of the first reset control signal line on the substrate does not overlap with the orthographic projection of the second initialization signal line on the substrate.

5. The display substrate according to claim 2, characterized in that, The light emission control signal line, the first reset control signal line, and the second reset control signal line are located in the first gate metal layer; The third initialization signal line is located in the second gate metal layer; The first initialization signal line and the second initialization signal line are located in the third gate metal layer; The first gate metal layer, the second gate metal layer, and the third gate metal layer are arranged sequentially in a direction away from the substrate.

6. The display substrate according to claim 5, characterized in that, The orthographic projection of the third initialization signal line on the substrate is located between the orthographic projections of the first initialization signal line on the substrate and the orthographic projections of the second initialization signal line on the substrate; The display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate. The first source / drain metal layer includes a first transition portion. The orthographic projection of the first transition portion on the substrate overlaps with the orthographic projection of either the third initialization signal line or the first electrode of the third reset transistor on the substrate. The first transition portion is electrically connected to the third initialization signal line and the first electrode of the third reset transistor respectively through vias. The orthographic projection of the first transition portion on the substrate is located between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the second initialization signal line on the substrate, and does not overlap with the orthographic projection of the first initialization signal line on the substrate.

7. The display substrate according to claim 5, characterized in that, The display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate, the first source / drain metal layer including at least one third auxiliary signal line extending along the second direction and at least one second transition portion; The orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the third auxiliary signal line on the substrate overlap with the orthographic projection of the second adapter on the substrate. The second adapter is electrically connected to the third auxiliary signal line and is also electrically connected to the third initialization signal line through a via. Furthermore, the orthographic projection of the second adapter on the substrate does not overlap with the orthographic projection of the first initialization signal line on the substrate, and / or the orthographic projection of the second adapter on the substrate does not overlap with the orthographic projection of the second initialization signal line on the substrate.

8. The display substrate according to claim 7, characterized in that, The first source / drain metal layer further includes at least one first auxiliary signal line extending along the second direction and at least one second auxiliary signal line extending along the second direction; The first source / drain metal layer further includes: At least one first redundant adapter, the orthographic projection of the first redundant adapter on the substrate overlaps with the orthographic projection of the third initialization signal line on the substrate, and the direction from the first redundant adapter to the first auxiliary signal line is the same as the direction from the second adapter to the third auxiliary signal line. The first redundant adapter is electrically insulated from the first auxiliary signal line, and the first redundant adapter is electrically connected to the third initialization signal line through a via. And / or, at least one second redundant adapter, the orthographic projection of the second redundant adapter on the substrate overlapping the orthographic projection of the third initialization signal line on the substrate, and the direction from the second redundant adapter to the second auxiliary signal line being the same as the direction from the second adapter to the third auxiliary signal line, the second redundant adapter being electrically insulated from the second auxiliary signal line, and the second redundant adapter being electrically connected to the third initialization signal line through a via.

9. The display substrate according to claim 8, characterized in that, The distance between the edge of the second adapter portion away from the third auxiliary signal line and the third auxiliary signal line is the first distance; The first source / drain metal layer includes at least one first redundant transition section and at least one second redundant transition section; The distance between the edge of the first redundant adapter that is away from the first auxiliary signal line and the first auxiliary signal line is the second distance; The distance between the edge of the second redundant adapter that is away from the second auxiliary signal line and the second auxiliary signal line is the third distance; The ratio of either the second distance or the third distance to the first distance is 0.5 to 1.

5.

10. The display substrate according to claim 5, characterized in that, The orthogonal projection of the second electrode of the second reset transistor onto the substrate is located on the side of the orthogonal projection of the third initialization signal line onto the substrate that is farther away from the first initialization signal line; The display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate. The first source / drain metal layer includes a third transition portion. Either the orthographic projection of the second electrode of the second reset transistor on the substrate and the orthographic projection of the second reset control signal line on the substrate overlap with the orthographic projection of the third transition portion on the substrate. The third transition portion is electrically connected to the second electrode of the second reset transistor and the second reset control signal line respectively through vias. The orthographic projection of the third transition portion on the substrate also overlaps with the orthographic projection of the third reset control signal line on the substrate.

11. The display substrate according to claim 4, characterized in that, The light emission control signal line, the first reset control signal line, and the second reset control signal line are located in the first gate metal layer; The second initialization signal line is located in the second gate metal layer; The first initialization signal line and the third initialization signal line are located in the third gate metal layer; The first gate metal layer, the second gate metal layer, and the third gate metal layer are arranged sequentially in a direction away from the substrate.

12. The display substrate according to claim 11, characterized in that, The orthographic projection of the second initialization signal line on the substrate is located between the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the third initialization signal line on the substrate, and the orthographic projection of the first reset control signal line on the substrate is located on the side of the orthographic projection of the second initialization signal line on the substrate that is away from the orthographic projection of the first initialization signal line on the substrate.

13. The display substrate according to claim 12, characterized in that, The display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate. The first source / drain metal layer includes a first transition portion. Either the orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the first electrode of the third reset transistor on the substrate overlaps with the orthographic projection of the first transition portion on the substrate. The first transition portion is electrically connected to the third initialization signal line and the first electrode of the third reset transistor through vias. The orthographic projection of the first transition portion on the substrate also overlaps with the orthographic projection of the second initialization signal line on the substrate. The orthographic projection of the first transition portion on the substrate does not overlap with the orthographic projection of the first initialization signal line on the substrate.

14. The display substrate according to claim 12, characterized in that, The display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate. The first source / drain metal layer includes a third transition portion. Either the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the second electrode of the second reset transistor on the substrate overlaps with the orthographic projection of the third transition portion on the substrate. The third transition portion is electrically connected to the second initialization signal line and the second electrode of the second reset transistor through vias, respectively. The orthographic projection of the third transition portion on the substrate does not overlap with the orthographic projection of the first reset control signal line on the substrate.

15. The display substrate according to claim 14, characterized in that, The first source / drain metal layer further includes at least one second auxiliary signal line extending along the second direction and at least one first connection portion, wherein the first connection portion is electrically connected to the second auxiliary signal line and the third adapter portion, respectively.

16. The display substrate according to claim 13, characterized in that, The display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate, the first source / drain metal layer including at least one third auxiliary signal line extending along the second direction; The orthographic projection of the third initialization signal line on the substrate and the orthographic projection of the third auxiliary signal line on the substrate have a first overlap area. The third auxiliary signal line is electrically connected to the third initialization signal line through a via. The orthographic projection of the via on the substrate is located within the orthographic projection range of the first overlap area on the substrate. The first overlap area overlaps with the orthographic projection of the first reset control signal line on the substrate.

17. The display substrate according to any one of claims 2 to 16, characterized in that, The first electrode of the first reset transistor is located in the first semiconductor layer, and the first semiconductor layer is located between the first gate metal layer and the substrate; The display substrate further includes a first source / drain metal layer located on the side of the third gate metal layer away from the substrate. The first source / drain metal layer also includes a fourth transition portion, which is electrically connected to the first initialization signal line and the integrated structure through vias.

18. The display substrate according to claim 17, characterized in that, The shape of the orthographic projection of the integrated structure onto the substrate is an asymmetrical figure.

19. The display substrate according to claim 17, characterized in that, The first auxiliary signal line is located in the first source-drain metal layer, and the first source-drain metal layer further includes at least one second connection portion, which is electrically connected to the first auxiliary signal line and the fourth adapter portion respectively.

20. A display panel, characterized in that, Includes the display substrate as described in any one of claims 1 to 19.

Images