Display panel, display device, and driving method

Abstract

The present application relates to the technical field of display, and discloses a display panel, a display device, and a driving method. The display panel comprises: a plurality of sub-pixels, a plurality of data lines, and a plurality of gating control circuits. One column of sub-pixels are correspondingly connected to at least two data lines, and the sub-pixels connected to the at least two data lines are different; the one column of sub-pixels correspond to one gating control circuit, and the gating control circuit is connected to the at least two data lines and is configured to provide a reference voltage to a portion of the at least two data lines and to provide a data voltage to the remaining data lines. In this way, in a picture display process of the display panel, the reference voltage in a portion of the data lines enables part of a picture to present a black state, while the data voltage in the remaining data lines enables the remaining parts of the picture to display normally, thereby realizing that the display panel displays in different display modes and improving the display flexibility of the display panel.

Description

A display panel, a display device and a driving method

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510346676.4, filed on March 21, 2025, with the State Intellectual Property Office of the People's Republic of China, entitled "A Display Panel, Display Device and Driving Method", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and provides a display panel, a display device, and a driving method. Background Technology

[0004] With the development of technology, the demand for multi-mode displays in different application scenarios of display modules is gradually increasing. For example, in-vehicle central control displays need to realize two display modes: shared display area and privacy protection. In the shared display mode, the driver and passenger can share the entire central control display; in the privacy protection mode, a part of the central control display can only be used by the passenger, while another part can be used by both the driver and passenger.

[0005] However, in related technologies, display modules are usually only used in one fixed display mode, and the application scenarios are relatively limited. Summary of the Invention

[0006] This application provides a display panel, a display device, and a driving method to realize different display modes of the display panel, thereby improving the display panel's display flexibility.

[0007] The specific technical solution provided in this application is as follows:

[0008] In a first aspect, embodiments of this application provide a display panel, including: multiple sub-pixels, multiple data lines, and multiple gating control circuits;

[0009] A column of subpixels is connected to at least two data lines, and at least two data lines are connected to different subpixels;

[0010] Each column of subpixels corresponds to a gating control circuit, which is connected to at least two data lines and configured to provide a reference voltage to a portion of the data lines and a data voltage to the other portion of the data lines.

[0011] Optionally, the gating control circuit includes: a first gating control sub-circuit and a second gating control sub-circuit;

[0012] The first gating control subcircuit is configured to, in response to a first gating control signal at the first gating control terminal, provide a first data voltage to the first data line and provide a reference voltage to the second data line; or

[0013] The second gating control sub-circuit is configured to provide a reference voltage to the first data line and, in response to a second gating control signal at the second gating control terminal, provide a second data voltage to the second data line.

[0014] The first gating control signal and the second gating control signal are inverse signals.

[0015] Optionally, it may also include: a first gating control line and a second gating control line;

[0016] The first gating control line is electrically connected to the first gating control terminal and is configured to provide the first gating control signal to the first gating control terminal.

[0017] The second gating control line is electrically connected to the second gating control terminal and is configured to provide a second gating control signal to the second gating control terminal.

[0018] Optionally, it also includes: voltage input lines and data input lines;

[0019] One end of the voltage input line is electrically connected to the first gating control subcircuit and the second gating control subcircuit, and is configured to provide a reference voltage to the first gating control subcircuit and the second gating control subcircuit;

[0020] One end of the data input line is electrically connected to the first gating control subcircuit and the second gating control subcircuit, and is configured to provide a first data voltage to the first gating control subcircuit and a second data voltage to the second gating control subcircuit.

[0021] Optionally, the first gating control sub-circuit includes: a first transistor and a second transistor;

[0022] The control terminal of the first transistor is electrically connected to the first gating control terminal, the first terminal of the first transistor is electrically connected to the first data line, and the second terminal of the first transistor is electrically connected to the data input line.

[0023] The control terminal of the second transistor is electrically connected to the first gating control terminal, the first terminal of the second transistor is electrically connected to the second data line, and the second terminal of the second transistor is electrically connected to the voltage input line.

[0024] Optionally, the second gating control sub-circuit includes: a third transistor and a fourth transistor;

[0025] The control terminal of the third transistor is electrically connected to the second gating control signal terminal, the first terminal of the third transistor is electrically connected to the first data line, and the second terminal of the third transistor is electrically connected to the voltage input line.

[0026] The control terminal of the fourth transistor is electrically connected to the second gating control terminal, the first terminal of the fourth transistor is electrically connected to the second data line, and the second terminal of the fourth transistor is electrically connected to the data input line.

[0027] Optionally, even-numbered row subpixels are electrically connected to the first data line, and odd-numbered row subpixels are electrically connected to the second data line.

[0028] Optionally, each sub-pixel includes a pixel driving circuit, which includes: a driving transistor, a light-emitting device, a data writing sub-circuit, a first reset sub-circuit, and a first capacitor;

[0029] The driving transistor is electrically connected to the light-emitting device;

[0030] The first terminal of the data writing sub-circuit is coupled to the first terminal of the driving transistor, and the second terminal of the data writing sub-circuit is coupled to the data signal terminal and is configured to provide the data voltage of the data signal terminal to the first terminal of the driving transistor in response to the signal of the scan signal terminal.

[0031] The first reset circuit is coupled to the control terminal of the driving transistor. The first reset circuit is configured to provide the signal of the first initialization signal terminal to the control terminal of the driving transistor in response to the signal of the reset control signal terminal.

[0032] The first capacitor is electrically connected to the control terminal and the first power supply terminal of the driving transistor and is configured to store a first data voltage or a second data voltage.

[0033] Optionally, the data writing sub-circuit includes: a data writing transistor;

[0034] The data signal terminal of the even-numbered row data writing transistor is electrically connected to the first data line, and the data signal terminal of the odd-numbered row data writing transistor is electrically connected to the second data line.

[0035] Optionally, the pixel driving circuit further includes: a conduction control sub-circuit, a first light emission control sub-circuit, a second light emission control sub-circuit, and a second reset sub-circuit;

[0036] The first terminal of the turn-on control sub-circuit is electrically connected to the control terminal of the driving transistor, and the second terminal of the turn-on control sub-circuit is electrically connected to the second terminal of the driving transistor. It is configured to turn on the control terminal of the driving transistor and the second terminal of the driving transistor in response to the signal of the turn-on control signal terminal.

[0037] The first terminal of the first light-emitting control sub-circuit is electrically connected to the first power supply terminal, and the second terminal of the first light-emitting control sub-circuit is electrically connected to the first terminal of the driving transistor. The first light-emitting control sub-circuit is configured to turn on the first power supply terminal and the first terminal of the driving transistor in response to the signal of the light-emitting control signal terminal.

[0038] The first terminal of the second light-emitting control sub-circuit is electrically connected to the second terminal of the driving transistor, and the second terminal of the second light-emitting control sub-circuit is electrically connected to the anode of the light-emitting device. It is configured to conduct the second terminal of the driving transistor and the anode of the light-emitting device in response to the signal of the light-emitting control signal terminal.

[0039] The second reset circuit is electrically connected to the anode of the light-emitting device. The second reset circuit is configured to provide the signal of the second initialization signal terminal to the anode of the light-emitting device in response to the signal of the reset control signal terminal.

[0040] Optionally, both the first data line and the second data line extend along the first direction.

[0041] Optionally, the light-emitting structures of even-numbered rows of sub-pixels are different from those of odd-numbered rows of sub-pixels.

[0042] Secondly, embodiments of this application also provide a display device, including the display panel of any of the above.

[0043] Optionally, it also includes a source drive circuit;

[0044] The source drive circuit is electrically connected to the other end of the data input line and is configured to provide a first data voltage or a second data voltage to the data input line.

[0045] Optionally, it also includes: a power management circuit PMIC, a timing controller TCON, and a level conversion unit LS;

[0046] The PMIC is electrically connected to the other end of the voltage input line and is configured to provide a reference voltage to the voltage input line.

[0047] The PMIC is also electrically connected to the source drive circuit and is configured to provide a reference voltage to the source drive circuit to drive the source drive circuit to operate.

[0048] The PMIC is also electrically connected to the TCON and is configured to provide a drive voltage to the TCON.

[0049] TCON is electrically connected to the source drive circuit and is configured to provide the source drive circuit with a preselected data voltage for generating a first data voltage and a second data voltage, generate a first gating control signal and a second gating control signal based on the drive voltage, and generate a logic voltage signal based on the drive voltage.

[0050] LS is electrically connected to TCON, the first strobe control line and the second strobe control line, and is configured to perform level conversion on the first strobe control signal and the second strobe control signal, provide the converted first strobe control signal to the first strobe control line, and provide the converted second strobe control signal to the second strobe control line.

[0051] The LS is also electrically connected to the gate drive circuit and is configured to level-convert the logic voltage signal and provide the resulting valid high-level signal and valid low-level signal to the gate drive circuit.

[0052] Optionally, it also includes an inverter, the input of which is electrically connected to TCON, and the output of which is electrically connected to LS;

[0053] The inverter is configured to invert the first gating control signal generated by TCON to obtain the second gating control signal, or to invert the second gating control signal generated by TCON to obtain the first gating control signal.

[0054] Thirdly, embodiments of this application also provide a driving method for the display panel described in any of the above claims, comprising:

[0055] The gating control circuit provides a reference voltage to a portion of the data lines connected to each sub-pixel; and

[0056] The gating control circuit provides data voltage to the other part of the data lines connected to each sub-pixel.

[0057] The beneficial effects of this application are as follows:

[0058] In summary, this application provides a display panel, a display device, and a driving method. The display panel includes multiple sub-pixels, multiple data lines, and multiple gating control circuits. Each column of sub-pixels is connected to at least two data lines, and the sub-pixels connected to the at least two data lines are different. Each column of sub-pixels corresponds to a gating control circuit, which is connected to at least two data lines and configured to provide a reference voltage to a portion of the data lines and a data voltage to the other portion of the data lines. Thus, during the display of the screen, the reference voltage in some data lines can make part of the screen appear black, while the data voltage in the other portion of the data lines can make the other portion of the screen display normally. This enables the display panel to display different display modes, improving the flexibility of the display panel.

[0059] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0060] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0061] Figure 1 is a connection diagram of the first type of display panel in an embodiment of this application;

[0062] Figure 2 is a schematic diagram of the structure of the second type of display panel in an embodiment of this application;

[0063] Figure 3 is a schematic diagram of the structure of the third type of display panel in the embodiment of this application;

[0064] Figure 4 is a schematic diagram of the structure of the fourth type of display panel in the embodiment of this application;

[0065] Figure 5 is a connection diagram of the first gating control circuit in the embodiment of this application;

[0066] Figure 6 is a connection diagram of the second gating control circuit in an embodiment of this application;

[0067] Figure 7 is a connection diagram of the third gating control circuit in the embodiment of this application;

[0068] Figure 8 is a schematic diagram of the connection between the first gating control circuit and the pixel driving circuit in the embodiment of this application;

[0069] Figure 9 is a schematic diagram showing the connection between the second gating control circuit and the pixel driving circuit in an embodiment of this application;

[0070] Figure 10 is a schematic diagram of the pixel driving circuit in an embodiment of this application;

[0071] Figure 11 is a circuit connection diagram of the pixel driving circuit in an embodiment of this application;

[0072] Figure 12 is a schematic diagram of the light-emitting structure of the sub-pixel in an embodiment of this application;

[0073] Figure 13 is a schematic diagram of a display panel displaying in full screen in display mode 1 according to an embodiment of this application;

[0074] Figure 14 is a timing diagram of the display panel in full screen display mode 1 in an embodiment of this application;

[0075] Figure 15 is a schematic diagram of a display panel displaying in full screen in display mode 2 according to an embodiment of this application;

[0076] Figure 16 is a timing diagram of the display panel being displayed in full screen in display mode 2 in an embodiment of this application;

[0077] Figure 17 is a schematic diagram of a display panel in which the upper and lower screens are displayed in display mode 1 and display mode 2 respectively, according to an embodiment of this application.

[0078] Figure 18 is a timing diagram showing the upper and lower screens of the display panel in display mode 1 and display mode 2 respectively in an embodiment of this application;

[0079] Figure 19 is a schematic diagram of a display panel in which the left and right screens are displayed in display mode 1 and display mode 2 respectively, according to an embodiment of this application.

[0080] Figure 20 is a timing diagram showing the left and right screens of the display panel in display mode 1 and display mode 2 respectively in an embodiment of this application;

[0081] Figure 21 is a schematic diagram of a flexible area of ​​a display panel in an embodiment of this application, which is displayed in display mode 1 and display mode 2 respectively;

[0082] Figure 22 is a timing diagram showing the flexible area of ​​the display panel in display mode 1 and display mode 2 in the embodiments of this application.

[0083] Figure 23 is a connection diagram of a display device according to an embodiment of this application;

[0084] Figure 24 is a connection diagram of an inverter in an embodiment of this application. Detailed Implementation

[0085] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this application. Obviously, the described embodiments are only some embodiments of the technical solutions of this application, and not all embodiments. Based on the embodiments recorded in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the technical solutions of this application.

[0086] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0087] With the development of technology, the demand for multi-mode displays in different application scenarios of display modules is gradually increasing. For example, in-vehicle central control displays need to realize two display modes: shared display area and privacy protection. In the shared display mode, the driver and passenger can share the entire central control display; in the privacy protection mode, a part of the central control display can only be used by the passenger, while another part can be used by both the driver and passenger.

[0088] However, in related technologies, display modules are typically used only in a fixed display mode, resulting in a relatively limited application scenario. This is because the light-emitting structures of each sub-pixel within the display module are identical; each sub-pixel is electrically connected to a gate line and a data line. During display, when the scan signal in the gate line corresponding to a sub-pixel is valid, the data voltage in the data line is supplied to a pixel driving circuit within that sub-pixel, thereby driving the light-emitting device in that pixel driving circuit to emit light. When the data voltage in the data line differs, the brightness of the image presented by that sub-pixel varies, but the display mode of the entire frame remains fixed; a single display panel cannot present different display modes in different application scenarios.

[0089] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0090] Referring to Figure 1, a display panel proposed in this application embodiment includes: multiple sub-pixels, multiple data lines, and multiple gating control circuits.

[0091] A column of subpixels is connected to at least two data lines, and at least two data lines are connected to different subpixels.

[0092] Unlike related technologies where the number of sub-pixels corresponds one-to-one with the number of data lines, in this embodiment, one column of sub-pixels is connected to at least two data lines. Referring to Figure 1, one column of sub-pixels is connected to two data lines. For example, the first column of sub-pixels is electrically connected to data line 1 and data line 2, the second column of sub-pixels is electrically connected to data line 3 and data line 4, the third column of sub-pixels is electrically connected to data line 5 and data line 6, and the Mth column of sub-pixels is electrically connected to data line 2M-1 and data line 2M.

[0093] For example, when there are two display modes, one column of subpixels is connected to two data lines; when there are three display modes, one column of subpixels is connected to three data lines, and so on.

[0094] It should also be noted that different data lines connect to different sub-pixels. Since a data line is shared by a column of sub-pixels, each sub-pixel in a column is electrically connected to one of at least two data lines.

[0095] For example, when a column of subpixels is connected to two data lines, the subpixels in even-numbered rows are electrically connected to one of the data lines, and the subpixels in odd-numbered rows are electrically connected to the other data line. For example, referring to Figure 1, subpixel 11 in the first row and subpixel L1 in the (2n+1)th row of the first column are electrically connected to data line 1; subpixel 21 in the second row and subpixel N1 in the (2n)th row of the first column are electrically connected to data line 2; subpixel 12 in the first row and subpixel L2 in the (2n+1)th row of the second column are electrically connected to data line 3; subpixel 22 in the second row and subpixel N2 in the (2n)th row of the second column are electrically connected to data line 4; subpixel 13 in the first row and subpixel L3 in the (2n+1)th row of the third column are electrically connected to data line 5; subpixel 23 in the second row and subpixel N3 in the (2n)th row of the third column are electrically connected to data line 6, and so on, where n is a natural number.

[0096] For example, when a column of subpixels is connected to three data lines, the subpixels in the (3n-2)th row are electrically connected to the first data line, the subpixels in the (3n-1)th row are electrically connected to the second data line, and the subpixels in the 3nth row are electrically connected to the third data line, where n is a natural number.

[0097] It should be noted that, from the perspective of the display panel comprising multiple pixel units, in this embodiment of the application, in order to realize the display of multiple display modes, the number of each sub-pixel included in a pixel unit has been doubled.

[0098] For example, referring to Figure 2, when a pixel unit in a display panel that can only display one display mode includes sub-pixels R, G, and B, in this embodiment, a pixel unit includes not only the sub-pixels R, G, and B located in the first row, but also the sub-pixels R, G, and B located in the second row. During implementation, the sub-pixels R, G, and B located in the first row are used for displaying the screen in display mode 1, and the sub-pixels R, G, and B located in the second row are used for displaying the screen in display mode 2. Other pixel units in the display panel in this embodiment are similar and will not be described in detail here.

[0099] For example, referring to Figure 3, when a pixel unit in a display panel that can only display one display mode includes sub-pixels R, G, and B, in this embodiment, a pixel unit includes not only the sub-pixels R, G, and B located in the first row, but also the sub-pixels B, G, and R located in the second row. During implementation, the sub-pixels R, G, and B located in the first row are used for displaying the screen in display mode 1, and the sub-pixels B, G, and R located in the second row are used for displaying the screen in display mode 2. That is, the arrangement order of the sub-pixels in the pixel unit is not limited during the display of different display modes. Furthermore, in this embodiment, other pixel units in the display panel are similar, and will not be described in detail here.

[0100] For example, referring to Figure 4, when a pixel unit in a display panel that can only display one display mode includes sub-pixels R, G, B, and W, in this embodiment, a pixel unit includes not only the sub-pixels R, G, B, and W in the first row, but also the sub-pixels R, G, B, and W in the second row. During implementation, the sub-pixels R, G, B, and W in the first row are used for displaying the screen in display mode 1, and the sub-pixels R, G, B, and W in the second row are used for displaying the screen in display mode 2. That is, the arrangement order of the sub-pixels in the pixel unit is not limited during the display of different display modes. Furthermore, in this embodiment, other pixel units in the display panel are similar, and will not be described in detail here.

[0101] When the number of sub-pixels included in a pixel unit increases, the number of data lines connected to the sub-pixels also increases accordingly. In this embodiment, for ease of description, the description is uniformly based on the perspective of the display panel including sub-pixels.

[0102] Each column of subpixels corresponds to a gating control circuit, which is connected to at least two data lines and configured to provide a reference voltage to a portion of the data lines and a data voltage to the other portion of the data lines.

[0103] Referring to Figure 5, this embodiment of the application also includes a gating control circuit, the number of which is the same as the number of columns of the sub-pixels. The gating control circuits are electrically connected to each of the at least two data lines.

[0104] During implementation, the gating control circuit provides a reference voltage to a portion of the data lines, enabling the electrically connected sub-pixels of these data lines to display under the influence of the reference voltage. Simultaneously, the gating control circuit also provides a data voltage to another portion of the data lines, allowing the electrically connected sub-pixels of this other portion of the data lines to display under the influence of the data voltage.

[0105] It should be further noted that the data voltage in the embodiments of this application is similar to the data voltage in related technologies, that is, the driving current used to generate the light-emitting device OLED in the pixel driving circuit that drives the sub-pixels to emit light.

[0106] Furthermore, in the embodiments of this application, the reference voltage is a fixed value of DC voltage, which is adapted to the power supply terminal in the pixel driving circuit of the sub-pixel. For example, the reference voltage is the AVDD, AVSS, or GND voltage used to enable the pixel driving circuit to display in black state. That is, the driving transistor DTFT in the pixel driving circuit of the sub-pixel is cut off under the action of the reference voltage, thereby presenting an effect of "no display".

[0107] The following is a detailed explanation using the example of a column of sub-pixels electrically connected to two data lines.

[0108] When a column of sub-pixels is electrically connected to two data lines, the gating control circuit will also be electrically connected to the two data lines simultaneously, and will provide data voltage and / or reference voltage to the two data lines respectively, which will be described in detail below.

[0109] Referring to Figure 6, the gating control circuit includes: a first gating control sub-circuit and a second gating control sub-circuit.

[0110] First, the first gating control signal and the second gating control signal are inverse signals.

[0111] It should be noted that, in the embodiments of this application, when the gating control circuit includes a first gating control sub-circuit and a second gating control sub-circuit, the first gating control signal used to control the first gating control sub-circuit and the second gating control signal used to control the second gating control sub-circuit are inverted signals. For example, when the first gating control signal is high, the second gating control signal is low; when the first gating control signal is low, the second gating control signal is high.

[0112] Furthermore, considering that the circuit structures constituting the first and second gating control subcircuits are identical, during implementation, when the first gating control signal is valid, the corresponding first gating control subcircuit is turned on. In this case, when the second gating control signal is invalid, the corresponding second gating control subcircuit is turned off. Conversely, when the first gating control signal is invalid, the corresponding first gating control subcircuit is turned off. In this case, when the second gating control signal is valid, the corresponding second gating control subcircuit is turned on. That is, only one of the first and second gating control subcircuits can be turned on.

[0113] The first gating control subcircuit is configured to, in response to a first gating control signal at the first gating control terminal, provide a first data voltage to the first data line and provide a reference voltage to the second data line. Alternatively...

[0114] During implementation, when the first gating control signal of the first gating control terminal is valid, the first gating control sub-circuit is turned on, and the first gating control sub-circuit provides the received first data voltage to the first data line, and the first gating control sub-circuit provides the received reference voltage to the second data line.

[0115] In the above scenario, the sub-pixel electrically connected to the first data line displays a normal image, while the sub-pixel electrically connected to the second data line displays a black screen. That is, the configuration of the first gating control sub-circuit enables the sub-pixels electrically connected to the first and second data lines to simultaneously present two display states, thus ensuring that the display panel can present at least two display modes.

[0116] The second gating control subcircuit is configured to provide a reference voltage to the first data line and a second data voltage to the second data line in response to a second gating control signal at the second gating control terminal.

[0117] During implementation, when the second gating control signal of the second gating control terminal is valid, the second gating control sub-circuit is turned on, and the second gating control sub-circuit provides the received reference voltage to the first data line, and the second gating control sub-circuit provides the received second data voltage to the second data line.

[0118] In the above situation, the sub-pixel electrically connected to the second data line displays the normal image, while the sub-pixel electrically connected to the first data line displays in black. Similarly, the configuration of the second gating control sub-circuit allows the sub-pixels electrically connected to the first and second data lines to simultaneously present two display states, thus ensuring that the display panel can present at least two display modes.

[0119] Referring to Figures 5 and 6, the above-mentioned display panel also includes: a first gating control line and a second gating control line.

[0120] The first gating control line is electrically connected to the first gating control terminal and is configured to provide the first gating control signal to the first gating control terminal.

[0121] The second gating control line is electrically connected to the second gating control terminal and is configured to provide a second gating control signal to the second gating control terminal.

[0122] In order to provide the gating control circuit with a first gating control signal and a second gating control signal, the display panel in this embodiment of the application further includes: a first gating control line and a second gating control line.

[0123] The aforementioned first gating control line is electrically connected to the first gating control terminal of the gating control circuit. During implementation, the first gating control line provides a first gating control signal to the first gating control terminal.

[0124] The aforementioned second gating control line is electrically connected to the second gating control terminal of the gating control circuit. During implementation, the second gating control line provides a second gating control signal to the second gating control terminal.

[0125] In addition, as shown in Figures 5 and 6, the above-mentioned display panel also includes voltage input lines and data input lines.

[0126] One end of the voltage input line is electrically connected to the first gating control subcircuit and the second gating control subcircuit, and is configured to provide a reference voltage to the first gating control subcircuit and the second gating control subcircuit.

[0127] In order to provide a reference voltage for the gating control circuit, the display panel in this embodiment of the application further includes a voltage input line. The first gating control sub-circuit and the second gating control sub-circuit are both electrically connected to one end of the voltage input line. During implementation, the voltage input line provides a reference voltage to the first gating control sub-circuit, or the voltage input line provides a reference voltage to the second gating control sub-circuit.

[0128] One end of the data input line is electrically connected to the first gating control subcircuit and the second gating control subcircuit, and is configured to provide a first data voltage to the first gating control subcircuit and a second data voltage to the second gating control subcircuit.

[0129] To provide the first and second data voltages to the gating control circuits in a time-division multiplexing manner, the display panel in this embodiment further includes a data input line, with both the first and second gating control sub-circuits electrically connected to one end of the data input line. During implementation, the data input line provides the first data voltage to the first gating control sub-circuit, or the data input line provides the second data voltage to the second gating control sub-circuit.

[0130] The circuit configurations of the first gating control sub-circuit and the second gating control sub-circuit are described in detail below. Referring to Figure 7, the first gating control sub-circuit includes: a first transistor M1 and a second transistor M2.

[0131] The control terminal of the first transistor M1 is electrically connected to the first gating control terminal, the first terminal of the first transistor M1 is electrically connected to the first data line, and the second terminal of the first transistor M1 is electrically connected to the data input line.

[0132] In this embodiment, the first transistor M1 is disposed between the data input line and the first data line. That is, after the source driving circuit transmits the first data voltage to the data input line, the data input line provides the first data voltage to the first data line through the conducting first transistor M1, and then the first data line provides the first data voltage to the corresponding connected sub-pixel.

[0133] For example, the first transistor M1 can be turned on under the control of the effective level of the first strobe control signal at the first strobe control terminal, and can be turned off under the control of the ineffective level of the first strobe control signal at the first strobe control terminal. For example, if the first transistor M1 is configured as an N-type transistor, then the effective level of the first strobe control signal at the first strobe control terminal is a high level, and the ineffective level of the first strobe control signal at the first strobe control terminal is a low level. Alternatively, if the first transistor M1 is configured as a P-type transistor, then the effective level of the first strobe control signal at the first strobe control terminal is a low level, and the ineffective level of the first strobe control signal at the first strobe control terminal is a high level.

[0134] Referring to Figure 7, the first transistor M1 is a P-type transistor. When the signal of the first strobe control signal at the first strobe control terminal is low, the first transistor M1 is turned on, and the first data voltage in the data input line is provided to the first data line through the first transistor M1.

[0135] The control terminal of the second transistor M2 is electrically connected to the first gating control terminal, the first terminal of the second transistor M2 is electrically connected to the second data line, and the second terminal of the second transistor M2 is electrically connected to the voltage input line.

[0136] In this embodiment, the second transistor M2 is disposed between the voltage input line and the second data line. That is, the voltage input line provides the reference voltage to the second data line through the conducting second transistor M2, and then the second data line provides the reference voltage to the corresponding connected sub-pixel.

[0137] For example, the second transistor M2 can be turned on under the control of the effective level of the first strobe control signal at the first strobe control terminal, and can be turned off under the control of the ineffective level of the first strobe control signal at the first strobe control terminal. For example, if the second transistor M2 is configured as an N-type transistor, then the effective level of the first strobe control signal at the first strobe control terminal is a high level, and the ineffective level of the first strobe control signal at the first strobe control terminal is a low level. Alternatively, if the second transistor M2 is configured as a P-type transistor, then the effective level of the first strobe control signal at the first strobe control terminal is a low level, and the ineffective level of the first strobe control signal at the first strobe control terminal is a high level.

[0138] Referring to Figure 7, the second transistor M2 is a P-type transistor. When the signal of the first gating control signal at the first gating control terminal is low, the second transistor M2 is turned on, and the reference voltage in the voltage input line is provided to the second data line through the second transistor M2.

[0139] Referring to Figure 7, the second gating control sub-circuit includes: a third transistor M3 and a fourth transistor M4.

[0140] The control terminal of the third transistor M3 is electrically connected to the second gating control signal terminal, the first terminal of the third transistor M3 is electrically connected to the first data line, and the second terminal of the third transistor M3 is electrically connected to the voltage input line.

[0141] In this embodiment, the third transistor M3 is disposed between the voltage input line and the first data line. That is, the voltage input line provides the reference voltage to the first data line through the conducting third transistor M3, and then the first data line provides the reference voltage to the corresponding connected sub-pixel.

[0142] For example, the third transistor M3 can be turned on under the control of the effective level of the second selection control signal at the second selection control terminal, and can be turned off under the control of the ineffective level of the second selection control signal at the second selection control terminal. For example, if the third transistor M3 is configured as an N-type transistor, then the effective level of the second selection control signal at the second selection control terminal is a high level, and the ineffective level of the second selection control signal at the second selection control terminal is a low level. Alternatively, if the third transistor M3 is configured as a P-type transistor, then the effective level of the second selection control signal at the second selection control terminal is a low level, and the ineffective level of the second selection control signal at the second selection control terminal is a high level.

[0143] Referring to Figure 7, the third transistor M3 is a P-type transistor. When the signal of the second gating control signal at the second gating control terminal is low, the third transistor M3 is turned on, and the reference voltage in the voltage input line is provided to the first data line through the third transistor M3.

[0144] The control terminal of the fourth transistor M4 is electrically connected to the second gating control terminal, the first terminal of the fourth transistor M4 is electrically connected to the second data line, and the second terminal of the fourth transistor M4 is electrically connected to the data input line.

[0145] In this embodiment, the fourth transistor M4 is disposed between the data input line and the second data line. That is, the data input line provides the second data voltage to the second data line through the conducting fourth transistor M4, and then the second data line provides the second data voltage to the corresponding connected sub-pixel.

[0146] For example, the fourth transistor M4 can be turned on under the control of the effective level of the second gating control signal at the second gating control terminal, and can be turned off under the control of the ineffective level of the second gating control signal at the second gating control terminal. For example, if the fourth transistor M4 is configured as an N-type transistor, then the effective level of the second gating control signal at the second gating control terminal is a high level, and the ineffective level of the second gating control signal at the second gating control terminal is a low level. Alternatively, if the fourth transistor M4 is configured as a P-type transistor, then the effective level of the second gating control signal at the second gating control terminal is a low level, and the ineffective level of the second gating control signal at the second gating control terminal is a high level.

[0147] Referring to Figure 7, the fourth transistor M4 is a P-type transistor. When the signal of the second selection control signal at the second selection control terminal is low, the fourth transistor M4 is turned on, and the second data voltage in the data input line is provided to the second data line through the fourth transistor M4.

[0148] In addition, both the first data line and the second data line mentioned above extend along the first direction.

[0149] It should be noted that the first direction is parallel to the column direction of the sub-pixel. In this embodiment, the first data line and the second data line are configured in the first direction, and the first data line and the second data line extend in the first direction. It should be noted that the first direction is a direction parallel to the column direction of the sub-pixel; for example, the first direction is a vertical direction.

[0150] Regarding the first and second data lines electrically connected to a column of sub-pixels, the first and second data lines can be routed on opposite sides of the column of sub-pixels, or they can be routed on the same side (e.g., the left or right side of the column of sub-pixels). The specific routing method needs to be flexibly set according to the actual scenario, and will not be elaborated here. In other words, the setting of the first and second data lines is based on the first and second data lines themselves, which facilitates routing, makes signal flow more convenient, and further saves routing space.

[0151] Referring to Figures 8 and 9, even-numbered row subpixels are electrically connected to the first data line, and odd-numbered row subpixels are electrically connected to the second data line.

[0152] In order to improve the display effect of the display panel when switching between different display modes, in this embodiment of the application, even-numbered row sub-pixels are electrically connected to the first data line. That is, for each column of sub-pixels, all even-numbered row sub-pixels are electrically connected to the first data line, and the first data line provides a first data voltage to each even-numbered row sub-pixel for normal display.

[0153] Similarly, the odd-numbered row sub-pixels are electrically connected to the second data line. That is, for each column of sub-pixels, all the odd-numbered row sub-pixels are electrically connected to the second data line, which provides the second data voltage to each sub-pixel in the odd-numbered row for normal display.

[0154] The arrangement of these sub-pixels in alternating even and odd rows allows for a more uniform display of the image on the display panel, resulting in a better display effect.

[0155] It should be further explained that in the embodiments of this application, the circuit configuration of the pixel driving circuit included in each different sub-pixel is the same. However, in the embodiments of this application, even the data signal terminals Vdata in the different pixel driving circuits connected to the same column of sub-pixels are connected to different data lines. For example, the pixel driving circuit 1 in the sub-pixel 1 of the same column is electrically connected to the data line 1, and the pixel driving circuit 2 in the sub-pixel 2 of the same column is electrically connected to the data line 2. In this way, in display mode 1, the data line 1 can provide data voltage 1 to the pixel driving circuit 1, and in display mode 2, the data line 2 can provide data voltage 2 to the pixel driving circuit 2.

[0156] The following describes the circuit configuration of the pixel driving circuit in this embodiment. Referring to Figure 10, the pixel driving circuit includes: a driving transistor DTFT, a conduction control sub-circuit 10, a data writing sub-circuit 20, a first light emission control sub-circuit 30, a second light emission control sub-circuit 40, a first reset sub-circuit 50, a second reset sub-circuit 60, a first capacitor C1, and a light-emitting device OLED. In this embodiment, each sub-pixel includes a pixel driving circuit.

[0157] Referring to Figures 10 and 11, the first terminal of the conduction control sub-circuit 10 is electrically connected to the control terminal of the driving transistor DTFT, and the second terminal of the conduction control sub-circuit 10 is electrically connected to the second terminal of the driving transistor DTFT. It is configured to conduct the control terminal of the driving transistor DTFT and the second terminal of the driving transistor DTFT in response to the signal of the conduction control signal terminal GT.

[0158] During implementation, when the signal at the conduction control signal terminal GT is valid, the conduction control sub-circuit 10 is turned on, and the control terminal of the driving transistor DTFT is connected to the second terminal of the driving transistor DTFT.

[0159] Referring to Figure 11, the conduction control sub-circuit 10 includes: a first switching transistor T1.

[0160] The control terminal of the first switching transistor T1 is electrically connected to the conduction control signal terminal GT, the first terminal of the first switching transistor T1 is electrically connected to the control terminal of the driving transistor DTFT, and the second terminal of the first switching transistor T1 is electrically connected to the second terminal of the driving transistor DTFT.

[0161] For example, the first switching transistor T1 can be turned on under the control of an active level of the turn-on control signal terminal GT, and can be turned off under the control of an inactive level of the turn-on control signal terminal GT. For example, if the first switching transistor T1 is configured as an N-type transistor, then the active level of the signal at the turn-on control signal terminal GT is a high level, and the inactive level of the signal at the turn-on control signal terminal GT is a low level. Alternatively, if the first switching transistor T1 is configured as a P-type transistor, then the active level of the signal at the turn-on control signal terminal GT is a low level, and the inactive level of the signal at the turn-on control signal terminal GT is a high level.

[0162] Referring to Figure 11, the first switching transistor T1 is a P-type transistor. When the signal at the control signal terminal GT is low, the first switching transistor T1 is turned on, and the control terminal of the driving transistor DTFT is connected to the second terminal of the driving transistor DTFT through the first switching transistor T1.

[0163] Referring to Figure 11, the first terminal of the data writing sub-circuit 20 is electrically connected to the first terminal of the driving transistor DTFT, and the second terminal of the data writing sub-circuit 20 is electrically connected to the data signal terminal Vdata. It is configured to provide the data voltage of the data signal terminal Vdata to the first terminal of the driving transistor DTFT in response to the signal of the scan signal terminal GT.

[0164] During implementation, when the signal at the scanning signal terminal GT is valid, the data writing sub-circuit 20 is turned on, and the data voltage at the data signal terminal Vdata is provided to the first terminal of the driving transistor DTFT through the data writing sub-circuit 20.

[0165] Referring to Figures 10 and 11, the data writing sub-circuit 20 includes a data writing transistor T0.

[0166] The control terminal of the data writing transistor T0 is electrically connected to the scan signal terminal GT, the first terminal of the data writing transistor T0 is electrically connected to the first terminal of the driving transistor DTFT, and the second terminal of the data writing transistor T0 is electrically connected to the data signal terminal Vdata.

[0167] For example, the data write transistor T0 can be turned on under the control of the active level of the scan signal terminal GT, and turned off under the control of the inactive level of the scan signal terminal GT. For example, if the data write transistor T0 is set to an N-type transistor, then the active level of the signal at the scan signal terminal GT is high, and the inactive level of the signal at the scan signal terminal GT is low. Alternatively, if the data write transistor T0 is set to a P-type transistor, then the active level of the signal at the scan signal terminal GT is low, and the inactive level of the signal at the scan signal terminal GT is high.

[0168] Referring to Figure 11, the data writing transistor T0 is a P-type transistor. When the signal at the scan signal terminal GT is low, the data writing transistor T0 is turned on, and the data voltage at the data signal terminal Vdata is provided to the first terminal of the driving transistor DTFT through the data writing transistor T0.

[0169] In this embodiment, the data signal terminal Vdata of the even-numbered row data writing transistor T0 is electrically connected to the first data line, and the data signal terminal Vdata of the odd-numbered row data writing transistor T0 is electrically connected to the second data line.

[0170] During implementation, the first data line provides a first data voltage or a reference voltage to the data signal terminal Vdata of the even-numbered row data writing transistor T0, thereby enabling the even-numbered row sub-pixels to be displayed normally or in a black state. The second data line provides a second data voltage or a reference voltage to the data signal terminal Vdata of the odd-numbered row data writing transistor T0, thereby enabling the odd-numbered row sub-pixels to be displayed normally or in a black state.

[0171] Referring to Figures 10 and 11, the first terminal of the first light-emitting control sub-circuit 30 is electrically connected to the first power supply terminal VDD, and the second terminal of the first light-emitting control sub-circuit 30 is electrically connected to the first terminal of the driving transistor DTFT.

[0172] The first light-emitting control sub-circuit 30 is configured to turn on the first power supply terminal VDD and the first terminal of the driving transistor DTFT in response to the signal of the light-emitting control signal terminal EM.

[0173] During implementation, when the signal of the light emission control signal terminal EM is valid, the first light emission control sub-circuit 30 is turned on, and the first power supply terminal VDD is turned on through the first light emission control sub-circuit 30 and the first terminal of the driving transistor DTFT.

[0174] Referring to Figure 11, the first light-emitting control sub-circuit 30 includes: a second switching transistor T2.

[0175] The control terminal of the second switching transistor T2 is electrically connected to the light emission control signal terminal EM, the first terminal of the second switching transistor T2 is electrically connected to the first power supply terminal VDD, and the second terminal of the second switching transistor T2 is electrically connected to the first terminal of the driving transistor DTFT.

[0176] For example, the second switching transistor T2 can be turned on under the control of the effective level of the light-emitting control signal terminal EM, and can be turned off under the control of the ineffective level of the light-emitting control signal terminal EM. For example, if the second switching transistor T2 is set as an N-type transistor, then the effective level of the signal at the light-emitting control signal terminal EM is a high level, and the ineffective level of the signal at the light-emitting control signal terminal EM is a low level. Alternatively, if the second switching transistor T2 is set as a P-type transistor, then the effective level of the signal at the light-emitting control signal terminal EM is a low level, and the ineffective level of the signal at the light-emitting control signal terminal EM is a high level.

[0177] Referring to Figure 11, the second switching transistor T2 is a P-type transistor. When the signal of the light emission control signal terminal EM is low, the second switching transistor T2 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the second switching transistor T2.

[0178] Referring to Figures 10 and 11, the first terminal of the second light-emitting control sub-circuit 40 is electrically connected to the second terminal of the driving transistor DTFT, and the second terminal of the second light-emitting control sub-circuit 40 is electrically connected to the anode of the light-emitting device OLED. The second light-emitting control sub-circuit 40 is configured to conduct the second terminal of the driving transistor DTFT to the anode of the light-emitting device OLED in response to the signal of the light-emitting control signal terminal EM.

[0179] During implementation, when the signal of the light emission control signal terminal EM is valid, the second light emission control sub-circuit 40 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light emission device OLED through the second light emission control sub-circuit 40.

[0180] Referring to Figure 11, the second light-emitting control sub-circuit 40 includes a third switching transistor T3.

[0181] The control terminal of the third switching transistor T3 is electrically connected to the light-emitting control signal terminal EM. The first terminal of the third switching transistor T3 is electrically connected to the second terminal of the driving transistor DTFT. The second terminal of the third switching transistor T3 is electrically connected to the anode of the light-emitting device OLED.

[0182] For example, the third switching transistor T3 can be turned on under the control of the effective level of the light-emitting control signal terminal EM, and can be turned off under the control of the ineffective level of the light-emitting control signal terminal EM. For example, if the third switching transistor T3 is set as an N-type transistor, then the effective level of the signal at the light-emitting control signal terminal EM is a high level, and the ineffective level of the signal at the light-emitting control signal terminal EM is a low level. Alternatively, if the third switching transistor T3 is set as a P-type transistor, then the effective level of the signal at the light-emitting control signal terminal EM is a low level, and the ineffective level of the signal at the light-emitting control signal terminal EM is a high level.

[0183] Referring to Figure 11, the third switching transistor T3 is a P-type transistor. When the signal at the light emission control signal terminal EM is low, the third switching transistor T3 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device OLED through the third switching transistor T3.

[0184] Referring to Figures 10 and 11, the first reset circuit 50 is electrically connected to the control terminal of the driving transistor DTFT.

[0185] The first reset sub-circuit 50 is configured to provide the signal of the first initialization signal terminal Vinit1 to the control terminal of the driving transistor DTFT in response to the signal of the reset control signal terminal Re.

[0186] During implementation, when the reset control signal terminal Re is valid, the signal of the first initialization signal terminal Vinit1 is provided to the control terminal of the driving transistor DTFT through the first reset sub-circuit 50, thereby resetting the control terminal of the driving transistor DTFT.

[0187] Referring to Figure 11, the first reset circuit 50 includes a fourth switching transistor T4.

[0188] The control terminal of the fourth switching transistor T4 is electrically connected to the reset control signal terminal Re, the first terminal of the fourth switching transistor T4 is electrically connected to the control terminal of the driving transistor DTFT, and the second terminal of the fourth switching transistor T4 is electrically connected to the first initialization signal terminal Vinit1.

[0189] For example, the fourth switching transistor T4 can be turned on under the control of an active level of the reset control signal terminal Re, and can be turned off under the control of an inactive level of the reset control signal terminal Re. For example, if the fourth switching transistor T4 is set as an N-type transistor, then the active level of the signal at the reset control signal terminal Re is a high level, and the inactive level of the signal at the reset control signal terminal Re is a low level. Alternatively, if the fourth switching transistor T4 is set as a P-type transistor, then the active level of the signal at the reset control signal terminal Re is a low level, and the inactive level of the signal at the reset control signal terminal Re is a high level.

[0190] Referring to Figure 11, the fourth switching transistor T4 is a P-type transistor. When the signal at the reset control signal terminal Re is low, the fourth switching transistor T4 is turned on, and the signal at the first initialization signal terminal Vinit1 is provided to the control terminal of the driving transistor DTFT through the fourth switching transistor T4, thereby resetting the control terminal of the driving transistor DTFT.

[0191] Referring to Figure 11, the second reset circuit 60 is electrically connected to the anode of the light-emitting device OLED.

[0192] The second reset sub-circuit 60 is configured to provide the signal of the second initialization signal terminal Vinit2 to the anode of the light-emitting device OLED in response to the signal of the reset control signal terminal Re.

[0193] During implementation, when the reset control signal terminal Re is valid, the signal of the second initialization signal terminal Vinit2 is provided to the anode of the light-emitting device OLED through the second reset sub-circuit 60, thereby resetting the anode of the light-emitting device OLED.

[0194] Referring to Figure 11, the second reset circuit 60 includes a fifth switching transistor T5.

[0195] The control terminal of the fifth switching transistor T5 is electrically connected to the reset control signal terminal Re, the first terminal of the fifth switching transistor T5 is electrically connected to the anode of the light-emitting device OLED, and the second terminal of the fifth switching transistor T5 is electrically connected to the second initialization signal terminal Vinit2.

[0196] For example, the fifth switching transistor T5 can be turned on under the control of the active level of the reset control signal terminal Re, and can be turned off under the control of the inactive level of the reset control signal terminal Re. For example, if the fifth switching transistor T5 is set as an N-type transistor, then the active level of the signal at the reset control signal terminal Re is a high level, and the inactive level of the signal at the reset control signal terminal Re is a low level. Alternatively, if the fifth switching transistor T5 is set as a P-type transistor, then the active level of the signal at the reset control signal terminal Re is a low level, and the inactive level of the signal at the reset control signal terminal Re is a high level.

[0197] Referring to Figure 11, the fifth switching transistor T5 is a P-type transistor. When the signal at the reset control signal terminal Re is low, the fifth switching transistor T5 is turned on, and the signal at the second initialization signal terminal Vinit2 is provided to the anode of the light-emitting device OLED through the fifth switching transistor T5, thereby resetting the anode of the light-emitting device OLED.

[0198] The first capacitor C1 is used to store the first data voltage or the second data voltage. In some embodiments, the first capacitor C1 is also used to store the threshold voltage of the driving transistor, which will not be specifically limited here.

[0199] It should also be noted that although sub-pixels R, G, and B in different display modes each include their own pixel driving circuits, the reset control signal terminals Re in the aforementioned at least two pixel driving circuits can be provided by the same gate driving circuit, i.e., Re GOA; the conduction control signal terminals GT in the aforementioned at least two pixel driving circuits can also be provided by the same gate driving circuit, i.e., GT GOA; the scan signal terminals GT in the aforementioned at least two pixel driving circuits can also be provided by the same gate driving circuit, i.e., GT GOA; and the light emission control signal terminals EM in the aforementioned at least two pixel driving circuits can also be provided by the same gate driving circuit, i.e., EM GOA. This arrangement effectively reduces the number of wirings in the display panel and the number of gate driving circuits used, thereby reducing the space occupied by the gate driving circuits and making it more conducive to achieving a narrow bezel in the display panel.

[0200] It should also be noted that the pixel driving circuit structure given in the embodiments of this application is only exemplary, that is, the structure of the pixel driving circuit in the embodiments of this application is not limited to that shown in FIG11, and other pixel driving circuits are also applicable to this application.

[0201] As shown in Figure 12, the light emission structures of even-numbered row sub-pixels are different from those of odd-numbered row sub-pixels.

[0202] To enable the display panel to display certain special display modes, such as a privacy mode, in this embodiment, the light-emitting structures of even-numbered rows of sub-pixels are different from those of odd-numbered rows of sub-pixels. For example, when even-numbered rows of sub-pixels are used in the normal display mode, the light-emitting structure of even-numbered rows of sub-pixels is shown in sub-pixel K in Figure 12, meaning that no microlens array is added to the light-emitting structure of sub-pixel K. When odd-numbered rows of sub-pixels are used in the privacy mode, the light-emitting structure of odd-numbered rows of sub-pixels is shown in sub-pixel L in Figure 12, meaning that a microlens array is added to the light-emitting structure of sub-pixel L. This microlens array is hemispherical in shape and can focus light and control the light-emitting angle during the display process, thereby achieving the purpose of privacy protection.

[0203] The following uses specific timing diagrams to illustrate the operation of the display panel in different display modes. It should be noted that, for ease of description, display mode 1 and display mode 2 are used to represent the two display modes of the display panel. Furthermore, the following explanation will use the following five cases as examples: even-numbered row subpixels are electrically connected to the first data line, odd-numbered row subpixels are electrically connected to the second data line, the light-emitting structure of even-numbered row subpixels does not include a microlens array, and the light-emitting structure of odd-numbered row subpixels includes a microlens array.

[0204] (1) Referring to Figures 9, 13 and 14, the entire display panel displays the image in display mode 1.

[0205] When the display panel displays the image in display mode 1, the second strobe control signal is a constant high-level signal, that is, the second strobe control signal is an invalid signal, and the third transistor M3 and the fourth transistor M4 are turned off.

[0206] During the Blank period, the first strobe control signal and the second strobe control signal are switched. After the switch, the first strobe control signal is a constant low level signal, that is, the first strobe control signal is an effective signal. The first transistor M1 and the second transistor M2 are turned on. The data input line provides the first data voltage to the first data line through the first transistor M1. The sub-pixel connected to the first data line displays normally, and all even-numbered rows of sub-pixels in the entire display panel display the image. The voltage input line provides the reference voltage to the second data line through the second transistor M2. The sub-pixel connected to the second data line displays in black, and all odd-numbered rows of sub-pixels in the entire display panel do not display the image.

[0207] (2) Referring to Figures 9, 15 and 16, the entire display panel displays the image in display mode 2.

[0208] When the display panel displays the image in display mode 2, the first strobe control signal is a constant high-level signal, that is, the first strobe control signal is an invalid signal, and the first transistor M1 and the second transistor M2 are turned off.

[0209] During the Blank period, the first and second gating control signals are switched. After the switch, the second gating control signal is a constant low-level signal, that is, the second gating control signal is an effective signal. The third transistor M3 and the fourth transistor M4 are turned on. The data input line provides the second data voltage to the second data line through the fourth transistor M4. The sub-pixels connected to the second data line display normally, and all odd-numbered rows of sub-pixels in the entire display panel display the image. The voltage input line provides a reference voltage to the first data line through the third transistor M3. The sub-pixels connected to the first data line display in black, and all even-numbered rows of sub-pixels in the entire display panel do not display the image.

[0210] (3) Referring to Figures 9, 17 and 18, the first row to the Kth row of the display panel is displayed in display mode 1, and the K+1th row to the Nth row is displayed in display mode 2.

[0211] During the display process of sub-pixels from the first row to the Kth row, the first strobe control signal and the second strobe control signal are switched during the Blank duration. After the switch, the first strobe control signal is a low-level signal, i.e., the first strobe control signal is an active signal. The first transistor M1 and the second transistor M2 are turned on. The data input line provides the first data voltage to the first data line through the first transistor M1. The sub-pixels connected to the first data line display normally, i.e., all even-numbered row sub-pixels from the first row to the Kth row display the image. The voltage input line provides a reference voltage to the second data line through the second transistor M2. The sub-pixels connected to the second data line are displayed in black, and all odd-numbered row sub-pixels from the first row to the Kth row do not display the image. The second strobe control signal is a constant high-level signal, i.e., the second strobe control signal is an inactive signal. The third transistor M3 and the fourth transistor M4 are turned off.

[0212] During the display of sub-pixels from row K+1 to row N, the first gating control signal is high, meaning it is invalid, and the first transistor M1 and the second transistor M2 are off. Simultaneously, during the Blank duration, the first and second gating control signals are switched. After the switch, the second gating control signal is low, meaning it is valid, and the third transistor M3 and the fourth transistor M4 are turned on. The data input line provides the second data voltage to the second data line via the fourth transistor M4, and the sub-pixels connected to the second data line display normally. All odd-numbered row sub-pixels from row K+1 to row N display the image. The voltage input line provides a reference voltage to the first data line via the third transistor M3, and the sub-pixels connected to the first data line display in black. All even-numbered row sub-pixels from row K+1 to row N do not display the image.

[0213] (4) Referring to Figures 9, 19 and 20, the first column to the Kth column of the display panel is displayed in display mode 1, and the K+1 column to the Mth column is displayed in display mode 2.

[0214] During the duration of Blank, the first strobe control signal and the second strobe control signal are switched. After the switch, during the display of sub-pixels from the first column to the Kth column, the first strobe control signal is a low level signal and the second strobe control signal is a high level signal. During the display of sub-pixels from the K+1th column to the Nth column, the first strobe control signal is a high level signal and the second strobe control signal is a low level signal.

[0215] When the first gating control signal is low (valid), the first transistor M1 and the second transistor M2 are turned on. The data input line provides a first data voltage to the first data line via the first transistor M1. The sub-pixels connected to the first data line from the first column to the Kth column are displayed normally, meaning all even-numbered row sub-pixels in columns 1 to K display the image. The voltage input line provides a reference voltage to the second data line via the second transistor M2. The sub-pixels connected to the second data line are displayed in black, and all odd-numbered row sub-pixels in columns 1 to K do not display the image. When the second gating control signal is high (invalid), the third transistor M3 and the fourth transistor M4 are turned off.

[0216] During the display of sub-pixels from column K+1 to column N, the first gating control signal is high, meaning it is invalid, and the first transistor M1 and the second transistor M2 are off. Simultaneously, the second gating control signal is low, meaning it is valid, and the third transistor M3 and the fourth transistor M4 are on. The data input line provides the second data voltage to the second data line via the fourth transistor M4, and the sub-pixels connected to the second data line display normally. All odd-numbered row sub-pixels from column K+1 to column N display the image. The voltage input line provides a reference voltage to the first data line via the third transistor M3, and the sub-pixels connected to the first data line display in black. All even-numbered row sub-pixels from column K+1 to column N do not display.

[0217] (5) Referring to Figures 9, 21 and 22, the first column to the Kth column of the display panel are displayed in display mode 1; the first row to the Hth row of the K+1th column to the K+Lth column are displayed in display mode 1; the H+1th row to the H+Jth row of the K+1th column to the K+Lth column are displayed in display mode 2; the H+J+1th row to the Nth row of the K+1th column to the K+Lth column are displayed in display mode 1; and the K+L+1th column to the Mth column are displayed in display mode 1.

[0218] During the display process of sub-pixels from the first to the Kth column, the first and second strobe control signals are switched during the Blank duration. After the switch, the first strobe control signal is a low-level signal, i.e., the first strobe control signal is valid. The first transistor M1 and the second transistor M2 are turned on. The data input line provides the first data voltage to the first data line through the first transistor M1. The sub-pixels from the first to the Kth column connected to the first data line are displayed normally, i.e., all even-numbered row sub-pixels in the first to Kth columns display the image. The voltage input line provides a reference voltage to the second data line through the second transistor M2. The sub-pixels connected to the second data line are displayed in black, and all odd-numbered row sub-pixels in the first to Kth columns do not display the image. The second strobe control signal is a high-level signal, i.e., the second strobe control signal is invalid. The third transistor M3 and the fourth transistor M4 are turned off.

[0219] Rows 1 to H in columns K+1 to K+L are displayed in display mode 1. The first strobe control signal is low, meaning it is active. The first transistor M1 and the second transistor M2 are turned on. The data input line provides a first data voltage to the first data line via the first transistor M1. The sub-pixels in rows 1 to H connected to the first data line are displayed normally; that is, all even-numbered row sub-pixels in rows 1 to H are displayed. The voltage input line provides a reference voltage to the second data line via the second transistor M2. The sub-pixels connected to the second data line are displayed in black; that is, all odd-numbered row sub-pixels in rows 1 to H are not displayed. The second strobe control signal is high, meaning it is inactive. The third transistor M3 and the fourth transistor M4 are turned off.

[0220] Rows H+1 to H+J in columns K+1 to K+L are displayed in display mode 2. The first gating control signal is high, meaning it is invalid, and the first transistor M1 and the second transistor M2 are off. The second gating control signal is low, meaning the third transistor M3 and the fourth transistor M4 are on. The data input line provides the second data voltage to the second data line via the fourth transistor M4, and the corresponding sub-pixels of the second data line display normally. All odd-numbered row sub-pixels in rows H+1 to H+J display the image. The voltage input line provides a reference voltage to the first data line via the third transistor M3, and the corresponding sub-pixels of the first data line display in black. All even-numbered row sub-pixels in rows H+1 to H+J do not display the image.

[0221] Rows H+J+1 to N in columns K+1 to K+L are displayed in display mode 1. When the first gating control signal is low (valid), the first transistor M1 and the second transistor M2 are turned on. The data input line provides a first data voltage to the first data line via the first transistor M1, and the sub-pixels in rows H+J+1 to N connected to the first data line are displayed normally (i.e., all even-numbered row sub-pixels in rows H+J+1 to N are displayed). The voltage input line provides a reference voltage to the second data line via the second transistor M2, and the sub-pixels in rows H+J+1 to N are displayed in black (i.e., all odd-numbered row sub-pixels in rows H+J+1 to N are not displayed). When the second gating control signal is high (invalid), the third transistor M3 and the fourth transistor M4 are turned off.

[0222] During the display process of sub-pixels from column K+L+1 to column M, the first gating control signal is low and the second gating control signal is high, meaning the first gating control signal is valid. The first transistor M1 and the second transistor M2 are turned on. The data input line provides the first data voltage to the first data line via the first transistor M1, and the sub-pixels from column K+L+1 to column M connected to the first data line display normally; that is, all even-numbered row sub-pixels from column K+L+1 to column M display the image. The voltage input line provides a reference voltage to the second data line via the second transistor M2, and the sub-pixels connected to the second data line display in black; all odd-numbered row sub-pixels from column K+L+1 to column M do not display the image. When the second gating control signal is high, meaning the second gating control signal is invalid, the third transistor M3 and the fourth transistor M4 are turned off.

[0223] In this embodiment, the gating control circuit is connected to at least two data lines. During implementation, the gating control circuit provides different voltage signals to each data line. For example, the gating control circuit provides a reference voltage to some data lines and a data voltage to another part of the data lines, so that different data lines can present at least two display states at the same time, thereby enabling the entire display panel to present different display modes and switch between different display modes, thereby improving the flexibility of the display panel.

[0224] Based on the same inventive concept, this application provides a display device including the display panel of any of the above.

[0225] Referring to Figure 23, the above-mentioned display device also includes a source drive circuit.

[0226] The source drive circuit is electrically connected to the other end of the data input line and is configured to provide a first data voltage or a second data voltage to the data input line.

[0227] In this embodiment, the source drive circuit is mainly used to generate a first data voltage and a second data voltage. The other end of the data input line is electrically connected to the source drive circuit. During implementation, when the data input line is electrically connected to the first transistor M1, the source drive circuit provides the first data voltage to the data input line, which in turn provides the first data voltage to the first transistor M1, and the first transistor M1 provides the first data voltage to the first data line. When the data input line is electrically connected to the fourth transistor M4, the source drive circuit provides the second data voltage to the data input line, which in turn provides the second data voltage to the fourth transistor M4, and the fourth transistor M4 provides the second data voltage to the second data line.

[0228] Referring to Figure 23, the above-mentioned display device also includes: a power management integrated circuit (PMIC), a timing controller (TCON), and a level shifter (LS).

[0229] Signal flow direction 1: PMIC to voltage input line.

[0230] The PMIC is electrically connected to the other end of the voltage input line and is configured to provide a reference voltage to the voltage input line.

[0231] In order to enable the voltage input line to provide a reference voltage, in this embodiment of the application, the PMIC is electrically connected to the other end of the voltage input line. In this way, the PMIC can provide a reference voltage to the voltage input line, thereby enabling the voltage input line to provide the reference voltage to the data line through the gating control circuit.

[0232] It should be noted that the specific voltage value of the above-mentioned reference voltage is related to the above-mentioned pixel driving circuit. That is, the specific voltage value of the reference voltage needs to be flexibly set according to the driving transistor DTFT of the pixel driving circuit, the first power supply voltage, and the second power supply voltage.

[0233] For example, in the 7T1C pixel driving circuit shown in Figure 11, the voltage of VDD is typically 4.6V and the voltage of VSS is typically -2.5V. Based on this, the reference voltage provided to the pixel driving circuit shown in Figure 11 must be greater than 4.6V. Furthermore, considering the threshold voltage of the driving transistor DTFT, the voltage range of the above reference voltage is typically between 7.5V and 8V. Thus, the driving transistor DTFT is turned off under the action of the above reference voltage, and the corresponding sub-pixel then presents a black state display.

[0234] Signal flow direction 2: from PMIC to the source drive circuit.

[0235] The PMIC is also electrically connected to the source drive circuit and is configured to provide a reference voltage to the source drive circuit to drive it to operate.

[0236] In order to ensure that the source drive circuit can work normally, in the embodiments of this application, when the PMIC is electrically connected to the source drive circuit, the PMIC will also provide the above-mentioned reference voltage to the source drive circuit. That is, the above-mentioned reference voltage is the analog working voltage required by the source drive circuit, and the source drive circuit works under the drive of the above-mentioned reference voltage.

[0237] Signal flow direction 3: from PMIC to TCON to source drive circuit.

[0238] In this case, the source drive circuit can generate the first data voltage and the second data voltage under the action of PMIC and TCON.

[0239] First, the PMIC is also electrically connected to the TCON and is configured to provide a drive voltage to the TCON.

[0240] To ensure that the TCON can work properly, in this embodiment of the application, when the PMIC is electrically connected to the TCON, the PMIC will also provide a driving voltage to the TCON. Usually, the driving voltage is different from the voltage value of the reference voltage mentioned above. The TCON starts to work under the drive of the driving voltage mentioned above.

[0241] After the TCON starts working, the TCON generates a preselected data voltage and provides the preselected data voltage to the source drive circuit. In this way, the source drive circuit can further generate a first data voltage and a second data voltage based on the preselected data voltage. Then, the source drive circuit provides the first data voltage to the first data line and the second data voltage to the second data line.

[0242] Signal flow direction 4: PMIC to TCON to LS to gating control circuit.

[0243] Similarly, the PMIC provides a drive voltage to the TCON, which is usually different from the reference voltage mentioned above. The TCON starts to work under the drive voltage.

[0244] After TCON starts working, TCON will also transform the above-mentioned drive voltage to generate a first gating control signal and a second gating control signal. Typically, the voltage values ​​of the first gating control signal and the second gating control signal generated by TCON are within 0 to 1.8V. TCON will further provide the first gating control signal and the second gating control signal within 0 to 1.8V to LS.

[0245] The LS is also electrically connected to the gating control circuit via the first gating control line and the second gating control line. In this embodiment, the LS will also perform level conversion on the first gating control signal and the second gating control signal, that is, convert the first gating control signal and the second gating control signal with voltage values ​​between 0 and 1.8V into the first gating control signal and the second gating control signal with voltage values ​​between -7V and +7V. The LS provides the converted first gating control signal to the first gating control line, so that the first gating control terminal can obtain the first gating control signal. The LS also provides the converted second gating control signal to the second gating control line, so that the second gating control terminal can obtain the second gating control signal.

[0246] Signal flow direction 5: PMIC to TCON to LS to gate drive circuit.

[0247] Similarly, the PMIC provides a drive voltage to the TCON, which is usually different from the reference voltage mentioned above. The TCON starts to work under the drive voltage.

[0248] After TCON starts working, TCON can also generate logic voltage signals according to the drive voltage. Usually, the above logic voltage signals are the logic voltage timing signals required for the gate drive circuit to work. However, if the voltage value is within 0 to 1.8V, the gate drive circuit cannot work normally and needs to be level-converted by LS.

[0249] In this embodiment, the LS is also electrically connected to the gate drive circuit. After receiving the logic voltage signal, the LS performs level conversion on the logic voltage signal, obtaining a valid high-level signal (commonly VGH) and a valid low-level signal (commonly VGL). It should be noted that the voltage values ​​of the valid high-level signal and the valid low-level signal are typically between -7V and +7V. The LS provides the converted valid high-level signal and the valid low-level signal to the gate drive circuit, so that the gate drive circuit generates a scan signal based on the valid high-level signal and the valid low-level signal. Thus, the gate drive circuit generates a scan signal under the action of the valid high-level signal and the valid low-level signal.

[0250] It should be noted that the voltage ranges of 0 to 1.8V and -7V to +7V mentioned above are related to the type of light-emitting device in the pixel driving circuit and the process structure of the display device. In specific implementation, the voltage ranges can be flexibly set according to the actual application scenario.

[0251] Referring to Figure 24, the above-mentioned display device also includes an inverter, the input terminal of which is electrically connected to TCON, and the output terminal of which is electrically connected to LS.

[0252] The inverter is configured to invert the first gating control signal generated by TCON to obtain the second gating control signal, or to invert the second gating control signal generated by TCON to obtain the first gating control signal.

[0253] Considering the limited number of general-purpose input / output (GPIO) pins of TCON, in order to save on the use of GPIO, an inverter is also electrically connected between LS and TCON in this embodiment.

[0254] In one embodiment, after TCON generates a first strobe control signal and outputs it through a GPIO port, an inverter can invert the first strobe control signal to obtain a second strobe control signal. Thus, both the first and second strobe control signals can be obtained using only GPIO_1. Compared to outputting the first strobe control signal through GPIO_1 and the second strobe control signal through GPIO_2, this effectively saves on the number of GPIO ports used.

[0255] Considering that the first strobe control signal and the second strobe control signal are inverted signals, in another embodiment, the TCON can also generate the second strobe control signal and output it through a GPIO port. The inverter can invert the second strobe control signal to obtain the first strobe control signal. In this way, the first strobe control signal and the second strobe control signal can be obtained by using a GPIO port.

[0256] In the embodiments of this application, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this application.

[0257] Based on the same inventive concept, this application provides a method for driving a display panel, including:

[0258] The gating control circuit provides a reference voltage to a portion of the data lines connected to each sub-pixel; and

[0259] In this embodiment, the sub-pixels in the display panel are electrically connected to the corresponding data lines.

[0260] During implementation, the gating control circuit responds to the first gating control signal and the second gating control signal by connecting a portion of the data lines to the voltage input lines. This means that the reference voltage in the voltage input lines is provided to the aforementioned portion of the data lines, thereby causing the pixel driving circuit of the corresponding portion of the sub-pixels to be displayed in a black state under the action of the reference voltage.

[0261] The gating control circuit provides data voltage to the other part of the data lines connected to each sub-pixel.

[0262] During implementation, the gating control circuit responds to the first gating control signal and the second gating control signal by connecting another part of the data lines to the data input lines. This means that the data voltage in the data input lines is provided to the other part of the data lines, so that the pixel driving circuit of the corresponding other part of the sub-pixels can display under the action of the data voltage.

[0263] For example, even-numbered row sub-pixels are electrically connected to the first data line, odd-numbered row sub-pixels are electrically connected to the second data line, and the light-emitting structures of even-numbered row sub-pixels and odd-numbered row sub-pixels are different.

[0264] During implementation, the first gating control subcircuit responds to the first gating control signal by providing the first data voltage in the data input line to the first data line, enabling even-numbered row sub-pixels to display the image in display mode 1, and providing the reference voltage to the second data line, enabling odd-numbered row sub-pixels to display in black. Since the first gating control signal and the second gating control signal are inverse signals, the second gating control subcircuit responds to the second gating control signal by being turned off.

[0265] Alternatively, in response to the second gating control signal being turned on, the second gating control sub-circuit provides the second data voltage in the data input line to the second data line, allowing the odd-numbered row sub-pixels to display the image in display mode 2, and provides a reference voltage to the first data line, allowing the even-numbered row sub-pixels to display in black. Since the first gating control signal and the second gating control signal are inverse signals, the first gating control sub-circuit is turned off in response to the first gating control signal.

[0266] In summary, the present application provides a display panel, display device, and driving method. The display panel includes multiple sub-pixels, multiple data lines, and multiple gating control circuits. Each column of sub-pixels is connected to at least two data lines, and the sub-pixels connected to the at least two data lines are different. Each column of sub-pixels corresponds to a gating control circuit, which is connected to at least two data lines and configured to provide a reference voltage to a portion of the data lines and a data voltage to the other portion of the data lines. Thus, during the display of the screen, the reference voltage in some data lines can make part of the screen appear black, while the data voltage in the other portion of the data lines can make the other portion of the screen display normally. This enables the display of different display modes of the display panel and improves the flexibility of the display panel.

[0267] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program product systems. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0268] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program product systems according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0269] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0270] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0271] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A display panel, wherein, include: Multiple sub-pixels, multiple data lines, and multiple gating control circuits; Each column of sub-pixels is connected to at least two data lines, and the at least two data lines are connected to different sub-pixels; Each column of the sub-pixels corresponds to one of the gating control circuits, and the gating control circuit is connected to the at least two data lines and configured to provide a reference voltage to a portion of the at least two data lines and a data voltage to the other portion of the data lines.

2. The display panel as claimed in claim 1, wherein, The gating control circuit includes: a first gating control sub-circuit and a second gating control sub-circuit; The first gating control subcircuit is configured to, in response to a first gating control signal at a first gating control terminal, provide a first data voltage to a first data line and provide the reference voltage to a second data line; or The second gating control subcircuit is configured to provide the reference voltage to the first data line and, in response to the second gating control signal of the second gating control terminal, provide the second data voltage to the second data line. The first gating control signal and the second gating control signal are inverse signals.

3. The display panel as described in claim 2, wherein, It also includes: the first gating control line and the second gating control line; The first gating control line is electrically connected to the first gating control terminal and is configured to provide the first gating control signal to the first gating control terminal. The second gating control line is electrically connected to the second gating control terminal and is configured to provide the second gating control signal to the second gating control terminal.

4. The display panel as claimed in claim 2, wherein, Also includes: Voltage input lines and data input lines; One end of the voltage input line is electrically connected to the first gating control subcircuit and the second gating control subcircuit, and is configured to provide the reference voltage to the first gating control subcircuit and the second gating control subcircuit; One end of the data input line is electrically connected to the first gating control subcircuit and the second gating control subcircuit, and is configured to provide the first data voltage to the first gating control subcircuit and the second data voltage to the second gating control subcircuit.

5. The display panel as described in any one of claims 2 to 4, wherein, The first gating control sub-circuit includes: a first transistor and a second transistor; The control terminal of the first transistor is electrically connected to the first gating control terminal, the first terminal of the first transistor is electrically connected to the first data line, and the second terminal of the first transistor is electrically connected to the data input line. The control terminal of the second transistor is electrically connected to the first gating control terminal, the first terminal of the second transistor is electrically connected to the second data line, and the second terminal of the second transistor is electrically connected to the voltage input line.

6. The display panel according to any one of claims 2 to 4, wherein, The second gating control sub-circuit includes: a third transistor and a fourth transistor; The control terminal of the third transistor is electrically connected to the second gating control signal terminal, the first terminal of the third transistor is electrically connected to the first data line, and the second terminal of the third transistor is electrically connected to the voltage input line. The control terminal of the fourth transistor is electrically connected to the second gating control terminal, the first terminal of the fourth transistor is electrically connected to the second data line, and the second terminal of the fourth transistor is electrically connected to the data input line.

7. The display panel according to any one of claims 2 to 6, wherein, The sub-pixels in even-numbered rows are electrically connected to the first data line, and the sub-pixels in odd-numbered rows are electrically connected to the second data line.

8. The display panel according to any one of claims 2 to 7, wherein, Each of the sub-pixels includes a pixel driving circuit, which includes: a driving transistor, a light-emitting device, a data writing sub-circuit, a first reset sub-circuit, and a first capacitor; The driving transistor is electrically connected to the light-emitting device; The first terminal of the data writing sub-circuit is coupled to the first terminal of the driving transistor, and the second terminal of the data writing sub-circuit is coupled to the data signal terminal and is configured to provide the data voltage of the data signal terminal to the first terminal of the driving transistor in response to the signal of the scan signal terminal. The first reset sub-circuit is coupled to the control terminal of the driving transistor, and the first reset sub-circuit is configured to provide the signal of the first initialization signal terminal to the control terminal of the driving transistor in response to the signal of the reset control signal terminal. The first capacitor is electrically connected to the control terminal and the first power supply terminal of the driving transistor and is configured to store a first data voltage or a second data voltage.

9. The display panel as claimed in claim 8, wherein, The data writing sub-circuit includes: a data writing transistor; The data signal terminal of the data writing transistor in even-numbered rows is electrically connected to the first data line, and the data signal terminal of the data writing transistor in odd-numbered rows is electrically connected to the second data line.

10. The display panel as claimed in claim 8, wherein, The pixel driving circuit further includes: a conduction control sub-circuit, a first light emission control sub-circuit, a second light emission control sub-circuit, and a second reset sub-circuit; The first terminal of the conduction control sub-circuit is electrically connected to the control terminal of the driving transistor, and the second terminal of the conduction control sub-circuit is electrically connected to the second terminal of the driving transistor. It is configured to conduct the control terminal of the driving transistor and the second terminal of the driving transistor in response to the signal of the conduction control signal terminal. The first terminal of the first light-emitting control sub-circuit is electrically connected to the first power supply terminal, and the second terminal of the first light-emitting control sub-circuit is electrically connected to the first terminal of the driving transistor. The first light-emitting control sub-circuit is configured to turn on the first power supply terminal and the first terminal of the driving transistor in response to the signal of the light-emitting control signal terminal. The first terminal of the second light-emitting control sub-circuit is electrically connected to the second terminal of the driving transistor, and the second terminal of the second light-emitting control sub-circuit is electrically connected to the anode of the light-emitting device. It is configured to conduct the second terminal of the driving transistor to the anode of the light-emitting device in response to the signal of the light-emitting control signal terminal. The second reset sub-circuit is electrically connected to the anode of the light-emitting device, and the second reset sub-circuit is configured to provide a signal from the second initialization signal terminal to the anode of the light-emitting device in response to a signal from the reset control signal terminal.

11. The display panel according to any one of claims 2 to 10, wherein, Both the first data line and the second data line extend along the first direction.

12. The display panel according to any one of claims 2 to 11, wherein, The light-emitting structures of the sub-pixels in even-numbered rows are different from those in odd-numbered rows.

13. A display device, wherein, include: The display panel as described in any one of claims 1 to 12.

14. The display device as claimed in claim 13, wherein, It also includes the source drive circuit; The source drive circuit is electrically connected to the other end of the data input line and is configured to provide a first data voltage or a second data voltage to the data input line.

15. The display device as claimed in claim 14, wherein, Also includes: The power management circuit includes a PMIC, a timing controller (TCON), and a level conversion unit (LS). The PMIC is electrically connected to the other end of the voltage input line and is configured to provide the reference voltage to the voltage input line. The PMIC is also electrically connected to the source drive circuit and is configured to provide the reference voltage to the source drive circuit to drive the source drive circuit to operate. The PMIC is also electrically connected to the TCON and is configured to provide a drive voltage to the TCON; The TCON is electrically connected to the source drive circuit and is configured to provide the source drive circuit with a preselected data voltage for generating the first data voltage and the second data voltage, generate a first gating control signal and a second gating control signal based on the drive voltage, and generate a logic voltage signal based on the drive voltage. The LS is electrically connected to the TCON, the first gating control line, and the second gating control line, and is configured to perform level conversion on the first gating control signal and the second gating control signal, provide the converted first gating control signal to the first gating control line, and provide the converted second gating control signal to the second gating control line. The LS is also electrically connected to the gate drive circuit and is configured to perform level conversion on the logic voltage signal and provide the converted effective high-level signal and effective low-level signal to the gate drive circuit.

16. The display device as claimed in claim 15, wherein, It also includes an inverter, the input of which is electrically connected to the TCON, and the output of which is electrically connected to the LS; The inverter is configured to invert the first gating control signal generated by the TCON to obtain the second gating control signal, or to invert the second gating control signal generated by the TCON to obtain the first gating control signal.

17. A driving method applied to a display panel as described in any one of claims 1 to 12, wherein, include: The gating control circuit provides a reference voltage to a portion of the data lines connected to each of the sub-pixels; as well as The gating control circuit provides data voltage to another part of the data lines corresponding to each of the sub-pixels.

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