Method for producing a hall sensor which comprises gaas
Patent Information
- Application Number
- PCT/EP2025/057136
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-03-15
- Publication Date
- 2026-09-24
Smart Images
Figure EP2025057136_24092026_PF_FP_ABST
Abstract
Description
[0001] Method for manufacturing a GaAs-based Hall sensor
[0002] A vertical III-V Hall sensor is known from DE 10 2023 002 342 Al. This vertical III-V Hall sensor comprises an insulating layer on a GaAs substrate, a GaAs semiconductor layer arranged on the insulating layer, and a second insulating layer formed on the semiconductor layer and interrupted by electrical contact areas. The second insulating layer is formed, among other things, from an InGaP compound. Furthermore, the vertical III-V Hall sensor has circumferential insulation, which is implemented, among other things, by hydrogen implantation.
[0003] Furthermore, various III-V Hall sensors for measuring the three components of a magnetic field are known from CN 102 520 376 A. For measuring magnetic fields parallel to a substrate surface, a column-shaped Hall sensor structure arranged perpendicular to the substrate surface is disclosed. The column-shaped structure is contacted, among other things, at its two end faces.
[0004] Other generic III-V Hall sensors are known from EP 0 204 135 Al, CN 102 244 234 B, DE 10 2011 002580 Al and CN 105 261 698 A.
[0005] Against this background, the object of the invention is to specify a method that advances the state of the art.
[0006] The problem is solved by a method for producing a GaAs-comprising Hall sensor with the features of claim 1. Advantageous embodiments of the invention are the subject of dependent claims. According to the subject matter of the invention, a method for producing a GaAs-comprising Hall sensor is provided.
[0007] For the execution of the process, a semiconductor wafer made of GaAs, configured as a substrate, is provided, having a top and a bottom surface, a first lattice constant, and a first band gap. In a further development, the semiconductor wafer has a diameter of 100 mm, 150 mm, or 200 mm or larger. In this case, the semiconductor wafer has a thickness of at least 100 µm during the epitaxy process.
[0008] In one process step, a III-V insulating layer having the first lattice constant is produced on the top side of the GaAs substrate using an epitaxy process.
[0009] In another process step, a GaAs semiconductor layer with the first grid constant and n-doping is grown on the insulation layer using the epitaxy method.
[0010] In a further process step, an n-doped GaAs shielding layer, which is bonded to the semiconductor layer, is epitaxially formed.
[0011] The shielding layer is more highly doped than the semiconductor layer. Furthermore, the shielding layer is at least ten times thinner than the semiconductor layer.
[0012] In one process step, a large number of masked first regions are generated using a masking process. In other words, a mask is formed on the first regions.
[0013] At least part of the first areas is completely enclosed by strip-shaped, mask-free second areas. It should be noted that in a further training course, all first areas are enclosed by second areas.
[0014] In one or more subsequent process steps, a vertical insulation layer is created in the second areas.
[0015] In a further process step, contacts are formed on at least part of the first areas in order to operate the semiconductor layer in the first area as a Hall sensor.
[0016] After the formation of contacts in one area, the semiconductor layer has a flat top surface, the area comprising at least two adjacent first areas electrically isolated from each other by the second area.
[0017] It should be noted that the aforementioned process steps are carried out in the specified order.
[0018] It should be noted that the terms contacts, metallic contacts, connection contacts and Meta II contacts are used synonymously below.
[0019] One advantage of this method is that, surprisingly, the electrical properties of the Hall sensors formed in the first regions are improved by forming a shielding layer. Because the shielding layer is very thin compared to the semiconductor layer, an operating current imposed by the contacts flows almost completely or exclusively through the semiconductor layer.
[0020] Another advantage is that the formation of a planar surface allows the Hall sensors to be electrically contacted in a simple and reliable way even after insulation.
[0021] In a continuing education course, the formation of epitaxially grown layers is carried out using a MOVPE process, an LPE process, or an MBE process. It should be noted that the MOVPE process using metal-organic precursors is currently predominantly used for the epitaxial production of GaAs layers.
[0022] It should be noted that, unlike silicon technology, doping of the GaAs layers is already inherent in the manufacturing process.
[0023] The implantation of dopants followed by activation through temperature steps such as RTA or furnace processes is only feasible to a limited extent with GaAs, due in part to its decomposition temperature above approximately 700 °C. Furthermore, passivation of GaAs by means of oxidation of the semiconductor material is also not as straightforward as with silicon technology. In summary, it should be noted that the fabrication of components using GaAs is not directly compatible with the fabrication of components using silicon technology.
[0024] In another training course, the semiconductor layer is doped with a concentration in a range between l*10 14 1 / cm 3 and 5*10 17 1 / cm 3 or in a range between 5*10 14 1 / cm 3 and l*10 16 1 / cm 3 or in a range between l*10 15 1 / cm 3 and 5*1015 1 / cm 3 grew up.
[0025] It is understood that, in order to achieve the highest possible mobility, the doping of the III-V semiconductor layer should be in a range below 1*10 over a predominant part of the thickness. 16 1 / cm 3 It should be located. In another further development, the doping of the semiconductor layer is grown with a homogeneous doping. In one embodiment, the semiconductor layer is doped with 2 * 10 15 1 / cm 3 grew up.
[0026] In one embodiment, the semiconductor layer is formed with a thickness in the range of 0.5 pm to 15 pm, or with a thickness in the range of 1.0 pm to 8 pm, or with a thickness in the range of 2.0 pm to 5 pm. In a further embodiment, the semiconductor layer consists of GaAs. In another embodiment, the shielding layer and / or the insulating layer consists of GaAs.
[0027] In a further training, the shielding layer is formed with the first lattice constant and the band gap of the semiconductor layer or the substrate.
[0028] In one embodiment, the shielding layer is doped with a concentration at least 10 times higher than the semiconductor layer, or with a concentration in a range between 5*10 16 1 / cm 3 and l*10 18 1 / cm 3 or with a doping concentration in a range between l*10 17 1 / cm 3 and 5«10 17 1 / cm 3grew up.
[0029] In another embodiment, the shielding layer is grown with a thickness in a range between 20 nm and 200 nm, or with a thickness in a range between 50 nm and 100 nm, or with a thickness in a range between 65 nm and 75 nm.
[0030] In another advanced training process, a III-V cover layer with the first lattice constant is epitaxially grown onto a semiconductor layer formed in a material bond with the shielding layer in a process step, whereby the cover layer is formed from a different material with a higher band gap than the semiconductor layer.
[0031] In one embodiment, the covering layer is formed with a thickness in a range between 3 nm and 50 nm or with a thickness in a range between 5 nm and 15 nm.
[0032] In another embodiment, the cover layer is doped with an n-number in a range between 5*10 17 1 / cm 3 and 5®10 19 1 / cm 3 or in a range between l*10 18 1 / cm 3 and l*10 19 1 / cm 3 manufactured.
[0033] In a further development, the cover layer is formed with an InGaP-containing compound or a compound consisting of an InGaP compound. In this further development, the thickness of the cover layer is less in the areas between the metal contacts compared to the areas below the metal contacts.
[0034] In another continuation
[0035]
[0036] The cover layer has a bottom surface formed on the shielding layer and a top surface opposite the bottom surface, with delta doping being formed on the bottom surface and / or on the top surface to reduce contact barriers.
[0037] One advantage of delta doping is that the conductivity at the contact layer becomes metallic, i.e., very low-resistance. In other words, the Fermi level lies within the conduction band.
[0038] In another advanced training course, delta doping with silicon is performed during layer growth in epitaxy. For example, in a MOVPE system, a corresponding precursor is briefly switched on and off to create silicon delta doping.
[0039] In another training course, a mask made of one material or a mask made of several layers of different materials is used when masking the first areas.
[0040] In one embodiment, a mask comprising an organic photoresist is formed on the surface of the semiconductor disk, i.e., on the surface of the last epitaxially applied semiconductor layer.
[0041] In another embodiment, a SiN layer is first deposited, preferably by means of a PECVD or PVD process, before the organic photoresist is applied, in order to protect the surface from contamination. In a subsequent process step, the photoresist is then applied across the entire surface and either directly structured or coated with a metal layer before structuring and then structured. It should be noted that with the structuring in the second area, the mask is removed in order to subsequently form the vertical insulating layer.
[0042] In a further development, the vertical insulating layer in the second regions is extended to the insulating layer above the GaAs substrate or into the insulating layer itself. In other words, the vertical insulating layer is formed as a continuous, full-surface vertical layer from the semiconductor surface down to the first insulating layer. In conjunction with the insulating layer, the enclosed adjacent first regions are completely electrically isolated from each other. It is understood that the insulating layer also isolates the first regions from the substrate.
[0043] In further training, the second areas have a width between 1.0 pm and 50 pm or a width between 2 pm and 5 pm.
[0044] In another advanced version, the vertical insulating layer is extended from the top of the semiconductor layer beyond the insulating layer itself, i.e., into the substrate. This results in particularly reliable electrical insulation between adjacent first regions.
[0045] In one embodiment, the vertical insulation layer is created by means of hydrogen implantation, and after implantation, the mask is removed from the first regions, or the vertical insulation layer is created by a trenching process. In each case, after the formation of the vertical insulation layer, a planar surface exists in a region comprising at least several of the first regions and at least one or more of the second regions.
[0046] In another embodiment, a p / n junction is created to form the first insulating layer and / or the insulating layer is formed from a III-V material with a second band gap, wherein the second band gap is larger than the first band gap. In a further development, a p-doped sublayer comprising GaAs and an n-doped sublayer comprising GaAs are formed as the insulating layer, wherein the p-doped sublayer is metallurgically bonded to the substrate and the n-doped sublayer is metallurgically bonded to the semiconductor layer.
[0047] In another advanced training, the two sublayers are grown using the epitaxy process, with the n-doped sublayer having a higher doping concentration than the semiconductor layer, in a lattice-matched manner to the lattice constant of the substrate.
[0048] In another training course, the p-doped sublayer is treated with a doping level in a range between l«1014 1 / cm 3 and l*10 16 1 / cm 3 or with a doping concentration in a range between l*10 15 1 / cm 3 and 8*10 15 1 / cm 3 and the n-doped sublayer with a doping concentration in a range between l*10 15 1 / cm 3 and l*10 17 1 / cm 3 or with a doping level in the range between 8*10 15 1 / cm 3 and 5*10 17 1 / cm 3 trained.
[0049] In one embodiment, the p-doped sublayer is formed with a thickness in a range between 50 nm and 2.0 pm or with a thickness in a range between 100 nm and 800 nm, and the n-doped sublayer is formed with a thickness in a range between 10 nm and 300 nm or with a thickness in a range between 30 nm and 100 nm.
[0050] In another embodiment, in an epitaxial process step, at least one n-doped III-V contact layer is formed on the cover layer or on the shielding layer in order to form a low-resistance electrical connection with the cover layer or with the shielding layer after the formation of metallic connection contacts.
[0051] In one further development, the contact layer in the non-contact areas is removed during the formation of the metallic terminal contacts, so that the contact layer is formed exclusively between the cover layer and the terminal contacts. In another further development, the contact layer is formed with the first lattice constant and / or the contact layer is formed with the same band gap as the semiconductor layer.
[0052] In one embodiment, the contact layer is formed as an n-doped GaAs layer and / or an n-doped InGaAs layer, or the contact layer is formed from an n-doped GaAs layer and / or an n-doped InGaAs layer.
[0053] In this advanced design, the contact layer comprises a first GaAs sublayer and a second InGaAs sublayer. The two sublayers are metallurgically bonded to each other. Furthermore, the first sublayer is metallurgically bonded to either the shielding layer or the cover layer.
[0054] The second sublayer is metallurgically bonded to the metal contact. It is understood that both sublayers are formed exclusively below the metal contacts to prevent a short circuit in the semiconductor layer.
[0055] In one embodiment, the contact layer is formed with a total thickness in a range between 10 nm and 150 nm or in a range between 30 nm and 100 nm.
[0056] In another embodiment, the doping of the contact layer is above l*10 18 1 / cm 3 or above 5*10 18 1 / cm 3 or above l*10 19 1 / cm 3 trained.
[0057] In a further development, at least a first geometric embodiment and a second geometric embodiment are formed as first regions, wherein the two embodiments of the first regions are isolated from each other by means of a second region. In another further development, the first embodiment is formed in a top view of the semiconductor surface as a rectangular, square, cross-shaped, or octagonal area for forming a lateral Hall sensor, and the second embodiment is formed for forming a vertical Hall sensor in a rectangular, double-axe-shaped, or butterfly-shaped configuration.
[0058] In a further development, in the first embodiment exactly four or exactly eight connection contacts are formed, and in the second embodiment exactly three connection contacts or exactly four or exactly five or exactly six or exactly seven connection contacts are formed.
[0059] In another further development, several first areas of the second embodiment are directly adjacent to each other, with each first area being isolated from the others by means of a second area.
[0060] In one embodiment, a region of the second embodiment is formed on each of two sides of the first embodiment, wherein the two regions of the second embodiment are arranged orthogonally to each other in order to form a 3D Hall sensor in the form of a pixel cell.
[0061] In the first embodiment, a Z-component of a magnetic field is detected, and in the second embodiment, an X-component and a Y-component of the magnetic field are detected by the first two regions.
[0062] It should be noted that a magnetic field component formed orthogonally on the semiconductor surface is called the Z-component, and two components that are orthogonally aligned with each other and run in the plane of the semiconductor surface are called X- and Y-components, respectively.
[0063] In a further development, first areas of the second embodiment are formed around a central first area of the first embodiment on at least two sides or on all sides in order to form a 3D Hall sensor.
[0064] In another advanced training course, at least part of the second area is covered in the training on guard rings. This involves, for example, creating trenches using a trenching process, and after forming sidewall insulation by filling with a conductive material and creating electrical contacts, the trenches are electrically connected.
[0065] The invention is explained in more detail below with reference to the drawings. Similar parts are labelled with identical designations. The illustrated embodiments are highly schematic; that is, the distances and the lateral and vertical extents are not to scale and, unless otherwise indicated, do not exhibit any derivable geometric relationships to one another. In this respect, the
[0066] Figures 1a-c show cross-sectional views of manufacturing stages of the process for the formation of a first embodiment of a Hall sensor.
[0067] Figure 2 shows a cross-sectional view of a second embodiment of a Hall sensor.
[0068] Figure 3 shows a top view of a semiconductor disk with lateral Hall sensors.
[0069] Figures 4a-c Top views of different embodiments of lateral Hall sensors,
[0070] Figure 5a-d Top views of different embodiments of vertical Hall sensors,
[0071] Figures 6a-d Top views of different embodiments of
[0072] Pixel cells, Figure 7 a cross-sectional view of a pixel cell of an embodiment of Fig. 6d.
[0073] Figures 1a-c show cross-sectional views of manufacturing stages of the process for producing a first embodiment of a GaAs Hall sensor. For clarity, a Cartesian coordinate system is shown. Accordingly, the cross-sections are formed in an XZ plane.
[0074] According to the illustration in Figure 1a, a III-V insulation layer IS is produced on a semiconductor disk formed as a GaAs substrate SUB with a top surface OS and a bottom surface US in one process step on the top surface OS of the GaAs substrate SUB by means of an epitaxy process.
[0075] The substrate SUB has a first lattice constant and a first band gap. The III-V insulating layer IS is grown on the substrate with the first lattice constant. The substrate is designed as a semi-insulated GaAs semiconductor wafer.
[0076] In a further process step, an n-doped GaAs semiconductor layer HLS with the first lattice constant is grown on the insulation layer IS using the epitaxy method.
[0077] In a subsequent process step, an n-doped GaAs shielding layer ABS is epitaxially formed on the semiconductor layer HLS, wherein the doping of the shielding layer ABS is greater than the doping of the semiconductor layer HLS.
[0078] The ABS shielding layer has the same lattice constant as the HLS semiconductor layer and a layer thickness at least 10 times smaller than the HLS semiconductor layer. According to the illustration in Figure 1b, a plurality of masked first regions G1 and second unmasked regions G2 are produced in a subsequent process step using a masking process.
[0079] The first regions Gl are completely enclosed by the strip-shaped, mask-free second regions G2.
[0080] In subsequent process steps, a vertical insulation layer VIS is created in the second areas.
[0081] In a process step not shown, the mask is removed from the first areas Gl. In other words, in a top view not shown, the top surface of the semiconductor wafer is free of resist and flat.
[0082] According to the illustration in Figure 1c, in a subsequent process step several metal contacts LK are formed on the first area Gl in order to form the semiconductor layer HLS in the first area Gl as a Hall sensor.
[0083] The semiconductor disk is formed flat on the top side of the ABS shielding layer after the formation of the contacts LK. In other words, an area comprising first regions G1, which are configured as Hall sensor regions, and second region G2, which are configured as vertical insulation regions, has no steps on the top side of the ABS shielding layer.
[0084] Figure 2 shows a cross-sectional view of a second embodiment of a Hall sensor. The differences from the first embodiment, illustrated in conjunction with Figure 1c, are explained below.
[0085] A thin InGaP cover layer ADS is formed on the upper surface of the ABS shielding layer, the cover layer ADS having a first lattice constant. The vertical insulating layer VIS also penetrates the InGaP cover layer ABS. Below the contacts LK, a first contact layer KS1 consisting of n-doped GaAs is formed on the upper surface of the cover layer ADS. The first contact layer KS1 has a doping concentration of more than 1*10 17 1 / cm 3 Between the first contact layer KS1 and the underside of the contacts LK, a second n-doped contact layer KS2 with the first lattice constant is formed. Preferably, the second contact layer KS2 has a doping concentration above 5 × 10⁻⁵. 18 1 / cm 3 up and is trained from InGaAs.
[0086] The insulating layer IS has a p-doped GaAs sublayer IST1 and an n-doped GaAs sublayer IST2. This creates a p / n junction between the two sublayers, electrically isolating the semiconductor layer HLS from the substrate.
[0087] The p-doped sublayer IST1 is formed between the substrate SUB and the n-doped sublayer IST2. The n-doped sublayer IST2 is formed between the p-doped sublayer IST1 and the semiconductor layer HLS.
[0088] In an embodiment not shown, the vertical insulation layer VIS penetrates the two sublayers IST1 and IST2 and extends into the substrate SUB.
[0089] Figure 3 shows a top view of a semiconductor disk arranged in the XY plane with a plurality of Hall sensors. The following section explains only the differences from the embodiments shown in conjunction with Figure 1c or Figure 2.
[0090] The Hall sensors formed in the first regions Gl are designed as lateral Hall sensors LH, in the form of so-called Hall plates. The individual lateral Hall sensors LH have a square geometry. Metal contacts LK are formed at the respective edges in the corners.
[0091] Each of the lateral Hall sensors LH is completely enclosed by a second area G2. For clarity, conductor tracks for connecting the metal contacts are not shown.
[0092] Figures 4a-c show top views of different embodiments of individual lateral Hall sensors LH configured in the XY plane. The differences between these embodiments and those shown in Figure 3 are explained below.
[0093] Figure 4a shows a detailed representation of the square embodiment of the lateral Hall sensor LH of Figure 3. For the sake of clarity, a representation of the second areas is not shown.
[0094] The four metal contacts LK are symmetrically arranged at the four corners of the Hall plate. It is understood that the Hall plate can detect a magnetic field component extending in the Z-direction.
[0095] Figure 4b shows a cross-shaped configuration of a lateral Hall sensor LH. The respective metal contacts LK are located at the ends of the cross. It is understood that the individual branches of the cross-shaped configuration are symmetrical to each other.
[0096] Figure 4c shows an octagonal configuration of a lateral Hall sensor LH. The respective metal contacts LK are located at the octagonal ends. It is understood that the individual branches of the octagonal configuration are symmetrical to each other.
[0097] In an embodiment not shown here, figures 4a and 4b are rotated by 45° in the xy plane about the z-axis.
[0098] Figures 5a-d show top views of different embodiments of individual vertical Hall sensors VH configured in the XY plane. In each of the illustrated embodiments, the vertical Hall sensors VH can detect a magnetic field configured in the Y direction. Only the differences from the preceding embodiments are explained below.
[0099] Figure 5a shows a top view of a rectangular embodiment of a vertical Hall sensor VH. For the sake of clarity, a representation of the second areas is not shown.
[0100] The vertical Hall sensor VH has three metal contacts VK of equal length in the Y direction. The middle metal contact VK is spaced a distance al from each of the two outer metal contacts VK in the X direction.
[0101] In an embodiment not shown, the two outer contacts VK extend to the edge of the first region Gl or beyond.
[0102] Figure 5b shows another double-axe-shaped embodiment of a vertical Hall sensor VH. Only the differences from the embodiment shown in Figure 5a are explained below.
[0103] The two outer metal contacts VK are of equal width in the Y-direction and significantly wider than the middle metal contact VK. All three metal contacts VK have a rectangular extent in the top view shown.
[0104] The first region Gl exhibits mirror symmetry with respect to a mirror axis extending in the Y direction through a center of the central metal contact VK.
[0105] Figure 5c depicts a butterfly-shaped extension with two wings, where a symmetry axis extending in the Y direction passes through the center of the central metal contact VK. The two wings are each crescent-shaped. In other words, the outer edge of the area Gl does not consist of straight lines, but is formed by arc-shaped segments.
[0106] The two outer metal contacts VK, unlike the middle metal contact VK, are not rectangular but are designed as circular segments.
[0107] Figure 5d shows another embodiment of a vertical Hall sensor VH. Only the differences from the embodiment shown in Figure 5a are explained below.
[0108] Four first regions Gl are arranged in a row in the X direction, each containing a vertical partial Hall sensor VHT with three metal contacts VK. The four first regions are separated from each other by second regions G2 and are also completely enclosed by the second regions G2.
[0109] By connecting the outer metal contacts VK of adjacent vertical Hall sensors to each other, the entire structure forms a vertical Hall sensor VH, consisting of four partial Hall sensors VHT, with four middle metal contacts VK.
[0110] Figures 6a-d show top views of different embodiments of pixel cells PZ. The term pixel cell refers to an extremely compact arrangement of Hall sensors capable of detecting various components, at least two, of a magnetic field at nearly the same location. Only the differences from the preceding embodiments are explained below.
[0111] Figure 6a shows a 2D pixel cell PZ, having a lateral Hall sensor LH in a square shape with a vertical Hall sensor VH on one side of the square.
[0112] It is understood that the two Hall sensors LH and VH are each arranged in a first region Gl. With the illustrated embodiment, the component and the X-component of a magnetic field can be detected.
[0113] Figure 6b shows a 3D pixel cell PZ, having a lateral Hall sensor LH in a
[0114]
[0115] The illustration shows a configuration with vertical Hall sensors VH arranged on two adjacent sides of the square. With this embodiment, the Z-component and the X and Y components of a magnetic field can be detected.
[0116] Figure 6c shows a 3D pixel cell PZ, comprising a lateral Hall sensor LH in a square shape in the middle with vertical Hall sensors VH arranged on all sides of the square.
[0117] Figure 6d shows a 3D pixel cell PZ, comprising a lateral Hall sensor LH in a cross-shaped configuration in the center with vertical Hall sensors VH arranged on all side branches. A section line AA is indicated.
[0118] Figure 7 shows a cross-sectional view along the section line AA' of the 3D pixel cell of the embodiment of Fig. 6d, with reference to the structure shown in Figure 2.
[0119] It turns out that in the first regions Gl either a vertical Hall sensor VH or a lateral Hall sensor LH is formed.
[0120] The lateral Hall sensor LH is surrounded at both ends by the vertical Hall sensors VH.
Claims
Patent claims 1. Method for manufacturing a GaAs-comprising Hall sensor, comprising - a semiconductor disk made of GaAs forming a substrate (SUB) with a top side (OS) and a bottom side (US) and a first lattice constant and a first band gap, - a process step on the top side of the GaAs substrate in which a III-V insulating layer (IS) having the first lattice constant is produced by means of an epitaxy process, - a process step on the insulation layer (IS) in which a GaAs-containing semiconductor layer (HLS) with the first lattice constant and n-doping is grown using the epitaxy process, - a process step in which a material bond is created with the semiconductor layer < a doped shielding layer (ABS) comprising GaAs is epitaxially formed, wherein the doping of the shielding layer (ABS) is higher than the doping of the semiconductor layer (HLS) and the shielding layer (ABS) has a thickness at least 10 times less than the semiconductor layer (HLS), - a process step in which a plurality of masked first regions (Gl) are generated by means of a masking process, wherein at least a part of the first regions (Gl) are completely enclosed by strip-shaped maskless second regions (G2), wherein a vertical insulation layer (VIS) is generated in the second regions (G2) by one or more subsequent process steps, - a process step in which contacts (LK, VK) are formed on at least part of the first regions (Gl) in order to operate the semiconductor layer (HLS) in first regions as a Hall sensor, - a flat top surface of the semiconductor layer after the formation of the contacts (LK, VK), in an area comprising at least two adjacent first areas (Gl) electrically isolated from each other by second areas (G2), - provided that the aforementioned process steps are carried out in the specified order.
2. Method according to claim 1, characterized in that the semiconductor layer (HLS) and / or the shielding layer (ABS) and / or the insulating layer (IS) consists of GaAs.
3. Method according to claim 1 or claim 2, characterized in that in a process step a III-V cover layer (ADS) with the first lattice constant is epitaxially grown on the shielding layer (ABS), wherein the cover layer (ADS) is formed from a different material with a higher band gap than the shielding layer (ABS).
4. Method according to claim 3, characterized in that the cover layer has a bottom surface formed on the shielding layer (ABS) and a top surface opposite the bottom surface, and delta doping is formed on the bottom surface and / or on the top surface to reduce contact barriers.
5. Method according to one of the preceding claims, characterized in that the shielding layer (ABS) is formed with the first lattice constant and the band gap of the semiconductor layer (HLS).
6. Method according to one of the preceding claims, characterized in that the vertical insulation layer (VIS) is formed in the second regions (G2) up to the insulation layer (IS).
7. Method according to one of the preceding claims, characterized in that the vertical isolation layer (VIS) is produced by means of hydrogen implantation and the mask is removed after implantation on the first areas, or the vertical isolation layer (VIS) is produced by a trenching process, wherein, in each case, after the formation of the vertical isolation layer (VIS), a planar surface is present in an area comprising at least several of the first areas (Gl) and at least one or more of the second areas (G2).
8. Method according to one of the preceding claims, characterized in that a p / n junction is generated for the formation of the insulation layer (IS) and / or the insulation layer (IS) is formed from a III-V material with a second band gap, wherein the second band gap is larger than the first band gap.
9. Method according to claim 8, characterized in that the two sublayers are grown by means of the epitaxy process in a lattice-adapted manner to the lattice constant of the substrate (SUB), wherein the n-doped sublayer has a higher doping concentration than the semiconductor layer (HLS).
10. Method according to one of the preceding claims, characterized in that in an epitaxial process step at least one n-doped III-V contact layer (KS1, KS2) is formed on the cover layer (ADS) or on the shielding layer (ABS) in order to form a low-resistance electrical connection with the cover layer (ADS) or with the shielding layer (ABS) after the formation of metallic connection contacts (LK, VK).
11. Method according to claim 10, characterized in that, during the formation of the metallic connection contacts (LK, VK), the contact layer (KS1, KS2) is removed in the contact-free areas, so that the contact layer (KS1, KS2) is formed exclusively between the cover layer (ADS) and the connection contacts (LK, VK).
12. A method according to any of the preceding claims, characterized in that at least one first geometric embodiment and a second geometric embodiment are formed as first regions (Gl) and the first regions are isolated from each other by means of a second region (G2).
13. A method according to claim 12, characterized in that the first embodiment is formed in a top view of the semiconductor surface as a square, rectangular, cruciform, or octagonal area for forming a lateral Hall sensor (LH), and the second embodiment is formed for forming a vertical Hall sensor (VH) in a rectangular, double-axe, or butterfly-shaped configuration.
14. Method according to claim 12 or claim 13, characterized in that in the first embodiment exactly four or exactly eight connection contacts (LK) are formed and in the second embodiment exactly three connection contacts (VK) or exactly four or exactly five or exactly six or exactly seven connection contacts (VK) are formed.
15. Method according to one of claims 12 to 14, characterized in that several first regions (Gl) of the second embodiment are directly adjacent to each other, wherein the first regions (Gl) are each isolated from each other by means of a second region (G2).
16. Method according to one of claims 12 to 15, characterized in that a first area (Gl) of the second embodiment is formed on each of two sides of the first embodiment, wherein the two first areas (Gl) of the second embodiment are arranged orthogonally to each other in order to form a 3D Hall sensor in the form of a pixel cell (PZ) in order to detect a Z-component of a magnetic field with the first area (Gl) of the first embodiment and to detect an X-component and a Y-component of the magnetic field with the two first areas (Gl) of the second embodiment.
17. Method according to one of claims 12 to 16, characterized in that first areas (Gl) of the second embodiment are formed around a central first area (Gl) of the first embodiment to form a 3D Hall sensor.
18. Method according to one of the preceding claims, characterized in that at least a part of the second areas (G2) are designed as guard rings.