Gaas hall sensor

Abstract

The invention relates to a III-V Hall sensor having a GaAs semiconductor wafer, wherein a III-V insulation layer (IS) is formed on the substrate (SUB); a semiconductor layer (HLS) which comprises GaAs and has an n-doping is provided on the insulation layer; an n-doped shielding layer (ABS) which comprises GaAs is integrally bonded to the semiconductor layer, the doping of the shielding layer being higher than the doping of the semiconductor layer; a plurality of first regions (G1) and second regions (G2) are formed, at least some of the first regions being completely enclosed by strip-shaped second regions, and a vertical insulation layer (VIS) being formed in the second regions; and metal contacts (LK, VK) are provided at least on some of the first regions in order to provide the semiconductor layer in the first region as a Hall sensor.

Description

[0001] GaAs Hall sensor

[0002] A vertical III-V Hall sensor is known from DE 10 2023 002 342 Al. This vertical III-V Hall sensor comprises an insulating layer on a GaAs substrate, a GaAs semiconductor layer arranged on the insulating layer, and a second insulating layer formed on the semiconductor layer and interrupted by electrical contact areas. The second insulating layer is formed, among other things, from an InGaP compound. Furthermore, the vertical III-V Hall sensor has circumferential insulation, which is implemented, among other things, by hydrogen implantation.

[0003] Furthermore, various III-V Hall sensors for measuring the three components of a magnetic field are known from CN 102 520 376 A. For measuring magnetic fields parallel to a substrate surface, a column-shaped Hall sensor structure arranged perpendicular to the substrate surface is disclosed. The column-shaped structure is contacted, among other things, at its two end faces.

[0004] Other generic III-V Hall sensors are known from EP 0 204 135 Al, CN 102 244 234 B, DE 10 2011 002580 Al and CN 105 261 698 A.

[0005] Against this background, the object of the invention is to provide a III-V Hall sensor that advances the state of the art.

[0006] The problem is solved by a III-V Hall sensor with the features of claim 1. Advantageous embodiments of the invention are the subject of dependent claims. According to the subject matter of the invention, a III-V Hall sensor is provided.

[0007] The III-V Hall sensor has a semiconductor disk made of GaAs as a substrate, with a top and a bottom surface, and a first lattice constant and a first band gap.

[0008] In a further training, the semiconductor wafer has a diameter of 100 mm, 150 mm, or 200 mm or larger. The semiconductor wafer has a thickness of at least 100 pm.

[0009] A III-V insulating layer with the first lattice constant is formed on the top side of the GaAs substrate.

[0010] A semiconductor layer comprising GaAs with the first lattice constant is formed on the insulating layer.

[0011] An n-doped GaAs shielding layer is arranged on the semiconductor layer and metallurgically bonded to the semiconductor layer.

[0012] The doping of the shielding layer is more extensive than that of the semiconductor layer. Furthermore, the shielding layer is at least ten times thinner than the semiconductor layer.

[0013] Furthermore, a multitude of first regions are formed, with the first regions being completely enclosed by strip-shaped second regions.

[0014] In the second areas, a vertical insulation layer is formed.

[0015] Metallic contacts are formed on at least some of the first areas to create a Hall sensor.

[0016] After the formation of contacts in one area, the semiconductor layer has a flat top surface, the area comprising at least two adjacent first areas electrically isolated from each other by the second area.

[0017] It should be noted that the terms contacts, connection contacts, metallic contacts and metal contacts are used synonymously below.

[0018] One advantage of the III-V Hall sensor is that, surprisingly, the electrical properties of the Hall sensors formed in the first regions are improved by the formation of a shielding layer. Because the shielding layer is very thin compared to the semiconductor layer, an operating current imposed by the contacts flows almost completely or exclusively through the semiconductor layer.

[0019] Another advantage is that the formation of a planar surface allows the Hall sensors to be electrically contacted in a simple and reliable way even after insulation.

[0020] It is understood that epitaxial techniques such as MOVPE, LPE, or MBE are used to form the III-V layers or the GaAs-encompassing or GaAs-containing layers. It is understood that the aforementioned III-V layers are of monolithic origin.

[0021] Furthermore, it is understood that mask processes are used for the training of first and second areas, and in particular that the first areas are at least temporarily covered with a mask during the training of the second areas.

[0022] It should be noted that the MOVPE process using metalloorganic precursors is currently predominantly used in the epitaxial fabrication of GaAs layers.

[0023] It should also be noted that, unlike silicon technology, doping of GaAs layers occurs inherently during the manufacturing process. Implantation of dopants followed by activation through temperature steps such as RTA or furnace processes is only feasible to a limited extent with GaAs, due in part to its decomposition temperature of approximately 700 °C.

[0024] Furthermore, passivation of GaAs by means of oxidation of the semiconductor material is also only feasible to a limited extent, unlike silicon technology.

[0025] In summary, it should be noted that the production of components in the field of GaAs is not compatible with and not comparable to the production of components in the field of silicon technology.

[0026] In another training course, the semiconductor layer exhibits a doping concentration in a range between l»10 14 1 / cm 3 and 5*10 17 1 / cm 3 or in a range between 5*10 14 1 / cm 3 and l*10 16 1 / cm 3 or in a range between l*10 15 1 / cm 3 and 5*10 15 1 / cm 3 on.

[0027] It is understood that, in order to achieve the highest possible mobility, the doping of the III-V semiconductor layer should be in a range below 1*10 over a predominant part of the thickness. 16 1 / cm 3 It should be located there.

[0028] In another embodiment, the semiconductor layer is homogeneously doped. In one embodiment, the semiconductor layer has a doping concentration of 2 × 10⁻⁵. 15 1 / cm 3 on.

[0029] In one embodiment, the semiconductor layer has a thickness in the range of 0.5 pm to 15 pm, or a thickness in the range of 1.0 pm to 8 pm, or a thickness in the range of 2.0 pm to 5 pm. In a further embodiment, the semiconductor layer consists of GaAs. In another embodiment, the shielding layer and / or the insulating layer consists of GaAs.

[0030] In a further development, the shielding layer exhibits the first lattice constant and the first band gap.

[0031] In one embodiment, the shielding layer has a doping concentration 10 times higher than that of the semiconductor layer, or a doping concentration in a range between 5*10 16 1 / cm 3 and l*10 18 1 / cm 3or doping in a range between l*10 17 1 / cm 3 and 5*10 17 1 / cm 3 on.

[0032] In another embodiment, the shielding layer has a thickness in a range between 20 nm and 200 nm, or a thickness in a range between 50 nm and 100 nm, or a thickness in a range between 65 nm and 75 nm.

[0033] In another further development, a III-V cover layer is metallurgically bonded to the shielding layer. The III-V cover layer has the first lattice constant. The III-V cover layer has a material with a larger band gap than the semiconductor layer.

[0034] In one embodiment, the covering layer has a thickness in a range between 3 nm and 50 nm or a thickness in a range between 5 nm and 15 nm.

[0035] In another embodiment, the cover layer has n-doping in a range between 5*10 17 1 / cm 3 and 5*10 19 1 / cm 3 or in a range between l*10 18 1 / cm 3 and l*10 19 1 / cm 3 on.

[0036] In one further development, the cover layer comprises or consists of an InGaP compound. In another further development, the thickness of the cover layer is less pronounced in the areas between the Meta II contacts than in the areas below the metal contacts.

[0037] In another further development, the cover layer has a bottom surface formed on the shielding layer and a top surface opposite the bottom surface, with delta doping being formed on the bottom surface and / or on the top surface to reduce contact barriers.

[0038] One advantage of delta doping is that the conductivity at the contact layer is metallic, i.e., very low resistance. In other words, the Fermi level lies within the conduction band.

[0039] In a further training course, delta doping with Si is performed during the growth of the layers in epitaxy.

[0040] For example, in a MOVPE system for the formation of a Si delta doping, a corresponding precursor is briefly switched on and off again.

[0041] In another advanced training course, the mask, which was trained in the first areas, has several layers made of different materials.

[0042] In one embodiment, an organic photoresist is applied to the surface of the semiconductor disk during the masking process, i.e., to the surface of the last epitaxially applied semiconductor layer.

[0043] In another embodiment, a SiN layer is formed before the application of the organic photoresist, preferably by means of a PECVD or PVD process, to protect the surface from contamination by the photoresist. In a subsequent process step, the photoresist is then applied over the entire surface and either directly structured or coated with a metal layer before structuring and then structured.

[0044] It should be noted that the second areas do not have a mask to form the vertical isolation layer.

[0045] In a further development, the vertical insulation layer in the second regions extends down to the insulation layer. In other words, the formation of the vertical insulation layer occurs as a continuous, full-surface vertical layer from the semiconductor surface down to the first insulation layer.

[0046] In conjunction with the insulating layer, the enclosed adjacent first regions are completely electrically isolated from each other. It is understood that the insulating layer also insulates the first regions from the substrate.

[0047] In further training, the second areas have a width between 1.0 pm and 50 pm or a width between 2 pm and 5 pm.

[0048] In another further development, the vertical insulating layer extends from the top of the semiconductor layer, or the semiconductor surface itself, beyond the insulating layer, i.e., into the substrate. This results in particularly reliable electrical insulation between adjacent first regions.

[0049] In one embodiment, the vertical insulation layer is created by means of hydrogen implantation or by a trenching process.

[0050] In this case, after the formation of the vertical insulation layer, a planar surface is present in a region comprising at least several of the first regions and at least one or more of the second regions. In another embodiment, the insulation layer comprises two partial layers with a p / n transition and / or the insulation layer consists of a III-V material with a second band gap, wherein the second band gap is larger than the first band gap.

[0051] In a further development, the insulating layer has a GaAs-comprising p-doped sublayer and a GaAs-comprising n-doped sublayer, wherein the p-doped sublayer is metallurgically bonded to the substrate and the n-doped sublayer is metallurgically bonded to the semiconductor layer.

[0052] In another further development, the two sublayers have the first grid constant, with the n-doped sublayer having a higher doping concentration than the semiconductor layer.

[0053] In another training course, the p-doped sublayer exhibits a doping level in a range between l*10 14 1 / cm 3 and l*10 16 1 / cm 3 or doping in a range between l*10 15 1 / cm 3 and 8*10 15 1 / cm 3 on and the n-doped sublayer a doping in a range between l*10 15 1 / cm 3 and l*10 17 1 / cm 3 or a doping level in a range between 8*10 15 1 / cm 3 and 5*10 17 1 / cm 3 on.

[0054] In one embodiment, the p-doped sublayer has a thickness in a range between 50 nm and 2.0 pm or a thickness in a range between 100 nm and 800 nm, and the n-doped sublayer has a thickness between 10 nm and 300 nm or a thickness in a range between 30 nm and 100 nm.

[0055] In another embodiment, at least one n-doped III-V contact layer is formed on the cover layer in order to form a low-resistance electrical connection with the cover layer after the formation of metallic connection contacts.

[0056] In a further development, the contact layer is removed in the areas not covered by metallic connection contacts, so that the contact layer is formed exclusively between the covering layer and the connection contacts.

[0057] In another advanced design, the contact layer has the first lattice constant and / or the contact layer has the same band gap as the semiconductor layer.

[0058] In one embodiment, the contact layer comprises an n-doped GaAs layer and / or an n-doped InGaAs layer, or the contact layer consists of an n-doped GaAs layer and / or an n-doped InGaAs layer.

[0059] In this further development, the contact layer comprises a first GaAs sublayer and a second InGaAs sublayer. The two sublayers are metallurgically bonded to each other. The first sublayer is also metallurgically bonded to the shielding layer or the cover layer.

[0060] The second sublayer is metallurgically bonded to the metal contact. It is understood that both sublayers are formed exclusively below the metal contacts to prevent a short circuit in the semiconductor layer.

[0061] In one embodiment, the contact layer has a total thickness in a range between 10 nm and 150 nm or in a range between 30 nm and 100 nm.

[0062] In another embodiment, the doping of the contact layer is located above l*10 18 1 / cm 3 or above 5*10 18 1 / cm 3 or above l*10 19 1 / cm 3 .

[0063] In a further embodiment, the first areas comprise at least a first geometric embodiment and a second geometric embodiment, wherein the two embodiments of the first areas are electrically isolated from each other by means of a second area. In another further embodiment, the first embodiment, in a top view of the semiconductor surface, has a rectangular, square, cross-shaped, or octagonal area for forming a lateral Hall sensor. The second embodiment has a rectangular, double-axe-shaped, or butterfly-shaped area for forming a vertical Hall sensor.

[0064] In a further development, in the first embodiment exactly four or exactly eight connection contacts are formed, and in the second embodiment exactly three connection contacts or exactly four or exactly five or exactly six or exactly seven connection contacts are formed.

[0065] In another further development, several first areas of the second embodiment are directly adjacent to each other, with each first area being isolated from the others by means of a second area.

[0066] In one embodiment, a first area of ​​the second embodiment is formed on each of two sides of the first embodiment, wherein the two first areas of the second embodiment are arranged orthogonally to each other in order to form a 3D Hall sensor in the form of a pixel cell.

[0067] In this case, the first embodiment allows the detection of a Z-component of a magnetic field, and the first two regions of the second embodiment allow the detection of an X-component and a Y-component of the magnetic field.

[0068] It should be noted that a magnetic field component formed orthogonally on the semiconductor surface is called the Z-component, and two components that are orthogonally aligned with each other and run in the plane of the semiconductor surface are called X- and Y-components, respectively.

[0069] In a further development, first areas of the second embodiment are formed around a central first area of ​​the first embodiment on at least two sides or around all sides in order to form a 3D Hall sensor as a so-called pixel cell.

[0070] In another advanced training course, at least part of the second area is designed as a guard ring. This involves creating trenches, for example, using a trenching process, and after forming sidewall insulation by filling with a conductive material and creating electrical contacts, the trenches are electrically connected.

[0071] The invention is explained in more detail below with reference to the drawings. Similar parts are labelled with identical designations. The illustrated embodiments are highly schematic; that is, the distances and the lateral and vertical extents are not to scale and, unless otherwise indicated, do not exhibit any derivable geometric relationships to one another. In these drawings, the

[0072] Figures aa-c show cross-sectional views of manufacturing stages for the formation of a first embodiment of a Hall sensor.

[0073] Figure 2 shows a cross-sectional view of a second embodiment of a Hall sensor.

[0074] Figure 3 shows a top view of a semiconductor disk with lateral Hall sensors.

[0075] Figures 4a-c Top views of different embodiments of lateral Hall sensors,

[0076] Figure 5a-d Top views of different embodiments of vertical Hall sensors,

[0077] Figures 6a-d Top views of different embodiments of

[0078] Pixel cells, Figure 7 a cross-sectional view of a pixel cell of an embodiment of Fig. 6d.

[0079] Figures 1a-c show cross-sectional views of manufacturing stages for the production of a first embodiment of a GaAs Hall sensor. For clarity, a Cartesian coordinate system is shown. Accordingly, the cross-sections are formed in an XZ plane.

[0080] According to the illustration in Figure 1a, a III-V insulation layer IS is produced on a semiconductor disk formed as a GaAs substrate SUB with a top surface OS and a bottom surface US in one process step on the top surface OS of the GaAs substrate SUB by means of an epitaxy process.

[0081] The substrate SUB has a first lattice constant and a first band gap. The III-V insulating layer IS is grown on the substrate with the first lattice constant. The substrate is designed as a semi-insulated GaAs semiconductor wafer.

[0082] In a further process step, an n-doped GaAs semiconductor layer HLS with the first lattice constant is grown on the insulation layer IS using the epitaxy method.

[0083] In a subsequent process step, an n-doped GaAs shielding layer ABS is epitaxially formed on the semiconductor layer HLS, wherein the doping of the shielding layer ABS is greater than the doping of the semiconductor layer HLS.

[0084] The ABS shielding layer has the same lattice constant as the HLS semiconductor layer and a layer thickness that is at least 10 times smaller than the HLS semiconductor layer.

[0085] According to the illustration in Figure 1b, in a subsequent process step a multitude of masked first regions Gl and second unmasked regions G2 are generated by means of a masking process. The first regions Gl are completely enclosed by the strip-shaped, unmasked second regions G2.

[0086] In subsequent process steps, a vertical insulation layer VIS is created in the second areas.

[0087] In a process step not shown, the mask is removed from the first areas Gl. In other words, in a top view not shown, the top surface of the semiconductor wafer is free of resist and flat.

[0088] According to the illustration in Figure 1c, several metal contacts LK are formed on the first area Gl to form the semiconductor layer HLS in the first area Gl as a Hall sensor.

[0089] The semiconductor disk is flat on the top side of the ABS shielding layer after the formation of the contacts LK. In other words, an area comprising first regions G1, which are configured as Hall sensor regions, and second region G2, which are configured as vertical insulation regions, has no steps on the top side of the ABS shielding layer.

[0090] Figure 2 shows a cross-sectional view of a second embodiment of a Hall sensor. The differences from the first embodiment, illustrated in conjunction with Figure 1c, are explained below.

[0091] A thin InGaP cover layer ADS is formed on the upper surface of the ABS shielding layer, the cover layer ADS having a first grid constant. The vertical insulating layer VIS also penetrates the InGaP cover layer ABS.

[0092] Below the contacts LK, a first contact layer KS1 consisting of n-doped GaAs is formed on the upper side of the cover layer ADS. The first contact layer KS1 has a doping concentration of more than 1*10 17 1 / cm 3 Between the first contact layer KS1 and the underside of the contacts LK, a second n-doped contact layer KS2 with the first lattice constant is formed. Preferably, the second contact layer KS2 has a doping concentration above 5 × 10⁻⁶. 18 1 / cm 3 up and is trained from InGaAs.

[0093] The insulating layer IS has a p-doped GaAs sublayer IST1 and an n-doped GaAs sublayer IST2. This creates a p / n junction between the two sublayers, electrically isolating the semiconductor layer HLS from the substrate.

[0094] The p-doped GaAs sublayer IST1 is formed between the substrate SUB and the n-doped sublayer IST2. The n-doped sublayer IST2 is formed between the p-doped sublayer IST1 and the semiconductor layer HLS.

[0095] In an embodiment not shown, the vertical insulating layer VIS penetrates the two sublayers IST1 and IST2 and extends into the substrate SUB.

[0096] Figure 3 shows a top view of a semiconductor disk arranged in the XY plane with a plurality of Hall sensors. The following explains only the differences from the embodiments shown in conjunction with Figure 1c or Figure 2.

[0097] The Hall sensors formed in the first regions Gl are designed as lateral Hall sensors LH, in the form of so-called Hall plates. The individual lateral Hall sensors LH have a square geometry. Metal contacts LK are formed at the respective edges in the corners.

[0098] Each of the lateral Hall sensors LH is completely enclosed by a second area G2.

[0099] For clarity, the conductor tracks for connecting the metal contacts are not shown. Figures 4a-c show top views of different embodiments of individual lateral Hall sensors LH configured in the XY plane. Only the differences compared to the embodiments shown in Figure 3 are explained below.

[0100] Figure 4a shows a detailed representation of the square embodiment of the lateral Hall sensor LH of Figure 3. For the sake of clarity, a representation of the second areas is not shown.

[0101] The four Meta II contacts (LK) are symmetrically arranged at the four corners of the reverberation plate. It follows that the reverberation plate can detect a magnetic field component oriented in the Z-direction.

[0102] Figure 4b shows a cross-shaped configuration of a lateral Hall sensor LH. The respective Meta II contacts LK are located at the cross-shaped ends. It is understood that the individual branches of the cross-shaped configuration are symmetrical to each other.

[0103] Figure 4c shows an octagonal configuration of a lateral Hall sensor LH. The respective Meta II contacts LK are located at the octagonal ends. It is understood that the individual branches of the octagonal configuration are symmetrical to each other.

[0104] In an embodiment not shown here, figures 4a and 4b are rotated by 45° in the xy plane about the z-axis.

[0105] Figures 5a-d show top views of different embodiments of individual vertical Hall sensors VH configured in the XY plane. In each of the illustrated embodiments, a magnetic field configured in the Y direction can be detected using the vertical Hall sensors VH. Only the differences from the preceding embodiments are explained below. Figure 5a shows a top view of a rectangular embodiment of a vertical Hall sensor VH. For clarity, a representation of the second region is not shown.

[0106] The vertical Hall sensor VH has three Meta II contacts VK of equal length in the Y direction. The middle metal contact VK is spaced a distance al from each of the two outer Meta II contacts VK in the X direction.

[0107] In an embodiment not shown, the two outer contacts VK extend to the edge of the first region Gl or beyond.

[0108] Figure 5b shows another double-axe-shaped embodiment of a vertical Hall sensor VH. Only the differences from the embodiment shown in Figure 5a are explained below.

[0109] The two outer metal contacts VK are of equal width in the Y-direction and significantly wider than the middle metal contact VK. All three Meta II contacts VK have a rectangular shape in the top view shown.

[0110] The first region Gl exhibits mirror symmetry with respect to a mirror axis running in the Y direction through a center of the central metal contact VK.

[0111] Figure 5c shows a butterfly-shaped extension with two wings, with a mirror axis extending in the Y direction passing through the center of the central metal contact VK.

[0112] The two wings are each crescent-shaped. In other words, the outer edge of the area Gl does not have straight lines, but is formed by arc-shaped segments. The two outer metal I contacts VK, unlike the central metal contact VK, are not rectangular, but circular segments.

[0113] Figure 5d shows another embodiment of a vertical Hall sensor VH. Only the differences from the embodiment shown in Figure 5a are explained below.

[0114] Four first regions Gl are arranged in a row in the X direction, each containing a vertical partial Hall sensor VHT with three metal contacts VK. The four first regions Gl are separated from each other by second regions G2 and are also completely enclosed by the second regions G2.

[0115] By connecting the outer Meta II contacts VK of adjacent vertical Hall sensors VH to each other, the entire structure forms a vertical Hall sensor VH, consisting of four partial Hall sensors VHT, with four middle Meta II contacts VK.

[0116] Figures 6a-d show top views of different embodiments of pixel cells PZ. The term pixel cell PZ refers to an extremely compact arrangement of Hall sensors capable of detecting various components, at least two, of a magnetic field at nearly the same location. Only the differences from the preceding embodiments are explained below.

[0117] Figure 6a shows a 2D pixel cell PZ, having a lateral Hall sensor LH in a square shape with a vertical Hall sensor VH on one side of the square.

[0118] It is understood that the two Hall sensors LH and VH are each arranged in a first region. With the illustrated embodiment, the Z-component and the X-component of a magnetic field can be detected.

[0119] Figure 6b shows a 3D pixel cell PZ comprising a lateral Hall sensor LH in a square configuration with vertical Hall sensors VH arranged on two adjacent sides of the square. The illustrated embodiment allows the detection of the Z-component and the X and Y components of a magnetic field.

[0120] Figure 6c shows a 3D pixel cell PZ, comprising a lateral Hall sensor LH in a square shape in the middle with vertical Hall sensors VH arranged on all sides of the square.

[0121] Figure 6d shows a 3D pixel cell PZ, comprising a lateral Hall sensor LH in a cross-shaped configuration in the center with vertical Hall sensors VH arranged on all side branches. A section line A-A' is indicated.

[0122] Figure 7 shows a cross-sectional view along the section line AA' of the 3D pixel cell of the embodiment of Fig. 6d, with reference to the structure shown in Figure 2.

[0123] It turns out that in the first regions Gl either a vertical Hall sensor VH or a lateral Hall sensor LH is formed.

[0124] The lateral Hall sensor LH is surrounded at both ends by the vertical Hall sensors VH.

Claims

Patent claims 1. III-V Hall sensor, comprising - a semiconductor disk made of GaAs formed as a substrate (SUB) with a top side (SS) and a bottom side (SUS) and a first lattice constant and a first band gap, - a III-V insulating layer (IS) formed on the top side of the GaAs substrate (SUB) and having the first lattice constant, - a GaAs-comprising semiconductor layer (HLS) arranged on the insulating layer (IS) with the first lattice constant and an n-doping, characterized by the fact that - an n-doped GaAs shielding layer (ABS) is formed on the semiconductor layer (HLS), wherein the doping of the shielding layer (ABS) is higher than the doping of the semiconductor layer (HLS) and the shielding layer (ABS) has a thickness at least 10 times less than the semiconductor layer (HLS), - a multitude of first regions (Gl) are formed, wherein the first regions (Gl) are completely enclosed by strip-shaped second regions (G2) and a vertical insulation layer (VIS) is formed in the second regions (G2), - metallic contacts (LK, VK) are formed on at least part of the first regions (Gl) to form a Hall sensor, - the semiconductor layer (HLS) after the formation of the contacts (LK, VK) has a flat top surface in one region, wherein the region comprises at least two adjacent first regions (Gl) electrically isolated from each other by the second region (G2).

2. III-V Hall sensor according to claim 1, characterized in that the semiconductor layer (HLS) and / or the shielding layer (ABS) and / or the insulating layer (IS) consists of GaAs.

3. III-V Hall sensor according to claim 1 or claim 2, characterized in that a III-V cover layer (ADS) with the first grating constant is epitaxially formed on the shielding layer (ABS), wherein the cover layer (ADS) consists of a different material with a higher band gap than the shielding layer (ABS).

4. III-V Hall sensor according to claim 3, characterized in that the cover layer (ADS) has a bottom surface formed on the shielding layer (ABS) and a top surface opposite the bottom surface and a delta doping is formed on the bottom surface and / or on the top surface for a reduction of contact barriers.

5. III-V Hall sensor according to one of the preceding claims, characterized in that the shielding layer (ABS) is formed with the first lattice constant and the band gap of the semiconductor layer (HLS).

6. III-V Hall sensor according to one of the preceding claims, characterized in that the vertical insulation layer (VIS) in the second regions (G2) extends to the insulation layer (IS).

7. III-V Hall sensor according to one of the preceding claims, characterized in that the vertical insulation layer (VIS) is produced by means of hydrogen implantation and / or the vertical insulation layer (VIS) comprises a trench, wherein after the formation of the vertical insulation layer (VIS) a planar surface is formed in a region comprising at least several of the first areas (Gl) and at least one or more of the second areas (G2).

8. III-V Hall sensor according to one of the preceding claims, characterized in that the insulation layer (IS) comprises two sublayers (IST1, IST2) with a p / n junction and / or the insulation layer (IS) consists of a III-V material with a second band gap, wherein the second band gap is larger than the first band gap.

9. III-V Hall sensor according to claim 8, characterized in that the two sublayers (IST1, IST2) are lattice-adapted to the lattice constant of the substrate (SUB), wherein the n-doped sublayer (IST2) has a higher doping than the semiconductor layer (HLS).

10. III-V Hall sensor according to one of the preceding claims, characterized in that at least one n-doped III-V contact layer (KS1, KS2) is formed on the cover layer (ADS) in order to form a low-resistance electrical connection with the cover layer (ADS) after forming metallic connection contacts (LK, VK).

11. III-V Hall sensor according to claim 10, characterized in that after the formation of the metallic connection contacts (LK, VK) the contact layer (KS1, KS2) is formed exclusively between the cover layer (ADS) and the connection contacts (LK, VK).

12. III-V Hall sensor according to one of the preceding claims, characterized in that the first regions (Gl) comprise at least a first geometric embodiment and a second geometric embodiment and the first regions (Gl) are each electrically isolated from each other by means of a second region (G2).

13. III-V Hall sensor according to claim 12, characterized in that the first embodiment for forming a lateral Hall sensor (LH) in a top view of the semiconductor surface comprises a rectangular or a square or a cross-shaped or an octagonal area and the second embodiment for forming a vertical Hall sensor (VH) comprises a rectangular or a double-axe-shaped or a butterfly-shaped design.

14. III-V Hall sensor according to claim 12 or claim 13, characterized in that in the first embodiment exactly four or exactly eight connection contacts (LK) are formed and in the second embodiment exactly three connection contacts (VK) or exactly four or exactly five or exactly six or exactly seven connection contacts (VK) are formed.

15. III-V Hall sensor according to one of claims 12 to 14, characterized in that several first regions (Gl) of the second embodiment are directly adjacent to each other, wherein the first regions (Gl) are each isolated from each other by means of a second region (G2).

16. III-V Hall sensor according to one of claims 12 to 15, characterized in that on two sides of a first area (Gl) of the first embodiment a first area (Gl) of the second embodiment is formed, wherein the two first areas (Gl) of the second embodiment are arranged orthogonally to each other in order to form a 3D Hall sensor in the form of a pixel cell (PZ) in order to detect a Z-component of a magnetic field with the first area (Gl) of the first embodiment and to detect an X-component and a Y-component of the magnetic field with the two first areas (Gl) of the second embodiment.

17. III-V Hall sensor according to one of claims 12 to 16, characterized in that first areas (Gl) of the second embodiment are formed around a central first area (Gl) of the first embodiment to form a 3D Hall sensor.

18. III-V Hall sensor according to one of the preceding claims, characterized in that at least a part of the second areas (G2) are designed as guard rings.

Images