Double soi substrate qubit device provided with buried charge-providing structure
Patent Information
- Application Number
- PCT/EP2026/057252
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-19
- Filing Date
- 2026-03-16
- Publication Date
- 2026-09-24
Smart Images
Figure EP2026057252_24092026_PF_FP_ABST
Abstract
Description
[0001] DESCRIPTION
[0002] TITLE: Buried Charge Carrier Reservoir Quantum Device
[0003] TECHNICAL FIELD
[0004] The field of the invention is that of quantum electronics. The invention relates in particular to a quantum device with spin qubits, enabling the filling of quantum dots with charge carriers.
[0005] PREVIOUS TECHNIQUE
[0006] The manipulation of quantum states, also called "qubits" (short for "quantum bits"), offers new possibilities in information manipulation. Quantum electronic circuits capable of manipulating qubits include islands, also called quantum dots, which can store qubits for the duration of their manipulation and measurement.
[0007] Quantum dots are typically formed in a layer of semiconductor material in which potential wells are implemented to confine carriers, electrons or holes, in the three dimensions of space. Quantum information is then encoded via the spin of the carrier.
[0008] In particular, electrons can be confined by field effect under gate electrodes similar to those in transistor structures. These so-called "front" gates are arranged above the set of quantum dots.
[0009] A spin qubit quantum device may include a matrix array of quantum dots and a set of grids to adjust the filling of the dots and the tunneling coupling between adjacent dots.
[0010] Such a network comprises an active level in which a semiconductor channel extends between charge carrier reservoirs forming the channel ends. These reservoirs are called source and drain by analogy with MOSFET technology. Front gates are positioned on the active level to confine charge carriers to specific portions of the channel, thus forming quantum dots. As described in [1], filling a quantum dot can be achieved by following a protocol for manipulating the state of the front gates. This filling involves transporting a charge carrier from one dot to another from one of the charge carrier reservoirs (e.g., from the source in the case of an electron). Such a protocol proves relatively complex to implement. Furthermore, because this protocol requires a number of operations, the filling process is quite slow.Furthermore, this filling technique, which requires all the dots to be perfect to ensure the transport of the charge carrier from dot to dot, is sensitive to defects. These difficulties are exacerbated when considering dense quantum dot arrays where the quantum dots can be quite far from the charge carrier reservoirs.
[0011] [1] presents a charge carrier transfer sequence for a 1D lattice of 9 boxes. While this approach may be suitable for small lattices, it is unlikely to be applicable to larger lattices for the reasons explained above.
[0012] DESCRIPTION OF THE INVENTION
[0013] The invention aims to provide a quantum dot filling technique that overcomes the aforementioned drawbacks and is capable of being used in large networks.
[0014] To this end, the invention relates to a spin qubit quantum device, comprising a component formed of quantum dots which extend into an active level and of control front grids of the quantum dots arranged on the active level, characterized in that it further comprises a charge carrier conduction channel, the charge carrier conduction channel being buried below the active level and separated from it by a charge carrier tunneling layer.
[0015] Some preferred, but not exhaustive, aspects of this system are as follows:
[0016] - It is formed on a dual semiconductor-on-insulator substrate which comprises:
[0017] o a semiconductor support layer; o on the semiconductor support layer, a first insulating layer; o on the first insulating layer, a buried semiconductor layer in which the charge carrier conduction channel is formed; o on the buried semiconductor layer, a second insulating layer forming the charge carrier tunneling transport layer; o on the second insulating layer, a surface semiconductor layer in which a quantum confinement channel is formed that accommodates the quantum dots.
[0018] It also includes:
[0019] o a rear control grid arranged on a rear face of the semiconductor support layer;
[0020] o a source region and a drain region arranged on either side of the component and between which the charge carrier conduction channel extends;
[0021] o the charge carrier conduction channel, the back control gate and the source and drain regions forming a buried transistor. The buried semiconductor layer has a thickness between 5 and 15 nm;
[0022] the second insulating layer has a thickness of between 1 and 2 nm; it also includes a grid oxide layer interposed between the active level and each of the front grids;
[0023] the first insulating layer and the grid oxide layer each have a thickness greater than 15 nm, for example a thickness between 20 and 25 nm.
[0024] The invention also relates to a method for controlling such a quantum device, comprising:
[0025] - control of the rear grid so as to populate the conduction channel with charge carriers;
[0026] - control of one of the front gates so as to cause the transport of one or more charge carriers into a quantum dot from the charge carrier conduction channel via the charge carrier tunneling layer.
[0027] The invention further relates to a method for manufacturing such a quantum device with spin qubits, comprising:
[0028] - the transfer of a surface semiconductor layer onto a semiconductor-on-insulator substrate, an insulating layer being at the interface between the semiconductor substrate and the surface semiconductor layer;
[0029] - a thinning annealing of the insulating layer;
[0030] - the formation of a component made up of quantum dots that extend into the surface semiconductor layer and front control grids of the quantum dots arranged on the surface semiconductor layer.
[0031] This manufacturing process may also include training:
[0032] - a back grid on a back face of the semiconductor-on-insulator substrate; - source and drain regions arranged on either side of the component and between which extends a charge carrier conduction channel formed in the semiconductor layer of the semiconductor-on-insulator substrate.
[0033] BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Other aspects, objectives, advantages, and features of the invention will become clearer upon reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the accompanying drawings in which:
[0035] - Figure 1 is a diagram of a quantum device according to the invention;
[0036] - Figure 2 is a diagram that illustrates a possible implementation of a manufacturing process for a quantum device according to the invention.
[0037] DETAILED DESCRIPTION OF SPECIFIC METHODS OF IMPLEMENTATION
[0038] With reference to Figure 1, the invention relates to a spin-1 qubit quantum device. The quantum device 1 comprises a component formed of quantum dots extending into an active level and FG1-FG6 front gates for controlling the quantum dots. The active level includes a semiconductor channel 2, referred to as a quantum confinement channel, configured to house one or more charge carriers exhibiting spin. The active level also includes isolation trenches T1, T2 on the flanks of the quantum confinement channel 2. The FG1-FG6 front gates are arranged on the active level, with a gate oxide layer 3 typically interposed between the active level and each of the FG1-FG6 front gates.
[0039] According to the invention, the device 1 comprises a charge carrier conduction channel 4. The charge carrier conduction channel 4 is buried below the active level and separated from it by a tunneling charge carrier transport layer 5. The charge carriers can be electrons or holes.
[0040] According to the previous technique, charge carrier reservoirs form the ends of the semiconductor channel extending into the active level. Charge carriers are available to quantum dots directly adjacent to the reservoirs, and a forward gate state manipulation protocol must be implemented to transport the charge carriers to the quantum dots at the center of the 1D lattice.
[0041] According to the invention, a charge carrier conduction channel 4 extends below the active level. Charge carriers can thus be made available under each of the quantum dots formed in the active level, and the filling of each of the quantum dots can be carried out via the charge carrier transport layer by tunneling effect 5. Unlike the prior art, the charge carriers are easily accessible by each of the quantum dots, including those located at the center of a quantum dot array.
[0042] In one possible embodiment illustrated in Figure 1, the quantum device 1 is formed on a dual semiconductor-on-insulator substrate, for example, a dual silicon-on-insulator substrate. The dual semiconductor-on-insulator substrate comprises:
[0043] - a semiconductor support layer 6;
[0044] - on the semiconductor support layer 6, a first insulating layer 7;
[0045] - on the first insulating layer 7, a buried semiconducting layer in which the charge carrier conduction channel 4 is formed; - on the buried semiconducting layer, a second insulating layer forming the charge carrier transport layer by tunneling effect 5;
[0046] - on the second insulating layer 5, a superficial semiconductor layer in which the quantum confinement semiconductor channel 2 is formed.
[0047] The second insulating layer, forming the transport layer 5, is sufficiently thin to allow the transport of charge carriers by tunneling. This layer 5 preferably has a thickness between 1 and 2 nm.
[0048] Furthermore, the first insulating layer 7 and the grid oxide layer 3 are each thicker than the transport layer 5 to prevent any unwanted tunneling transport processes. Specifically, the first insulating layer 7 and the grid oxide layer 3 can each be thicker than 15 nm, for example, between 20 and 25 nm.
[0049] The buried semiconductor layer, for example, has a thickness of between 5 and 15nm.
[0050] As shown in Figure 1, this device 1 may further include a rear control grid BG disposed on a rear face of the semiconductor support layer 6.
[0051] Source and drain regions S, D can be arranged on either side of the component, particularly on either side of the isolation trenches T1, T2. The charge carrier conduction channel 4 formed in the buried semiconductor layer extends between the source and drain regions S, D. The source and drain regions S, D are semiconductor regions that have been treated to increase their doping. The source and drain regions S, D are N-doped and P-doped, respectively, depending on whether the charge carriers considered are electrons and holes, respectively.
[0052] In this configuration, the charge carrier conduction channel 4, the back control gate BG, and the drain source regions S and D together form a buried transistor. This buried transistor can be activated by the back control gate BG to direct charge carriers into the charge carrier conduction channel 4. The charge carrier density, electrons or holes, in the conduction channel 4 depends on the bias of the back control gate BG. This density can reach up to 10 12 carriers / cm 2 The charge carriers present in the conduction channel 4 are made available for transfer, by tunneling through the transport layer 5, to the upper active level and in particular to the quantum confinement channel 2. This tunneling effect is achieved when a front gate FG1-FG6 is controlled to form and fill the corresponding quantum box.
[0053] The invention also relates to a method for controlling quantum device 1, comprising:
[0054] - control of the rear grid BG so as to populate the buried conduction channel 4 with charge carriers;
[0055] - control of one of the front gates FG1-FG6 so as to cause the transport of one or more charge carriers into a quantum dot from the buried conduction channel 4 via the transport layer 5.
[0056] The invention thus enables the deterministic filling of quantum dots, based on the density of states formed under the front grids by the chemical potential imposed by the values applied to the front grids. Charge carriers can be easily loaded into the quantum dots using a structure that can be fabricated with existing FDSOI technology. This loading can be individualized at the scale of a quantum dot by manipulating the state of the corresponding front grid. Loading therefore requires fewer front grid state manipulation operations. This implies that loading is faster and does not disturb other quantum dots.
[0057] An example of the implementation of a manufacturing process for a quantum device according to the invention is as follows.
[0058] With reference to Figure 2, this process includes a step (A) of providing a semiconductor-on-insulator substrate comprising a semiconductor support 6, a first surface semiconductor layer 4 and a buried insulating layer 7 interposed between the semiconductor support 6 and the surface semiconductor layer 4. This process includes a step (B) of providing a semiconductor substrate 20 and a transfer, illustrated by steps (C) and (D) in Figure 2, of a second surface semiconductor layer 2 from the semiconductor substrate 20 to the semiconductor-on-insulator substrate, an insulating layer 30 being at the interface between the semiconductor-on-insulator substrate and the second surface semiconductor layer 2. A double semiconductor-on-insulator substrate is obtained at the end of step (D).
[0059] In one possible embodiment, this transfer is carried out according to the Smart Cut™ process and includes the formation of a weakening plane F by ion implantation within the thickness of the semiconductor substrate 20, the bonding in step (C) of the semiconductor substrate 20 and the semiconductor-on-insulator substrate, and the detachment in step (D) of the semiconductor substrate 20 along the weakening plane. This detachment, achieved by the application of mechanical and / or thermal energy, leads to the transfer of the second surface semiconductor layer 2 onto the semiconductor-on-insulator substrate.
[0060] The insulating layer 30, for example a SiCh layer, is present during bonding to one or both of the semiconductor substrate 20 and the semiconductor-on-insulator substrate. In the example in Figure 2, the insulating layer 30 covers the semiconductor substrate 20 in step (B). The insulating layer 30 typically has a thickness between 15 and 25 nm.
[0061] Following the postponement of step (D), the process involves applying a thinning anneal to the insulating layer 30 on the semiconductor-on-insulator substrate. This annealing results in a thinned insulating layer 3 of sufficient thickness to allow charge carrier transport by tunneling, for example, a thickness between 1 and 2 nm. This annealing is carried out, for example, for one hour at a temperature above 1150°C. Taking the example of a SiO2 insulating layer 30, this annealing process sublimates the dioxygen O2, leading to its thinning.
[0062] In one embodiment, this thinning is achieved locally by blocking the diffusion of dioxygen (O2) in specific regions of the double semiconductor-on-insulator substrate. This is accomplished by depositing a sacrificial oxide layer and then etching it locally using lithography. In regions where this sacrificial layer is present, the thinning process is blocked. Consequently, in these regions, the insulating layer 30 remains unthinned and retains its initial thickness. In regions where this thinning process is not blocked, a thinned insulating layer 3 is found. The process then involves the formation of a component composed of quantum dots extending into the surface semiconductor layer 2 and control grids for the quantum dots arranged on the surface semiconductor layer.
[0063] It may further include the formation of a back grid on a back face of the semiconductor-on-insulator substrate and the formation of source and drain regions arranged on either side of the component and between which extends a charge carrier conduction channel formed in the semiconductor layer 4 of the semiconductor-on-insulator substrate.
[0064] Bibliography
[0065] [1] Mills, AR, Zajac, DM, Gullans, MJ. et al. Shuttling a single charge across a one-dimensional array of silicon quantum dots. Nat Commun 10, 1063 (2019). https: / / doi.org / 10.1038 / s41467-019-08970-z
Claims
DEMANDS 1. Spin qubit quantum device (1), comprising a component formed of quantum dots which extend into an active level and front gates (FG1-FG6) for controlling the quantum dots arranged on the active level, characterized in that the device is formed on a substrate of the type double semiconductor on insulator which comprises: - a semiconductor support layer (6); - on the semiconductor support layer (6), a first insulating layer (7); - on the first insulating layer (7), a buried semiconductor layer in which a charge carrier conduction channel (4) is formed; - on the buried semiconducting layer, a second insulating layer forming a transport layer of charge carriers by tunneling effect (5); - on the second insulating layer (5), a superficial semiconductor layer in which a quantum confinement channel (2) is formed which accommodates the quantum dots; and in that the device further comprises: - a back control grid (BG) disposed on a back face of the semiconductor support layer (6); - a source region (S) and a drain region (D) arranged on either side of the component and between which extends the charge carrier conduction channel (4); the charge carrier conduction channel (4), the back control gate (BG) and the source (S) and drain (D) regions forming a buried transistor.
2. Device according to claim 1, in which the buried semiconductor layer has a thickness of between 5 and 15 nm.
3. Device according to any one of claims 1 and 2, wherein the second insulating layer has a thickness of between 1 and 2 nm.
4. Device according to any one of claims 1 to 3, further comprising a grid oxide layer (3) interposed between the active level and each of the front grids (FG1-FG6) and wherein the first insulating layer (7) and the grid oxide layer (3) each have a thickness greater than 15 nm, for example a thickness of between 20 and 25 nm.
5. A method for controlling a quantum device according to any one of claims 1 to 4, comprising: - control of the back grid (BG) so as to populate the charge carrier conduction channel (4) with charge carriers; - control of one of the front gates (FG1-FG6) so as to cause the transport of one or more charge carriers into a quantum dot from the charge carrier conduction channel (4) via the tunneling charge carrier transport layer (5).
6. Method for manufacturing a spin qubit quantum device, comprising: - the transfer of a surface semiconductor layer onto a semiconductor-on-insulator substrate, an insulating layer being at the interface between the semiconductor substrate and the surface semiconductor layer; - a thinning annealing of the insulating layer; - the formation of a component made up of quantum dots that extend into the surface semiconductor layer and of control front grids of the quantum dots arranged on the surface semiconductor layer; - the formation of a back grid on a back face of the semiconductor-on-insulator substrate; - the formation of source and drain regions arranged on either side of the component, between which extends a charge carrier conduction channel formed in a semiconductor layer of the semiconductor-on-insulator substrate