Single frame high dynamic range SPAD imager

Abstract

A high dynamic range imager comprising circuitry configured to: count detected photons locally within a pixel during a frame measurement period, the frame measurement period being divided into consecutive measurement periods of increasing length; evaluate the photon count against a predefined threshold at the end of each measurement period; and record the period number locally when the photon count exceeds the threshold and stop the photon counting.

Description

[0001] SINGLE FRAME HIGH DYNAMIC RANGE SPAD IMAGER

[0002] TECHNICAL FIELD

[0003] The present invention relates to the field of imaging and sensor technology, in particular to devices and methods for imaging.

[0004] TECHNICAL BACKGROUND

[0005] Single Photon Avalanche Detectors (SPADs) are increasingly utilized in various imaging applications. Their implementation in image sensing allows for shot-noise limited operation, which enables the acquisition of images at extremely low light levels. This advancement positions SPADs as a significant technology for applications requiring high sensitivity and precision in low-light conditions.

[0006] High dynamic range (HDR) operation in image sensors is an advancement in imaging technology, enabling the simultaneous capture of both low light and high light levels within a single image. This capability can be used for applications that require accurate representation of scenes with a wide range of illumination conditions. Achieving HDR operation involves sophisticated methods to manage the varying light intensities, ensuring that details are preserved across the entire dynamic range.

[0007] Despite the existence of HDR technology, there remains a need for further improvement.

[0008] SUMMARY

[0009] According to a first aspect the disclosure provides a high dynamic range imager comprising circuitry configured to: count detected photons locally within a pixel during a frame measurement period, the frame measurement period being divided into consecutive periods of increasing length; evaluate the photon count against a predefined threshold at the end of each measurement period; and record the period number locally when the photon count exceeds the threshold and stop the photon counting.

[0010] According to a further aspect the disclosure provides a high dynamic range imager comprising a plurality of pixels, each pixel including: a photon detector configured to detect photons; a local photon counter coupled to the photon detector, configured to count detected photons during a frame measurement period, the frame measurement period being divided into consecutive periods of increasing length; a threshold comparator coupled to the local photon counter, configured to evaluate the photon count against a predefined threshold at the end of eachmeasurement period; a period number register coupled to the threshold comparator, configured to record the period number locally when the photon count exceeds the threshold and to stop the photon counter.

[0011] According to another aspect the disclosure provides a method for high dynamic range imaging, comprising: detecting photons locally within a pixel during a frame measurement period, wherein the frame measurement period is divided into consecutive periods of increasing length; evaluating the photon count against a predefined threshold at the end of each measurement period; and recording the period number locally when the photon count exceeds the threshold and stopping the photon counting.

[0012] Further aspects are set forth in the dependent claims, the drawings and the following description.

[0013] BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Embodiments are explained by way of example with respect to the accompanying drawings, in which:

[0015] Fig. 1 shows an embodiment of a pixel of an image sensor according to a digital implementation. Fig. 2 provides a timing diagram demonstrating the principle of subdividing the exposure frame period into smaller consecutive periods to achieve high dynamic range (HDR) imaging.

[0016] Fig. 3 provides a table with example operating parameters for a digital implementation, showing 12 periods and a growth factor of 1.8, achieving a dynamic range of more than 120 dB in a single 0.996 ms frame.

[0017] Fig. 4 illustrates the behavior of photon counting over time within an exposure frame for a SPAD-based image sensor, showing how a margin may be implemented to support the coverage of shot-noise variations and increased photon flux.

[0018] Fig. 5 shows a preferred embodiment of an image sensor pixel, according to an analog implementation.

[0019] Fig. 6 illustrates the behavior of the analog photon counter within a SPAD-based image sensor, demonstrating how the voltage increases with photon detection over consecutive periods and how a margin is defined to accommodate shot-noise variations and fluctuating photon flux. Fig. 7 shows an example of operating parameters for an analog implementation, showing 11 periods and a growth factor of 2, achieving a dynamic range of more than 120 dB in a single 1.024 ms frame.Fig. 8 provides an embodiment of an image sensor pixel according to a digital implementation, using a local counter for period number generation and memorization.

[0020] Fig. 9 illustrates the control architecture of the SPAD-based image sensor system, featuring the integration of a controller 900 responsible for providing the necessary control signals to the pixel circuitry.

[0021] It should be noted that the drawings are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to actual reductions to practice. In the different figures, the same reference numbers refer to the same or analogous elements.

[0022] DETAILED DESCRIPTION OF EMBODIMENTS

[0023] Before a detailed description of the embodiments under reference of Fig. 1 is given, some general explanations are made.

[0024] The embodiments describe an high dynamic range imager comprising circuitry configured to count detected photons locally within a pixel during a frame measurement period, the frame measurement period being divided into consecutive measurement periods of increasing length, evaluate the photon count against a predefined threshold at the end of each measurement period, and record a period number locally when the photon count exceeds the threshold and stop the photon counter. This aspect can enable the imager to achieve HDR imaging by counting photons locally within each pixel. By dividing the frame measurement period into consecutive measurement periods of increasing length, the imager can capture varying light intensities.

[0025] Evaluating the photon count against a predefined threshold may allow the sensor to determine when to stop counting and record the period number, ensuring precise measurement and efficient data processing.

[0026] Circuitry may generally refer to any combination of electronic components, devices, or systems that are configured to perform specific functions or operations. This includes but is not limited to integrated circuits, discrete components, microprocessors, programmable logic devices, analog and digital circuits, and any other hardware or software elements necessary to implement the described functionality. Circuitry can encompass both physical hardware and any associated firmware or software that contribute to the overall operation of the system.

[0027] A frame measurement period may generally refer to the entire duration during which the high dynamic range imager collects light and detects photons to form an image. This period mayencompass the full time span of a single exposure cycle, starting from the initiation of photon detection to the final collection of data that will be used to generate the image.

[0028] The consecutive measurement periods refer to sequential subdivisions within the frame measurement period during which the high dynamic range imager detects and counts photons. These measurement periods may be arranged in a sequential manner, each following the previous one without any overlap.

[0029] According to some embodiments, counting detected photons locally within a pixel during a frame measurement period is performed in that the photon counting process is performed directly within each individual pixel of the imager. This localized counting enables each pixel to independently detect and count the photons that it receives, allowing for precise and immediate measurement of light intensity at a granular level. Local counting in the high dynamic range imager may structurally be achieved by integrating specific components directly within each pixel. Each pixel may for example be equipped with a SPAD for detecting individual photons, a local photon counter to count the pulses generated by the SPAD.

[0030] The predefined threshold may refer to a specific photon count value that is established prior to the commencement of the frame measurement period. This threshold may serve as a reference point for evaluating the photon count detected by the imager within each consecutive measurement period. The predefined threshold may determine when the photon counting should be halted and the current period number should be recorded. According to the embodiments, the predefined threshold remains constant throughout the entire frame measurement period, providing consistency in the evaluation process for each measurement period. The threshold may be set based on the desired sensitivity and dynamic range requirements of the imaging application, allowing the imager to effectively distinguish between varying light intensities and achieve precise high dynamic range imaging.

[0031] An aspect of the embodiments includes the imager comprising circuitry that incorporates a memory configured to continuously copy a current period number into a latched period register until a first signal is received. The first signal may for example be an explicit stop signal.

[0032] Alternatively, the first signal could be any signal that is interpreted by the circuitry as an indication to stop. This aspect may ensure that the current period number is consistently mirrored and stored in the latched register during the photon counting process, and updated continuously until stopped or reset. Upon receiving the first signal, the circuitry halts the copying mechanism, thereby preserving the period number at which the photon count surpassed the predefinedthreshold. This local recording of period numbers enables precise tracking of the photon counting process.

[0033] The predefined threshold may be used to evaluate the photon count at the end of each measurement period. For example, according to the embodiments, the imager’s circuitry consistently applies this threshold to determine whether the photon count has exceeded the specified limit. If the count surpasses the common predefined threshold during any of the consecutive measurement periods, the period number is recorded locally, and the photon counting is stopped.

[0034] An aspect of the embodiments includes the imager comprising circuitry that features a local counter configured to generate and keep track of period numbers locally within each pixel. This aspect may allow each pixel to independently manage its period counting, eliminating the need for global routing of period indication signals and enhancing the pixel array's resolution. The local counter is reset at the start of the frame and increments with each received second signal (Next) until the first signal (Stop) is triggered. Once the first signal (Stop) is received, the current period number is latched and recorded within the local counter, ensuring that the precise moment when the photon count exceeded the threshold is captured.

[0035] An aspect of the embodiments also includes the imager comprising circuitry configured to latch a latest period number and stop the photon counter at the end of the frame if the threshold is not exceeded. This aspect can ensure that the photon counter stops counting at the end of the frame measurement period if the predefined threshold is not exceeded. By latching the latest period number, the sensor can accurately record the measurement period during which photon counting occurred.

[0036] An aspect of the embodiments includes the imager comprising circuitry configured to perform an evaluation at the end of each measurement period to check whether during said measurement period the photon counter has surpassed a predefined threshold (trip value). This aspect can involve evaluating the photon count at the end of each measurement period to determine if the count has surpassed the predefined threshold.

[0037] An aspect of the embodiments includes the imager comprising circuitry configured to continue subsequent evaluations during following (consecutive) measurement periods and keep the photon counter running if the predefined trip value is not surpassed. This aspect can ensure that the photon counter continues to operate during consecutive measurement periods if a predefinedtrip value is not surpassed. By performing ongoing evaluations, the sensor can capture a wide dynamic range of light intensities without interruptions in the counting process.

[0038] An aspect of the embodiments includes the imager comprising a SPAD configured to detect individual photons. This aspect can involve using SPAD technology to detect individual photons with high precision. SPADs may enable the sensor to achieve extreme sensitivity, making it ideal for low-light imaging and HDR applications.

[0039] An aspect of the embodiments includes the imager comprising circuitry configured to stop the photon counter at its latest value by reducing a SPAD’s excess bias to zero and / or by disabling the counter when the predefined threshold is surpassed. This approach may minimize power consumption and ensure precise measurement.

[0040] An aspect of the embodiments includes the imager comprising circuitry configured to receive and process a set of control signals that govern the operation of the photon counting and a comparison with the predefined threshold. This aspect can enable the sensor to operate systematically by receiving and processing control signals that manage photon counting and threshold comparisons, ensuring synchronized and accurate HDR imaging. The naming of the signals as first, second, third, fourth, and fifth in the description below does not indicate any specific order of occurrence or priority. These labels are used solely for the purpose of distinguishing between different control signals that govern various aspects of the high dynamic range imager’s operation.

[0041] An aspect of the embodiments includes the imager comprising circuitry configured to, upon receiving a second signal (Next), trigger evaluation of the photon count against the predefined threshold and increment a period counter to transition to the next measurement period. This aspect can ensure that the photon counting is systematically divided across multiple measurement periods within the frame measurement period, synchronizing transitions between periods for accurate HDR imaging. Each consecutive measurement period may be initiated by a Next signal pulse, which synchronizes the transition between periods. This may ensure that the photon counting is systematically divided across the multiple measurement periods within the frame measurement period.

[0042] An aspect of the embodiments includes the imager comprising circuitry configured to generate the second signal (Next) globally and provide it to all pixels in the array simultaneously, ensuring synchronized transitions between consecutive measurement periods across the entiresensor array. This aspect can ensure consistent and synchronized operation across the entire pixel array, contributing to reliable HDR imaging.

[0043] An aspect of the embodiments includes the circuitry comprising a digital photon counter and a digital comparator, the digital comparator configured to utilize the most significant bit (MSB) of the digital photon counter to determine if the predefined threshold is exceeded. This MSB-based threshold evaluation can simplify the circuit design, allowing for a compact implementation that supports high resolution in the pixel array. It may further reduce power consumption by minimizing the need for complex comparison circuits, contributing to the energy efficiency of the pixel array.

[0044] An aspect of the embodiments includes the imager comprising circuitry wherein the digital comparator is configured to generate a first signal (Stop) by AND-gating the MSB with the second signal (Next) pulse to halt the photon counter when the threshold is surpassed. This aspect can provide a straightforward mechanism for stopping the photon counter when the predefined threshold is exceeded, ensuring efficient and reliable HDR imaging.

[0045] An aspect of the embodiments includes the imager comprising consecutive periods that increase in length according to a predefined factor. The period length can for example be dynamically adjusted based on a predefined growth factor, and synchronization with the second signal (Next) may ensure that each subsequent measurement period has a systematically increasing length compared to the previous period. This aspect allows the sensor to capture a wide range of light intensities during the frame measurement period, enhancing HDR imaging capabilities. The period length may for example be dynamically adjusted based on a predefined growth factor, and the synchronization with the second signal (Next) may ensure that each subsequent period has a systematically increasing length compared to the previous period.

[0046] An aspect of the embodiments includes the imager comprising circuitry wherein the predefined growth factor is less than 2. By using a growth factor smaller than 2, this aspect can ensure that the period lengths increase gradually, providing a balanced approach to photon counting and improving the accuracy and reliability of HDR imaging.

[0047] An aspect of the embodiments includes the imager comprising circuitry configured to, upon receiving a third signal (Reset), initialize the photon counter and digital comparator at the beginning of each imaging cycle. This aspect can ensure that the photon counter and digital comparator are properly initialized at the start of each frame measurement period, providing a fresh starting point for accurate photon counting and HDR imaging.An aspect of the embodiments includes the imager comprising circuitry configured to, upon receiving a fourth signal (Start), commence the photon counting process. Each pixel may include a local photon counter configured to count detected photons, and the local photon counter can be reset at the start of the frame measurement period by a fourth signal (Start).

[0048] An aspect of the embodiments includes the imager comprising circuitry configured to, upon receiving a first signal (Stop), halt the photon counting when the predefined threshold is exceeded. This aspect ensures that the photon counting process is stopped when the threshold is surpassed, preventing unnecessary counting and conserving power.

[0049] An aspect of the embodiments includes the imager comprising circuitry configured to, upon receiving a fifth signal (Readout), control the transfer of captured data from the imager to an external processing unit. This aspect ensures that the captured photon count and period number data are properly transferred for further processing, supporting efficient and accurate HDR imaging. It should be noted that the period numbers may not necessarily be numerical values but can more generally be data designating and / or identifying a particular period. There is flexibility in how the periods are represented and how they provide the identification of the measurement period during which the photon count exceeded the predefined threshold.

[0050] An aspect of the embodiments includes the imager comprising circuitry configured to, upon receiving a Threshold Setting signal, dynamically adjust the predefined threshold for photon count evaluation. This aspect allows for dynamic adjustment of the threshold based on various factors, enhancing the flexibility and accuracy of HDR imaging.

[0051] An aspect of the embodiments includes the imager comprising circuitry configured to apply an end-of-frame signal globally at the end of the frame, and if the photon counter is still running, to latch the latest period number as the recorded period value and stop the photon counter. This aspect may ensure that the photon counting process is finalized at the end of the frame measurement period, accurately recording the latest period number and stopping the counter. An aspect of the embodiments includes the imager comprising circuitry configured to read out the recorded period number and the photon counter stored in each pixel. This aspect ensures that the recorded data from each pixel is properly read out for further processing, supporting efficient HDR imaging.

[0052] An aspect of the embodiments includes the imager comprising circuitry configured to receive period indication signals configured to represent the current period number. These signals may enable the imager to track and synchronize the progression of consecutive measurement periodswithin the frame measurement period. By receiving and processing these period indication signals, each pixel in the imager can accurately record the period during which the photon count exceeds the predefined threshold.

[0053] An aspect of the embodiments includes the imager comprising circuitry configured to implement a margin within an exposure frame to accommodate shot-noise variations and increased photon flux during photon counting.

[0054] An aspect of the embodiments includes a high dynamic range imager comprising a plurality of pixels, each pixel including a photon detector configured to detect photons, a local photon counter coupled to the photon detector, configured to count detected photons during a frame measurement period, the frame measurement period being divided into consecutive measurement periods of increasing length, a threshold comparator coupled to the local photon counter, configured to evaluate the photon count against a predefined threshold at the end of each measurement period, and a period number register coupled to the threshold comparator, configured to record the period number locally when the photon count exceeds the threshold and to stop the photon counter. This aspect ensures that each pixel in the imager can independently count photons, evaluate the count against a threshold, and record the period number, contributing to accurate and efficient HDR imaging across the entire sensor array. By implementing these features locally within each pixel, the imager can achieve high resolution and sensitivity, capturing detailed light intensity variations in a wide dynamic range.

[0055] Moreover, an aspect of the embodiments is that the circuitry's adaptability allows it to be implemented in analog, digital, or mixed electronic configurations, providing flexibility to meet different technological requirements and application needs.

[0056] Embodiments of an HDR Imager with Single Photon Avalanche Diodes (SPAD) are now described in more detail by reference to the drawings.

[0057] A Single Photon Avalanche Diode (SPAD) is a highly sensitive photodetector capable of detecting individual photons. It operates in Geiger mode, where the diode is reverse-biased beyond its breakdown voltage, creating a high electric field. When a photon strikes the SPAD, it generates an electron-hole pair that triggers an avalanche multiplication process, resulting in a detectable electrical pulse. This ability to detect single photons with high timing precision makes SPADs ideal for applications requiring extreme sensitivity, such as low-light imaging and time-of-flight measurements. SPADs are integral to advanced imaging technologies, enabling high dynamic range (HDR) imaging and other sophisticated optical sensing applications.The embodiments described below in more detail disclose a SPAD-based image sensor capable of achieving HDR operation within a single measurement frame. That is, the SPAD-based image sensor is capable of capturing and processing a wide range of light intensities — from very low to very high — during one complete exposure period or cycle. This single measurement frame encompasses the entire duration in which the sensor collects light and generates the image data. The HDR operation is achieved without the need for multiple exposures or frames, allowing the sensor to simultaneously capture details in both bright and dark areas of the scene within one continuous exposure period. This capability can be used for accurately representing scenes with significant variations in illumination and for ensuring motion robustness, as it eliminates the need for combining multiple frames, which can introduce artifacts or misalignments due to movement.

[0058] The SPAD-based image sensor pixel operates by subdividing the exposure frame into multiple consecutive measurement periods, each with systematically increasing lengths according to a predefined growth factor.

[0059] The embodiments described below in more detail disclose circuitry for a pixel of an image sensor designed for high dynamic range (HDR) imaging, the pixel featuring a Single Photon Avalanche Diode (SPAD) system that generates count pulses in response to photon detection, which are then recorded by a digital counter. The counter's value is periodically evaluated against a tripping threshold at the end of each subdivided period within the exposure frame. If the threshold is surpassed, the SPAD system is disabled to conserve power, and the period number is latched for readout.

[0060] Fig. 1 shows an embodiment of a pixel 200 of an image sensor according to a digital implementation. The pixel circuitry includes a Single Photon Avalanche Diode (SPAD) system 101, which consists of one or more SPADs and the necessary circuitry to operate them. The SPAD system 101 generates a count pulse on the wire Count 123 each time a photon is received. This count pulse is sent to a digital counter 204, which increases its count value by one with each pulse. The counter 204 has a reset input “Reset”, a clock input “Clk”, and an enable input “en”. A compact ripple counter may be used for counting, but other types of counters are also possible. The counter 204 further has an output “out” which outputs the photon count value PhotoCount 211. The photon count value PhotoCount 211 is the value held by digital counter 204, representing the number of photons detected by the Single Photon Avalanche Diode (SPAD) system 101 during the exposure period.The pixel is provided with several control signals (e.g. by a controller 901 in Fig. 9), including Next 121, End 124, Start 122, period indication signals Hl and HO, tripping value 125 and RowSelect 120, which coordinate the timing and operation of the image sensor to achieve high dynamic range (HDR) imaging. The Start signal 122 initiates the exposure frame. The pixel operation begins with the signal Start 122 pulsing high, which resets the counter 204 to zero. As described in more detail below (see the timing diagram of Fig. 2), the time after the starting pulse until the end of the exposure frame is divided into a number of subsequent periods. At the end of each period, the signal Next 121 pulses high, marking an evaluation moment for the counter value PhotoCount 211. The End signal 124 is applied globally at the end of the exposure frame, ensuring that any ongoing counting is stopped and the final period number is latched. The period indication signals Hl and HO provide the current period number, which is continuously copied into the latched period J<1 :0> until the EnableCount signal 110 goes low.

[0061] The pixel circuitry includes a comparator 202 which is configured to continuously evaluate the photon count value PhotoCount 211 against a predefined tripping threshold Trip 125 at the end of each subdivided period within the exposure frame. When the photon count surpasses this threshold at the end of a subdivided period, the comparator generates a Stop signal (Stop 126), which is provided to SR-flipflop State 103.

[0062] The PhotoCount 211, which represents the number of photons detected by the Single Photon Avalanche Diode (SPAD) system, is provided to the comparator 202. The comparator 202 evaluates the PhotoCount 211 against the predefined tripping threshold, Trip 125. At the end of each subdivided period within the exposure frame, the comparator checks whether the PhotoCount 211 has surpassed the tripping threshold. If the threshold is exceeded, the comparator outputs a signal Stop 126 that triggers the SPAD system to stop counting, thereby conserving power and finalizing the count for that period. To this end, the counter value PhotoCount 211 is compared with the tripping value, Trip 125, using a comparator Compi. If the counter value surpasses the tripping value during the latest period, the output of the comparator Compi is AND-gated by gate ANDi with the Next 121 signal pulse, resulting in the Stop 126 signal pulsing high. This action flips the SR-flipflop State 103 into the off-state, bringing the EnableCount 110 signal to low. This low state will remain until a new measurement frame is initiated. When EnableCount 110 goes low, it disconnects the latched period J<1 :0> in memory PeriodMem 106 from the period indication signal H<l:0>, which carries the current period number. The latched period J<1 :0> will then remember the period number in which the counter value surpassed the tripping value.SR-flipflop State 103 (Set-Reset flipflop) is a bistable circuit used to control the enablement of the counting process within the SPAD-based image sensor pixel. The SR-flipflop consistst of two NOR gates NORi and NOR2 that maintain a stable state until an input signal changes. SR-flipflop State 103 has two states: set and reset. The primary function of the SR-flipflop State 103 is to manage the EnableCount signal 110, which determines whether the SPAD system 101 and the counter 204 are active or inactive. When the Stop signal from the comparator 202 is received, the SR-flipflop State 103 transitions to the reset state, causing the EnableCount signal 110 to go low. This action effectively disables the SPAD system 101 and halts the counting process in the counter 204, thereby conserving power by preventing unnecessary counting. The SPAD system 101 stops operating and the counter 204 stops counting when EnableCount 110 is low, reducing power consumption. The counter 204 may surpass the tripping value in one of the subsequent periods, but at very low light levels, it may not, and counting will stop at the end of the exposure frame due to the End 124 signal pulsing high.

[0063] The pixel circuitry further comprises a memory component PeriodMem 106 that stores the period number at which the counter value, PhotoCount 211, exceeds the tripping threshold, Trip 125. This memory component ensures that the specific period during which the threshold was surpassed is accurately recorded, which is later used for reconstructing the high dynamic range (HDR) image data. The period number is latched into PeriodMem 106 when the EnableCount signal 110 goes low, effectively capturing the moment when the photon count exceeded the threshold.

[0064] The implementation of PeriodMem 106 relies on capacitive storage elements combined with transistor-based sampling and readout circuits, forming a compact and efficient sample-and-hold structure. Two capacitors, labeled Ci and C2, are connected to storage nodes Jo and Ji. These capacitors Ci and C2 act as analog memory cells, holding voltages that encode the period number. The capacitors are charged or discharged through transistors M5 and Me, which act as pass gates. These pass gates allow new period values to be sampled and written into the capacitors, controlled by period indication signals Hi and Ho which provide the current period number (H<1 :0> in a binary representation of a value using two bits) which is continuously copied into the latched period (J<1 :0> a binary representation of a value using two bits) until the EnableCount signal 110 goes low.

[0065] In the provided embodiment, PeriodMem 106 is shown in a two-bit implementation, which is done for simplification; however, in an actual implementation, more bits may be used to accommodate a larger number of periods and enhance the precision of the HDR imaging process.In an implementation with 12 consecutive periods, a four-bit implementation may be used with the controller providing the current period number H<3:0> in a binary representation as a value using four bit and the latched period J<3:0> is also a binary representation of a value using four bits.

[0066] The pixel circuitry further includes a read-out circuit 207 which is responsible for transferring the final photon count value PhotoCount 211 (indicated as D<m-1 :0> in Fig. 1) and the latched period number (indicated as outputs CO and Cl in Fig. 1, J<1 :0> or more bits if necessary) from each pixel to the column lines for further processing. This process occurs after the exposure frame has ended and the counting operation has been completed. The read-out mechanism is activated by a RowSelect 120 signal , which enables the connection of the pixel's data to the column read-out circuitry.

[0067] Read Out 207 features a block called m x Bufi, which is an array of buffers or multiplexers. This array reads the voltages stored on the capacitors Ci and C2 and prepares them for further processing. The "dis" signal controls whether the readout is enabled or disabled, allowing for selective access to the stored data. Once the stored voltage is accessed, it is passed through a buffer circuit formed by transistors Mi through M4. This buffer acts as a sense amplifier, reading the relatively weak analog signal stored on the capacitors and driving a stronger output suitable for downstream digital processing. Pixel read-out 207 is activated by making RowSelect 120 low, which connects the PhotoCount 211 value to the column lines D<m-1 :0> through buffer m x Bufi, and propagates the latched J<1 :0> values to C<1 :0>. The extrapolated number of photons can be calculated from the read-out values D<m-1 :0> and C<1 :0> by dividing the read-out value by the end of the period where latching occurred and multiplying by the end of the last period. In summary, the pixel circuitry of the SPAD-based image sensor outputs two pieces of information: the photon count value PhotoCount 211 (J<1 :0> or more bits) and the latched period number (D<m-1 :0>). The photon count value represents the total number of photons detected by the SPAD system during the exposure frame, providing a measure of the light intensity captured by the pixel. The latched period number indicates the specific period during the exposure frame in which the photon count value surpassed a predefined tripping threshold. These outputs are read out at the end of the exposure frame and used to reconstruct the high dynamic range (HDR) image data.

[0068] The SPAD-based image sensor circuitry describe in Fig. 1 has the ability to achieve high dynamic range (HDR) imaging, capturing a wide spectrum of light intensities within a single exposure frame. This capability ensures accurate representation of scenes with varyingillumination, preserving details in both bright and dark areas. By achieving HDR within a single measurement frame, the circuitry eliminates the need for multiple exposures, thereby reducing the risk of motion artifacts and ensuring robustness against scene movement, which is particularly beneficial in dynamic or fast-changing environments.

[0069] Additionally, the circuitry is designed to minimize power consumption by stopping the SPAD system and counter from operating once the tripping threshold is surpassed. This efficient power management can beneficially be used for example in battery-operated devices and applications requiring long operational periods. The integration of the SPAD system, counter, and associated control circuitry within each pixel allows for a compact design, enabling high-resolution imaging without compromising performance.

[0070] The systematic subdivision of the exposure frame into periods with dynamically increasing lengths ensures precise photon counting and accurate light level measurements. The use of a tripping threshold and period latching further enhances the accuracy of the captured data. The direct readout of the photon count value and latched period number in a compressed digital format facilitates efficient data transport and processing, supporting real-time imaging applications and reducing the computational load on subsequent processing stages.

[0071] Fig. 2 illustrates a timing diagram with the first five periods of the single frame image capture, demonstrating the principle of subdividing the exposure frame period into smaller consecutive periods to achieve high dynamic range (HDR) imaging.

[0072] The timing diagram begins with the signal Start 112 pulsing high for a brief duration, such as 10 ns, as shown by curve 300. This Start signal resets the counter 204 (or 104 in the analog implementation of Fig. 5), initializing it to zero. The time span following the Start pulse until the end of the exposure frame is divided into a number p of subsequent periods, denoted as Atoto Atp-i. In Fig. 2, the first 5 periods are shown, labeled as Ato, Ati, At2, Ats, and At4, corresponding to n = 0 to 4.

[0073] At the end of each period Atn, the signal Next 121 pulses high, as indicated by curve 301. This Next signal 121 marks the end of the current period and the beginning of the next period. The end of the last period Atp-i (not shown in Fig. 2) defines the end of the exposure frame period. The periods Atnincrease in length from Ati onwards compared to their previous period Atn-i, following a systematic growth pattern. A growth factor (GF) is defined to achieve this systematic increment, which can be, for example, 1.8 or 2. In this embodiment, the period lengthdistribution follows the formula tn= t0x GFn, where tnis the length of the n-th period and t0is the length of the length of the first period.

[0074] The signals Start 112, Next 121, End 124, and period indication signal H<l:0> is provided globally to all pixels in the array (by a controller, e.g. 901 in Fig. 9). The period indication signal H<1 :0> is shown as having 2 bits, Hl and HO, in Fig. 2. In practice, more bits may be used to represent a larger number of periods, such as 4 bits for 12 periods as shown in other figures. The period indication signal H<l:0> increases by one just after each Next 121 pulse, indicating the current period number. This signal is continuously copied into the latched period J<1 :0> in memory PeriodMem 106 by pass-gate transistors Ms and Me, which are conductive when their gates are high. Therefore, the period indication signal H<1 :0> carries the period number n when a pulse is applied on signal Next 121.

[0075] The SPAD system 101 generates a count pulse on the wire Count 123 each time a photon is received. This count pulse is sent to the counter 204 (or 104 in the analog implementation) to increase the count value by one. An enable input, driven by EnableCount 110, controls whether the count signal can operate. When EnableCount 110 is low, the counter is inhibited from counting, and the SPAD system 101 reduces its excess bias to 0V to stop triggering, thereby conserving power.

[0076] At each end of period tn, marked by the Next 121 pulse, the counter value PhotoCount 211 is compared with a tripping value, Trip 125, using the comparator Compi. If the counter value surpasses the tripping value (at Cross in Fig. 2) during the latest period, the output of the comparator Compi is AND-gated with the Next 121 signal pulse, resulting in the Stop 126 signal pulsing high, as shown by arrow 320. A shown by arrow 321, this action flips the SR-flipflop State 103 into the off-state, bringing EnableCount 110 to low, as indicated by curve 303. This low state will remain until a new measurement frame is initiated. When EnableCount 110 goes low, it disconnects the latched period J<1 :0> from the period indication signal H<1 :0>, which carries the current period number. The latched period J<1 :0> will then remember the period number in which the counter value surpassed the tripping value.

[0077] The rising value of the counter 204 likely surpasses the Trip level 125 in one of the subsequent periods Ato to Atp-i. However, at very low light levels, it may not, and the counting process will stop at the end of the exposure frame due to the signal End 124 pulsing high, which also brings EnableCount 110 low.In summary, the SPAD-based image sensor disclosed in Figs. 1 and 2 is designed to achieve high dynamic range (HDR) imaging, capable of capturing a wide spectrum of light intensities within a single exposure frame. This capability allows for simultaneous acquisition of both low light and high light levels within the same image, ensuring accurate representation of scenes with varying illumination conditions. The sensor employs a digital counter for photon counting, which facilitates precise measurement and can be integrated on a per-pixel basis. This technology can be implemented in analog, digital, or mixed electronic configurations, offering flexibility to meet different technological requirements.

[0078] A compact circuit is provided that can efficiently represent the captured HDR value in a compressed format, ready for efficient data transport. The sensor features a local shut-off mechanism for each SPAD, which activates after reaching the necessary count for targeted precision. This ensures optimal power usage and minimizes unnecessary counting, contributing to low power consumption. Additionally, the sensor maintains small precision variation across most of the dynamic range, ensuring accurate light level measurement, including the shot-noise of the incident light.

[0079] The SPAD-based image sensor achieves HDR imaging within a single measurement frame, eliminating the need for multiple exposures and ensuring motion robustness for each light level and each pixel. This single-frame operation reduces the risk of artifacts and misalignments due to movement, making the sensor particularly beneficial in dynamic or fast-changing environments. The design allows for a compact implementation, enabling high-resolution imaging without compromising performance. Furthermore, the sensor incorporates a margin to accommodate shot-noise variations and fluctuating photon flux, ensuring reliable recording and accurate light level representation across the entire dynamic range.

[0080] The disclosed SPAD-based image sensor provides a trade-off between power dissipation and precision, allowing for settable configurations to optimize performance. The direct read-out in digital bits, in a compressed format, ensures efficient data handling. The design achieves high dynamic range without compromises at both low and high light levels, ensuring optimal motion robustness for each light level for each pixel. Additionally, the small pixel size implementation ensures that the sensor can be integrated into high-resolution imaging systems, effectively covering shot-noise and increasing photon flux with margin provision.

[0081] Fig. 3 shows a table with example operating parameters for a digital implementation of the sensor, having 12 periods Ato to Atn and a growth factor GF of 1.8, achieving a dynamic range of more than 120 dB in a single 0.996 ms frame. The table provides practical values for achieving a122-dB range with a 0.996 ms exposure frame, 11 bits for the count value, and 4 bits for the indication of the period. As an 11 bits counter for Count 204 is chosen, the Counter range 330 is from 0 to 2047. The ends of periods to to tn increase with a growth factor GF of 1.8, and the last end of period tn is at 996160 ns (~0.996ms). The Trip value (threshold 125 in Fig. 1) is chosen conveniently, at 1024, halfway the maximum count up of 2047. The most significant bit (MSB) of the Counter 204 turns high when the value reaches 1024. That makes the comparison circuit for Compi very small, i.e. one can consider that the most significant bit provides already the outcome of the comparison with the 1024 value. Since smaller circuits help making a higher pixel resolution possible, this method is preferred. So, the most significant bit of Counter 204 can directly be ANDed with the NEXT 121 signal (by gate ANDi) for providing Stop 126 signal. The column “Extrapolated Photons in 0.996 ms Frame” provides the extrapolated number of photons detected during the entire 0.996 ms frame. The extrapolated photon count is calculated based on the counter value and the period in which the counting stopped. The maximum number of photons that can be estimated is 1,315,574, the lowest is 0. The dynamic range is thus 122.4 dB. The system’s dynamic range of approximately 122.4 dB is obtained by calculating the 20 loglO logarithm of the ratio between the maximum detectable photon count (1,315,574 photons) and the minimum detectable signal (1 photon). This logarithmic calculation is a standard method for expressing dynamic range, as it captures the large span between the smallest and largest measurable signals in a way that aligns with how signals and noise typically scale in photoncounting systems. The reason 1 photon is used as the minimum detectable signal instead of 0 is because a logarithmic scale cannot handle a ratio involving zero, as the logarithm of zero is undefined. Additionally, in practical terms, a photon-counting system can detect the presence of a single photon, making 1 photon the smallest non-zero signal that can be meaningfully measured.

[0082] The precision of the system is determined by the counter, which, when it stops in the range of 1024 to 2047 counts, represents a signal-to-noise ratio (SNR) between 30.1 and 33.1 dB, respectively. The SNR is calculated based on the assumption that the noise in the system follows a Poisson distribution, which is typical for photon-counting systems. In such systems, the noise is proportional to the square root of the signal, meaning that as the number of detected photons increases, the noise increases as well, but at a slower rate (specifically, the noise is the square root of the number of detected photons).

[0083] At very low light levels, however, it is possible that during the final period Atn, the photon count may not reach the threshold where the most significant bit (MSB) of the counter turns high (i.e.,the count remains below 1024). When this happens, the SNR will be lower because the signal (number of detected photons) is low, and the noise, being proportional to the square root of the signal, will have a more significant impact relative to the signal. This results in a reduced SNR at very low light levels, as the precision of the measurement decreases when fewer photons are detected.

[0084] It should be noted that in the example provided in Figure 3, the growth factor GF of 1.8 is not applied between the first two periods, Ato and Ati due to initialization and starting reasons. That is, the first period, Ato has a different length compared to subsequent periods. This deviation is beneficial for proper system initialization and accurate photon counting from the outset. The system is designed to accurately track the end of each period and handle deviations from the fixed growth factor appropriately.

[0085] The overall design principle is that the periods should grow on average over successive periods to achieve high dynamic range (HDR) imaging. This systematic increment in period length ensures that the sensor can capture a wide range of light intensities within a single exposure frame. Therefore, while the first period may differ, the subsequent periods follow the predefined growth pattern to maintain the intended HDR capability.

[0086] Fig. 4 shows how a margin 389 may be implemented to support the coverage of shot-noise variations and an increased photon flux in the second half of the period that the counter is running.

[0087] It provides for a reason why the growth factor GF is preferably chosen smaller than 2.

[0088] Fig. 4 illustrates the behavior of photon counting over time within an exposure frame for a SPAD-based image sensor. The vertical axis of the diagram represents the photon count, ranging from 0 to the maximum counter value MaxD of 2047. This axis shows the number of photons detected and counted by the sensor over time. The horizontal axis represents time, which is divided into multiple periods (Ato, Ati, At2, etc.) within the total exposure frame. The points labeled to, ti, t2, etc. correspond to the end of each period within the total exposure frame. Each period increases in length according to a predefined growth factor, which in this case is 1.8. TripD refers to the tripping threshold value (Trip 155 in Fig. 1) for the photon count. This is the predefined count value at which the system evaluates whether the counter should stop counting photons. In the context of the diagram, TripD is set at 1024. When the photon count reaches or exceeds this threshold, the comparator generates a Stop signal, which then triggers the SR-flipflop to disable further counting.Curves 350 and 351 represent linear increases in photon count, not showing any shot noise behavior on them. Curve 350 has the lowest incoming photon rate of the two and brings the count value close to the trip value (TripD = 1024). In the figure, latching in period Ats is assumed. With one photon less, latching during the next period At4, would occur. The curve 351 has a higher photon rate. Here, period At2 was not selected, and the counter continues to count, surpassing the tripping threshold TripD. Consequently, the counter will be classified at moment t3 as part of period Ats. Assuming a linear increase of the counter, the value reaches 1843 (indicated by LinMaxD = 1843), due to the growth factor GF of 1.8. This leaves approximately 10% room (margin 389) below the maximum counter value (MaxD = 2047), providing a buffer to accommodate higher values in case shot noise or fluctuations in light intensity cause faster counting during period Ats. Given that shot noise typically accounts for about 3% of the signal, the likelihood of reaching the maximum counter value of 2047 is minimal, ensuring reliable recording. Curve 304 represents an example of regular case whereby the photon count increases at a rate between that of 350 and 351. At t3 it is decided that it has surpassed the 1024 value (TripD) in the period Ats.

[0089] It should be noted that to prevent counter overflow under varying light conditions, it is possible to implement a circuit that prohibits the counter from exceeding its maximum value of 2047. With the digital example given, 4 bits have to be read out for the period number, and 11 bits for the final count value. However, it is an option to have a very short additional last period, during which only the period counter increases, and just after which the End 124 signal pulse is applied. If then the captured period number is 0 to 11 (recorded in the latched period J<3 :0>), the MSB must have been flagged high in one of the original periods, and if the period number is 12, it is known that it happened in this short additional last period and that said MSB was still low. In this way, it is no longer needed to communicate and / or store the MSB, and the 4 bits for the period number and 10 least significant bits (instead of 11) for the count value will suffice.

[0090] Fig. 5 shows an embodiment of an image sensor pixel 100, according to an analog implementation. In this analog implementation of an image sensor pixel 100, the counter 104 is of an analog type, featuring EnableCount 110 as the enable (en) input, Count 123 as the clock (elk) input, and Start 122 as the reset input. The EnableCount 110 input controls whether the counter is active, while the Start 122 input resets the counter at the beginning of each measurement period by making gate of transistor Mis high, pulling the voltage on C4 to ground. Vbias is a bias voltage applied setting the saturation voltage for the counter. Ground connections provide the reference potential for the circuit.Unlike the digital counter Count 204 of Fig. 1, the output here is an analog voltage, PhotoCount 111, which can vary within a Counter Voltage Range 630 from 0 V to the supply voltage Vbias. Vbias is a fixed voltage supplied across the entire array, typically set to a value such as IV. The analog Counter 104 operates based on the charge-pump principle, which is a method used to incrementally increase the voltage on a capacitor in response to detected events, in this case, photon detections.

[0091] Each time the SPAD system 101 detects a photon, it generates a trigger signal on the Count 123 line. This trigger signal prompts a clock generator (ClockGen) 105 to produce a sequence of clock pulses. The ClockGen 105 toggles by first bringing the voltage on the clock signal 4> 1 down, then pulsing the clock signal (|>2 temporarily high, and finally bringing the voltage on (|>2 back up. This sequence is indicated by the symbol used for ClockGen 105 in the diagram.

[0092] The clock signals 4> 1 and (|>2 are designed to be non-overlapping, meaning that they do not go high at the same time. This non-overlapping nature allows for the correct operation of two NMOS pass gates, M13 and M14.

[0093] During the 4> 1 phase, the clock signal brings the voltage on 4> 1 down, turning on NMOS transistor M13. This action allows a small amount of charge to pass from capacitor C3 to capacitor C4. Capacitor C3, in this context, acts as a charge reservoir, providing the necessary charge to increment the voltage on C4. When (|>2 pulses high, it turns on NMOS transistors M14 . M14 ensures that the charge is effectively transferred and stored on C4. The non-overlapping nature of 4> 1 and (|>2 ensures that M13 andMuare never conductive simultaneously, since this would charge the counter voltage in one go to its maximum voltage, killing the counting operation.

[0094] The voltage on C4, which is also the voltage at node PhotoCount 111, represents the cumulative count of detected photons. As more photons are detected, the ClockGen 105 continues to toggle, and the voltage on C4 rises proportionally. This incremental increase in voltage is governed by the relationship between the capacitance values of C3 and C4, ensuring that each photon detection results in a precise and incremental voltage change on C4.

[0095] The voltage PhotoCount 111 will vary on the number of counts nc that made the ClockGen 105 toggle (since the occurrence of the Start 122 pulse, curve 300), according to following formula:

[0096] — T? C "yC c30

[0097] V

[0098]

[0099] (PhotoCount 111) = Vbias(1 - e

[0100] When nc reaches the value of—, V(PhotoCount 111) will be 63.2% of Vbias.To compare with a known number of photons, such as approximately 500 photo-counts, the system can be defined by choosing the capacitance values such that C4 is 500 times C3. For example, C3 can be defined with a capacitance value of 0.1 fF, and C4 with a capacitance value of 50 fF. The implementation of C3 and C4 can be done in a manner preferred by the person skilled in the art and will depend on the options available in the target semiconductor technology. To achieve a low value for C3, it is an option to define it as the parasitic capacitance of the diffusion source / drain terminal diodes of transistors M13 and M14 that are connected to each other.

[0101] With these capacitance values, Vbias can be chosen to be IV. The comparator 102 will then compare the voltage of PhotoCount 111 to 63.2% of IV, which is 632mV. The total effect is that when the photon count surpasses 500, the output of the comparator 102 (the signal Stop 124) will go high. Comparator 102 detects whether the voltage of 632 mV is surpassed.

[0102] One can devise many comparator circuits to achieve this, but the smallest version is by using an inverter that has a tripping point TripA = 632 mV. In Figure 5 this is demonstrated by PMOS M12 and NMOS Mio that together form an inverter Inv2 with a tripping voltage TripA defined by their respective aspect ratios Wp / Lpand Wn / Ln(not shown but known to person skilled in the art). That inverter is made to be only active (and dissipating some power) at the end of periods to to tp-i when NMOS transistor M9 is conductive in response to signal Next 121 pulsing high. After Invi the Stop 124 signal is provided that will reset the state of the RS flipflop State 103 to output a low on EnableCount 110, in the event of surpassing and in case this had not yet happened during an earlier evaluation. In short, State 103 drives EnableCount 110 high at the start of the exposure frame (when Start 122 pulses high), and goes low, at the end of period tnwherein the analog signal PhotoCount 111 surpasses the tripping voltage of Inv2. If this doesn’t happen at any of the end of periods to to tp-i the counting will this time stop due to End 124 pulsing high at the end of the exposure frame resetting State 103 to an output state low, i.e.

[0103] EnableCount 110 becoming low.

[0104] Fig. 6 illustrates the behavior of the analog photon counter within a SPAD-based image sensor, demonstrating how the voltage increases with photon detection over consecutive periods and how a margin is defined to accommodate shot-noise variations and fluctuating photon flux. The vertical axis represents the Counter Voltage Range 630, spanning from 0 V to Vbias. The horizontal axis denotes time, which is divided into multiple periods (Ato, Ati, At2, etc.) within the total exposure frame. The points labeled to, ti, t2, and t3 correspond to the end of each period within the exposure frame . The tripping threshold voltage, TripA, is set at 63.2% of Vbias (632mV). This threshold is used for evaluating whether the photon count has surpassed a predefined value during each period.

[0105] Curve 604 demonstrates a photon count with a lower photon flux, evaluated at each end of the periods. At t3, it is on the edge of surpassing the TripA threshold, indicating that it could either stop counting (Curve 604B) or continue to the next period (Curve 604A). If the count is above 500 photons, the Stop signal 124 pulses high, resetting the SR-flipflop State 103, causing the EnableCount signal 110 to go low and halting the count. The period indication signal H<1 :0> that until then has been copied into the PeriodMem 106 by Me and M? being conductive, will also be latched in the latched period J<1 :0> and keep the value of 3. If the photon count is below 500 counts, Stop 124 will not go high, State 103 will not be reset, and EnableCount 110 will not go low. Counting will continue (Curve 604 A). Due to the positive feedback in the State 103 flipflop, there will be either flipping or no flipping, with very low chances of metastability. Curve 651 represents a higher photon flux. At t2, it is just below the threshold (for example, 498 counts) and continues to t3, where it reaches approximately 996 counts, assuming the photon flux remains constant. With a growth factor GF = 2, this corresponds to a voltage LinMax that is 86.5% of Vbias. There is still a voltage margin 680 that remains, corresponding to an infinite number of counts. This margin ensures that there is enough buffer space below the maximum counter value (Vbias) to accommodate shot-noise and variations in photon flux during the second half of the counting period (At3), preventing counter overflow and contributing to reliable recording.

[0106] At the last end of the period (At4), the signal End 124 pulses high, terminating the frame and exposure. The readout process involves bringing RowSelect 120 low, which makes PMOS pass gates M2, M4, and M8 conductive, allowing the column circuitry to measure the JO and JI states on lines CO and Cl, and read out the analog value on PhotoCount 111 through voltage follower PMOS M7 on the analog column line A.

[0107] At the last end of the period (Atf), the signal End pulses high, terminating the frame and exposure. The readout process involves bringing RowSelect low to connect the column circuitry, allowing the measurement of the latched period and the analog value on PhotoCount.

[0108] Fig. 7 shows example operating parameters for an analog implementation of the present invention, having 11 periods Ato to Atio and a growth factor of 2 achieving a dynamic range of more than 120 dB in a single 1.024 ms frame. The figure provides a table of example operating parameters for an analog implementation of a high dynamic range (HDR) SPAD imager. Thetable includes 11 periods (n = 0, ... 11), labeled Ato to Atio, with lengths increasing by a growth factor of 2. The total exposure frame duration is 1.024 ms. The period length Atnstart at 1000 ns for the initial two periods and doubles in duration for each subsequent period, following the growth factor of 2. The end time tnof the periods begins at 1000ns and extends to 1024000 ns by the final period. The photon counter values at the stopping point vary between 500 and 1000 counts for each period (except of the last period). Based on these values, the extrapolated number of photons detected during the entire 1.024 ms frame ranges from a minimum of 0 photons in the last period to 1024000 photons in the first period.

[0109] The signal-to-noise ratio (SNR) for each period is between 27.0 and 30.0 dB. The dynamic range of the system, calculated to be approximately 120.2 dB, is determined using the ratio between the maximum and minimum detectable photon counts, as described with regard to Fig. 4 above. It should be noted that in the example provided in Figure 7, the growth factor GF of 2 is not applied between the first two periods, Ato and Ati due to initialization and starting reasons. That is, the first period, Ato has a different length compared to subsequent periods. The reasons are the same as set out with regard to Fig. 3 above. This deviation is beneficial for proper system initialization and accurate photon counting from the outset.

[0110] Fig. 8 illustrates an embodiment of an image sensor pixel (Pixel Circuit 700) according to a digital implementation. This embodiment is similar to the one described in Fig. 2 but introduces the use of a local counter (PeriodCounter Mem 706) to generate and keep track of period numbers locally within each pixel, rather than relying on global routing of period numbers.

[0111] In the embodiment shown in Fig. 2, period indication signals (H<l:0>) are provided globally to all pixels in the array, and these signals are copied into the latched period memory (PeriodMem 106) using pass-gate transistors. In contrast, Fig. 8 avoids the global routing of period numbers by incorporating a local counter (PeriodCounter Mem 706) within each pixel. This local counter is reset at the start of the frame by the Start 122 signal and increments each time the Next 121 signal pulses, until its enable input (EnableCount 110) goes low. When EnableCount 110 goes low, the current period number is latched into PeriodCounter Mem 706 (Jq-l:O), capturing the moment when the photon count exceeded the threshold.

[0112] The primary advantage of using a local counter for period number generation is the elimination of the need for global routing of period indication signals, which can simplify the pixel circuitry and potentially enhance pixel resolution. This method requires a slightly larger counter (PeriodCounter Mem 706) for period number generation and memorization compared to thememory PeriodMem 106 in Fig. 2. Depending on the used CMOS technology, target pixel resolution, and the number of metal routing layers, one approach may be preferred over the other.

[0113] The basic operation of the SPAD system 101, digital counter 204, and comparator 202 remains the same as in Fig. 2. The SPAD system generates a count pulse each time a photon is detected, incrementing the digital counter. The photon count value (PhotoCount 211) is continuously evaluated against a predefined tripping threshold (Trip 125) by the comparator. If the photon count surpasses the threshold, the comparator generates a Stop 126 signal, which resets the SR-flipflop State 103, causing EnableCount 110 to go low and halting the counting process.

[0114] Additionally, the local period counting principle is equally applicable when the photon counter is of the analog type, and the period counter itself may also be of the analog type.

[0115] The read-out circuit 207 is responsible for transferring the final photon count value (PhotoCount 211) and the latched period number (Jq-1 :0) from each pixel to the column lines for further processing. This process is activated by the RowSelect 120 signal, which enables the connection of the pixel's data to the column read-out circuitry.

[0116] Furthermore, the SPAD system can incorporate various quenching techniques, including passive quenching, active quenching, or clocked recharging. Clocked recharging is particularly useful in very high light level conditions, as it helps mitigate the effect of photons triggering a SPAD during its deadtime and therefore not getting counted. This principle may be applied during one or a few consecutive periods starting from the first period.

[0117] Fig. 9 illustrates the control architecture of a SPAD-based imaging device 900, featuring the integration of a controller 901 responsible for providing the necessary control signals to the pixel circuitry 902. The controller 901 generates and manages the timing signals including Start 122, Next 121, and End 124, as well as the period indication signals Hl and HO and the tripping threshold Trip 125. These control signals are distributed globally to all pixels in the image sensor array 902 to ensure synchronized operation and accurate high dynamic range (HDR) imaging. The controller 901 coordinates the initialization, counting, evaluation, latching, and read-out processes, facilitating seamless integration and efficient management of the SPAD-based image sensor system for real-time imaging applications. During the read-out process, the controller 901 sequentially accesses the data from the pixel circuitry 902. This involves generating the necessary control signals to activate the row and column lines, thereby selecting individual pixels for read-out. The controller 901 ensures that the image data, which may include photon counts and timing information, is accurately latched and transferred to the output buffers orstorage registers. From there, the data is sent to subsequent processing stages, such as analog-to-digital conversion and image reconstruction, ensuring high-quality image capture and processing.

[0118] ***

[0119] It should be noted that the division of entities in Fig. 1 into distinct units such as the SPAD system 101, digital counter 204, comparator 202, SR-flipflop State 103, and memory PeriodMem 106 is presented solely for illustrative purposes. The present disclosure is not confined to any particular division of functionalities across these units. The functionalities depicted by these entities can be implemented using various technologies, including programmed processors, field-programmable gate arrays (FPGAs), custom application-specific integrated circuits (ASICs), or any combination of these technologies. The specific implementation of these functionalities may vary based on application requirements, available hardware resources, and design preferences. In certain embodiments, these functionalities may be integrated within a single processing unit or distributed across multiple processing units. Additionally, the implementation may involve software components, such as firmware, operating system-level drivers, and application-specific software routines, to achieve the desired control and processing functionalities. The flexibility in selecting hardware and software components allows for customized solutions that optimize performance, power consumption, and cost-effectiveness, addressing the specific needs of the imaging system and its intended applications.

[0120] All units and entities described in this specification and claimed in the appended claims can, unless otherwise specified, be implemented as integrated circuit logic, for example, on a chip, with the functionality provided by such units and entities potentially being implemented through software.

[0121] The methods as described herein are also implemented in some embodiments as a computer program causing a computer and / or a processor to perform the method, when being carried out on the computer and / or processor. In some embodiments, also a non-transitory computer-readable recording medium is provided that stores therein a computer program product, which, when executed by a processor, such as the processor described above, causes the methods described herein to be performed.

[0122] It should be noted that the term "comprising," as used in the claims, should not be interpreted as being restricted to only the means listed thereafter. Therefore, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting solely ofcomponents A and B. This means that, in the context of the present invention, the most relevant components of the device are A and B.

[0123] Similarly, it is to be noticed that the term "coupled" should not be interpreted as being restricted to direct connections only. Thus, the scope of the expression "a device A coupled to a device B" should not be limited to devices or systems wherein an output of device A is directly connected to an input of device B. It means that there exists a path between an output of A and an input of B which may be a path including other devices or means.

[0124] Note that the present technology can also be configured as described below.

[0125] [1] A high dynamic range imager comprising circuitry configured to:

[0126] count detected photons locally within a pixel (200) during a frame measurement period, the frame measurement period being divided into consecutive measurement periods of increasing length;

[0127] evaluate the photon count against a predefined threshold at the end of each measurement period; and

[0128] record a period number locally when the photon count exceeds the predefined threshold and stop the photon counting.

[0129] [2] The imager according to [1], wherein the circuitry comprises a memory (PeriodMem 106) configured to continuously copy a current period number into a latched period register until a first signal (Stop 126) is received.

[0130] [3] The imager according to [1] or [2], wherein the circuitry comprises a local counter (204) configured to generate and keep track of period numbers locally within each pixel.

[0131] [4] The imager according to any one of [1] to [3], wherein the circuitry is further configured to latch a latest period number and stop the photon counter at the end of the frame if the threshold is not exceeded.

[0132] [5] The imager according to any one of [1] to [4], wherein the circuitry is configured to perform an evaluation at the end of each period, to check whether during said period the photon counter has surpassed a predefined trip value (125).

[0133] [6] The imager according to any one of [1] to [5], wherein the circuitry is configured to continue subsequent evaluations during following measurement periods and keep the photon counter running if a predefined trip value is not surpassed.[7] The imager according to any one of [1] to [6], wherein the circuitry comprises a SPAD (101) configured to detect individual photons.

[0134] [8] The imager according to any one of [1] to [7], wherein the circuitry is configured to stop the photon counter at its latest value by reducing a SPAD’s excess bias to zero and / or by disabling the counter when the predefined threshold is surpassed.

[0135] [9] The imager according to any one of [1] to [8], wherein the circuitry is configured to receive and process a set of control signals that govern the operation of the photon counting and a comparison with the predefined threshold.

[0136]

[0010] The imager according to any one of [1] to [9], wherein the circuitry is configured to, upon receiving a second signal (Next 121), trigger evaluation of the photon count against the predefined threshold and increment a period counter to transition to the next measurement period.

[0137]

[0011] The imager according to

[0010] , wherein the second signal (Next 121) is generated globally and provided to all pixels in the array simultaneously, ensuring synchronized transitions between consecutive measurement periods across the entire sensor array.

[0138]

[0012] The imager according to any one of [1] to

[0011] , wherein the circuitry comprises a digital photon counter (204) and a digital comparator (202), the digital comparator configured to utilize the most significant bit (MSB) of the digital photon counter to determine if the predefined threshold is exceeded.

[0139]

[0013] The imager according to

[0012] , wherein the digital comparator is configured to generate a first signal (Stop 126) by AND-gating the MSB with the second signal (Next 121) pulse to halt the photon counter when the threshold is surpassed.

[0140]

[0014] The imager according to any one of [1] to

[0013] , wherein the consecutive measurement periods increase in length according to a predefined factor.

[0141]

[0015] The imager according to

[0014] , wherein the predefined growth factor is less than 2.

[0142]

[0016] The imager according to any one of

[0010] , wherein the circuitry is configured to, upon receiving a third signal (Reset), initialize a photon counter (204) and a digital comparator (202) at the beginning of each imaging cycle.

[0143]

[0017] The imager according to any one of [1] to

[0016] , wherein the circuitry is configured to, upon receiving a fourth signal (Start 122), commence the photon counting process.

[0018] The imager according to any one of [1] to

[0017] , wherein the circuitry is configured to, upon receiving a first signal (Stop 126), halt the photon counting when the predefined threshold is exceeded.

[0144]

[0019] The imager according to any one of [1] to

[0018] , wherein the circuitry is configured to, upon receiving a fifth signal (Readout), control the transfer of captured data from the imager to an external processing unit.

[0145]

[0020] The imager according to any one of [1] to

[0019] , wherein the circuitry is configured to, upon receiving a Threshold Setting signal, dynamically adjust the predefined threshold for photon count evaluation.

[0146]

[0021] The imager according to any one of [1] to

[0020] , wherein the circuitry is configured to apply an end-of-frame signal globally at the end of the frame, and if the photon counter is still running, to latch the latest period number as the recorded period value and stop the photon counter.

[0147]

[0022] The imager according to any one of [1] to

[0021] , wherein the circuitry is configured to read out the recorded period number and the photon counter stored in each pixel.

[0148]

[0023] The imager according to any one of [1] to

[0022] , wherein the circuitry comprises period indication signals (Hl, HO) configured to represent the current period number.

[0149]

[0024] The imager according to any one of [1] to

[0023] , wherein the circuitry is configured to implement a margin within an exposure frame to accommodate shot-noise variations and increased photon flux during photon counting.

[0150]

[0025] A high dynamic range imager comprising a plurality of pixels, each pixel including:

[0151] a photon detector (101) configured to detect photons;

[0152] a local photon counter (204) coupled to the photon detector, configured to count detected photons during a frame measurement period, the frame measurement period being divided into consecutive measurement periods of increasing length;

[0153] a threshold comparator (202) coupled to the local photon counter, configured to evaluate the photon count against a predefined threshold (125) at the end of each measurement period;

[0154] a period number register (106) coupled to the threshold comparator, configured to record the period number locally when the photon count exceeds the threshold and to stop the photon counter.

[0155]

[0026] A method for high dynamic range imaging, comprising:detecting photons locally within a pixel during a frame measurement period, wherein the frame measurement period is divided into consecutive measurement periods of increasing length;

[0156] evaluating the photon count against a predefined threshold at the end of each measurement period; and

[0157] recording the period number locally when the photon count exceeds the threshold and stopping the photon counting.

[0158] LIST OF REFERENCE SIGNS

[0159] 101 SPAD system

[0160] 102 Comparator

[0161] 103 SR-flipflop State

[0162] 104 Analog Counter

[0163] 105 Clock Generator (Cl ockGen)

[0164] 106 Memory PeriodMem

[0165] 110 EnableCount signal

[0166] 111 PhotoCount signal (analog)

[0167] 120 RowSelect signal

[0168] 121 Next signal

[0169] 122 Start signal

[0170] 123 Count wire

[0171] 124 End signal

[0172] 125 Trip threshold

[0173] 126 Stop signal

[0174] 200 Image sensor pixel (digital implementation)

[0175] 204 Digital Counter

[0176] 207 Read-out circuit

[0177] 300 Timing diagram (start pulse)301 Next signal pulse

[0178] 302 Stop signal pulse

[0179] 303 EnableCount signal (low state)

[0180] 330 Counter range

[0181] 350 Photon count curve (lower photon rate)

[0182] 351 Photon count curve (higher photon rate)

[0183] 389 Margin for shot-noise variations

[0184] 604 Photon count curve at t3 (edge of threshold)

[0185] 604A Photon count curve (continued counting)

[0186] 604B Photon count curve (stopped counting)

[0187] 630 Counter Voltage Range

[0188] 651 Higher photon flux curve

[0189] 680 Voltage margin

[0190] 700 Pixel Circuit (digital implementation with local counter) 706 Local counter PeriodCounter Mem

[0191] 900 Imaging device ("Imager")

[0192] 901 Controller

[0193] 902 Pixel circuitry (multiple pixels)

Claims

CLAIMS1. A high dynamic range imager comprising circuitry configured to:count detected photons locally within a pixel during a frame measurement period, the frame measurement period being divided into consecutive measurement periods of increasing length;evaluate the photon count against a predefined threshold at the end of each measurement period; andrecord a period number locally when the photon count exceeds the predefined threshold and stop the photon counting.

2. The imager of claim 1 , wherein the circuitry comprises a memory configured to continuously copy a current period number into a latched period register until a first signal (Stop) is received.

3. The imager of claim 1 , wherein the circuitry comprises a local counter configured to generate and keep track of period numbers locally within each pixel.

4. The imager of claim 1, wherein the circuitry is further configured to latch a latest period number and stop the photon counter at the end of the frame if the threshold is not exceeded.

5. The imager of claim 1, wherein the circuitry is configured to perform an evaluation at the end of each period, to check whether during said period the photon counter has surpassed a predefined trip value.

6. The imager of claim 1, wherein the circuitry is configured to continue subsequent evaluations during following measurement periods and keep the photon counter running if a predefined trip value is not surpassed.

7. The imager of claim 1, wherein the circuity comprises a SPAD configured to detect individual photons.

8. The imager of claim 1, wherein the circuitry is configured to stop the photon counter at its latest value by reducing a SPAD’s excess bias to zero and / or by disabling the counter when the predefined threshold is surpassed.

9. The imager of claim 1, wherein the circuitry is configured to receive and process a set of control signals that govern the operation of the photon counting and a comparison with the predefined threshold.

10. The imager of claim 1, wherein the circuitry is configured to, upon receiving a second signal (Next), trigger evaluation of the photon count against the predefined threshold and increment a period counter to transition to the next measurement period.

11. The imager of claim 10, wherein the second signal (Next) is generated globally and provided to all pixels in the array simultaneously, ensuring synchronized transitions between consecutive measurement periods across the entire sensor array.

12. The imager of claim 1, wherein the circuity comprises a digital photon counter and a digital comparator, the digital comparator configured to utilize the most significant bit (MSB) of the digital photon counter to determine if the predefined threshold is exceeded.

13. The imager of claim 12, wherein the digital comparator is configured to generate a first signal (Stop) by AND-gating the MSB with the second signal (Next) pulse to halt the photon counter when the threshold is surpassed.

14. The imager of claim 1, wherein the consecutive measurement periods increase in length according to a predefined factor.

15. The imager of claim 14, wherein the predefined growth factor is less than 2.

16. The imager of claim 1, wherein the circuitry is configured to, upon receiving a third signal (Reset), initialize a photon counter and a digital comparator at the beginning of each imaging cycle.

17. The imager of claim 1, wherein the circuitry is configured to, upon receiving a fourth signal (Start), commence the photon counting process.

18. The imager of claim 1, wherein the circuitry is configured to, upon receiving a first signal (Stop), halt the photon counting when the predefined threshold is exceeded.

19. The imager of claim 1, wherein the circuitry is configured to, upon receiving a fifth signal (Readout), control the transfer of captured data from the imager to an external processing unit.

20. The imager of claim 1, wherein the circuitry is configured to, upon receiving a Threshold Setting signal, dynamically adjust the predefined threshold for photon count evaluation.

21. The imager of claim 1, wherein the circuitry is configured to apply an end-of-frame signal globally at the end of the frame, and if the photon counter is still running, to latch the latest period number as the recorded period value and stop the photon counter.

22. The imager of claim 1, wherein the circuitry is configured to read out the recorded period number and the photon counter stored in each pixel.

23. The imager according to any one of claims 1 to 22, wherein the circuitry is configured to receive period indication signals configured to represent the current period number.

24. The imager of claim 1, wherein the circuitry is configured to implement a margin within an exposure frame to accommodate shot-noise variations and increased photon flux during photon counting.

25. A high dynamic range imager comprising a plurality of pixels, each pixel including:a photon detector configured to detect photons;a local photon counter coupled to the photon detector, configured to count detected photons during a frame measurement period, the frame measurement period being divided into consecutive measurement periods of increasing length;a threshold comparator coupled to the local photon counter, configured to evaluate the photon count against a predefined threshold at the end of each measurement period;a period number register coupled to the threshold comparator, configured to record the period number locally when the photon count exceeds the threshold and to stop the photon counter.

26. A method for high dynamic range imaging, comprising:detecting photons locally within a pixel during a frame measurement period, wherein the frame measurement period is divided into consecutive measurement periods of increasing length;evaluating the photon count against a predefined threshold at the end of each measurement period; andrecording the period number locally when the photon count exceeds the threshold and stopping the photon counting.

Images