Semiconductor device
Patent Information
- Application Number
- PCT/JP2025/010702
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-03-19
- Publication Date
- 2026-09-24
Smart Images
Figure JP2025010702_24092026_PF_FP_ABST
Abstract
Description
Semiconductor device
[0001] The present disclosure relates to a semiconductor device.
[0002] In semiconductor devices called FinFETs (Field Effect Transistors) or nanosheet transistors, there is a technology in which semiconductor layers of mutually different conductivity types are brought into contact with each other and used as a diode. Further, a CFET (Complementary Field Effect Transistor) obtained by stacking two types of nanosheet transistors respectively corresponding to a PMOSFET and an NMOSFET has been proposed.
[0003] US Patent Application Publication No. 2023 / 0284427 Specification, US Patent No. 10504890 Specification, US Patent No. 11532607 Specification, US Patent No. 11075273 Specification, US Patent No. 11764154 Specification
[0004] H. Mertens et al., "Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning", 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 11-16 June 2023; H. Horiguchi et al., "3D Stacked Devices and MOL Innovations for Post-Nanosheet CMOS Scaling", 2023 International Electron Devices Meeting (IEDM), 09-13 December 2023
[0005] When a wiring is arranged on the back surface of a substrate, no detailed study has been conducted on how to form a connection structure between the wiring and a semiconductor structure portion including a diode structure.
[0006] This disclosure provides a semiconductor device that can save space, having a configuration in which semiconductor structures and wiring arranged on opposing surfaces of a substrate are electrically connected.
[0007] Embodiments of the present disclosure include a substrate; a first semiconductor structure disposed on a first surface of the substrate and comprising a plurality of semiconductor layers having different conductivity types and having a diode structure; a second semiconductor structure disposed on the first semiconductor structure and comprising a plurality of semiconductor layers having different conductivity types and having a diode structure; a first wiring disposed on a second surface of the substrate facing the first surface; and a first via penetrating from the first surface to the second surface of the substrate, directly connected to the first semiconductor structure, and electrically connected to the first wiring.
[0008] According to the disclosed technology, a semiconductor device having a configuration in which semiconductor structures and wiring arranged on opposing surfaces of a substrate are electrically connected can be made more space-efficient.
[0009] This is a schematic plan view showing the lower region of the semiconductor device according to the first embodiment. This is a schematic plan view showing the upper region of the semiconductor device according to the first embodiment. This is a schematic cross-sectional view showing the semiconductor device along line III-III shown in Figures 1 and 2. This is a schematic cross-sectional view showing the semiconductor device along line IV-IV shown in Figures 1 and 2. This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment second embodiment. This is a schematic plan view showing the lower region of the semiconductor device according to the second embodiment. This is a schematic plan view showing the upper region of the semiconductor device according to the second embodiment. Figures 17 and 18 show schematic cross-sectional views of a semiconductor device along the XIX-XIX line. Figures 17 and 18 show schematic cross-sectional views of a semiconductor device along the XXA-XXA line. Figures 17 and 18 show schematic cross-sectional views of a semiconductor device along the XXB-XXB line. Figure 17 and 18 show schematic plan views of the lower region of a semiconductor device according to Modification 1 of the second embodiment. Figure 1 shows schematic plan views of the lower region of a semiconductor device according to the third embodiment. Figure 23 shows schematic cross-sectional views of a semiconductor device along the XXIV-XXIV line.
[0010] The embodiments for implementing this disclosure will be described in detail below with reference to the drawings. The embodiments described below are examples for realizing the technical concept of the invention and do not limit this disclosure to the configurations and numerical values described. In each drawing, the same reference numerals are used for the same components, and redundant explanations are omitted as appropriate. The size, positional relationships, etc., of each component shown in each drawing may be exaggerated to facilitate understanding of the invention. Also, for convenience, the size of each component, the distance between multiple components, etc., may differ in each drawing.
[0011] In each drawing, directions may be indicated by mutually orthogonal X, Y, and Z axes. The X direction, parallel to the X axis, corresponds to the width direction of the semiconductor device according to the embodiment. The Y direction, parallel to the Y axis, corresponds to the depth direction of the semiconductor device according to the embodiment. The Z direction, parallel to the Z axis, corresponds to the thickness direction of the semiconductor device according to the embodiment. Directions parallel to the XY plane, which include the X and Y directions, are sometimes referred to as in-plane directions. In the Z direction, the side in which the arrow points is sometimes called "up," and the opposite side of the arrow is sometimes called "down."
[0012] (First Embodiment) An example of the configuration of the semiconductor device 100 according to the first embodiment will be described with reference to Figures 1 to 4. Figure 1 is a schematic plan view showing the lower region of the semiconductor device 100 according to the first embodiment (the region including the first semiconductor structure 20). Figure 2 is a schematic plan view showing the upper region of the semiconductor device 100 according to the first embodiment (the region including the second semiconductor structure 30). In Figures 1 and 2, parts or components that are not actually visible because they overlap with part or all of other components are shown with dashed lines. The same applies to the other plan views. Also, for convenience, in Figures 1 and 2, the first semiconductor structure 20 and the second semiconductor structure 30 are shown with a textured surface. Figure 3 is a schematic cross-sectional view showing the semiconductor device 100 along line III-III shown in Figures 1 and 2. Figure 4 is a schematic cross-sectional view showing the semiconductor device 100 along line IV-IV shown in Figures 1 and 2.
[0013] The semiconductor device 100 according to the first embodiment includes a substrate 10, a first semiconductor structure 20, a second semiconductor structure 30, a first wiring 40, and vias 50a and 50b. In this embodiment, vias 50a and 50b are provided, but one of vias 50a and 50b may be omitted. The semiconductor device 100 may further include other components such as second wirings 60a and 60b and vias 70a to 70c. When describing vias 50a and 50b without distinction, they may be collectively referred to as "via 50". Via 50 is an example of a "first via". When describing second wirings 60a and 60b without distinction, they may be collectively referred to as "second wiring 60". Similarly, when describing vias 70a to 70c without distinction, they may be collectively referred to as "via 70". Via 70 is an example of a "second via".
[0014] The substrate 10 is, for example, a semiconductor substrate such as a single-crystal silicon substrate. Alternatively, the substrate 10 may have a laminated structure composed of multiple layers, such as an SOI (Silicon On Insulator) substrate. The substrate 10 includes a first surface 11 and a second surface 12 facing the first surface 11.
[0015] As shown in Figure 3, the first semiconductor structure 20 is arranged on the first surface 11 of the substrate 10. The first semiconductor structure 20 also comprises a plurality of semiconductor layers having different conductivity types and has a diode structure. The first semiconductor structure 20 comprises semiconductor layer 21, semiconductor layer 22, and semiconductor layer 23. The first semiconductor structure 20 may further comprise semiconductor layer 24. Semiconductor layer 21 is an example of the "first semiconductor layer". Semiconductor layer 22 is an example of the "second semiconductor layer". Semiconductor layer 23 is an example of the "third semiconductor layer". Semiconductor layer 24 is an example of the "seventh semiconductor layer". Note that semiconductor layer 24 may be another example of the "third semiconductor layer", and semiconductor layer 23 may be another example of the "seventh semiconductor layer". Here, "diode structure" means a structure having a pn junction region formed by the contact of two semiconductor layers having different conductivity types.
[0016] As shown in Figure 3, semiconductor layer 21 and semiconductor layer 22 are separated in the in-plane direction. Semiconductor layer 21 and semiconductor layer 22 may have the same conductivity type. However, semiconductor layer 21 and semiconductor layer 22 may have different conductivity types. Semiconductor layer 21 and semiconductor layer 22 have a planar shape, for example, a rectangle, and thickness in the Z direction. Semiconductor layer 21 and semiconductor layer 22 are, for example, silicon layers.
[0017] At least one of semiconductor layer 23 and semiconductor layer 24 is in contact with semiconductor layer 21 and semiconductor layer 22, and has a conductivity type different from at least one of semiconductor layer 21 and semiconductor layer 22. In this embodiment, semiconductor layer 21 and semiconductor layer 22 have the same conductivity type, and semiconductor layer 23 and semiconductor layer 24 have the same conductivity type. Also in this embodiment, semiconductor layer 23 and semiconductor layer 24 have a conductivity type different from semiconductor layer 21 and semiconductor layer 22. The first semiconductor structure 20 has a pn junction between semiconductor layer 23 and at least one of semiconductor layer 21 and semiconductor layer 22. The first semiconductor structure 20 may have a pn junction between semiconductor layer 23 and both semiconductor layer 21 and semiconductor layer 22. However, the conductivity types of semiconductor layer 21, semiconductor layer 22, semiconductor layer 23, and semiconductor layer 24 are not limited thereto. Semiconductor layer 23 and semiconductor layer 24 may have different conductivity types.
[0018] In the example shown in Figure 3, semiconductor layers 23 and 24 are arranged between semiconductor layer 21 and semiconductor layer 22. This allows for space saving in the first semiconductor structure 20. Semiconductor layers 23 and 24 have a planar shape, for example, a rectangle, and thickness in the Z direction. Semiconductor layer 23 is, for example, a silicon layer. Semiconductor layer 24 is, for example, a silicon germanium (SiGe) layer. Semiconductor layer 24 may include a region located at the top of the first semiconductor structure 20.
[0019] The semiconductor layer 23 can be in contact with the semiconductor layers 21 and 22. This forms a pn junction region in the first semiconductor structure 20. On the other hand, in the example shown in Figure 3, an insulating film 25 is placed on the side surface of the semiconductor layer 24. Therefore, the semiconductor layer 24 is not in contact with the semiconductor layers 21 and 22. However, the insulating film 25 may be omitted, and the semiconductor layer 24 may be in contact with the semiconductor layers 21 and 22.
[0020] In the examples shown in Figures 3 and 4, the semiconductor layer 24 covers the semiconductor layer 23. Specifically, the semiconductor layer 24 covers the top surface, bottom surface, and both sides in the Y direction of the semiconductor layer 23. In this case, if the conductivity type of the semiconductor layer 23 is different from that of the semiconductor layer 24, the area of the pn junction in the first semiconductor structure 20 can be further expanded while saving space in the first semiconductor structure 20. The semiconductor layer 23 is a semiconductor layer known as a nanosheet.
[0021] The second semiconductor structure 30 is disposed on the first semiconductor structure 20. The second semiconductor structure 30, like the first semiconductor structure 20, comprises a plurality of semiconductor layers having different conductivity types and has a diode structure. The second semiconductor structure 30, like the first semiconductor structure 20, comprises semiconductor layers 31 and 32 spaced apart in the in-plane direction, and a semiconductor layer 33 disposed between semiconductor layers 31 and 32. The second semiconductor structure 30 may further comprise a semiconductor layer 34. Semiconductor layer 31 is an example of the "fourth semiconductor layer." Semiconductor layer 32 is an example of the "fifth semiconductor layer." Semiconductor layer 33 is an example of the "sixth semiconductor layer." Semiconductor layer 34 is an example of the "eighth semiconductor layer." Note that semiconductor layer 34 may be another example of the "sixth semiconductor layer," and semiconductor layer 33 may be another example of the "eighth semiconductor layer." The semiconductor layer 31 and the semiconductor layer 32 are separated from the semiconductor layer 21 and the semiconductor layer 22 of the first semiconductor structure 20, for example, via an interlayer insulating film.
[0022] In the second semiconductor structure 30, semiconductor layers 33 and 34 are arranged between semiconductor layer 31 and semiconductor layer 32. In the example shown in Figure 3, semiconductor layer 33 is in contact with semiconductor layer 31 and semiconductor layer 32. The second semiconductor structure 30 has a pn junction between semiconductor layer 33 and at least one of semiconductor layer 31 and semiconductor layer 32. The second semiconductor structure 30 may also have a pn junction between semiconductor layer 33 and both semiconductor layer 31 and semiconductor layer 32. On the other hand, semiconductor layer 34 is separated from semiconductor layer 31 and semiconductor layer 32 via an insulating film 35. However, semiconductor layer 34 may be in contact with semiconductor layer 31 and semiconductor layer 32. Semiconductor layer 33 and semiconductor layer 34 may have the same conductivity type or different conductivity types.
[0023] In the example shown in Figure 3, the semiconductor layer 34 includes a region located at the bottom of the second semiconductor structure 30. The semiconductor layer 34 is in contact with the semiconductor layer 24 of the first semiconductor structure 20. The semiconductor layer 34 can have a different conductivity type than the semiconductor layer 24 of the first semiconductor structure 20. For example, the conductivity types of semiconductor layers 21, 22, and 34 are p-type, the conductivity types of semiconductor layers 24, 31, and 32 are n-type, and the conductivity types of semiconductor layers 23 and 33 are arbitrary. This forms a thyristor having semiconductor layers 21 and 22 as anodes, semiconductor layer 34 as a gate, and semiconductor layers 31 and 32 as cathodes. However, the conductivity types of each semiconductor layer are not limited to these. The conductivity types of semiconductor layers 21, 31, 22, 32, 23, 33, and 24, 34 can be appropriately selected so that a thyristor is formed by the first semiconductor structure 20 and the second semiconductor structure 30. Furthermore, the conductivity types of each semiconductor layer can be appropriately selected so that the first semiconductor structure 20 and the second semiconductor structure 30 have a diode structure other than a thyristor. The same applies to the modifications of this embodiment described later.
[0024] The other components of the second semiconductor structure 30 may be the same as those of the first semiconductor structure 20. Therefore, a further detailed explanation of the second semiconductor structure 30 is omitted.
[0025] The first wiring 40 is arranged on the second surface 12 of the substrate 10. In the example shown in Figure 3, the first wiring 40 is arranged below the second surface 12 of the substrate 10. Also in the example shown in Figure 3, the first wiring 40 is electrically connected to the semiconductor layer 21 and semiconductor layer 22 of the first semiconductor structure 20. However, the first wiring 40 may also be electrically connected to the semiconductor layer 24 of the first semiconductor structure 20. Furthermore, the first wiring 40 may also be electrically connected to the semiconductor layer 23.
[0026] The first wiring 40 has a metallic material such as copper, ruthenium, molybdenum, cobalt, iridium, or tantalum, or an alloy material containing these metals.
[0027] The via 50 penetrates from the first surface 11 to the second surface of the substrate 10. The via 50 may include the metallic or alloy material exemplified in the first wiring 40.
[0028] The via 50 is directly connected to the first semiconductor structure 20 and is also electrically connected to the first wiring 40. Alternatively, the via 50 may be directly connected to both the first semiconductor structure 20 and the first wiring 40. In the example shown in Figure 3, via 50a is directly connected to both the semiconductor layer 21 of the first semiconductor structure 20 and the first wiring 40. Via 50b is directly connected to both the semiconductor layer 22 of the first semiconductor structure 20 and the first wiring 40. Unlike the example shown in Figure 3, via 50 may also be directly connected to both the semiconductor layer 23 and semiconductor layer 24, including the region located at the bottom of the first semiconductor structure 20, and the first wiring 40. Here, "directly connected" means that the members A and B to be connected are connected without the need for other members. The via 50 may be made of a metallic material or alloy material as exemplified by the first wiring 40.
[0029] The first wiring 40 is arranged on the second surface 12 of the substrate 10. In addition, the via 50 is directly connected to the first semiconductor structure 20 and electrically connected to the first wiring 40. Therefore, when electrically connecting the first semiconductor structure 20 and the first wiring 40, which are arranged on the first surface 11 and second surface 12 of the substrate 10, respectively, it is possible to reduce the space required for the semiconductor device 100. Furthermore, it is possible to prevent an increase in the wiring density on the first surface 11 of the substrate 10. As a result, while reducing the space required for the semiconductor device 100, it is possible to reduce the possibility of short circuits between wirings arranged on the first surface 11 of the substrate 10.
[0030] The second wiring 60 is arranged on the second semiconductor structure 30. In the example shown in Figure 2, the second wiring 60a is electrically connected to the semiconductor layer 31 and semiconductor layer 32 of the second semiconductor structure 30. The second wiring 60b may be electrically connected to the semiconductor layer 33 and semiconductor layer 34, including the region located at the top of the second semiconductor structure 30. In the examples shown in Figures 2 and 3, the second wiring 60b is electrically connected to the semiconductor layer 34 of the second semiconductor structure 30. The second wiring 60 may have a metallic material as exemplified by the first wiring 40, or an alloy material containing these metals.
[0031] Via 70a is directly connected to the semiconductor layer 31 and the second wiring 60a of the second semiconductor structure 30. Via 70b is directly connected to the semiconductor layer 32 and the second wiring 60a of the second semiconductor structure 30. Via 70c is directly connected to the semiconductor layer including the uppermost region of the second semiconductor structure 30 among the semiconductor layers 33 and 34, and to the second wiring 60b. In the example shown in Figures 2 and 3, via 70c is directly connected to the semiconductor layer 34 and the second wiring 60b of the second semiconductor structure 30. In other words, each via 70 is directly connected to the semiconductor layer 31, semiconductor layer 32, and at least one of the semiconductor layers 33 and 34 of the second semiconductor structure 30, and to the second wiring 60. This makes it possible to save space in the semiconductor device 100.
[0032] (Manufacturing Method) Next, an example of a manufacturing method for the semiconductor device 100 according to the first embodiment will be described with reference to Figures 5 to 11. Figures 5 to 11 are cross-sectional views illustrating an example of a manufacturing method for the semiconductor device 100 according to the first embodiment.
[0033] First, as shown in Figure 5, a laminated film 200 is formed on the substrate 10. The laminated film 200 includes a plurality of semiconductor layers 200a and a plurality of semiconductor layers 200b. Each of the plurality of semiconductor layers 200a and the plurality of semiconductor layers 200b contains impurities and has a predetermined conductivity type. Semiconductor layer 200b is a sacrificial layer and has different etching selectivity from semiconductor layer 200a. For example, if semiconductor layer 200a is a silicon layer, semiconductor layer 200b is a silicon germanium layer. The laminated film 200 is formed, for example, using an epitaxial method.
[0034] Next, after placing a mask over a portion of the laminated film 200, the areas of the laminated film 200 not covered by the mask are removed, as shown in Figure 6. This forms the laminated film 201 on the substrate 10. Of the multiple semiconductor layers 200a included in the laminated film 201, the multiple semiconductor layers 200a located below the intermediate portion C in a cross-sectional view are semiconductor layers 23 provided by the first semiconductor structure 20 (see Figure 3). Also, of the multiple semiconductor layers 200a included in the laminated film 201, the multiple semiconductor layers 200a located above the intermediate portion C in a cross-sectional view are semiconductor layers 33 provided by the second semiconductor structure 30 (see Figure 3).
[0035] Next, after removing the mask covering the laminated film 201, insulating films 25 and 35 are formed on the side surface of the semiconductor layer 200b, as shown in Figure 7. At this time, in the laminated film 201, a portion of the semiconductor layer 200b may be etched before forming the insulating films 25 and 35, so that the side surface of the semiconductor layer 200b is located inside the side surface of the semiconductor layer 200a. The insulating films 25 and 35 are formed, for example, using the CVD (Chemical Vapor Deposition) method.
[0036] Next, after forming a mask layer M1 on the laminated film 201, semiconductor layers 21, 31 and semiconductor layers 22, 32 are formed on the side surfaces of the laminated film 201, as shown in Figure 8. The semiconductor layers 21, 31 and semiconductor layers 22, 32 are formed, for example, using an epitaxial method.
[0037] Next, the mask layer M1 is removed to expose the semiconductor layer 200b located at the top of the laminated film 201, as shown in Figure 9. Subsequently, an interlayer insulating film may be formed outside the laminated film 201 and outside the semiconductor layers 21, 31 and 22, 32. After that, the semiconductor layer 200b of the laminated film 201 may be selectively removed using, for example, an etching method.
[0038] Next, as shown in Figure 10, semiconductor layers 24 and 34 are formed in the gap after the semiconductor layer 200b of the laminated film 201 has been removed. The semiconductor layers 24 and 34 are formed, for example, using an epitaxial method. Note that semiconductor layer 200a is denoted as semiconductor layer 23 or semiconductor layer 33 in Figure 10. This forms the first semiconductor structure 20 and the second semiconductor structure 30.
[0039] Next, after forming holes that penetrate from the first surface 11 to the second surface 12 of the substrate 10, vias 50a and 50b are formed as shown in Figure 11. Also, as shown in Figure 11, the first wiring 40 is formed on the second surface 12 of the substrate 10.
[0040] Furthermore, a second wiring 60 and a via 70 are formed on the second semiconductor structure 30. The method for forming the second wiring 60 may be the same as the method for forming the first wiring 40. The method for forming the via 70 may be the same as the method for forming the via 50. The timing for forming the second wiring 60 and the via 70 may be the same as the timing for forming the first wiring 40 and the via 50, or it may be before or after the timing for forming the first wiring 40 and the via 50.
[0041] The semiconductor device 100 can be manufactured through these steps. However, the method for manufacturing the semiconductor device 100 may further include steps different from those described above.
[0042] (Modification 1 of the First Embodiment) Next, with reference to Fig. 12, an example of the configuration of a semiconductor device 100A according to Modification 1 of the first embodiment will be described. Fig. 12 is a cross-sectional view schematically showing the semiconductor device 100A according to Modification 1 of the first embodiment. In Modification 1, the same reference numerals are given to constituent members similar to those in the first embodiment, and the description thereof will be omitted as appropriate.
[0043] As shown in Fig. 12, in Modification 1, the semiconductor layer 24a included in the first semiconductor structure portion 20a and the semiconductor layer 34a included in the second semiconductor structure portion 30a are provided integrally. The semiconductor layer 24a included in the first semiconductor structure portion 20a and the semiconductor layer 34a included in the second semiconductor structure portion 30a have the same conductivity type. Accordingly, compared with a case where the semiconductor layer 24a included in the first semiconductor structure portion 20a and the semiconductor layer 34a included in the second semiconductor structure portion 30a are provided separately, the configuration of the first semiconductor structure portion 20a and the second semiconductor structure portion 30a can be simplified, and the cost can be reduced. Note that the semiconductor layer 24a is an example of "the seventh semiconductor layer". The semiconductor layer 34a is an example of "the eighth semiconductor layer".
[0044] In the example shown in Fig. 12, in the first semiconductor structure portion 20a, the semiconductor layer 21 and the semiconductor layer 22 have the same conductivity type as each other. However, the semiconductor layer 21 and the semiconductor layer 22 may have different conductivity types from each other. In this case, the formation of one of the via 50a and the via 50b may be omitted, and the semiconductor layer 21 and the semiconductor layer 22 may be electrically isolated from each other. In addition, the semiconductor layer 23a and the semiconductor layer 24a may have different conductivity types from each other. Note that the semiconductor layer 23a is an example of "the third semiconductor layer".
[0045] In the second semiconductor structure portion 30a, the semiconductor layer 31 and the semiconductor layer 32 may have the same conductivity type as each other. In addition, the semiconductor layer 31 and the semiconductor layer 32 may have different conductivity types from each other. In this case, the semiconductor layer 31 and the semiconductor layer 32 may be electrically isolated from each other. In addition, the semiconductor layer 33a and the semiconductor layer 34a may have different conductivity types. Note that the semiconductor layer 33a is an example of "the sixth semiconductor layer".
[0046] (Modification 2 of the First Embodiment) Next, an example configuration of a semiconductor device 100B according to Modification 2 of the first embodiment will be described with reference to FIG. 13. FIG. 13 is a cross-sectional view schematically illustrating the semiconductor device 100B according to Modification 2 of the first embodiment. In Modification 2, constituent members that are the same as those in the first embodiment and the above-mentioned modifications are denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.
[0047] As shown in FIG. 13, in the first semiconductor structure portion 20b, the insulating film 25 disposed on a side surface of the semiconductor layer 24 can be omitted. In the example shown in FIG. 13, the semiconductor layer 24 is in contact with each of the semiconductor layer 21 and the semiconductor layer 22 included in the first semiconductor structure portion 20b. Further, the semiconductor layer 24 may have a conductivity type different from that of the semiconductor layer 21 and the semiconductor layer 22, and may have the same conductivity type as that of the semiconductor layer 23. This makes it possible to widen the region of the pn junction in the first semiconductor structure portion 20b. From the viewpoint of widening the region of the pn junction, it is preferable that the semiconductor layer 21 and the semiconductor layer 22 have the same conductivity type. However, the semiconductor layer 21 and the semiconductor layer 22 may have different conductivity types. In this case, formation of one of the via 50a and the via 50b may be omitted, and the semiconductor layer 21 and the semiconductor layer 22 may be electrically isolated from each other.
[0048] As shown in FIG. 13, in the second semiconductor structure portion 30b, the insulating film 35 disposed on a side surface of the semiconductor layer 34 can be omitted. In the example shown in FIG. 13, the semiconductor layer 34 is in contact with each of the semiconductor layer 31 and the semiconductor layer 32 included in the second semiconductor structure portion 30b. Other configurations of the second semiconductor structure portion 30b may be the same as those of the first semiconductor structure portion 20b. Therefore, further detailed description of the second semiconductor structure portion 30b is omitted.
[0049] (Modification 3 of the First Embodiment) Next, an example configuration of a semiconductor device 100C according to Modification 3 of the first embodiment will be described with reference to FIG. 14. FIG. 14 is a cross-sectional view schematically illustrating the semiconductor device 100C according to Modification 3 of the first embodiment. In Modification 3, constituent members that are the same as those in the first embodiment and the above-mentioned modifications are denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.
[0050] As shown in Figure 14, in the first semiconductor structure 20c, multiple semiconductor layers 23c and multiple semiconductor layers 24c are stacked alternately. At this time, both sides of semiconductor layer 23c in the Y direction are not covered by semiconductor layer 24c. That is, the sides of semiconductor layer 23c in the X and Y directions are exposed. Note that semiconductor layer 23c is an example of a "third semiconductor layer". Semiconductor layer 24c is an example of a "seventh semiconductor layer".
[0051] In the second semiconductor structure 30c, multiple semiconductor layers 33c and multiple semiconductor layers 34c are stacked alternately. At this time, both sides of semiconductor layer 33c in the Y direction are not covered by semiconductor layer 34c. That is, the sides of semiconductor layer 33c in the X and Y directions are exposed. Semiconductor layer 33c is an example of a "sixth semiconductor layer". Semiconductor layer 34c is an example of an "eighth semiconductor layer".
[0052] (Modification 4 of the First Embodiment) Next, an example of the configuration of the semiconductor device 100D according to Modification 4 of the First Embodiment will be described with reference to Figure 15. Figure 15 is a schematic cross-sectional view showing the semiconductor device 100D according to Modification 4 of the First Embodiment. In Modification 4, the same reference numerals are used for components that are the same as those in the First Embodiment and the Modification described above, and their descriptions are omitted as appropriate.
[0053] As shown in Figure 15, the semiconductor device 100D comprises at least three first wirings 40 (40d1 to 40d3) and at least three vias 50 (50d1 to 50d3). The semiconductor device 100D also comprises at least three second wirings 60 (60d1 to 60d3) and at least three vias 70 (70d1 to 70d3).
[0054] In the example shown in Figure 15, via 50d1 is directly connected to the semiconductor layer 21 and the first wiring 40d1, respectively. Via 50d2 is directly connected to the semiconductor layer 22 and the first wiring 40d2, respectively. Via 50d3 is directly connected to the semiconductor layer 23 and the semiconductor layer 24, which includes the region located at the bottom of the first semiconductor structure 20, and to the first wiring 40d3, respectively. In the example shown in Figure 15, via 50d3 is directly connected to the semiconductor layer 24 and the first wiring 40d3, respectively.
[0055] In the example shown in Figure 15, via 70d1 is directly connected to the semiconductor layer 31 and the second wiring 60d1, respectively. Via 70d2 is directly connected to the semiconductor layer 32 and the second wiring 60d2, respectively. Via 70d3 is directly connected to the semiconductor layer 33 and the semiconductor layer 34, which includes the region located at the top of the second semiconductor structure 30, and to the second wiring 60d3, respectively. In the example shown in Figure 15, via 70d3 is directly connected to the semiconductor layer 34 and the second wiring 60d3, respectively.
[0056] (Second Embodiment) Next, an example of the configuration of the semiconductor device 100E according to the second embodiment will be described with reference to Figures 16 to 20. Figure 16 is a circuit diagram showing an example of the circuit configuration of the semiconductor device 100E according to the second embodiment. Figure 17 is a schematic plan view showing the lower region of the semiconductor device 100E according to the second embodiment (the region including the first semiconductor structure 20e). Figure 18 is a schematic plan view showing the upper region of the semiconductor device 100E according to the second embodiment (the region including the second semiconductor structure 30e). For convenience, in Figures 17 and 18, the first semiconductor structure 20e, the second semiconductor structure 30e, the transistor 80a, and the transistor 80b are shown with a textured surface. Figure 19 is a schematic cross-sectional view showing the semiconductor device 100E along the XIX-XIX line shown in Figures 17 and 18. Figure 20A is a schematic cross-sectional view showing the semiconductor device 100E along the XXA-XXA line shown in Figures 17 and 18. Figure 20B is a schematic cross-sectional view showing the semiconductor device 100E along the XXB-XXB line shown in Figures 17 and 18. In the second embodiment, components similar to those in the first embodiment and the modified examples described above are denoted by the same reference numerals, and their descriptions are omitted as appropriate.
[0057] The semiconductor device 100E according to the second embodiment includes a substrate 10, a first semiconductor structure 20e, a second semiconductor structure 30e, an insulating member 37, first wiring 40 (40a, 40b), vias 50 (50a, 50b, 50e), second wiring 60, via 70, transistor 80a, and transistor 80b. The semiconductor device 100E may further include other components such as vias 53, 55, 57, via 73, and wiring 90 (90a, 90b). Wiring 90 is an example of a "third wiring". In the second embodiment, transistors 80a and 80b, as well as connecting members connected to transistors 80a and 80b such as vias 53, 55, 57, via 73, and wiring 90b, can be omitted as appropriate.
[0058] In the semiconductor device 100E, an insulating member 37 is positioned between the first semiconductor structure 20e and the second semiconductor structure 30e (see Figure 19). Therefore, in the semiconductor device 100E, there is no region where the first semiconductor structure 20e and the second semiconductor structure 30e are directly connected. In this embodiment, the first semiconductor structure 20e and the second semiconductor structure 30e each function as diodes. Transistors 80a and 80b function as different types of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). In this embodiment, transistor 80a functions as a PMOSFET and transistor 80b functions as an NMOSFET. However, transistor 80a may function as an NMOSFET and transistor 80b may function as a PMOSFET.
[0059] In the example shown in Figure 16, the first semiconductor structure 20e is connected to node N1, which is electrically connected to the output terminal 72, and to the second power line VDD. The second semiconductor structure 30e is connected to the first power line VSS and to node N1. The voltage of the second power line VDD is higher than the voltage of the first power line VSS. In the first semiconductor structure 20e, the direction from node N1 toward the second power line VDD is the forward direction. In the second semiconductor structure 30e, the direction from the first power line VSS toward node N1 is the forward direction.
[0060] In the example shown in Figure 16, an inverter having transistors 80a and 80b is provided between the first power line VSS and the second power line VDD. The source, gate, and drain of transistor 80a are electrically connected to the second power line VDD, input terminal 74, and output terminal 72, respectively. The source, gate, and drain of transistor 80b are electrically connected to the first power line VSS, input terminal 74, and output terminal 72, respectively. Transistors 80a and 80b are stacked in the Z direction to form a CFET.
[0061] Multiple first wirings 40 (40a, 40b) are arranged on the second surface 12 of the substrate 10. As shown in Figure 17, the first wiring 40a is electrically connected to the semiconductor layers 21e and 22e of the first semiconductor structure 20e via vias 50a and 50b. In this embodiment, the semiconductor layers 21e and 22e correspond to the anode of the first semiconductor structure 20e. Semiconductor layer 21e is an example of a "first semiconductor layer". Semiconductor layer 22e is an example of a "second semiconductor layer". The first wiring 40a is also electrically connected to the semiconductor layer 82a of the transistor 80a via via 53. In this embodiment, the semiconductor layer 82a corresponds to the drain of the transistor 80a. The first wiring 40a is electrically connected to the output terminal 72.
[0062] The first wiring 40b is electrically connected to the semiconductor layer 24e of the first semiconductor structure 20e via via 50e. In this embodiment, the semiconductor layer 24e corresponds to the cathode of the first semiconductor structure 20e. The semiconductor layer 24e covers the semiconductor layer 23e. The semiconductor layer 23e is an example of a "third semiconductor layer". The semiconductor layer 24e is an example of a "seventh semiconductor layer". The first wiring 40b is also electrically connected to the semiconductor layer 81a of the transistor 80a via via 55. In this embodiment, the semiconductor layer 81a corresponds to the source of the transistor 80a. The first wiring 40b is electrically connected to the second power line VDD.
[0063] By arranging the multiple first wirings 40, which are electrically connected to the first semiconductor structure 20e and the transistor 80a, on the second surface 12 of the substrate 10, it is possible to prevent an increase in the wiring density on the first surface 11 of the substrate 10. As a result, the semiconductor device 100E can be made more compact.
[0064] Other wiring 41 may be arranged on the second surface 12 of the substrate 10. The wiring 41 is electrically connected to the gate electrode 84a of the transistor 80a via 57. The wiring 41 is electrically connected to the input terminal 74.
[0065] As shown in Figure 18, the second wiring 60 is electrically connected to the semiconductor layer 34e of the second semiconductor structure 30e via a via 70. In this embodiment, the semiconductor layer 34e corresponds to the anode of the second semiconductor structure 30e. The semiconductor layer 34e is placed between the semiconductor layer 31e and the semiconductor layer 32e. The semiconductor layer 34e covers the semiconductor layer 33e. The semiconductor layer 31e is an example of a "fourth semiconductor layer". The semiconductor layer 32e is an example of a "fifth semiconductor layer". The semiconductor layer 33e is an example of a "sixth semiconductor layer". The semiconductor layer 34e is an example of an "eighth semiconductor layer". The second wiring 60 is also electrically connected to the semiconductor layer 81b of the transistor 80b via a via 73. In this embodiment, the semiconductor layer 81b corresponds to the source of the transistor 80b. The second wiring 60 is electrically connected to the first power line VSS.
[0066] As shown in Figures 20A and 20B, the wiring 90a electrically connects the first semiconductor structure 20e and the second semiconductor structure 30e. As shown in Figure 20A, the wiring 90a extends in the Z-axis direction. Also, as shown in Figure 20B, for example, a portion 90a1 of the wiring 90a at the same height as the first semiconductor structure 20e is connected to the semiconductor layer 21e via wiring 92, and a portion 90a2 at the same height as the second semiconductor structure 30e is connected to the semiconductor layer 31e via wiring 93. As shown in Figure 20B, wiring 92 is positioned between wiring 90a and the semiconductor layer 21e, and wiring 93 is positioned between wiring 90a and the semiconductor layer 31e. Also, as shown in Figures 17 and 18, wiring 92 may be positioned to connect wiring 90a and the semiconductor layer 22e, and wiring 93 may be positioned to connect wiring 90a and the semiconductor layer 32e. In the examples shown in Figures 17, 18, and 20A and 20B, the wiring 90a electrically connects the anode (semiconductor layer 21e, semiconductor layer 22e) of the first semiconductor structure 20e to the cathode (semiconductor layer 31e, semiconductor layer 32e) of the second semiconductor structure 30e. In this example, semiconductor layer 34e, semiconductor layer 21e, and semiconductor layer 22e have a p-type conductivity, while semiconductor layer 24e, semiconductor layer 31e, and semiconductor layer 32e have an n-type conductivity. An example of wiring 90a is MRW (Middle Routing Wire). However, the configuration of wiring 90a is not limited to this.
[0067] The wiring 90b electrically connects the drain (semiconductor layer 82a) of transistor 80a and the drain (semiconductor layer 82b) of transistor 80b. The configuration of the wiring 90b may be the same as that of the wiring 90a.
[0068] Next, with reference to Figure 19, an example of the first semiconductor structure 20e, the second semiconductor structure 30e, the transistor 80a, and the transistor 80b will be described in detail. Note that only the configurations of the first semiconductor structure 20e and the second semiconductor structure 30e that differ from those of the first embodiment will be described.
[0069] As shown in Figure 19, in this embodiment, an insulating member 37 is placed between the uppermost part of the semiconductor layer 24e of the first semiconductor structure 20e and the lowermost part of the semiconductor layer 34e of the second semiconductor structure 30e. That is, the semiconductor layer 24e of the first semiconductor structure 20e and the semiconductor layer 34e of the second semiconductor structure 30e are not in contact. By arranging the first semiconductor structure 20e, the insulating member 37, and the second semiconductor structure 30e in this order in the Z direction, multiple diodes corresponding to the first semiconductor structure 20e and the second semiconductor structure 30e can be compactly stacked. This makes it possible to save space in the semiconductor device 100E. The insulating member 37 may be an insulating film such as silicon oxide or silicon nitride.
[0070] The transistor 80a is positioned on the first surface 11 of the substrate 10, spaced apart from the first semiconductor structure 20e in the in-plane direction. In the example shown in Figure 19, the transistor 80a comprises a semiconductor layer 81a, a semiconductor layer 82a, a semiconductor layer 83a, and a gate electrode 84a. The semiconductor layers 81a, 82a, 83a, and 84a have a planar shape, for example, that is rectangular, and have thickness in the Z direction.
[0071] In the example shown in Figure 19, the transistor 80a may further include a gate insulating film 85a and an insulating film 86a disposed between the gate insulating film 85a and the semiconductor layer 81a and the semiconductor layer 82a, respectively.
[0072] The semiconductor layer 81a and the semiconductor layer 82a are arranged spaced apart in the in-plane direction on the first surface 11 of the substrate 10. In this embodiment, the semiconductor layer 81a corresponds to the source of the transistor 80a. The semiconductor layer 82a corresponds to the drain of the transistor 80a. However, the semiconductor layer 81a may correspond to the drain of the transistor 80a, and the semiconductor layer 82a may correspond to the source of the transistor 80a.
[0073] Semiconductor layers 81a and 82a have the same conductivity type (p-type in this embodiment). Semiconductor layer 83a has a different conductivity type (n-type in this embodiment) from semiconductor layers 81a and 82a. Semiconductor layers 81a, 82a, and 83a are, for example, silicon layers.
[0074] The semiconductor layer 83a and the gate electrode 84a are arranged between the semiconductor layer 81a and the semiconductor layer 82a. The semiconductor layer 83a is in contact with the semiconductor layers 81a and 82a. Furthermore, the semiconductor layer 83a is covered by the gate electrode 84a. Specifically, the semiconductor layer 83a is covered by the gate electrode 84a via the gate insulating film 85a. For example, the top surface, bottom surface, and both sides in the Y direction of the semiconductor layer 83a are covered by the gate electrode 84a. The semiconductor layer 83a is a semiconductor layer known as a nanosheet.
[0075] The gate electrode 84a may be a semiconductor layer such as polysilicon, or it may be a metal layer or an alloy layer. When a voltage is applied to the gate electrode 84a, current flows through the semiconductor layer 83a located between the semiconductor layer 81a and the semiconductor layer 82a. As a result, the transistor 80a functions as a MOSFET.
[0076] As shown in Figure 19, transistor 80b is placed on transistor 80a. Like transistor 80a, transistor 80b may also include semiconductor layers 81b, 82b, 83b, and gate electrode 84b. Transistor 80b functions as a MOSFET. In this embodiment, transistor 80b is an NMOSFET. However, transistor 80b may also be a PMOSFET.
[0077] In the example shown in Figure 19, the transistor 80b may further include a gate insulating film 85b and an insulating film 86b disposed between the gate insulating film 85b and the semiconductor layer 81b and the semiconductor layer 82b, respectively.
[0078] The gate electrode 84b of transistor 80b is provided integrally with the gate electrode 84a of transistor 80a. However, the gate electrode 84b of transistor 80b may be provided separately from the gate electrode 84a of transistor 80a.
[0079] The conductivity type (n-type in this embodiment) of semiconductor layers 81b and 82b of transistor 80b is different from that of semiconductor layers 81a and 82a of transistor 80a. Furthermore, the conductivity type (p-type in this embodiment) of semiconductor layer 83b of transistor 80b is different from that of semiconductor layer 83a of transistor 80a. Other configurations of transistor 80b may be the same as those of transistor 80a.
[0080] (Manufacturing Method) Next, an example of a manufacturing method for the semiconductor device 100E according to the second embodiment will be described. For example, a first semiconductor structure 20e, an insulating member 37, and a second semiconductor structure 30e are formed stacked on the first surface 11 of the substrate 10. The first semiconductor structure 20e, the insulating member 37, and the second semiconductor structure 30e are formed, for example, using a known film formation method. Next, wiring 90a is formed to electrically connect the first semiconductor structure 20e and the second semiconductor structure 30e.
[0081] Furthermore, a multilayer film is formed on another location on the first surface 11 of the substrate 10, including a semiconductor layer 83a of transistor 80a, a first sacrificial layer, a semiconductor layer 83b of transistor 80b, and a second sacrificial layer. The multilayer film includes portions in which a plurality of semiconductor layers 83a and a plurality of first sacrificial layers are stacked alternately, and portions in which a plurality of semiconductor layers 83b and a plurality of second sacrificial layers are stacked alternately.
[0082] Next, semiconductor layers 81a and 82a of transistor 80a, and semiconductor layers 81b and 82b of transistor 80b are formed on the side surface of the laminated film. Next, the first sacrificial layer and the second sacrificial layer are selectively removed. Next, the gate electrode 84a and gate insulating film 85a of transistor 80a, and the gate electrode 84b and gate insulating film 85b of transistor 80b are formed in the gap after the first and second sacrificial layers have been removed. The semiconductor layers 81a, 81b, semiconductor layers 82a, 82b, semiconductor layers 83a, 83b, gate electrode 84a, 84b, and gate insulating films 85a, 85b are formed, for example, using a known film formation method.
[0083] Next, vias 53, 55, and 57 are formed to electrically connect transistor 80a to the first wiring 40. Furthermore, via 73 is formed to electrically connect transistor 80b to the second wiring 60.
[0084] The semiconductor device 100E can be manufactured through these steps. However, the method for manufacturing the semiconductor device 100E may further include steps different from those described above.
[0085] (Modification 1 of the Second Embodiment) Next, an example of the configuration of a semiconductor device according to Modification 1 of the Second Embodiment will be described with reference to Figure 21. Figure 21 is a schematic plan view showing the lower region of the semiconductor device according to Modification 1 of the Second Embodiment (the region including the first semiconductor structure 20e and the transistor 80a). In Modification 1 of the Second Embodiment, the same reference numerals are used for components that are the same as those in the First Embodiment, the Second Embodiment, and the aforementioned modifications, and their descriptions are omitted as appropriate.
[0086] As shown in Figure 21, the semiconductor device may further include a resistive element 87. In the example shown in Figure 21, the resistive element 87 is electrically connected to the anode of the first semiconductor structure 20e and to the drain of the transistor 80a.
[0087] In the example shown in Figure 21, the resistive element 87 is arranged on the second surface 12 of the substrate 10. The resistive element 87 also includes a plurality of patterns 87a to 87g that are electrically connected to the first semiconductor structure 20e and the transistor 80a, respectively. Specifically, pattern 87a is electrically connected to the drains of transistor 80a and transistor 80b, and pattern 87g is electrically connected to the first wiring 40a. As a result, the resistive element 87 is positioned between transistors 80a and 80b and the first wiring 40a. The plurality of patterns 87a to 87g can be made of a metallic material or an alloy material. Furthermore, the plurality of patterns 87a to 87g may be electrically connected via connecting members that include vias penetrating the substrate 10 and wiring arranged on the second surface 12 of the substrate 10. This makes it possible to save space in the semiconductor device including the resistive element 87 without increasing the wiring density on the first surface 11 of the substrate 10. However, the configuration of the resistive element 87 is not limited to the example shown in Figure 21. The first wiring 40b and wiring 41 are, for example, positioned below the multiple patterns 87a to 87g.
[0088] (Third Embodiment) Next, an example of a semiconductor device 100G according to the third embodiment will be described with reference to Figures 22 to 24. Figure 22 is a schematic plan view showing the lower region of the semiconductor device 100G according to the third embodiment (the region including the first semiconductor structure 20g and the transistor 80a). Figure 23 is a schematic plan view showing the upper region of the semiconductor device 100G according to the third embodiment (the region including the second semiconductor structure 30g and the transistor 80b). For convenience, in Figures 22 and 23, the first semiconductor structure 20g, the second semiconductor structure 30g, the transistor 80a, and the transistor 80b are shown with a textured surface. Figure 24 is a schematic cross-sectional view showing the semiconductor device 100G along line XXIV-XXIV shown in Figures 22 and 23. In the third embodiment, the same reference numerals are used for components similar to those in the first embodiment, the second embodiment, and the modified examples described above, and their descriptions are omitted as appropriate.
[0089] The semiconductor device 100G according to the third embodiment comprises a first semiconductor structure 20g and a second semiconductor structure 30g, each including a structure called a gated diode. As shown in Figure 24, the first semiconductor structure 20g is directly connected to the second semiconductor structure 30g. The semiconductor device 100G according to the third embodiment may further include other components such as transistors 80a and 80b. In the third embodiment as well, transistors 80a and 80b may be omitted as appropriate.
[0090] The first semiconductor structure 20g comprises a semiconductor layer 21g, a semiconductor layer 22g, a semiconductor layer 23g, and a first conductor layer 291. Semiconductor layer 21g is an example of a "first semiconductor layer". Semiconductor layer 22g is an example of a "second semiconductor layer". Semiconductor layer 23g is an example of a "third semiconductor layer". The first semiconductor structure 20g may also include a first insulating film 292 disposed between the first conductor layer 291 and each of the semiconductor layers 21g, 22g, and 23g. Furthermore, the first semiconductor structure 20g may also include an insulating film 25g disposed between the first insulating film 292 and each of the semiconductor layers 21g and 22g.
[0091] The semiconductor layer 21g and semiconductor layer 22g have different conductivity types. In this embodiment, the conductivity type of semiconductor layer 21g is p-type, and the conductivity type of semiconductor layer 22g is n-type. Semiconductor layer 23g is in contact with semiconductor layers 21g and 22g, and has a conductivity type different from one of semiconductor layers 21g and 22g. In this embodiment, the conductivity type of semiconductor layer 23g is p-type. However, the conductivity types of semiconductor layers 21g, 22g, and 23g are not limited to these.
[0092] The first conductor layer 291 includes a region located at the top of the first semiconductor structure 20g. The first conductor layer 291 is integrally provided with the second conductor layer 295, which includes a region located at the bottom of the second semiconductor structure 30g. This simplifies the structure of the first semiconductor structure 20g and the second semiconductor structure 30g, thereby reducing costs. The first conductor layer 291 can have a configuration similar to that of the gate electrode 84a of the transistor 80a.
[0093] The semiconductor layer 23g is covered by a first insulating film 292 and a first conductive layer 291. For example, the top surface, bottom surface, and both sides in the Y direction of the semiconductor layer 23g are covered by the first insulating film 292 and the first conductive layer 291. The semiconductor layer 23g is a semiconductor layer known as a nanosheet.
[0094] The vias 50 (50g1, 50g2) are directly connected to the first semiconductor structure 20g and are also electrically connected to the first wiring 40 (40a, 40b). As shown in Figure 22, via 50g1 is directly connected to the semiconductor layer 21g and the first wiring 40a of the first semiconductor structure 20g. Via 50g2 is directly connected to the semiconductor layer 22g and the first wiring 40b of the first semiconductor structure 20g. This makes it possible to save space in the semiconductor device 100G when electrically connecting the first semiconductor structure 20g and the first wiring 40 which are arranged on the first surface 11 and the second surface 12 of the substrate 10, respectively.
[0095] As shown in Figure 24, the second semiconductor structure 30g comprises a semiconductor layer 31g, a semiconductor layer 32g, a semiconductor layer 33g, and a second conductor layer 295. Semiconductor layer 31g is an example of a "fourth semiconductor layer". Semiconductor layer 32g is an example of a "fifth semiconductor layer". Semiconductor layer 33g is the position of a "sixth semiconductor layer". The second conductor layer 295 includes a region located at the bottom of the second semiconductor structure 30g. The second semiconductor structure 30g comprises a second insulating film 296. Semiconductor layer 33g is covered by the second insulating film 296 and the second conductor layer 295. The second conductor layer 295 may have a configuration similar to the gate electrode 84b of the transistor 80b.
[0096] The second semiconductor structure 30g may be electrically connected to the first semiconductor structure 20g via wiring 90g. Wiring 90g is an example of a "third wiring". Other configurations of the second semiconductor structure 30g may be the same as those of the first semiconductor structure 20g.
[0097] As shown in Figure 23, via 70 (70g) is directly connected to the semiconductor layer 31g and the second wiring 60 of the second semiconductor structure 30g.
[0098] Although the present invention has been described above based on various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified as long as they do not impair the spirit of the present invention, and can be appropriately determined according to their application.
[0099] 100, 100A, 100B, 100C, 100D, 100E, 100G Semiconductor device 10 Substrate 11 First surface 12 Second surface 20, 20a, 20b, 20c, 20e, 20g First semiconductor structure 21, 21e, 21g Semiconductor layer 22, 22e, 22g Semiconductor layer 23, 23a, 23c, 23g Semiconductor layer 24, 24a, 24c, 24e Semiconductor layer 30, 30a, 30b, 30c, 30e, 30g Second semiconductor structure 31, 31e, 31g Semiconductor layer 32, 32e, 32g Semiconductor layer 33, 33a, 33c, 33g Semiconductor layer 34, 34a, 34c, 34e Semiconductor layer 37 Insulating member 40, 40a, 40b First wiring 50, 50a, 50b, 50e, 50g1, 50g2 Vias 60, 60a, 60b Second wiring 70, 70a, 70b, 70c, 70g Vias 80a Transistor 80b Transistor 81a, 81b Semiconductor layer 82a, 82b Semiconductor layer 83a, 83b Semiconductor layer 84a, 84b Gate electrode 85a, 85b Gate insulating film 87 Resistor element 90, 90a, 90b, 90g Wiring 291 First conductor layer 295 Second conductor layer
Claims
circuit board and A first semiconductor structure is provided on the first surface of the substrate and comprises a plurality of semiconductor layers having different conductivity types and having a diode structure, A second semiconductor structure is disposed on the first semiconductor structure and comprises a plurality of semiconductor layers having different conductivity types and having a diode structure, A first wiring is arranged on the second surface of the substrate facing the first surface, A first via penetrates the substrate from the first surface to the second surface, is directly connected to the first semiconductor structure, and is electrically connected to the first wiring, A semiconductor device equipped with the following features. A thyristor having the first semiconductor structure and the second semiconductor structure, The semiconductor device according to claim 1. The first semiconductor structure comprises a first semiconductor layer and a second semiconductor layer spaced apart in the in-plane direction, and a third semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer. The second semiconductor structure comprises a fourth semiconductor layer and a fifth semiconductor layer spaced apart in the in-plane direction, and a sixth semiconductor layer disposed between the fourth semiconductor layer and the fifth semiconductor layer. The first semiconductor structure has a pn junction between the third semiconductor layer and at least one of the first semiconductor layer and the second semiconductor layer. The second semiconductor structure has a pn junction between the sixth semiconductor layer and at least one of the fourth semiconductor layer and the fifth semiconductor layer. The semiconductor device according to claim 2. The second wiring arranged on the second semiconductor structure, A second via directly connected to one of the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer, and to the second wiring, Furthermore, A semiconductor device according to claim 3. The first semiconductor structure comprises a seventh semiconductor layer covering the third semiconductor layer, The second semiconductor structure comprises an eighth semiconductor layer covering the sixth semiconductor layer, Furthermore, the semiconductor device according to claim 3 satisfies at least one of the following conditions (1) and (2). (1) The seventh semiconductor layer has a different conductivity type than the third semiconductor layer. (2) The eighth semiconductor layer has a different conductivity type than the sixth semiconductor layer. The seventh semiconductor layer includes a region located at the uppermost part of the first semiconductor structure. The eighth semiconductor layer is in contact with the seventh semiconductor layer, including the region located at the bottom of the second semiconductor structure, and has a conductivity type different from that of the seventh semiconductor layer. The semiconductor device according to claim 5. The seventh semiconductor layer includes a region located at the uppermost part of the first semiconductor structure. The eighth semiconductor layer includes a region located at the bottom of the second semiconductor structure, The seventh semiconductor layer and the eighth semiconductor layer are provided integrally. The semiconductor device according to claim 5. The system further comprises an insulating member disposed between the first semiconductor structure and the second semiconductor structure. The semiconductor device according to claim 1. The first semiconductor structure comprises a first semiconductor layer and a second semiconductor layer spaced apart in the in-plane direction, and a third semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer. The second semiconductor structure comprises a fourth semiconductor layer and a fifth semiconductor layer spaced apart in the in-plane direction, and a sixth semiconductor layer disposed between the fourth semiconductor layer and the fifth semiconductor layer. The first semiconductor structure has a third semiconductor layer and a pn junction between at least one of the first semiconductor layer and the second semiconductor layer. The sixth semiconductor layer has a pn junction between it and at least one of the fourth semiconductor layer and the fifth semiconductor layer. The semiconductor device according to claim 8. The third wiring further comprises a portion of the same height as the first semiconductor structure and a portion of the same height as the second semiconductor structure, and electrically connects the first semiconductor structure and the second semiconductor structure. The semiconductor device according to claim 8. The first semiconductor structure comprises a first semiconductor layer and a second semiconductor layer spaced apart in the in-plane direction, and a third semiconductor layer and a first conductor layer disposed between the first semiconductor layer and the second semiconductor layer. The second semiconductor structure comprises a fourth semiconductor layer and a fifth semiconductor layer spaced apart in the in-plane direction, and a sixth semiconductor layer and a second conductor layer disposed between the fourth semiconductor layer and the fifth semiconductor layer. The third semiconductor layer is in contact with the first semiconductor layer and the second semiconductor layer, and has a conductivity type different from at least one of the first semiconductor layer and the second semiconductor layer. The sixth semiconductor layer is in contact with the fourth semiconductor layer and the fifth semiconductor layer, and has a conductivity type different from at least one of the fourth semiconductor layer and the fifth semiconductor layer. The semiconductor device according to claim 1.