First communication device, second communication device, and communication system

Abstract

This first communication device comprises a first communication unit and a second communication unit. The first communication unit: receives first serial data at a first transmission rate; generates second serial data at a second transmission rate higher than the first transmission rate, the second serial data including a data region that includes a plurality of first bits of the first serial data that are to be transmitted, and dummy data; and transmits the second serial data. The second communication unit receives the second serial data transmitted by the first communication unit, and transmits transmission data including the data region included in the second serial data. The first communication unit starts transmission of the second serial data during reception of the first serial data.

Description

First communication device, second communication device, and communication system

[0001] The present disclosure relates to communication technology.

[0002] Patent Document 1 discloses a technology related to communication.

[0003] Japanese Unexamined Patent Application Publication No. 2001-45066

[0004] For example, responsiveness is required for communication in a system that controls an object such as a robot. Therefore, it is desired that generated control data and sensor data indicating control results be transmitted and received without delay to enable accurate control. Responsiveness is also required for communication in FA (factory automation). In such systems, delay in data transmission and reception, that is, latency, is a problem.

[0005] Accordingly, the present disclosure has been made in view of the above points, and an object of the present disclosure is to provide a technology capable of reducing latency.

[0006] One aspect of the first communication device includes a first communication unit and a second communication unit. The first communication unit receives first serial data at a first transmission rate, generates second serial data at a second transmission rate higher than the first transmission rate, the second serial data including a data area containing a plurality of first bits to be transmitted and dummy data from the first serial data, and transmits the second serial data. The second communication unit receives the second serial data transmitted by the first communication unit, and transmits transmission data including the data area included in the second serial data. The first communication unit starts transmission of the second serial data while receiving the first serial data.

[0007] Furthermore, one embodiment of the second communication device receives transmission data transmitted by the first communication device described above. The second communication device comprises a third communication unit and a fourth communication unit. The third communication unit receives the transmission data, generates restored second serial data by restoring the second serial data based on the transmission data, and transmits the restored second serial data. The fourth communication unit receives the restored second serial data transmitted by the third communication unit, generates restored first serial data by restoring the first serial data based on the restored second serial data, and transmits the restored first serial data.

[0008] Furthermore, one embodiment of the communication system comprises the first communication device described above and the second communication device described above.

[0009] This reduces the latency between the start of receiving the first serial data and the start of transmitting the transmission data.

[0010] Figure 1 is a schematic diagram showing an example of the configuration of the processing system. Figure 2 is a schematic diagram showing an example of the configuration of the communication system. Figure 3 is a schematic diagram showing an example of the configuration of a high-speed packet. Figure 4 is a schematic diagram showing an example of the configuration of low-speed serial data (low-speed packet). Figure 5 is a schematic diagram showing an example of the configuration of the generation unit. Figure 6 is a schematic diagram showing an example of the configuration of the data area. Figure 7 is a schematic diagram showing an example of the configuration of the restoration unit. Figure 8 is a schematic diagram showing an example of the operation of the communication system. Figure 9 is a schematic diagram showing an example of the configuration of the low-speed side communication unit of the generation unit. Figure 10 is a schematic diagram showing an example of a table. Figure 11 is a schematic diagram showing an example of a data area. Figure 12 is a schematic diagram showing an example of a data area. Figure 13 is a schematic diagram showing an example of a data area. Figure 14 is a schematic diagram showing an example of the configuration of the low-speed side communication unit of the generation unit. Figure 15 is a schematic diagram showing an example of the configuration of the low-speed side communication unit of the restoration unit. Figure 16 is a schematic diagram showing an example of the configuration of the low-speed side communication unit of the restoration unit. Figure 17 is a schematic diagram showing an example of the configuration of the low-speed side communication unit of the generation unit. Figure 18 is a schematic diagram showing an example of the configuration of the low-speed side communication unit of the restoration unit. Figure 19 is a schematic diagram showing an example of a table.

[0011] <Outline of an Example of a Processing System> Figure 1 is a schematic diagram showing an example of a processing system 1. As shown in Figure 1, the processing system 1 includes, for example, a processing unit 2A, a processing unit 2B, and a communication system 5 that can communicate with processing units 2A and 2B.

[0012] Processing unit 2A and processing unit 2B are located in separate locations, for example. Processing unit 2A and processing unit 2B can communicate with each other through the communication system 5. Each of processing unit 2A and processing unit 2B can also be called a communication unit or communication device, for example. Processing unit 2A and processing unit 2B can communicate with each other, for example, using a command response method. Processing unit 2A can, for example, send command data indicating a command to processing unit 2B through the communication system 5. Processing unit 2B can send response data indicating a response to processing unit 2A through the communication system 5 in response to receiving command data from processing unit 2A. The communication system 5 functions, for example, as a bridge system connecting processing unit 2A and processing unit 2B to each other.

[0013] The processing unit 2A may be, for example, a control device that controls a power supply unit (also called a power supply device) that supplies power to a load located around the processing unit 2B. In this case, the processing unit 2B may be a sensor device that detects the state of the load. For example, if the load is a motor, the sensor device as the processing unit 2B may include an encoder that detects the rotation angle of the motor. In this case, the processing unit 2A may send command data requesting the detection result from the encoder, and the processing unit 2B may send response data indicating the detection result from the encoder. The processing unit 2A may control the motor as a load through the power supply unit by controlling the power supply unit based on the detection result from the encoder indicated by the received response data. For example, if the load is a three-phase motor, the power supply unit may include an inverter circuit that supplies three-phase power to the three-phase motor. Each of the processing units 2A and 2B may also be called a processing unit, for example.

[0014] The communication system 5 includes, for example, communication devices 10A and 10B located at different locations from each other. Communication device 10A is located, for example, in the vicinity of processing unit 2A and is capable of communicating with processing unit 2A. Communication device 10B is located, for example, in the vicinity of processing unit 2B and is capable of communicating with processing unit 2B. Communication devices 10A and 10B are capable of communicating with each other.

[0015] Communication device 10A receives command data transmitted by processing unit 2A and transmits the received command data to communication device 10B. Communication device 10B transmits the command data received from communication device 10A to processing unit 2B. As a result, the command data transmitted by processing unit 2A is input to processing unit 2B through the communication system 5.

[0016] Communication device 10B receives the response data transmitted by processing unit 2B and transmits the received response data to communication device 10A. Communication device 10A transmits the response data received from communication device 10B to processing unit 2A. As a result, the response data transmitted by processing unit 2B is input to processing unit 2A through the communication system 5.

[0017] Hereafter, unless it is necessary to distinguish between communication device 10A and communication device 10B, they will each be referred to as communication device 10. Similarly, unless it is necessary to distinguish between processing unit 2A and processing unit 2B, they will each be referred to as processing unit 2.

[0018] Communication devices 10A and 10B can, for example, perform power line communication (PLC). Communication devices 10A and 10B are connected to each other, for example, by a power line. The power line connecting communication devices 10A and 10B may be a power line that transmits power output from a power supply unit controlled by processing unit 2A to a load such as a motor.

[0019] Communication device 10A and communication device 10B can exchange first packets with each other. A first packet is a data transmission unit between communication device 10A and communication device 10B and consists of multiple bits. Communication device 10A communicates data with communication device 10B in units of first packets. Each communication device 10, for example, transmits one first packet, then, after a time interval, transmits the next first packet. The first packets flow through the transmission path (e.g., a power line) between communication device 10A and communication device 10B.

[0020] The communication device 10 transmits a first packet at a predetermined transmission rate. The transmission rate of the first packet may be, for example, 32 Mbps, greater than 32 Mbps, or 100 Mbps or more. For example, the transmission rate of the first packet may be 120 Mbps, or any other value. bps is an abbreviation for bits per second. The transmission rate is sometimes called, for example, the transfer rate or bit rate.

[0021] The processing unit 2A and the communication device 10A can, for example, perform serial communication. The processing unit 2A and the communication device 10A can exchange serial data. The processing unit 2B and the communication device 10B can, for example, perform serial communication. The processing unit 2B and the communication device 10B can exchange serial data. The communication method between the processing unit 2A and the communication device 10A and the communication method between the processing unit 2B and the communication device 10B are, for example, the same. The processing unit 2A and the communication device 10A are connected to each other, for example, by a wire. The processing unit 2B and the communication device 10B are connected to each other, for example, by a wire.

[0022] Processing unit 2A and communication device 10A can exchange second packets with each other. Processing unit 2B and communication device 10B can also exchange second packets with each other. The second packet is a data transmission unit between processing unit 2 and communication device 10, and consists of multiple bits. The second packet has a different structure from the first packet. Processing unit 2 performs data communication with communication device 10 in units of second packets. The second packet is, for example, serial data consisting of multiple consecutive bits.

[0023] Processing unit 2A sends a second packet (in other words, serial data) containing command data to communication device 10A, and processing unit 2B sends a second packet containing response data to communication device 10B. Each processing unit 2, for example, sends one second packet, then waits a time interval before sending the next second packet. The second packets flow through the transmission path (e.g., an electric wire) between processing unit 2 and communication device 10.

[0024] The processing unit 2 transmits the second packet at a transmission rate lower than the transmission rate of the first packet. The transmission rate of the second packet may be one-tenth or less of the transmission rate of the first packet, or one-hundredth or less. The transmission rate of the second packet may be, for example, 1 Mbps, or it may be any other value.

[0025] Hereafter, the first packet may be referred to as a high-speed packet, and the second packet as a low-speed packet. Furthermore, a communication method that uses high-speed packets may be referred to as a high-speed communication method. Similarly, a communication method that uses low-speed packets may be referred to as a low-speed communication method. In this example, the PLC method is adopted as the high-speed communication method, and the serial communication method is adopted as the low-speed communication method.

[0026] Communication devices 10A and 10B, for example, have the same configuration. Communication device 10A has a conversion unit 11A, and communication device 10B has a conversion unit 11B. The conversion unit 11A converts low-speed packets received by communication device 10A into high-speed packets. Also, the conversion unit 11A converts high-speed packets received by communication device 10A into low-speed packets. Similarly, the conversion unit 11B converts low-speed packets received by communication device 10B into high-speed packets. Also, the conversion unit 11B converts high-speed packets received by communication device 10B into low-speed packets.

[0027] The conversion unit 11A converts the low-speed packet containing command data received by the communication device 10A into a high-speed packet containing command data. The communication device 10A then transmits the high-speed packet obtained by the conversion unit 11A to the communication device 10B. The conversion unit 11B converts the high-speed packet containing command data received by the communication device 10B into a low-speed packet containing command data. The communication device 10B then transmits the low-speed packet obtained by the conversion unit 11B to the processing unit 2B. It can also be said that the communication system 5 relays the low-speed packets transmitted by the processing unit 2A and transmits them to the processing unit 2B.

[0028] Furthermore, the conversion unit 11B converts the low-speed packet containing response data received by the communication device 10B into a high-speed packet containing response data. The communication device 10B then transmits the high-speed packet obtained by the conversion unit 11B to the communication device 10A. The conversion unit 11A converts the high-speed packet containing response data received by the communication device 10A into a low-speed packet containing response data. The communication device 10A then transmits the low-speed packet obtained by the conversion unit 11A to the processing unit 2A. It can also be said that the communication system 5 relays the low-speed packets transmitted by the processing unit 2B and transmits them to the processing unit 2A. Hereafter, when there is no need to distinguish between the conversion unit 11A and the conversion unit 11B, they will each be referred to as the conversion unit 11.

[0029] Note that the low-speed and high-speed communication methods are not limited to the examples above. Also, the functions of processing unit 2A and processing unit 2B are not limited to the examples above.

[0030] <Example of Communication Device Configuration> Figure 2 is a schematic diagram showing an example of the configuration of communication device 10A and communication device 10B. Each of communication device 10A and communication device 10B is implemented, for example, by hardware circuits that do not require software to realize their functions. Each of communication device 10A and communication device 10B can also be called a communication circuit.

[0031] As shown in Figure 2, the conversion unit 11A of the communication device 10A has, for example, a generation unit 20A and a restoration unit 30A. The conversion unit 11B of the communication device 10B has, for example, a generation unit 20B and a restoration unit 30B. Each of the generation unit 20A and generation unit 20B can be called, for example, a generation circuit, and each of the restoration unit 30A and restoration unit 30B can be called, for example, a restoration circuit.

[0032] Hereafter, for the sake of explanation, the processing unit 2A may be referred to as the upper side of the processing system 1, and the low-speed packets transmitted by the processing unit 2A may be referred to as upper-side low-speed packets. Also, for the sake of explanation, the processing unit 2B may be referred to as the lower side of the processing system 1, and the low-speed packets transmitted by the processing unit 2B may be referred to as lower-side low-speed packets. Furthermore, the high-speed packets generated by the communication device 10A based on the upper-side low-speed packets may be referred to as upper-side high-speed packets. Furthermore, the high-speed packets generated by the communication device 10B based on the lower-side low-speed packets may be referred to as lower-side high-speed packets.

[0033] The generation unit 20A can communicate with the processing unit 2A, for example, via a wired connection. The generation unit 20A may be directly connected to the processing unit 2A or connected via another configuration. The generation unit 20A receives high-speed packets from the processing unit 2A. The generation unit 20A generates high-speed packets based on the high-speed packets received from the processing unit 2A. The generation unit 20A can communicate with the restoration unit 30B of the communication device 10B via a power line between the communication device 10A and the communication device 10B. The generation unit 20A transmits the generated high-speed packets to the restoration unit 30B via the power line.

[0034] The generation unit 20B can communicate with the processing unit 2B, for example, via a wired connection. The generation unit 20B may be directly connected to the processing unit 2B or connected via another configuration. The generation unit 20B receives lower-side low-speed packets from the processing unit 2B. The generation unit 20B generates lower-side high-speed packets based on the lower-side low-speed packets received from the processing unit 2B. The generation unit 20B can communicate with the restoration unit 30A of the communication device 10A through the power line between the communication device 10A and the communication device 10B. The generation unit 20B transmits the generated lower-side high-speed packets to the restoration unit 30A through the power line.

[0035] The restoration unit 30B can communicate with the processing unit 2B, for example, via a wired connection. The restoration unit 30B may be directly connected to the processing unit 2B or connected via another configuration. The restoration unit 30B restores the upper-side low-speed packets based on the upper-side high-speed packets received from the generation unit 20A. The restoration unit 30B then transmits the restored upper-side low-speed packets (also called restored upper-side low-speed packets) to the processing unit 2B. As a result, the processing unit 2B can receive the upper-side low-speed packets transmitted by the processing unit 2A through the communication system 5. It can also be said that the restoration unit 30B generates restored upper-side low-speed packets by restoring the upper-side low-speed packets based on the upper-side high-speed packets received from the generation unit 20A.

[0036] The restoration unit 30A can communicate with the processing unit 2A, for example, via a wired connection. The restoration unit 30A may be directly connected to the processing unit 2A or connected via another configuration. The restoration unit 30A restores the lower-side low-speed packets based on the lower-side high-speed packets received from the generation unit 20B. The restoration unit 30A then transmits the restored lower-side low-speed packets (also called restored lower-side low-speed packets) to the processing unit 2A. As a result, the processing unit 2A can receive the lower-side low-speed packets transmitted by the processing unit 2B through the communication system 5. It can also be said that the restoration unit 30A generates restored lower-side low-speed packets by restoring the lower-side low-speed packets based on the lower-side high-speed packets received from the generation unit 20B.

[0037] Hereafter, unless it is necessary to distinguish between the generation unit 20A and the generation unit 20B, they will each be referred to as the generation unit 20. Similarly, unless it is necessary to distinguish between the restoration unit 30A and the restoration unit 30B, they will each be referred to as the restoration unit 30.

[0038] Furthermore, when focusing on the operation of the communication device 10 to convert low-speed packets to high-speed packets, the communication device 10 may be referred to as the conversion-side communication device 10. Also, when focusing on the operation of the communication device 10 to restore low-speed packets from high-speed packets, the communication device 10 may be referred to as the restoration-side communication device 10.

[0039] <Example of High-Speed ​​Packet Configuration> Figure 3 is a schematic diagram showing an example of the configuration of a high-speed packet 100. The high-speed packet 100 comprises, for example, a data area 101 and associated data 105 attached to the data area 101. The data area 101 contains the data body 110. The data area 101 is data obtained by performing predetermined processing on the data body 110. The predetermined processing includes, for example, encoding and interleaving, as will be described later. The data length of the data area 101 is greater than the data length of the original data body 110. The data area 101 can also be said to be the data body 110 that has undergone predetermined processing. The data body 110 is sometimes called, for example, the payload or actual data.

[0040] The accompanying data 105 includes, for example, a preamble 106 and a synchronization word 107 that are appended before the data area 101, and a postamble 108 that is appended after the data area 101. The preamble 106 is a bit sequence for synchronizing with the high-speed packet 100. The synchronization word 107 is a bit sequence for identifying the beginning of the data area 101. The postamble 108 is a bit sequence for identifying the end of the data area 101.

[0041] <Configuration Example of Low-Speed Packet> FIG. 4 is a schematic diagram showing a configuration example of a low-speed packet 200. As shown in FIG. 4, the low-speed packet 200 is composed of, for example, A blocks BL, where A is an integer of 2 or more. Each block BL is composed of a bit string including a plurality of bits, for example. In the example of FIG. 4, each block BL is composed of 10 bits. For example, when A=2, the low-speed packet 200 is composed of 20 bits. That is, the data length of the low-speed packet 200 is 20 bits.

[0042] Each block BL conforms to, for example, a UART frame. UART is an abbreviation for Universal Asynchronous Receiver Transmitter. The plurality of bits constituting the block BL are composed of, for example, a start bit, a stop bit, and a data bit string including a plurality of data bits. For example, the start bit indicates "0" (low level in other words), and the stop bit indicates "1" (high level in other words). The data bit string is composed of, for example, 8-bit data bits.

[0043] In the low-speed packet 200, the leading block BL constitutes a header 205, and the remaining (A-1) blocks BL constitute a data body 201. The data body 201 is composed of at least one block BL.

[0044] The data body 201 included in the upper-layer low-speed packet 200 contains command data. Specifically, the data bit strings of the (A-1) blocks BL constituting the data body 201 included in the upper-layer low-speed packet 200 indicate command data. Furthermore, the data body 201 included in the lower-layer low-speed packet 200 contains response data. Specifically, the data bit strings of the (A-1) blocks BL constituting the data body 201 included in the lower-layer low-speed packet 200 indicate response data.

[0045] The header 205 includes, for example, a synchronization code and an ID code. ID is an abbreviation for identification. A data bit string included in a block BL constituting the header 205 constitutes the synchronization code and the ID code. For example, the synchronization code is composed of 3 bits, and the ID code is composed of 5 bits. The synchronization code is a bit string for achieving synchronization with the low-speed packet 200. The ID code is a bit string for specifying the data length of the low-speed packet 200. It can also be said that the ID code is a bit string for specifying the number of bits among the plurality of bits that constitute the low-speed packet 200.

[0046] The processing unit 2 can, for example, change the transmission rate of low-speed packets. The processing unit 2 changes the transmission rate of low-speed packets in accordance with, for example, an instruction from a user. In other words, the processing unit 2 sets the transmission rate of low-speed packets in accordance with an instruction from a user. The processing unit 2 can transmit low-speed packets having a plurality of types of transmission rates.

[0047] In this example, the communication device 10 generates a high-speed packet including a plurality of first bits to be transmitted among the plurality of first bits constituting a low-speed packet (in other words, serial data) input from the processing unit 2, and transmits the generated high-speed packet to a counterpart communication device 10. Hereinafter, the plurality of first bits to be transmitted is also referred to as a first bit group to be transmitted.

[0048] The first bit group to be transmitted is composed of, for example, all of the plurality of first bits constituting the low-speed packet. In other words, all of the plurality of first bits constituting the low-speed packet constitute the first bit group to be transmitted. When A=2, the number of bits of the first bit group to be transmitted is equal to the number of bits of the low-speed packet, and is 20 bits (=2×10 bits). The first bit group to be transmitted includes a start bit, a stop bit, and a data bit string.

[0049] The communication device 10, upon receiving a high-speed packet from the other communication device 10, extracts the first set of bits to be transmitted from the high-speed packet and reconstructs the low-speed packet containing the extracted first set of bits to be transmitted. The communication device 10 then transmits the reconstructed low-speed packet (also called the reconstructed low-speed packet) to the processing unit 2. Hereafter, the low-speed packet that is reconstructed may be referred to as the original low-speed packet.

[0050] The generation unit 20A generates a high-speed upper-side packet containing the first group of bits to be transmitted, which is included in the high-speed upper-side packet from the processing unit 2A, and the header 302, which will be described later, in the data body 110. The restoration unit 30B extracts the first group of bits to be transmitted from the high-speed upper-side packet from the generation unit 20A and restores the high-speed upper-side packet containing the extracted first group of bits to be transmitted.

[0051] The generation unit 20B generates a lower-side high-speed packet containing the first group of bits to be transmitted, which are included in the lower-side low-speed packet from the processing unit 2B, and the header 302, in the data body 110. The restoration unit 30A extracts the first group of bits to be transmitted from the lower-side high-speed packet from the generation unit 20B and restores the lower-side low-speed packet containing the extracted first group of bits to be transmitted.

[0052] The first bit group to be transmitted may consist of a portion of the multiple first bits that make up the low-speed packet. For example, the first bit group to be transmitted may be the data bit sequences of A block BLs that make up the low-speed packet. In this case, the communication device 10 that receives the high-speed packet from the other communication device 10 adds a start bit and a stop bit to each of the A data bit sequences that make up the first bit group to be transmitted included in the high-speed packet, thereby restoring the low-speed packet composed of A block BLs.

[0053] <Example of Configuration of the Conversion Unit of the Communication Device> Figure 5 is a schematic diagram showing an example of the configuration of the generation unit 20A and the generation unit 20B. The configurations of the generation unit 20A and the generation unit 20B are, for example, the same. As shown in Figure 5, the generation unit 20 includes, for example, a communication unit 25 and a communication unit 28. Each of the communication unit 25 and the communication unit 28 is implemented, for example, by a hardware circuit that does not require software to realize its function.

[0054] The communication unit 25 receives the low-speed packet 200 from the processing unit 2, generates serial data 300 that includes the first bit group to be transmitted from the low-speed packet 200, and transmits the serial data 300 to the communication unit 28. In this example, since the first bit group to be transmitted consists of all of the multiple first bits that make up the low-speed packet 200, it can also be said that the communication unit 25 generates serial data 300 that includes the low-speed packet 200.

[0055] The communication unit 28 receives the serial data 300 transmitted by the communication unit 25. The communication unit 28 generates a high-speed packet 100 containing the first group of bits to be transmitted included in the serial data 300, and transmits the high-speed packet 100 to the restoration unit 30 of the other communication device 10 via the power line. The high-speed packet 100 can also be said to be the transmission data. The communication unit 28 generates transmission data containing the first group of bits to be transmitted included in the serial data 300, and transmits the transmission data.

[0056] The transmission rate of serial data 300 is higher than the transmission rate of low-speed packet 200, which is serial data. The transmission rate of serial data 300 is, for example, 32 Mbps. The transmission rate of low-speed packet 200 is, for example, 1 Mbps or more and less than 32 Mbps. If the transmission rate of low-speed packet 200 is expressed in QMbps, then Q is set to an integer between 1 and 31, for example.

[0057] Hereafter, the low-speed packet 200 may be referred to as low-speed serial data 200. Similarly, the serial data 300 may be referred to as high-speed serial data 300. The communication unit 25 can also be said to convert, for example, the low-speed serial data 200, which has a low transmission rate, into high-speed serial data 300, which has a high transmission rate.

[0058] Figure 6 is a schematic diagram showing an example of the configuration of high-speed serial data 300. High-speed serial data 300 includes, for example, a data area 301 composed of multiple bits and a header 302 composed of at least one bit. The data area 301 includes the first group of bits to be transmitted, which are included in the low-speed serial data 200, and dummy data. The dummy data consists of at least one dummy bit. Dummy data is data whose value has no meaning. Similarly, a dummy bit is a bit whose value has no meaning. The header 302 will be described in detail later.

[0059] The communication unit 25 generates high-speed serial data 300 which includes a data area 301 containing the first bit group to be transmitted and dummy data included in the low-speed packet 200, and transmits the high-speed serial data 300 to the communication unit 28. The communication unit 28 generates a high-speed packet 100 which includes the data area 301 included in the high-speed serial data 300 from the communication unit 25 in the data body 110. The communication unit 28 transmits the high-speed packet 100 to the restoration unit 30 of the other communication device 10 via the power line. Hereafter, the communication unit 25 may be referred to as the low-speed side communication unit 25, and the communication unit 28 may be referred to as the high-speed side communication unit 28.

[0060] The low-speed communication unit 25 transmits the first group of bits to be transmitted (which in this example can also be called low-speed serial data 200) by adding dummy data to it, thereby disguising it as data with a high transmission rate. In other words, the low-speed communication unit 25 transmits the first group of bits to be transmitted as data with a high transmission rate by adding dummy data to it. It can also be said that the low-speed communication unit 25 transmits the serial data to be transmitted as serial data with a high transmission rate by adding at least one dummy bit to the serial data to be transmitted.

[0061] Figure 7 is a schematic diagram showing an example of the configuration of the restoration unit 30A and the restoration unit 30B. The configurations of the restoration unit 30A and the restoration unit 30B are, for example, the same. As shown in Figure 7, the restoration unit 30 includes, for example, a communication unit 35 and a communication unit 38. Each of the communication unit 35 and the communication unit 38 is implemented, for example, by hardware circuits that do not require software to realize their functions.

[0062] The communication unit 38 receives the high-speed packet 100 transmitted by the high-speed communication unit 28 of the conversion-side communication device 10 via the power line. The communication unit 38 reconstructs the high-speed serial data 300 based on the high-speed packet 100. It can also be said that the communication unit 38 generates reconstructed high-speed serial data 300, which is the reconstructed high-speed serial data 300 based on the high-speed packet 100. The communication unit 38 transmits the reconstructed high-speed serial data 300 to the communication unit 35.

[0063] The communication unit 35 receives the restored high-speed serial data 300 transmitted by the communication unit 38. Based on the restored high-speed serial data 300, the communication unit 35 restores the low-speed serial data 200 (i.e., the low-speed packet 200). It can also be said that the communication unit 35 generates restored low-speed serial data 200 by restoring the low-speed serial data 200 based on the restored high-speed serial data 300. For example, the communication unit 35 can be said to convert high-speed serial data 300 with a high transmission rate to low-speed serial data 200 with a low transmission rate. The communication unit 35 removes dummy data from the data area 301 contained in the high-speed serial data 300 to obtain the first bit group to be transmitted, and restores the low-speed serial data 200 including the first bit group to be transmitted. Hereafter, the communication unit 35 may be referred to as the low-speed side communication unit 35, and the communication unit 38 may be referred to as the high-speed side communication unit 38. The low-speed serial data 200 that is restored may also be referred to as the original low-speed serial data 200.

[0064] Figure 8 is a schematic diagram showing an example of the operation of the conversion-side communication device 10 and the restoration-side communication device 10. As shown in Figure 8, the low-speed side communication unit 25 of the conversion-side communication device 10 starts receiving low-speed serial data 200 (in other words, low-speed packets 200) from the processing unit 2 at timing t1, and then starts transmitting high-speed serial data 300 at timing t2, which follows timing t1. For example, the low-speed side communication unit 25 starts transmitting high-speed serial data 300 while receiving low-speed serial data 200.

[0065] The high-speed communication unit 28 of the conversion-side communication device 10 starts receiving high-speed serial data 300 from the low-speed communication unit 25 at timing t3, following timing t2. Then, at timing t4, following timing t3, it starts transmitting high-speed packets 100. For example, the high-speed communication unit 28 starts transmitting high-speed packets 100 while the low-speed communication unit 25 is receiving low-speed serial data 200. Also, for example, the high-speed communication unit 28 starts transmitting high-speed packets 100 while receiving high-speed serial data 300.

[0066] The high-speed communication unit 38 of the restoration-side communication device 10 starts receiving high-speed packets 100 from the high-speed communication unit 28 of the conversion-side communication device 10 at timing t5, after timing t4. Then, at timing t6, after timing t5, the high-speed communication unit 38 starts transmitting the restored high-speed serial data 300.

[0067] The high-speed communication unit 38 starts transmitting the restored high-speed serial data 300, for example, while the low-speed communication unit 25 of the conversion-side communication device 10 is receiving the low-speed serial data 200. The high-speed communication unit 38 also starts transmitting the restored high-speed serial data 300, for example, while the high-speed communication unit 28 of the conversion-side communication device 10 is receiving the high-speed serial data 300. Furthermore, the high-speed communication unit 38 starts transmitting the restored high-speed serial data 300, for example, while receiving the high-speed packet 100.

[0068] The low-speed communication unit 35 of the restoration-side communication device 10 starts receiving the restored high-speed serial data 300 from the high-speed communication unit 38 at timing t7, following timing t6. Then, at timing t8, following timing t7, the low-speed communication unit 35 starts transmitting the restored low-speed serial data 200 (i.e., the restored low-speed packet 200).

[0069] The low-speed communication unit 35 starts transmitting restored low-speed serial data 200 (i.e., restored low-speed packets 200) while the low-speed communication unit 25 of the conversion-side communication device 10 is receiving low-speed serial data 200. The low-speed communication unit 35 also starts transmitting restored low-speed serial data 200 while the high-speed communication unit 28 of the conversion-side communication device 10 is receiving high-speed serial data 300. The low-speed communication unit 35 also starts transmitting restored low-speed serial data 200 while the high-speed communication unit 38 is receiving high-speed packets 100. The low-speed communication unit 35 also starts transmitting restored low-speed serial data 200 while the high-speed communication unit 38 is receiving restored high-speed serial data 300.

[0070] Thus, in this example, the low-speed communication unit 25 starts transmitting high-speed serial data 300, which includes the first bit group to be transmitted and dummy data of the low-speed serial data 200, while receiving the low-speed serial data 200. This allows the high-speed communication unit 28 to start receiving the first bit group to be transmitted earlier. Therefore, the high-speed communication unit 28 can start transmitting the high-speed packet 100, which includes the first bit group to be transmitted, earlier. This reduces the latency Da (see Figure 8) from the start of reception of the low-speed serial data 200 at the conversion-side communication device 10 to the start of transmission of the high-speed packet 100, which includes the first bit group to be transmitted contained in the low-speed serial data 200, at the conversion-side communication device 10. Furthermore, by reducing latency Da, the latency Db (see Figure 8) from the time the conversion-side communication device 10 starts receiving the original low-speed serial data 200 (i.e., the original low-speed packet 200) until the restoration-side communication device 10 starts transmitting the restored low-speed serial data 200 (in other words, the restored low-speed packet 200), which is the original low-speed serial data 200, can be reduced. In other words, the communication system 5 that relays the low-speed packet 200 between one processing unit 2 and the other processing unit 2 can reduce the latency Db from the time it starts receiving the low-speed serial data 200 from one processing unit 2 until it starts transmitting the low-speed serial data 200 to the other processing unit 2.

[0071] <Detailed explanation of the configuration example of the conversion unit> As shown in Figure 5 above, the high-speed communication unit 28 of the generation unit 20 of the conversion unit 11 includes, for example, a packet generation unit 280 and an interface 281. Also, as shown in Figure 7 above, the high-speed communication unit 38 of the restoration unit 30 of the conversion unit 11 includes, for example, an interface 381 and a data acquisition unit 380.

[0072] The packet generation unit 280 generates a high-speed packet 100 in which the data body 110 contains multiple second bits that constitute the high-speed serial data 300 from the communication unit 25. The packet generation unit 280 outputs the high-speed packet 100 to the interface 281. Hereafter, the multiple second bits that constitute the high-speed serial data 300 may be referred to as a group of second bits.

[0073] The packet generation unit 280 performs predetermined processing on the data body 110 including the second bit group to generate a data area 101 including the second bit group. The packet generation unit 280 generates the data area 101 by performing, for example, 4b5b encoding, error correction encoding, and interleaving on the data body 110. Then, the packet generation unit 280 adds ancillary data 105 including a preamble 106, a synchronization word 107, and a postamble 108 to the data area 101 to generate a high-speed packet 100.

[0074] Interface 281 transmits high-speed packets 100 from the packet generation unit 280. Interface 281 of the conversion-side communication device 10 is connected to interface 381 of the restoration unit 30 of the restoration-side communication device 10, for example, by a power line. Interface 281 can communicate with interface 381 through the power line. The high-speed packets 100 transmitted by interface 281 are input to interface 381 through the power line. Interface 281 performs modulation processing based on the high-speed packets 100 to generate a modulated signal that includes the high-speed packets 100. Interface 281 then transmits the modulated signal to interface 381 by superimposing the modulated signal onto the power line.

[0075] The high-speed communication unit 28 starts processing, for example, when the first bit of the high-speed serial data 300 is input. The high-speed communication unit 28 generates a high-speed packet 100 by performing pipeline processing on the high-speed serial data 300, for example. The high-speed communication unit 28 starts transmitting the high-speed packet 100 a predetermined time after the first bit of the high-speed serial data 300 is input.

[0076] The interface 381 of the high-speed communication unit 38 included in the restoration unit 30 of the restoration-side communication device 10 receives high-speed packets 100 from the interface 281 of the generation unit 20 of the conversion-side communication device 10. Interface 381 extracts the modulated signal containing the high-speed packets 100 transmitted by interface 281 from the power line, performs demodulation processing on the extracted modulated signal, and acquires the high-speed packets 100. Interface 381 outputs the high-speed packets 100 to the data acquisition unit 380.

[0077] The data acquisition unit 380 acquires restored high-speed serial data 300 by restoring the high-speed serial data 300 based on the high-speed packet 100 from the interface 381. The data acquisition unit 380 acquires a second bit group from the data body 110 contained in the high-speed packet 100 from the interface 381. Specifically, the data acquisition unit 380 removes the accompanying data 105 from the high-speed packet 100 to acquire the data area 101. Next, the data acquisition unit 380 performs reverse interleaving, error correction, and 5b4b decoding on the data area 101 to restore the data body 110. Then, the data acquisition unit 380 acquires a second bit group from the restored data body 110. The data acquisition unit 380 transmits the second bit group as restored high-speed serial data 300 to the communication unit 35 at a predetermined transmission rate (e.g., 32 Mbps).

[0078] The high-speed communication unit 38 starts processing, for example, when the first bit of the high-speed packet 100 is input. The high-speed communication unit 38 generates restored high-speed serial data 300 by performing pipeline processing on the high-speed packet 100, for example. The high-speed communication unit 38 starts transmitting the restored high-speed serial data 300 a predetermined time after the first bit of the high-speed packet 100 is input.

[0079] <Example of Configuration of the Low-Speed ​​Communication Unit of the Generation Unit> Figure 9 is a schematic diagram showing an example of the configuration of the low-speed communication unit 25 of the generation unit 20. The low-speed communication unit 25 includes, for example, an interface 250, a data processing unit 251, and a generation unit 252. The interface 250 receives low-speed serial data 200 from the processing unit 2. The data processing unit 251 performs processing based on the low-speed serial data 200 received by the interface 250. The generation unit 252 generates high-speed serial data 300 including the target transmission first bit group included in the low-speed serial data 200. The generation unit 252 transmits the high-speed serial data 300 to the high-speed communication unit 28 at a predetermined transmission rate (for example, 32 Mbps).

[0080] Interface 250 can communicate with processing unit 2. Interface 250 is connected to processing unit 2 by, for example, a wire. Processing unit 2 transmits, for example, low-speed serial data 200 as a differential signal. Interface 250 converts the received differential signal into a single-ended signal. Interface 250 then outputs the low-speed serial data 200 as a single-ended signal to data processing unit 251.

[0081] The data processing unit 251 includes, for example, a transmission rate acquisition unit 251a that acquires the transmission rate (also called the low transmission rate) of the low-speed serial data 200. The transmission rate acquisition unit 251a outputs transmission rate data 260 indicating the acquired low transmission rate to the generation unit 252. The transmission rate data 260 is composed of, for example, multiple bits. The transmission rate data 260 indicates the current setting value of the low transmission rate.

[0082] The transmission rate acquisition unit 251a acquires a low transmission rate based on, for example, the header 205 included in the low-speed serial data 200. For example, the transmission rate acquisition unit 251a acquires a low transmission rate based on the synchronization code included in the header 205.

[0083] The transmission rate acquisition unit 251a includes, for example, a counter that counts up based on a 240 MHz clock signal. The counter increases its count value by one each time the clock signal rises. The transmission rate acquisition unit 251a uses the counter to determine the low transmission rate. Three methods for determining the low transmission rate are described below.

[0084] <First Method of Determination> In the first method of determination, the transmission rate acquisition unit 251a uses a counter to measure the time from the first rising edge after the start bit of the header 205 to the first falling edge after the start bit. As shown in Figure 4, the first rising edge after the start bit is the rising edge of the second bit from the beginning of the synchronization code. Also, the first falling edge after the start bit is the falling edge of the second bit from the beginning of the synchronization code.

[0085] The transmission rate acquisition unit 251a takes the counter count from the first rising edge after the start bit to the first falling edge after the start bit as the measurement result of the time from the first rising edge after the start bit to the first falling edge after the start bit. Then, based on the measurement result, that is, based on the acquired count, the transmission rate acquisition unit 251a determines the low transmission rate. If the acquired count is C1 and the low transmission rate is LT (in Mbps), the transmission rate acquisition unit 251a determines the low transmission rate LT using the following equation (1).

[0086]

[0087] <Second Method of Calculation> In the second method of calculation, the transmission rate acquisition unit 251a uses a counter to measure the time from the falling edge of the start bit of the header 205 to the first rising edge after the start bit. The transmission rate acquisition unit 251a uses the number of counters from the falling edge of the start bit to the first rising edge after the start bit as the measurement result of the time from the falling edge of the start bit to the first rising edge after the start bit. Then, the transmission rate acquisition unit 251a calculates the low transmission rate based on the measurement result, that is, based on the acquired count. If the acquired count is C2, the transmission rate acquisition unit 251a calculates the low transmission rate LT using the following equation (2).

[0088]

[0089] As can be understood from the above explanation, in the second method, the low transmission rate is determined based on the count of time for 2 bits of the low-speed serial data 200. On the other hand, in the first method, the low transmission rate is determined based on the count of time for 1 bit of the low-speed serial data 200. Therefore, the effect of timing differences in bit changes in the low-speed serial data 200 on the count is smaller in the second method than in the first method. Thus, the second method can determine the low transmission rate with greater accuracy than the first method.

[0090] <Third Method of Determination> In the third method of determination, the transmission rate acquisition unit 251a uses a counter to measure the time from the falling edge of the start bit of the header 205 to the first falling edge after the start bit. The transmission rate acquisition unit 251a uses the counter count from the falling edge of the start bit to the first falling edge after the start bit as the measurement result of the time from the falling edge of the start bit to the first falling edge after the start bit. Then, the transmission rate acquisition unit 251a determines the low transmission rate based on the measurement result, that is, based on the acquired count. If the acquired count is C3, the transmission rate acquisition unit 251a determines the low transmission rate LT using the following equation (3).

[0091]

[0092] As can be understood from the above explanation, in the third method, the low transmission rate is determined based on the count of the time for 3 bits of the low-speed serial data 200. Therefore, the influence of the timing difference of bit changes in the low-speed serial data 200 on the count is smaller in the third method than in the second and first methods. Thus, the third method can determine the low transmission rate with greater accuracy than the second and first methods.

[0093] The generation unit 252 that generates the high-speed serial data 300 includes, for example, a buffer 253, a write control unit 254, a read control unit 255, a selection unit 256, a header addition unit 257, and a table processing unit 258. The data processing unit 251 outputs the first group of bits to be transmitted (in this example, multiple first bits that constitute the low-speed serial data 200) included in the low-speed serial data 200 from the interface 250 to the buffer 253 one bit at a time from the beginning. The data processing unit 251 outputs the first group of bits to be transmitted one bit at a time in serial format at a low transmission rate.

[0094] Buffer 253 is, for example, a FIFO buffer capable of storing at least one bit of data. FIFO is an abbreviation for First In First Out. The write control unit 254 controls the writing of data to buffer 253. The write control unit 254 outputs a write pointer to buffer 253, for example. By controlling the write pointer, the write control unit 254 writes the first bit, output one bit at a time by the data processing unit 251, to buffer 253 one bit at a time.

[0095] Here, the bit period of the low-speed serial data 200 is called the low-speed bit period. The low-speed bit period is the reciprocal of the low transmission rate. The low-speed bit period can also be said to be the transmission time per bit of the low-speed serial data 200. If the low transmission rate is, for example, 1 Mbps, the low-speed bit period will be 1 μs. The write control unit 254 obtains the low-speed bit period based on the transmission rate data 260 output from the data processing unit 251. Then, the write control unit 254 writes the first bit, which is sequentially output from the data processing unit 251 at the low transmission rate, to the buffer 253 at each low-speed bit period.

[0096] The read control unit 255 controls the reading of data from the buffer 253. For example, the read control unit 255 outputs a read pointer to the buffer 253. By controlling the read pointer, the read control unit 255 sequentially reads the first bit from the buffer 253.

[0097] The read control unit 255 reads one bit of the first bit from buffer 253 each time one bit of the first bit is written to buffer 253. The read control unit 255 also starts reading the first bit from buffer 253 as soon as writing of the first bit to buffer 253 begins. In other words, the read control unit 255 starts reading the first bit from buffer 253 as soon as the first bit of the first bit group to be transmitted is written to buffer 253. It can also be said that the read control unit 255 starts reading the first bit from buffer 253 in response to the first bit written to buffer 253. For example, when the nth bit (n is a non-negative integer) is written to buffer 253, the read control unit 255 reads the nth bit from buffer 253 before the (n+1)th bit is written to buffer 253. The 0th bit is the first bit of the first bit group to be transmitted.

[0098] The first bit of each of the first bit group to be transmitted, which is read out one bit at a time from the buffer 253, is sequentially input one bit at a time to the selection unit 256.

[0099] Here, the bit period of the high-speed serial data 300 is called the high-speed bit period. The high-speed bit period is the reciprocal of the transmission rate (also called the high transmission rate) of the high-speed serial data 300. The high-speed bit period can also be said to be the transmission time per bit of the high-speed serial data 300. In this example, the high transmission rate is 32 Mbps, so the high-speed bit period is 0.03125 μs. The high-speed bit period is known in the communication device 10.

[0100] The selection unit 256 is capable of performing a selective output process that selects and outputs either the first bit or the dummy bit output from the buffer 253. By repeatedly executing the selective output process, the selection unit 256 generates a data area 301 consisting of the first bit group to be transmitted and at least one dummy bit, and outputs the data area 301 to the header addition unit 257. By repeatedly executing the selective output process at a high bit period (i.e., the reciprocal of the high transmission rate), the selection unit 256 outputs the data area 301 as serial data at a high transmission rate (e.g., 32 Mbps) to the header addition unit 257. In the data area 301, each first bit of the first bit group to be transmitted is arranged sequentially from the beginning, starting from the front of the data area 301.

[0101] The header addition unit 257 adds a header 302 to the data area 301 from the selection unit 256 to generate high-speed serial data 300, and transmits the high-speed serial data 300 to the high-speed communication unit 28. The header addition unit 257 transmits the high-speed serial data 300 to the high-speed communication unit 28 at a high transmission rate.

[0102] In the data area 301, which consists of the first bit group to be transmitted and dummy data, the multiple first bits constituting the first bit group to be transmitted are positioned in an order based on the ratio of the high transmission rate to the low transmission rate. Hereafter, the ratio of the high transmission rate to the low transmission rate may be referred to as the rate ratio. Also, the order of the first bits in the data area 301 based on the rate ratio may be referred to as the first bit order.

[0103] The low-speed communication unit 25 stores, for example, sequence data 271 representing a sequence of multiple first bits in the data area 301. The low-speed communication unit 25 generates the data area 301 based on the sequence data 271. The low-speed communication unit 25 can easily generate the data area 301 by generating the data area 301 based on the sequence data 271.

[0104] In this example, there are B types of setting values ​​(where B is an integer of 2 or more) for the low transmission rate. The low-speed communication unit 25 stores a table 270 containing B sequence data 271 corresponding to each of the B types of setting values. Hereafter, when simply referred to as a setting value, it means the setting value for the low transmission rate.

[0105] Figure 10 is a schematic diagram showing an example of table 270 when B = 6. Table 270 contains B IDs 272, each assigned to a B sequence of data 271. Table 270 also contains B setting value data 273, each representing a B type of setting value for a low transmission rate.

[0106] In table 270, for each of the B IDs 272, there is a corresponding sequence data 271 to which the ID 272 is assigned, and a setting value data 273 indicating the setting value to which the sequence data 271 corresponds. ID 272 can also be considered an ID assigned to a setting value for a low transmission rate.

[0107] Figure 10 shows an example of Table 270 when there are six different settings for low transmission rates: 1 Mbps, 2 Mbps, 3 Mbps, 5 Mbps, 10 Mbps, and 21 Mbps. In the example in Figure 10, Table 270 includes sorting data 271 corresponding to 1 Mbps (first from the top in Figure 10), second sorting data 271 corresponding to 2 Mbps (second from the top in Figure 10), and sorting data 271 corresponding to 3 Mbps (third from the top in Figure 10). Additionally, Table 270 includes sorting data 271 corresponding to 5 Mbps (fourth from the top in Figure 10), sorting data 271 corresponding to 10 Mbps (fifth from the top in Figure 10), and sorting data 271 corresponding to 21 Mbps (sixth from the top in Figure 10).

[0108] In this example, the high transmission rate is, for example, 32 Mbps. The sequence data 271 corresponding to 1 Mbps represents the first bit sequence based on the ratio of 32 Mbps to 1 Mbps. The sequence data 271 corresponding to 2 Mbps represents the first bit sequence based on the ratio of 32 Mbps to 2 Mbps. The sequence data 271 corresponding to 3 Mbps represents the first bit sequence based on the ratio of 32 Mbps to 3 Mbps. The sequence data 271 corresponding to 5 Mbps represents the first bit sequence based on the ratio of 32 Mbps to 5 Mbps. The sequence data 271 corresponding to 10 Mbps represents the first bit sequence based on the ratio of 32 Mbps to 10 Mbps. The sequence data 271 corresponding to 21 Mbps represents the first bit sequence based on the ratio of 32 Mbps to 21 Mbps.

[0109] ID272 is, for example, 3-bit data. For example, the sequence data 271 corresponding to 1 Mbps is assigned an ID272 that represents "000" (decimal notation "0"). For example, the sequence data 271 corresponding to 2 Mbps is assigned an ID272 that represents "001" (decimal notation "1"). For example, the sequence data 271 corresponding to 3 Mbps is assigned an ID272 that represents "010" (decimal notation "2"). For example, the sequence data 271 corresponding to 5 Mbps is assigned an ID272 that represents "011" (decimal notation "3"). For example, the sequence data 271 corresponding to 10 Mbps is assigned an ID272 that represents "100" (decimal notation "4"). The sorting data 271 corresponding to 21 Mbps is assigned an ID 272, for example, that represents "101" ("5" in decimal notation).

[0110] The setting value data 273 is, for example, 5-bit data. In the setting value data 273, for example, "00001" (decimal "1") indicates 1 Mbps, "00010" (decimal "2") indicates 2 Mbps, and "00011" (decimal "3") indicates 3 Mbps. Also, in the setting value data 273, "00101" (decimal "5") indicates 5 Mbps, "01010" (decimal "10") indicates 10 Mbps, and "10101" (decimal "21") indicates 21 Mbps. The transmission rate data 260, which indicates the current setting value for the low transmission rate, is also 5-bit data, similar to the setting value data 273, and the meaning of the value indicated by the transmission rate data 260 is the same as the meaning of the value indicated by the setting value data 273. For example, when the transmission rate data 260 shows "00011", the transmission rate data 260 indicates 3 Mbps. Hereafter, the setting value being explained will be referred to as the target setting value. The target setting value can also be said to be the setting value of interest.

[0111] The sequence data 271 is K-bit data (where K is an integer greater than or equal to 2). The number of bits K in the sequence data 271 is set to be greater than or equal to, for example, the ratio of the high transmission rate to the minimum value of the low transmission rate setting. In this example, the minimum value of the low transmission rate setting is, for example, 1 Mbps. Therefore, the number of bits K in the sequence data 271 is set to 32 or more. Figure 10 shows an example of the sequence data 271 when K = 32.

[0112] The k-th bit (0 ≤ k ≤ K-1) in the sequence data 271 corresponds to the (k + 32 × j)-th bit in the data area 301. The variable j is an integer that increases from 0 to 1, such as 0, 1, 2, and so on. For example, the 0th bit of the sequence data 271 corresponds to the (0 + 32 × j)-th bit in the data area 301. In other words, the 0th bit of the sequence data 271 corresponds to the 0th, 32nd, 64th, 96th, ... bits in the data area 301. Also, the 1st bit of the sequence data 271 corresponds to the 1st, 33rd, 65th, 97th, ... bits in the data area 301.

[0113] In the sequence data 271 corresponding to the low transmission rate setting, if the k-th bit is "1", it means that when the low transmission rate is the target setting, the first bit of the first bit group to be transmitted is placed at the (k + 32 × j)th bit in the data area 301. More specifically, if the k-th bit in the sequence data 271 corresponding to the target setting is "1", it means that when the low transmission rate is the target setting, the first bit of the ((u-1) + (U × j))th bit of the first bit group to be transmitted is placed at the (k + 32 × j)th bit in the data area 301. On the other hand, if the k-th bit in the sequence data 271 corresponding to the target setting is "0", it means that when the low transmission rate is the target setting, a dummy bit is placed at the (k + 32 × j)th bit in the data area 301. The sequence data 271 can be said to be data representing a sequence of multiple bits that constitute the data area 301, or it can be said to be data representing a sequence of the first bit and dummy bits in the data area 301.

[0114] Here, the bit that represents "1" in the sequence data 271 is called a specific bit. The k-th bit that represents "1" can be said to be the specific bit located at the k-th bit. The above U is an integer greater than or equal to 1 and represents the number of specific bits included in the sequence data 271. The above u indicates the order in which the specific bit located at the k-th bit appears when the U specific bits included in the sequence data 271 are examined from the 0th bit to the (K-1)th bit of the sequence data 271. u is an integer greater than or equal to 1 and less than or equal to U. For example, when the U specific bits included in the sequence data 271 are examined from the 0th bit to the (K-1)th bit of the sequence data 271, if the specific bit located at the k-th bit appears second, then u = 2.

[0115] For example, in the sequenced data 271 corresponding to 1 Mbps, as shown in Figure 10, the 0th bit represents "1" (k=0), and the other bits represent "0". In this case, U=1, and for the specific bit located at the 0th bit, u=1. Therefore, when the low transmission rate is 1 Mbps, in the data area 301, the (0 + 32 × j)th bit is the first bit of the ((1 - 1) + (1 × j))th bit of the first bit group to be transmitted. Then, dummy bits are placed at bit positions other than the (0 + 32 × j)th bit. Specifically, when the low transmission rate is 1 Mbps, in the data area 301, the first bit of the 0th bit of the first bit group to be transmitted (in other words, the first bit of the beginning) is placed in the 0th bit position (when j=0), the first bit of the 1st bit of the first bit group to be transmitted is placed in the 32nd bit position (when j=1), and the first bit of the 2nd bit of the first bit group to be transmitted is placed in the 64th bit position (when j=2). In addition, dummy bits are placed in the 1st to 31st bits of the data area 301, and dummy bits are placed in the 33rd to 63rd bits. If the first bit of the i-th bit (where i is a non-negative integer) of the first bit group to be transmitted is represented by Di, then the data area 301 when the low transmission rate is 1 Mbps will be as shown in Figure 11.

[0116] In the sequenced data 271 corresponding to 2 Mbps, the 0th and 16th bits indicate "1" (k=0, 16), and the other bits indicate "0". In this case, U=2, so u=1 for the specific bit located at the 0th bit position and u=2 for the specific bit located at the 16th bit position. Therefore, when the low transmission rate is 2 Mbps, in the data area 301, the first bit of the ((1-1)+(2×j))th bit of the first bit group to be transmitted is arranged at the (0+32×j)th bit position, and the first bit of the ((2-1)+(2×j))th bit of the first bit group to be transmitted is arranged at the (16+32×j)th bit position. Then, dummy bits are arranged at bit positions other than the (0+32×j)th bit position and the (16+32×j)th bit position.

[0117] In the sequenced data 271 corresponding to 5Mbps, the 0th, 6th, 13th, 19th, and 26th bits indicate "1" (k = 0, 6, 13, 19, 26), and the other bits indicate "0". In this case, U = 5. Furthermore, for the specific bit located at the 0th bit, u = 1; for the specific bit located at the 6th bit, u = 2; for the specific bit located at the 13th bit, u = 3; for the specific bit located at the 19th bit, u = 4; and for the specific bit located at the 26th bit, u = 5. Therefore, when the low transmission rate is 5 Mbps, in the data area 301, the (0 + 32 × j) bit position is occupied by the ((1 - 1) + (5 × j)) bit position of the first bit group to be transmitted, the (6 + 32 × j) bit position is occupied by the ((2 - 1) + (5 × j)) bit position of the first bit group to be transmitted, and the (13 + 32 × j) bit position is occupied by the ((3 - 1) + (5 × j)) bit position of the first bit group to be transmitted. Also, in the data area 301, the (19 + 32 × j) bit position is occupied by the ((4 - 1) + (5 × j)) bit position of the first bit group to be transmitted, and the (26 + 32 × j) bit position is occupied by the ((5 - 1) + (5 × j)) bit position of the first bit group to be transmitted. Then, dummy bits are placed at all bit positions except for the (0 + 32 × j)th, (6 + 32 × j)th, (13 + 32 × j)th, (19 + 32 × j)th, and (26 + 32 × j)th bits.

[0118] Figure 12 is a schematic diagram showing an example of the data area 301 when the low transmission rate is 5 Mbps. Figure 13 is a schematic diagram showing an example of the data area 301 when the low transmission rate is 21 Mbps.

[0119] <Example of a method for generating the first sorting data> The sorting data 271 is generated based on the low transmission rate and the high transmission rate. For example, the sorting data 271 is generated based on the rate ratio, that is, the ratio of the high transmission rate to the low transmission rate.

[0120] Here, the rate ratio is represented by R. The rate ratio R is expressed with two or more decimal places. In this example, we assume that the rate ratio R is expressed with two decimal places. Also, S is the value obtained by multiplying the rate ratio R by the variable w (R × w) and rounding the decimal part (i.e., an integer). The variable w is an integer that increases from 0 to 1 (Q-1). When Q = 1, that is, when the low transmission rate is 1 Mbps, w is fixed at 0.

[0121] In the sequence data 271, the S-th bit is set to "1", and the other bits are set to "0". When the low transmission rate is 1 Mbps, R = 32, w = 0, and S = 0. Therefore, as shown in Figure 10, the 0th bit is set to "1", and the other bits are set to "0".

[0122] When the low transmission rate is 2 Mbps, R = 16, w = 0, 1, and S = 0, 16. Therefore, as shown in Figure 10, the 0th and 16th bits are set to "1", and the other bits are set to "0".

[0123] When the low transmission rate is 3 Mbps, R = 10.67, w = 0, 1, 2, and S = 0, 11, 21. Therefore, as shown in Figure 10, the 0th, 11th, and 21st bits are set to "1", and the other bits are set to "0".

[0124] When the low transmission rate is 5 Mbps, R = 6.40, w = 0, 1, 2, 3, 4, and S = 0, 6, 13, 19, 26. Therefore, as shown in Figure 10, the 0th, 6th, 13th, 19th, and 26th bits are set to "1", and the other bits are set to "0".

[0125] When the low transmission rate is 10 Mbps, R = 3.20, w = 0 to 9, and S = 0, 3, 6, 10, 13, 16, 19, 22, 26, 29. Therefore, as shown in Figure 10, the 0th, 3rd, 6th, 10th, 13th, 16th, 19th, 22nd, 26th, and 29th bits are set to "1", and the other bits are set to "0".

[0126] When the low transmission rate is 21 Mbps, R = 1.52, w = 0 to 20, and S = 0, 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23, 24, 26, 27, 29, 30. Therefore, as shown in Figure 10, bits 0, 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23, 24, 26, 27, 29, and 30 are set to "1", and the other bits are set to "0".

[0127] When the low transmission rate is 31 Mbps, R = 1.03, w = 0 to 30, and S = 0 to 16 and 18 to 31. Therefore, bits 0 to 16 and bits 18 to 31 are set to "1", and bit 17 is set to "0".

[0128] Thus, since the sequence data 271 representing the sequence of multiple first bits in the data area 301 is generated based on the rate ratio, the multiple first bits in the data area 301 are positioned in a sequence based on the rate ratio.

[0129] <Detailed explanation of the operation example of the read control unit, selection unit and header addition unit> The header addition unit 257 obtains the low transmission rate indicated by the transmission rate data 260 output by the data processing unit 251, that is, the current setting value of the low transmission rate. The header addition unit 257 obtains an ID 272 in the table 270 that is associated with the setting value data 273 indicating the current setting value. The ID 272 obtained by the header addition unit 257 is the ID 272 assigned to the sequence data 271 corresponding to the current setting value. If the current setting value is, for example, 3 Mbps, the header addition unit 257 obtains an ID 272 indicating "010". The header addition unit 257 adds the header 302 containing the ID 272 obtained from the table 270 to the data area 301 from the selection unit 256 to generate high-speed serial data 300.

[0130] The table processing unit 258 performs processing based on the table 270. The table processing unit 258 obtains the current setting value indicated by the transmission rate data 260 output by the data processing unit 251. Next, the table processing unit 258 obtains the sorting data 271 associated with the setting value data 273 indicating the current setting value in the table 270. The sorting data 271 obtained by the table processing unit 258 from the table 270 is sorting data 271 corresponding to the current setting value of the low transmission rate.

[0131] The table processing unit 258 performs a verification process that repeatedly executes a unit verification process to check the value of each of the K bits contained in the acquired sequence data 271. The table processing unit 258 starts the verification process when the write control unit 254 writes the first bit of the first bit group to be transmitted to the buffer 253.

[0132] In the unit verification process, the table processing unit 258 sequentially verifies the values ​​of the K bits contained in the sequenced data 271, one bit at a time, from the 0th bit to the (K-1)th bit, at a high bit period (i.e., the reciprocal of the high transmission rate). Then, in the unit verification process, when the value of the verified bit is "1", that is, when a specific bit is verified, the table processing unit 258 outputs a 1-bit data indicating "1", and when the value of the verified bit is "0", it outputs a 1-bit data indicating "0". Hereafter, the 1-bit data indicating "1" will be called data 1, and the 1-bit data indicating "0" will be called data 0.

[0133] In the unit verification process, the table processing unit 258 checks the value of the (K-1)th bit of the sequenced data 271 and outputs the data, then starts the execution of the next unit verification process to check the value of the 0th bit of the sequenced data 271. After checking the value of the (K-1)th bit of the sequenced data 271, the table processing unit 258 checks the value of the 0th bit of the sequenced data 271 in the next unit verification process after a high bit cycle. In the verification process, the table processing unit 258 repeatedly checks the value of each bit of the sequenced data 271 from the 0th bit to the (K-1)th bit at a high bit cycle. The table processing unit 258 repeatedly outputs 1-bit data at a high bit cycle.

[0134] The read control unit 255 reads one bit of data from the buffer 253 each time the table processing unit 258 outputs data 1, thereby reading one bit of each first bit of the first bit group to be transmitted that is written to the buffer 253 in sequence. The table processing unit 258 outputs data 1 in response to one bit of first bits being written to the buffer 253. After the first bit is written to the buffer 253, the read control unit 255 reads one bit of data from the buffer 253 each time the table processing unit 258 outputs data 1, thereby reading the nth first bit from the buffer 253 before the (n+1)th first bit is written to the buffer 253. The buffer 253 outputs the nth first bit before the (n+1)th first bit is written.

[0135] The selection unit 256 performs a selection output process, selecting and outputting either the first bit or a dummy bit output by the buffer 253 each time the table processing unit 258 outputs 1 bit data. Since the table processing unit 258 outputs 1 bit data at a high bit cycle, the selection unit 256 performs the selection output process at a high bit cycle. In the selection output process, when the table processing unit 258 outputs data 1, the selection unit 256 selects and outputs the first bit output by the buffer 253. The selection unit 256 selects and outputs the first bit that the read control unit 255 reads from the buffer 253 in response to the output of data 1 from the table processing unit 258. In other words, the selection unit 256 selects and outputs the first bit output from the buffer 235 in response to the output of data 1 from the table processing unit 258. On the other hand, in the selection output process, when the table processing unit 258 outputs data 0, the selection unit 256 selects and outputs a dummy bit. The selection unit 256 performs selection output processing at a high bit cycle, thereby outputting the data area 301, which consists of the first group of bits to be transmitted and at least one dummy bit, as serial data to the header addition unit 257 at a high transmission rate (e.g., 32 Mbps).

[0136] The first processing unit, consisting of a read control unit 255 and a selection unit 256, reads the first bit from the buffer 253 and outputs it to the header addition unit 257 when the table processing unit 258 outputs data 1, and outputs a dummy bit to the header addition unit 257 when the table processing unit 258 outputs data 0. The first processing unit also outputs either the first bit or the dummy bit to the header addition unit 257 at a high bit cycle.

[0137] Here, in the verification process in which the unit verification process is repeatedly executed, the v-th data 1 output by the table processing unit 258 (where v is an integer of 2 or more) is called the v-th data 1. Furthermore, the specific bit that is the source of the output of the v-th data 1, that is, the specific bit that is checked one bit at a time from the 0th bit to the (K-1)th bit in the verification process, is called the v-th specific bit.

[0138] In the verification process, the table processing unit 258 outputs the v-th data 1 at a time Z after the output of the (v-1)th data 1. Time Z is equal to the time obtained by multiplying the number of bits verified from the (v-1)th specific bit to the v-th specific bit by the high-speed bit period. The number of bits verified refers to the number of bits verified by the table processing unit 258 from the (v-1)th specific bit to the v-th specific bit when it repeatedly verifies each bit of the sequenced data 271 in the verification process. Hereafter, the number of bits verified may be referred to as the v-th verification bit number. Also, time Z may be referred to as the v-th output interval Z.

[0139] For example, consider the case where sequence data 271 corresponding to 1 Mbps is used in the verification process. In sequence data 271 corresponding to 1 Mbps, only the 0th bit is a specific bit. Therefore, in each unit verification process, the specific bit is verified at the 0th bit. In this case, regardless of the value of v, the number of v-th verification bits is fixed at 32, and the v-th output interval Z is fixed at the time obtained by multiplying the high-speed bit period by 32. When the current setting is 1 Mbps, regardless of the value of v, the v-th output interval Z coincides with the low-speed bit period (i.e., the reciprocal of the low transmission rate). When the current setting is 1 Mbps, the table processing unit 258 outputs data 1 at the low-speed bit period. Therefore, the read control unit 255 reads the first bit from the buffer 253 at the low-speed bit period. In other words, the buffer 253 outputs the first bit at the low-speed bit period. The selection unit 256 also outputs the first bit at the low-speed bit period.

[0140] As another example, consider the case where the sorted data 271 corresponding to 2 Mbps is used in the verification process. In the sorted data 271 corresponding to 2 Mbps, the 0th and 16th bits are specific bits. Therefore, in each unit verification process, the specific bits are verified at the 0th and 16th bits. In this case, regardless of the value of v, the number of v-th verification bits is fixed at 16, and the output interval Z for the v-th bit is fixed at the time obtained by multiplying the high-speed bit period by 16. When the current setting is 2 Mbps, regardless of the value of v, the output interval Z for the v-th bit coincides with the low-speed bit period. When the current setting is 2 Mbps, the table processing unit 258 outputs data 1 at the low-speed bit period. Therefore, the read control unit 255 reads the first bit from the buffer 253 at the low-speed bit period. Also, the selection unit 256 outputs the first bit at the low-speed bit period.

[0141] As another example, consider the case where the sorted data 271 corresponding to 3 Mbps is used in the verification process. In the sorted data 271 corresponding to 3 Mbps, the 0th, 11th, and 21st bits are specific bits. Therefore, in each unit verification process, the specific bits are verified at the 0th, 11th, and 21st bits. In this case, the v-th output interval Z does not perfectly match the slow bit period. For example, the number of bits to verify in the second step is 11, and the output interval Z of the second step is the time obtained by multiplying the fast bit period by 11 (0.34 μs), which does not perfectly match the slow bit period (0.33 μs). Also, the number of bits to verify in the third step is 10, and the output interval Z of the third step is the time obtained by multiplying the fast bit period by 10 (0.32 μs), which does not perfectly match the slow bit period (0.33 μs). Therefore, if the current setting is 3 Mbps, the table processing unit 258 outputs data 1 at a time interval slightly different from the slow bit period. Consequently, the read control unit 255 reads the first bit from the buffer 253 at a time interval slightly different from the slow bit period. Also, the selection unit 256 outputs the first bit at a time interval slightly different from the slow bit period.

[0142] As another example, consider the case where the sorted data 271 corresponding to 10 Mbps is used in the verification process. In the sorted data 271 corresponding to 10 Mbps, the 0th, 3rd, 6th, 10th, 13th, 16th, 19th, 22nd, 26th, and 29th bits are specific bits. Therefore, in each unit verification process, the specific bits are verified at the 0th, 3rd, 6th, 10th, 13th, 16th, 19th, 22nd, 26th, and 29th bits. In this case, the vth output interval Z does not perfectly match the slow bit period. For example, the number of verification bits for the 2nd, 3rd, 5th, 6th, 7th, 8th, and 10th will be 3. Therefore, the output intervals Z for the 2nd, 3rd, 5th, 6th, 7th, 8th, and 10th bits are the time obtained by multiplying the high-speed bit period by 3 (0.094 μs), which does not perfectly match the low-speed bit period (0.10 μs). Also, the number of verifiable bits for the 4th and 9th bits is 4. Therefore, the output intervals Z for the 4th and 9th bits are the time obtained by multiplying the high-speed bit period by 4 (0.125 μs), which does not perfectly match the low-speed bit period (0.10 μs). Therefore, when the current setting is 10 Mbps, the table processing unit 258 outputs data 1 at a time interval slightly different from the low-speed bit period. Therefore, the read control unit 255 reads the first bit from the buffer 253 at a time interval slightly different from the low-speed bit period. Also, the selection unit 256 outputs the first bit at a time interval slightly different from the low-speed bit period.

[0143] As can be understood from the above explanation, when the rate ratio, i.e., the ratio of the high transmission rate to the low transmission rate (specifically the current setting), is an integer multiple, such as when the low transmission rate is 1 Mbps, 2 Mbps, and 4 Mbps, the table processing unit 258 outputs data 1 with the same period as the low-speed bit period. Therefore, the buffer 253 outputs the first bit with the same period as the low-speed bit period. In other words, the buffer 253 outputs the first bit at the same transmission rate as the low transmission rate (specifically the current setting). Also, the selection unit 256 outputs the first bit with the same period as the low-speed bit period.

[0144] On the other hand, when the rate ratio R is not an integer, such as when the low transmission rate is 3 Mbps, 5 Mbps, or 6 Mbps, the table processing unit 258 outputs data 1 at a time interval different from the low-speed bit period. Therefore, the buffer 253 and the selection unit 256 output the first bit at a time interval different from the low-speed bit period. This is because, as described above, S is the value obtained by rounding the decimal part of the value obtained by multiplying the rate ratio R by the variable w (R × w), and in the sequenced data 271, the S-th bit is set to "1". When the rate ratio R is not an integer, the difference between the time interval of data 1 output by the table processing unit 258 (in other words, the time interval of the first bit output by the buffer 253 and the selection unit 256) and the low-speed bit period is less than or equal to half of the low-speed bit period. When the rate ratio R is not an integer, the time interval of data 1 output by the table processing unit 258 is not constant.

[0145] Thus, when the rate ratio is an integer multiple, the time interval of data 1 output by the table processing unit 258 is the same as the low-speed bit period, and the selection unit 256 outputs the first bit at the same period as the low-speed bit period. For this reason, in the data area 301 output by the selection unit 256, the multiple first bits constituting the first bit group to be transmitted are positioned at time intervals that match the low-speed bit period (in other words, the reciprocal of the low transmission rate). For example, if the current setting is 1 Mbps, the low-speed bit period is 1 μs. Therefore, if the number of bits in the first bit group to be transmitted is 32 bits or more, in the data area 301, for example, 32 first bits are positioned at time intervals of 1 μs. Also, if the current setting is 8 Mbps, the low-speed bit period is 0.125 μs. Therefore, if the number of bits in the first bit group to be transmitted is 8 bits or more, in the data area 301, for example, 8 first bits are positioned at time intervals of 0.125 μs.

[0146] When the rate ratio is an integer multiple, in the data area 301, multiple first bits are positioned at intervals of the number of bits corresponding to the rate ratio. For example, if the current setting is 1 Mbps, the rate ratio is 32, and in the data area 301, multiple first bits are positioned at 32-bit intervals, as shown in Figure 11. Also, if the current setting is 2 Mbps, the rate ratio is 16, and in the data area 301, multiple first bits are positioned at 16-bit intervals.

[0147] Furthermore, if the rate ratio R is not an integer, the time interval of data 1 output by the table processing unit 258 will differ from the slow bit period. In this case, if the first bit output by the data processing unit 251 at the slow bit period is directly input to the selection unit 256, the selection unit 256 may not be able to output the multiple first bits constituting the first bit group to be transmitted one bit at a time in sequence. For example, suppose the current setting is 3 Mbps. In this case, as described above, the third output interval Z (v=2) becomes 0.32 μs, which is shorter than the slow bit period (0.33 μs). As a result, the selection unit 256 may select and output data from the data processing unit 251 before the first bit of the second bit corresponding to the third specific bit (in other words, the third first bit from the beginning) is output from the data processing unit 251. In other words, the selection unit 256 may not be able to select and output the first bit of the second bit corresponding to the third specific bit.

[0148] In contrast, in this example, a buffer 253 is provided to which the first bit output by the data processing unit 251 is written. Therefore, the read control unit 255 can read each first bit constituting the first bit group to be transmitted from the buffer 253 after the first bit has been written to the buffer 253. As a result, the selection unit 256, which selects the first bit from the buffer 253, can appropriately select and output one bit at a time from the multiple first bits constituting the first bit group to be transmitted. In this example, it can also be said that the buffer 253 can absorb the discrepancy between the time interval of the data 1 output by the table processing unit 258 and the low-speed bit period when the rate ratio R is not an integer.

[0149] As mentioned above, when the rate ratio R is not an integer, the difference between the time interval of data 1 output by the table processing unit 258 and the slow bit period is less than or equal to half of the slow bit period. Therefore, the buffer 253 only needs to be able to store at least one bit of the first bit.

[0150] In this example, as shown in Figures 11 to 13 above, the first bit of the first set of first bits constituting the first bit group to be transmitted is located at the beginning of the data area 301 output from the selection unit 256. This allows the high-speed communication unit 28 to start receiving the first bit earlier. Therefore, the high-speed communication unit 28 can start transmitting the high-speed packet 100 containing the first bit group to be transmitted earlier.

[0151] Furthermore, in this example, as shown in Figures 11 to 13, the data area 301 includes a plurality of unit data 310, each containing a portion of the first bit group to be transmitted and at least one dummy bit, and the sequence of the portion of the first bit group to be transmitted and the at least one dummy bit is the same for all of them. In other words, the data area 301 includes a plurality of unit data 310, each containing at least one first bit and at least one dummy bit, and the sequence of the at least first bit and the at least one dummy bit is the same for all of them. In the data area 301, unit data 310 containing at least one first bit and at least one dummy bit appear repeatedly. At the beginning of the unit data 310 is the first bit of the portion of the first bit group to be transmitted included in the unit data 310.

[0152] When the low transmission rate setting is 2 Mbps or higher, the unit data 310 contains multiple first bits (see Figures 12 and 13). When the low transmission rate setting is 2 Mbps or higher, in the unit data 310, multiple first bits that constitute a part of the group of first bits to be transmitted are positioned in an order based on the rate ratio. As can be understood from the above explanation, when the low transmission rate setting is 2 Mbps or higher, the positions of multiple specific bits in the order data 271 are set based on the rate ratio, so it can be said that in the unit data 310, multiple first bits are positioned in an order based on the rate ratio.

[0153] Furthermore, when the low transmission rate setting is 2 Mbps or higher and the rate ratio is an integer multiple, in the unit data 310, the multiple first bits contained in the unit data 310 are positioned at time intervals that match the low-speed bit period (in other words, the reciprocal of the low transmission rate). For example, if the current setting is 2 Mbps, the low-speed bit period is 0.5 μs. Therefore, in the unit data 310, two first bits are positioned at a time interval of 0.5 μs. Also, if the current setting is 16 Mbps, the low-speed bit period is 0.0625 μs. Therefore, in the unit data 310, sixteen first bits are positioned at a time interval of 0.0625 μs.

[0154] Furthermore, when the low transmission rate setting is 2 Mbps or higher, and the rate ratio is an integer multiple, in the unit data 310, multiple first bits are positioned at intervals of the number of bits corresponding to the rate ratio. For example, if the current setting is 4 Mbps, the rate ratio is 8. Therefore, in the unit data 310, four first bits are positioned at 8-bit intervals.

[0155] In this way, because unit data 310 containing at least one first bit repeatedly appears in the data area 301, the high-speed communication unit 28 can receive the first bit between the start of receiving the first unit data 310 and the start of receiving the second unit data 310. Therefore, the start of receiving the first bit in the high-speed communication unit 28 can be accelerated. As a result, the high-speed communication unit 28 can accelerate the start of transmission of the high-speed packet 100 containing the first bit group to be transmitted.

[0156] Furthermore, in this example, since the first bit of a portion of the first bit group to be transmitted included in the unit data 310 is located at the beginning of the unit data 310, the reception of the first bit by the high-speed communication unit 28 can be started earlier. As a result, the high-speed communication unit 28 can start transmitting the high-speed packet 100, which includes the first bit group to be transmitted, earlier.

[0157] The low-speed communication unit 25 may generate the data area 301 without using the sequence data 271. Figure 14 is a schematic diagram showing an example of the configuration of the low-speed communication unit 25 in this case.

[0158] The low-speed communication unit 25 (also referred to as the low-speed communication unit 25A) shown in Figure 14 includes a data processing unit 259. The low-speed communication unit 25A generates a data area 301 based, for example, on the low-speed transmission rate and the high-speed transmission rate. For example, the low-speed communication unit 25A generates a data area 301 based on the ratio of the high-speed transmission rate to the low-speed transmission rate, i.e., the rate ratio.

[0159] The data processing unit 259 stores a second table. The second table is the table 270 with the sorting data 271 removed. The data processing unit 259 obtains the low transmission rate indicated by the transmission rate data 260 output by the data processing unit 251, that is, the current setting value of the low transmission rate. The data processing unit 259 then obtains the ID 272 associated with the setting value data 273 indicating the current setting value from the second table and outputs it to the header addition unit 257. The header addition unit 257 adds the header 302 containing the ID 272 from the data processing unit 259 to the data area 301 from the selection unit 256 to generate high-speed serial data 300.

[0160] Furthermore, the data processing unit 259 obtains a rate ratio based on the acquired current setting value and the high-speed transmission rate stored in advance. Then, the data processing unit 259 obtains the above value S by multiplying the acquired rate ratio by the variable w and rounding the decimal part of the resulting value (R × w). The data processing unit 259 increases the variable w from 0 to 1 (Q-1) in increments, obtaining Q values ​​S.

[0161] The data processing unit 259 has a counter that repeatedly counts up from 0 to 31 at a high bit period. The data processing unit 259 performs a comparison process that compares the counter's count value with a value S. In the comparison process, the data processing unit 259 first sets w = 0. Then, the data processing unit 259 starts the counter's operation and compares the count value with the value S when w = 0. After that, the data processing unit 259 compares the count value with the value S each time the count value changes. In the comparison process, if the count value and the value S match, the data processing unit 259 outputs data 1 and increments the variable w by 1. In the comparison process, if the count value and the value S do not match, the data processing unit 259 outputs data 0. In this case, the variable w does not change.

[0162] As the data processing unit 259 operates in this manner, it outputs 1-bit data indicating "1" or "0" at a high bit cycle, similar to the table processing unit 258 described above. The read control unit 255 and the selection unit 256 operate in the same manner as described above, and the data area 301 is output from the selection unit 256 at a high transmission rate. Alternatively, the data processing unit 259 may store a third table containing the Q values ​​S in advance, rather than calculating the Q values ​​S, and perform the comparison process using the third table.

[0163] <Example of Configuration of the Low-Speed ​​Communication Unit of the Restoration Unit> Figure 15 is a schematic diagram showing an example of the configuration of the low-speed communication unit 35 of the restoration unit 30. The low-speed communication unit 35 includes, for example, an interface 350 and a generation unit 351. The generation unit 351 receives the restored high-speed serial data 300 transmitted at a high transmission rate by the high-speed communication unit 38. The generation unit 351 restores the low-speed serial data 200 based on the restored high-speed serial data 300. In other words, the generation unit 351 generates restored low-speed serial data 200 by restoring the low-speed serial data 200 based on the restored high-speed serial data 300. The generation unit 351 outputs the restored low-speed serial data 200 to the interface 350 at a low transmission rate.

[0164] Interface 350 can communicate with processing unit 2. Interface 350 is connected to processing unit 2 by, for example, an electric wire. Interface 350 transmits the restored low-speed serial data 200 output from generation unit 351 to processing unit 2 as a differential signal.

[0165] The generation unit 351 includes, for example, a header separation unit 352, a buffer 353, a write control unit 354, a read control unit 355, and a table processing unit 358.

[0166] The header separation unit 352 receives the restored high-speed serial data 300 transmitted at a high transmission rate by the high-speed communication unit 38. The header separation unit 352 separates the header 302 from the restored high-speed serial data 300 and obtains the data area 301. The header separation unit 352 outputs the data area 301 to the buffer 353 one bit at a time from the beginning. The header separation unit 352 outputs the data area 301 one bit at a time in serial format at a high transmission rate. The header separation unit 352 also obtains the ID 272 contained in the header 302 and outputs it to the table processing unit 358.

[0167] Buffer 353 is, for example, a FIFO buffer capable of storing at least one bit of data. The write control unit 354 controls the writing of data to buffer 353. The write control unit 354 outputs a write pointer to buffer 353, for example. By controlling the write pointer, the write control unit 354 writes each first bit included in the data area 301 output by the header separator unit 352 to buffer 353 one bit at a time.

[0168] The read control unit 355 controls the reading of data from the buffer 353. For example, the read control unit 355 outputs a read pointer to the buffer 353. By controlling the read pointer, the read control unit 355 sequentially reads the first bit from the buffer 353 one bit at a time.

[0169] The read control unit 355 reads one bit of the first bit from buffer 353 each time one bit of the first bit is written to buffer 353. The read control unit 355 also starts reading the first bit from buffer 353 as soon as writing of the first bit to buffer 353 begins. In other words, the read control unit 355 starts reading the first bit from buffer 353 as soon as the first of several first bits contained in the data area 301 is written to buffer 353. It can also be said that the read control unit 355 starts reading the first bit from buffer 353 in response to the first write of the first bit to buffer 353. The read control unit 355 also reads the nth first bit from buffer 353 when the nth first bit is written to buffer 353, before the (n+1)th first bit is written to buffer 353.

[0170] The read control unit 355 reads the first bit one bit at a time from the buffer 353 at a low bit period (i.e., the reciprocal of the low transmission rate). As a result, the buffer 353 sequentially outputs one bit at a time at a low bit period from multiple first bits contained in the data area 301, that is, multiple first bits that constitute the group of first bits to be transmitted. The first bits output from the buffer 353 are input to the interface 350.

[0171] In this example, all of the multiple first bits constituting the low-speed serial data 200 constitute the first bit group to be transmitted. Therefore, the buffer 353, which sequentially outputs the multiple first bits constituting the first bit group to be transmitted one bit at a time at a low bit period, can also be said to output the restored low-speed serial data 200 (in other words, the low-speed packet 200) to the interface 350 at a low transmission rate. The low-speed communication unit 35 can also be said to generate the restored low-speed serial data 200 by sequentially reading the multiple first bits constituting the first bit group to be transmitted one bit at a time from the buffer 353.

[0172] The low-speed communication unit 35 stores, for example, the same table 370 as the table 270 stored by the low-speed communication unit 25. The low-speed communication unit 35 generates restored low-speed serial data 200 based on the sequence data 271 included in table 370 and the restored high-speed serial data 300 from the high-speed communication unit 38. The low-speed communication unit 35 can easily generate restored low-speed serial data 200 by generating it based on the sequence data 271.

[0173] The table processing unit 358 performs processing based on the table 370. The table processing unit 358 obtains the sequence data 271 from the table 370 that corresponds to the ID 272 output by the header separation unit 352. The sequence data 271 obtained by the table processing unit 358 from the table 370 is sequence data 271 that corresponds to the current setting value of the low transmission rate.

[0174] The table processing unit 358 outputs 1-bit data indicating "1" or "0" based on the acquired sequence data 271, in the same manner as the table processing unit 258 described above, at a high bit cycle. The table processing unit 358 also performs a verification process, in the same manner as the table processing unit 258, which repeatedly performs a unit verification process. The table processing unit 358 starts the verification process at the timing when the header separation unit 352 outputs the first bit of the first bit group to be transmitted.

[0175] In the unit verification process, the table processing unit 358 sequentially checks the values ​​of the K bits contained in the sequence data 271, one bit at a time at a high bit cycle, from the 0th bit to the (K-1)th bit. Then, in the unit verification process, the table processing unit 358 outputs data 1 when the value of the checked bit is "1", that is, when a specific bit is checked, and outputs data 0 when the value of the checked bit is "0". In the verification process, the table processing unit 358 repeatedly checks the values ​​of the sequence data 271 one bit at a time at a high bit cycle, from the 0th bit to the (K-1)th bit, and repeatedly outputs 1-bit data at a high bit cycle.

[0176] The timing at which the table processing unit 358 checks the bit values ​​of the sequence data 271 and outputs 1-bit data is synchronized with the timing at which the header separation unit 352 outputs the first bit. At the timing when the header separation unit 352 outputs the first bit, the table processing unit 358 checks the value of the 0th bit of the sequence data 271 and outputs 1-bit data (in this example, the value of the 0th bit is "1", so data 1). Then, the table processing unit 358 outputs 1-bit data at each timing when the header separation unit 352 outputs the first bit.

[0177] The write control unit 354 writes the data output by the header separator unit 352 to the buffer 353 each time the table processing unit 258 outputs data 1. As a result, each first bit of the first group of bits to be transmitted output by the header separator unit 352 is written to the buffer 353 one bit at a time. On the other hand, the dummy bits output by the header separator unit 352 are not written to the buffer 353. The first bits that are sequentially written to the buffer 353 by the write control unit 354 are read out sequentially from the buffer 353 at a slow bit rate by the read control unit 355 as described above and input to the interface 350.

[0178] As can be understood from the above explanation, when the rate ratio is an integer multiple, such as when the low transmission rate is 1 Mbps, 2 Mbps, and 4 Mbps, the time interval between the first bits in the data area 301 output from the header separation unit 352 matches the low-speed bit period.

[0179] On the other hand, when the rate ratio is not an integer multiple, such as when the low transmission rate is 3 Mbps, 5 Mbps, or 6 Mbps, the time interval between the first bits in the data area 301 output from the header separation unit 352 will differ from the low-speed bit period. In this case, if a sampling unit is provided and the sampling unit attempts to sample the data area 301 output by the header separation unit 352 at the low-speed bit period to acquire the first bit and output it to the interface 350, it may not be possible to properly acquire each first bit that constitutes the first bit group to be transmitted. For example, suppose the current setting is 3 Mbps. In this case, as described above, the second output interval Z (v=2) becomes 0.34 μs, which is longer than the low-speed bit period (0.33 μs). As a result, when the sampling unit (in other words, the acquisition unit) attempts to sample the first bit of the first bit corresponding to the second specific bit (in other words, the second first bit from the beginning), it may sample data from the header separation unit 352 before the first bit of the first bit is output from the header separation unit 352. In other words, the sampling unit may not be able to acquire and output the first bit of the first bit corresponding to the second specific bit.

[0180] In contrast, in this example, a buffer 353 is provided to which the first bit output by the header separation unit 352 is written. Therefore, the read control unit 355 can read each first bit constituting the first bit group to be transmitted from the buffer 353 after the first bit has been written to the buffer 353. As a result, the buffer 353 can output multiple first bits constituting the first bit group to be transmitted one bit at a time in order. In this example, it can also be said that the buffer 353 can absorb the shift in the time interval of the arrangement of the first bits in the data area 301 relative to the slow bit period when the rate ratio is not an integer multiple.

[0181] As mentioned above, when the rate ratio is not an integer multiple, the difference between the time interval for the arrangement of the first bit in the data area 301 and the slow bit period is less than or equal to half of the slow bit period. Therefore, buffer 353 only needs to be able to store at least one bit of the first bit.

[0182] The low-speed communication unit 35 may generate the restored low-speed serial data 200 without using the sequence data 271. Figure 16 is a schematic diagram showing an example of the configuration of the low-speed communication unit 35 in this case.

[0183] The low-speed communication unit 35 (also referred to as the low-speed communication unit 35A) shown in Figure 16 includes a data processing unit 359. The low-speed communication unit 35A generates reconstructed low-speed serial data 200 based, for example, on the low-speed transmission rate and the high-speed transmission rate. For example, the low-speed communication unit 35A generates reconstructed low-speed serial data 200 based on the ratio of the high-speed transmission rate to the low-speed transmission rate, i.e., the rate ratio.

[0184] The data processing unit 359 stores the second table described above. The second table is obtained by deleting the sequence data 271 from table 370 (in other words, table 270). The data processing unit 359 obtains the setting value data 273 corresponding to the ID 272 output by the header separation unit 352 from the second table. The data processing unit 359 then sets the setting value indicated by the obtained setting value data 273 as the current setting value for the low transmission rate.

[0185] The data processing unit 359 obtains a rate ratio based on the acquired current setting value and the high-speed transmission rate stored in advance. The data processing unit 359 obtains the above value S by multiplying the acquired rate ratio by the variable w and rounding the decimal part of the resulting value (R × w). The data processing unit 359 increases the variable w from 0 to 1 (Q-1) to obtain Q values ​​S.

[0186] The data processing unit 359 has a counter that repeatedly performs a process of counting up from 0 to 31 at a high bit period. The data processing unit 359 performs a comparison process that compares the counter's count value with the value S, similar to the data processing unit 259 described above. In the comparison process, the data processing unit 359 first sets w = 0. Then, the data processing unit 359 starts the counter's operation and compares the count value with the value S when w = 0. After that, the data processing unit 359 compares the count value with the value S each time the count value changes. In the comparison process, if the count value and the value S match, the data processing unit 359 outputs data 1 and increments the variable w by 1. In the comparison process, if the count value and the value S do not match, the data processing unit 359 outputs data 0.

[0187] As the data processing unit 359 operates in this manner, it outputs 1-bit data indicating "1" or "0" at a high bit cycle, similar to the table processing unit 358 described above. The write control unit 354 operates in the same manner as above and writes each first bit output by the header separation unit 352 to the buffer 353. Alternatively, the data processing unit 359 may store a third table containing the Q values ​​S in advance, rather than calculating the Q values ​​S, and perform the comparison process using the third table.

[0188] The low-speed communication unit 25 of the generation unit 20 may generate high-speed serial data 300 based on a plurality of first bits that are not written to the buffer 253 when the rate ratio is an integer multiple, and transmit the high-speed serial data 300. Figure 17 is a schematic diagram showing an example of the configuration of the low-speed communication unit 25 in this case.

[0189] In the low-speed communication unit 25 (also called the low-speed communication unit 25B) shown in Figure 17, the selection unit 256 selects and outputs either the first bit or the dummy bit output from the buffer 253 in the same manner as described above when the rate ratio is not an integer multiple. On the other hand, when the rate ratio is an integer multiple, the selection unit 256 selects and outputs either the first bit or the dummy bit output from the data processing unit 251. As described above, when the rate ratio is an integer multiple, the table processing unit 258 outputs data 1 with the same period as the low-speed bit period. Therefore, the selection unit 256 can appropriately select the first bit at the timing when the data processing unit 251, which sequentially outputs the first bit with the low-speed bit period, outputs the first bit. Thus, the selection unit 256 can output the data area 301 at a low transmission rate.

[0190] In the low-speed communication unit 25B, if the rate ratio is an integer multiple, the write control unit 254 may or may not write the first bit output by the data processing unit 251 to the buffer 253. Even if the first bit output by the data processing unit 251 is written to the buffer 253 when the rate ratio is an integer multiple, the selection unit 256 does not select the first bit from the buffer 253, but rather selects the first bit from the data processing unit 251 that is not written to the buffer 253.

[0191] Thus, when the rate ratio is an integer multiple, the low-speed communication unit 25 generates high-speed serial data 300 based on multiple first bits that are not written to the buffer 253, thereby reducing the latency from the start of receiving the low-speed serial data 200 to the start of transmitting the high-speed serial data 300. Therefore, the high-speed communication unit 28 can start transmitting the high-speed packet 100, which includes the group of first bits to be transmitted, earlier.

[0192] The low-speed communication unit 35 of the restoration unit 30 may generate restored low-speed serial data 200 based on a plurality of first bits that are not written to the buffer 353 when the rate ratio is an integer multiple, and transmit the restored low-speed serial data 200. Figure 18 is a schematic diagram showing an example of the configuration of the low-speed communication unit 35 in this case.

[0193] In the low-speed communication unit 35 (also called the low-speed communication unit 35B) shown in Figure 18, if the rate ratio is not an integer multiple, the interface 350 transmits the restored low-speed serial data 200 output from the buffer 353 to the processing unit 2 in the same manner as described above. On the other hand, if the rate ratio is an integer multiple, the interface 350 transmits the restored low-speed serial data 200 output from the sampling unit 360 to the processing unit 2.

[0194] The sampling unit 360 samples the data area 301 output by the header separation unit 352 at a slow bit period to acquire each first bit constituting the data area 301 and outputs it to the interface 350. As a result, the sampling unit 360 generates restored slow serial data 200 based on the multiple first bits output from the header separation unit 352 that are not written to the buffer 353, and outputs the restored slow serial data 200 to the interface 350. As described above, when the rate ratio is an integer multiple, the time interval of the arrangement of first bits in the data area 301 matches the slow bit period, so the sampling unit 360 can acquire each first bit of the group of first bits to be transmitted contained in the data area 301 by sampling the data area 301 at a slow bit period.

[0195] In the low-speed communication unit 35B, if the rate ratio is an integer multiple, the write control unit 254 may or may not write the first bit output by the header separation unit 352 to the buffer 353. Even if the first bit output by the header separation unit 352 is written to the buffer 353 when the rate ratio is an integer multiple, the interface 350 does not transmit the restored low-speed serial data 200 from the buffer 353, but rather transmits the restored low-speed serial data 200 generated from the sampling unit 360 using multiple first bits that are not written to the buffer 353.

[0196] Thus, when the rate ratio is an integer multiple, the low-speed communication unit 35 generates the restored low-speed serial data 200 based on a plurality of first bits that are not written to the buffer 353, thereby enabling the low-speed communication unit 35 to start transmitting the restored low-speed serial data 200 earlier.

[0197] Tables 270 and 370 are not limited to the examples above. For example, tables 270 and 370 do not necessarily contain ID 272. In this case, the header 302 included in the high-speed serial data 300 may contain transmission rate data 260. The low-speed communication unit 25 can obtain sequence data 271 from table 270 according to the current setting value based on the transmission rate data 260. The low-speed communication unit 35 can obtain sequence data 271 from table 370 according to the current setting value based on the transmission rate data 260 included in the header 302.

[0198] Furthermore, the table 270 stored by the low-speed communication unit 25B shown in Figure 17 may include storage time data 275 indicating the time for the buffer 253 to store the first bit, as shown in Figure 19. As shown in Figure 19, the storage time data 275 is associated with the setting value data 273. The storage time data 275 is, for example, 2-bit data. If the setting value data 273 indicates a setting value for which the rate ratio is an integer multiple, the storage time data 275 indicating, for example, "00" is associated with the setting value data 273. On the other hand, if the setting value data 273 indicates a setting value for which the rate ratio is not an integer multiple, the storage time data 275 indicating, for example, "01" is associated with the setting value data 273.

[0199] The low-speed communication unit 25B obtains storage time data 275 from the table 270 that corresponds to the setting value data 273 indicating the current setting value. If the obtained storage time data 275 indicates "01", the low-speed communication unit 25B writes the first bit output by the data processing unit 251 to the buffer 253 as described above, and reads the first bit from the buffer 253 before the next first bit is written to the buffer 253. As a result, the first bit is stored in the buffer 253 for a maximum of time equivalent to one bit, that is, for the low-speed bit period. Then, the selection unit 256 selects the first bit from the buffer 253 and generates the data area 301. The "01" indicated by the storage time data 275 means that the buffer 253 stores the first bit for a maximum of time equivalent to one bit (in other words, the low-speed bit period).

[0200] On the other hand, the low-speed communication unit 25 does not write the first bit to the buffer 253 if the acquired storage time data 275 indicates "00". Then, the selection unit 256 selects the first bit output by the data processing unit 251 to generate the data area 301. The "00" indicated by the storage time data 275 means that the buffer 253 does not store the first bit.

[0201] Furthermore, the table 370 stored by the low-speed communication unit 35B shown in Figure 18 may also include storage time data 275 indicating the time that the buffer 353 stores data, similar to the table 270 shown in Figure 19. The low-speed communication unit 35B obtains the storage time data 275 corresponding to the setting value data 273 indicating the current setting value from the table 370. If the obtained storage time data 275 indicates "01", the low-speed communication unit 35 writes the first bit output by the header separation unit 352 to the buffer 353 as described above, and reads the first bit from the buffer 353 before the next first bit is written to the buffer 353. As a result, the first bit is stored in the buffer 353 for a maximum of one bit's worth of time, i.e., the low-speed bit period. Then, the interface 350 transmits the restored low-speed serial data 200 from the buffer 353.

[0202] On the other hand, the low-speed communication unit 35 does not write the first bit to the buffer 353 if the acquired storage time data 275 indicates "00". Then, the interface 350 transmits the restored low-speed serial data 200 output by the sampling unit 360.

[0203] The position of a specific bit (i.e., a bit indicating "1") in the sequence data 271 is not limited to the example above. For example, the value of the 0th bit of the sequence data 271 may indicate "0". In this case, a dummy bit is located at the beginning of the data area 301.

[0204] Furthermore, for example, in the sequence data 271 corresponding to 3Mbps, the value of the 0th bit may be "0", and the values ​​of the 10th and 11th bits may consecutively be "1". In this case, by buffer 253 simultaneously accumulating at least two first bits, the read control unit 255 can appropriately read each first bit of the first bit group to be transmitted from buffer 253. In this case, by appropriately setting the start timing of reading data from buffer 253 so that the read control unit 255 can read the first bits sequentially from buffer 253, the first bits will be accumulated in buffer 253 for a maximum time equivalent to two bits (i.e., twice the slow bit period). Also, by buffer 353 simultaneously accumulating at least two first bits, the read control unit 355 can appropriately read each first bit of the first bit group to be transmitted from buffer 353. The read control unit 355 sets the start timing of data reading from buffer 353 appropriately so that it can read the first bit sequentially from buffer 353. As a result, the first bit is stored in buffer 353 for a maximum of two bits.

[0205] Furthermore, in the sequence data 271 corresponding to 3Mbps, the values ​​of the 0th and 13th bits may be "0", and the values ​​of the 19th, 20th, and 21st bits may consecutively be "1". In this case, by buffer 253 simultaneously accumulating at least 3 bits of the first bit, the read control unit 255 can appropriately read each first bit of the first bit group to be transmitted from buffer 253. In this case, the first bit will be accumulated in buffer 253 for a time equivalent to a maximum of 3 bits (i.e., 3 times the low-speed bit period). Also, by buffer 353 simultaneously accumulating at least 3 bits of the first bit, the read control unit 355 can appropriately read each first bit of the first bit group to be transmitted from buffer 353. In buffer 353, the first bit will be accumulated for a time equivalent to a maximum of 3 bits. Depending on the number of bits that buffers 253 and 353 can accumulate, the position of a specific bit in the sequence data 271 can be appropriately changed.

[0206] Furthermore, even if the value of the 0th bit of the sequence data 271 is "0", the sequence data 271 may have specific bits (i.e., bits that represent "1") arranged evenly or nearly evenly, as in the example in Figure 10.

[0207] If the time for which the first bit is stored in buffers 253 and 353 changes depending on the low transmission rate setting, in order for the first bit to be properly read from buffers 253 and 353, then in tables 270 and 370, storage time data 275 may be associated with the setting value data 273. In this case, the read control unit 255 sets the start timing for reading data from buffer 253 based on the storage time data 275 corresponding to the current setting included in table 270, and the read control unit 355 sets the start timing for reading data from buffer 353 based on the storage time data 275 corresponding to the current setting included in table 370. By reducing the storage time of the first bit in buffer 253, the timing at which the high-speed side communication unit 28 starts receiving high-speed serial data 300 can be brought forward. Also, by reducing the storage time of the first bit in buffer 353, the timing at which the processing unit 2 starts receiving restored low-speed serial data 200 can be brought forward.

[0208] In the example above, the processing unit 2 transmits the low-speed serial data 200 in packets, but the low-speed serial data 200 may be transmitted continuously instead of in packets. Furthermore, the processing unit 2 may receive the low-speed serial data 200 continuously instead of in packets.

[0209] Furthermore, in the above example, the number of unit data 310 corresponding to the sequence data 271 included in the data area 301 is multiple, but it may also be one. In this case, the number of bits in the sequence data 271 is determined such that one unit data 310 included in the data area 301 contains all of the multiple first bits that constitute the first bit to be transmitted.

[0210] Furthermore, in the above example, the communication device 10A is implemented by hardware circuits that do not require software to realize its functions. However, all or some of the functions of the communication device 10A may be realized by a processor such as a CPU (Central Processing Unit) executing software (in other words, a program) in memory. For example, all or some of the functions of the generation unit 20A may be realized by a processor executing software, and all or some of the functions of the restoration unit 30A may be realized by a processor executing software. Similarly, all or some of the functions of the communication device 10B may be realized by a processor executing software.

[0211] The functions of the elements disclosed herein may be implemented using general-purpose processors, dedicated processors, integrated circuits, ASICs ("Application-Specific Integrated Circuits"), conventional circuit configurations and / or combinations thereof, or processing circuit configurations, which are configured to perform the disclosed elements or programmed to perform the disclosed functions. A processor is considered a processing circuit configuration or circuit configuration if it includes transistors and other circuit configurations within it. In this disclosure, a circuit configuration, unit or means is hardware that performs the listed functions or hardware programmed to perform such functions. Hardware may be any hardware disclosed herein or other known hardware programmed to perform the listed functions or configured to perform such functions. When hardware is a processor that may be considered a certain type of circuit configuration, a circuit configuration, means or unit is a combination of hardware and software, software used to configure the hardware and / or processor.

[0212] As described above, the communication system has been explained in detail, but the above explanation is illustrative in all respects, and this disclosure is not limited thereto. Furthermore, the various examples described above can be combined and applied insofar as they do not contradict each other. And it is understood that countless variations not illustrated can be envisioned without falling outside the scope of this disclosure.

[0213] This disclosure includes the following aspects:

[0214] A first communication device according to the first embodiment includes a first communication unit that receives first serial data at a first transmission rate, generates second serial data at a second transmission rate higher than the first transmission rate, which includes a data area in the first serial data that includes a plurality of first bits to be transmitted and dummy data, and transmits the second serial data; and a second communication unit that receives the second serial data transmitted by the first communication unit and transmits transmission data including the data area included in the second serial data, wherein the first communication unit starts transmitting the second serial data while receiving the first serial data.

[0215] The first communication device according to the second embodiment is the first communication device according to the first embodiment, wherein the second communication unit starts transmitting the transmission data while receiving the second serial data.

[0216] The first communication device according to the third embodiment is a first communication device according to the first or second embodiment, wherein the positions of the plurality of first bits in the data area are determined based on the ratio of the second transmission rate to the first transmission rate.

[0217] The first communication device according to the fourth embodiment is a first communication device according to any one of the first to third embodiments, wherein in the data area, the plurality of first bits are located at intervals of a number of bits corresponding to the ratio of the second transmission rate to the first transmission rate.

[0218] The first communication device according to the fifth embodiment is a first communication device according to any one of the first to fourth embodiments, wherein the first bit of the plurality of first bits is located at the beginning of the data area.

[0219] A first communication device according to the sixth embodiment is a first communication device according to the first embodiment, wherein the dummy data includes a plurality of dummy bits, and the data area includes a plurality of unit data, each of which includes a portion of the plurality of first bits and at least one dummy bit, and the arrangement of the portion of the plurality of first bits and the at least one dummy bit is the same as that of the others.

[0220] The first communication device according to the seventh embodiment is the first communication device according to the sixth embodiment, wherein in each of the plurality of unit data, a portion of the plurality of first bits is positioned in an arrangement based on the ratio of the second transmission rate to the first transmission rate.

[0221] The first communication device according to the eighth embodiment is the first communication device according to the sixth or seventh embodiment, wherein in each of the plurality of unit data, a portion of the plurality of first bits is located at an interval of a number of bits that matches the ratio of the second transmission rate to the first transmission rate.

[0222] The first communication device according to the ninth embodiment is a first communication device according to any one of the sixth to eighth embodiments, wherein the first bit of the first bit of the portion of the plurality of first bits is located at the beginning of each of the plurality of unit data.

[0223] The first communication device according to the tenth embodiment is a first communication device according to any one of the first to ninth embodiments, wherein the first communication unit stores first sequence data representing the sequence of the plurality of first bits in the data area, and generates the data area based on the first sequence data.

[0224] The first communication device according to the eleventh embodiment is a first communication device according to any one of the first to tenth embodiments, wherein the first communication unit has a first buffer, sequentially writes the plurality of first bits to the first buffer, and sequentially reads the plurality of first bits from the first buffer to generate the second serial data.

[0225] The first communication device according to the twelfth embodiment is the first communication device according to the eleventh embodiment, wherein the first communication unit generates the second serial data by sequentially writing the plurality of first bits to the first buffer and sequentially reading the plurality of first bits from the first buffer when the ratio of the second transmission rate to the first transmission rate is not an integer multiple, and generates the second serial data based on the plurality of first bits that are not written to the first buffer when the ratio is an integer multiple.

[0226] The first communication device according to the 13th embodiment is a first communication device according to any one of the first to 12th embodiments, wherein the second communication unit transmits the transmission data superimposed on a power line.

[0227] A second communication device according to the 14th embodiment is a second communication device that receives the transmission data transmitted by a first communication device according to any one of the first to 13th embodiments, and comprises a third communication unit that receives the transmission data, generates restored second serial data by restoring the second serial data based on the transmission data, and transmits the restored second serial data, and a fourth communication unit that receives the restored second serial data transmitted by the third communication unit, generates restored first serial data by restoring the first serial data based on the restored second serial data, and transmits the restored first serial data.

[0228] The second communication device according to the 15th embodiment is the second communication device according to the 14th embodiment, wherein the fourth communication unit starts transmitting the first restored serial data while receiving the second restored serial data.

[0229] A second communication device according to the sixteenth embodiment is a second communication device according to the fourteenth or fifteenth embodiment, wherein the fourth communication unit stores second sequence data representing the sequence of the plurality of first bits in the data area, and generates the restored first serial data based on the second sequence data and the restored second serial data.

[0230] The second communication device according to the 17th embodiment is a second communication device according to any one of the 14th to 16th embodiments, wherein the fourth communication unit has a second buffer, and sequentially writes the plurality of first bits included in the restored second serial data to the second buffer, and sequentially reads the plurality of first bits from the second buffer to generate the restored first serial data.

[0231] The second communication device according to the 18th embodiment is the second communication device according to the 17th embodiment, wherein the fourth communication unit generates the restored first serial data by sequentially writing the plurality of first bits to the second buffer and sequentially reading the plurality of first bits from the second buffer when the ratio of the second transmission rate to the first transmission rate is not an integer multiple, and generates the restored first serial data based on the plurality of first bits that are not written to the second buffer when the ratio is an integer multiple.

[0232] The communication system according to the 19th embodiment comprises a first communication device according to any one of the first to 13th embodiments and a second communication device according to any one of the 14th to 18th embodiments.

[0233] 5 Communication System 10, 10A, 10B Communication Devices 25, 28, 35, 38 Communication Unit 100 First Packet, High-Speed ​​Packet (Transmit Data) 200 Second Packet, Low-Speed ​​Packet, Low-Speed ​​Serial Data, Restored Low-Speed ​​Serial Data 253, 353 Buffer 271 Arranged Data 270, 370 Table 300 High-Speed ​​Serial Data, Restored High-Speed ​​Serial Data

Claims

1. A first communication device comprising: a first communication unit that receives first serial data at a first transmission rate, generates second serial data at a second transmission rate higher than the first transmission rate, which includes a data area containing a plurality of first bits to be transmitted and dummy data from the first serial data, and transmits the second serial data; and a second communication unit that receives the second serial data transmitted by the first communication unit and transmits transmission data including the data area contained in the second serial data, wherein the first communication unit starts transmitting the second serial data while receiving the first serial data.

2. The first communication device according to claim 1, wherein the second communication unit starts transmitting the transmission data while receiving the second serial data.

3. The first communication device according to claim 1, wherein the positions of the plurality of first bits in the data area are determined based on the ratio of the second transmission rate to the first transmission rate.

4. The first communication device according to claim 1, wherein in the data area, the plurality of first bits are located at intervals of a number of bits corresponding to the ratio of the second transmission rate to the first transmission rate.

5. The first communication device according to claim 1, wherein the first bit of the plurality of first bits is located at the beginning of the data area.

6. The first communication device according to claim 1, wherein the dummy data includes a plurality of dummy bits, and the data area includes a plurality of unit data, each of which includes a portion of the plurality of first bits and at least one dummy bit, and the arrangement of the portion of the plurality of first bits and the at least one dummy bit is the same as that of the others.

7. The first communication device according to claim 6, wherein in each of the plurality of unit data, a portion of the plurality of first bits is positioned in an arrangement based on the ratio of the second transmission rate to the first transmission rate.

8. The first communication device according to claim 6, wherein in each of the plurality of unit data, a portion of the plurality of first bits is located at an interval of a number of bits corresponding to the ratio of the second transmission rate to the first transmission rate.

9. The first communication device according to claim 6, wherein the first bit of the first bit of the portion of the plurality of first bits is located at the beginning of each of the plurality of unit data.

10. A first communication device according to claim 1, wherein the first communication unit stores first sequence data representing the sequence of a plurality of first bits in the data area, and generates the data area based on the first sequence data.

11. A first communication device according to claim 1, wherein the first communication unit has a first buffer, sequentially writes the plurality of first bits to the first buffer, and sequentially reads the plurality of first bits from the first buffer to generate the second serial data.

12. A first communication device according to claim 11, wherein the first communication unit generates second serial data by sequentially writing the plurality of first bits to the first buffer and sequentially reading the plurality of first bits from the first buffer when the ratio of the second transmission rate to the first transmission rate is not an integer multiple, and when the ratio is an integer multiple, generates second serial data based on the plurality of first bits that are not written to the first buffer.

13. The first communication device according to claim 1, wherein the second communication unit transmits the transmission data superimposed on a power line.

14. A second communication device for receiving transmission data transmitted by a first communication device according to claim 1, comprising: a third communication unit for receiving the transmission data, generating restored second serial data by restoring the second serial data based on the transmission data, and transmitting the restored second serial data; and a fourth communication unit for receiving the restored second serial data transmitted by the third communication unit, generating restored first serial data by restoring the first serial data based on the restored second serial data, and transmitting the restored first serial data.

15. The second communication device according to claim 14, wherein the fourth communication unit starts transmitting the restored first serial data while receiving the restored second serial data.

16. The second communication device according to claim 14, wherein the fourth communication unit stores second sequence data representing the sequence of the plurality of first bits in the data area, and generates the restored first serial data based on the second sequence data and the restored second serial data.

17. The second communication device according to claim 14, wherein the fourth communication unit has a second buffer, sequentially writes the plurality of first bits included in the restored second serial data to the second buffer, and sequentially reads the plurality of first bits from the second buffer to generate the restored first serial data.

18. The second communication device according to claim 17, wherein the fourth communication unit, when the ratio of the second transmission rate to the first transmission rate is not an integer multiple, sequentially writes the plurality of first bits to the second buffer, sequentially reads the plurality of first bits from the second buffer to generate the restored first serial data, and when the ratio is an integer multiple, generates the restored first serial data based on the plurality of first bits that are not written to the second buffer.

19. A communication system comprising a first communication device according to any one of claims 1 to 13 and a second communication device according to any one of claims 14 to 18.

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