Structure, light-emitting diode, display device, lighting device, transistor, and integrated circuit

Abstract

This structure includes an amorphous substrate, a single crystal layer on the amorphous substrate, and junction portions between the amorphous substrate and the single crystal layer. The junction portions are discontinuously formed and dispersed. A peripheral part surrounding the junction portions is further included between the amorphous substrate and the single crystal layer, and the peripheral part has a gap formed between the amorphous substrate and the single crystal layer.

Description

Structure, light-emitting diode, display device, illumination device, transistor, and integrated circuit

[0001] An embodiment of the present invention relates to a structure using a single crystal, a light-emitting diode including the structure using a single crystal, a display device, an illumination device, a transistor, and an integrated circuit.

[0002] Gallium nitride (GaN), which is a typical single crystal material, has the characteristic of being a direct transition semiconductor with a large band gap. Utilizing this characteristic of gallium nitride, light-emitting diodes (LEDs) using gallium nitride have already been put into practical use. Gallium nitride also has characteristics of high electron saturation mobility and high withstand voltage. In recent years, utilizing these characteristics of gallium nitride, development of transistors for high-frequency power device applications has been progressing. A gallium nitride film for a light-emitting diode or transistor is generally formed at a high temperature of 800°C to 1000°C on a sapphire substrate by MOCVD (Metal Organic Chemical Vapor Deposition) or HVPE (Hydride Vapor Phase Epitaxy).

[0003] Furthermore, gallium nitride sputtering targets are being developed, and affinity between flat panel display (FPD) processes and gallium nitride has emerged. However, even in FPD processes, it is still necessary to use expensive single crystal substrates made of sapphire or silicon carbide with small substrate sizes as in conventional processes, and there are various issues such as difficulty in increasing the size of substrates.

[0004] For growing a single crystal gallium nitride layer, an example is known in which a glass substrate or the like is used instead of a single crystal substrate, a single crystal silicon layer is formed on the glass substrate, and the single crystal gallium nitride layer is grown on the single crystal silicon layer (for example, Patent Document 1).

[0005] Japanese National Publication of International Patent Application No. 2011-501431

[0006] However, when bonding the single crystal gallium nitride layer to a substrate and when growing a crystal layer on the single crystal gallium nitride layer, thermal stress occurs due to the difference in thermal expansion coefficient between the single crystal gallium nitride layer and the substrate.

[0007] One embodiment of the present invention, in view of the above problems, aims to provide a structure having a single-crystal layer on an amorphous substrate that has high crystallinity and suppresses the occurrence of defects.

[0008] One embodiment of the present invention, in view of the above problems, aims to provide a light-emitting diode that includes a structure having a single-crystal layer on an amorphous substrate, which has high crystallinity and suppresses the occurrence of defects.

[0009] One embodiment of the present invention, in view of the above problems, includes a structure having a single-crystal layer on an amorphous substrate that has high crystallinity and suppresses the occurrence of defects, and one of its objectives is to provide a large-area display device.

[0010] One embodiment of the present invention, in view of the above problems, aims to provide a transistor that includes a structure having a single-crystal layer on an amorphous substrate that has high crystallinity and suppresses the occurrence of defects.

[0011] A structure according to one embodiment of the present invention includes an amorphous substrate, a single crystal layer on the amorphous substrate, and a junction between the amorphous substrate and the single crystal layer, wherein the junction is formed discontinuously and dispersed.

[0012] A light-emitting diode according to one embodiment of the present invention includes an amorphous substrate, a single-crystal layer on the amorphous substrate, and a junction between the amorphous substrate and the single-crystal layer, wherein the junction includes a discontinuously formed and dispersed structure.

[0013] A display device according to one embodiment of the present invention includes an amorphous substrate, a single-crystal gallium nitride layer on the amorphous substrate, and a junction between the amorphous substrate and the single-crystal gallium nitride layer, wherein the junction includes a light-emitting diode having a discontinuously formed and dispersed structure.

[0014] A transistor according to one embodiment of the present invention includes an amorphous substrate, a single-crystal gallium nitride layer on the amorphous substrate, and a junction between the amorphous substrate and the single-crystal gallium nitride layer, wherein the junction includes a discontinuously formed and dispersed structure.

[0015] This is a schematic plan view of a display device according to one embodiment of the present invention. This is a schematic plan view of a pixel of a display device according to one embodiment of the present invention. This is a schematic cross-sectional view of a pixel of a display device according to one embodiment of the present invention. This is a schematic plan view of a structure according to one embodiment of the present invention. This is a schematic cross-sectional view of a transistor according to one embodiment of the present invention. This is a flowchart of a method for manufacturing a structure according to one embodiment of the present invention. This is a schematic plan view of a single-crystal gallium nitride layer according to one embodiment of the present invention. This is a schematic plan view of a single-crystal gallium nitride layer according to one embodiment of the present invention. This is a schematic perspective view and cross-sectional view showing a method for manufacturing a structure according to one embodiment of the present invention. This is a schematic cross-sectional view showing a method for reusing a structure according to one embodiment of the present invention.

[0016] The embodiments of the present invention will be described below with reference to the drawings. Note that each embodiment is merely an example, and any embodiment that a person skilled in the art could easily conceive by modifying it appropriately while maintaining the spirit of the invention is naturally included within the scope of the present invention. Furthermore, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention.

[0017] In this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A through C unless otherwise specified. Furthermore, these expressions do not exclude cases where α includes other elements.

[0018] In this specification, for the sake of explanation, the terms "up" or "above" or "down" or "below" will be used. However, as a general rule, the substrate on which the structure is formed is used as the reference point, and the direction from the substrate toward the structure is defined as "up" or "above." Conversely, the direction from the structure toward the substrate is defined as "down" or "below." Therefore, in the expression "light-emitting diode on a substrate," the substrate-side surface of the light-emitting diode is the bottom surface, and the opposite side is the top surface. Furthermore, the expression "light-emitting diode on a substrate" merely describes the top-down relationship between the substrate and the light-emitting diode, and other components may be placed between the substrate and the light-emitting diode. In addition, the terms "up" or "above" or "down" or "below" refer to the stacking order in a structure in which multiple layers are stacked, and do not necessarily mean that the layers are in a superimposed positional relationship in a plan view.

[0019] In this specification, "display device" broadly includes devices that display images using light-emitting diodes, and may include not only display panels and display modules, but also devices to which other optical components (e.g., polarizing members, backlights, touch panels, etc.) are attached.

[0020] The following embodiments can be combined with each other, provided that no technical inconsistencies arise.

[0021] <First Embodiment> (Overall Configuration) This embodiment describes the structure of a display device 10 according to one embodiment. Figure 1 is a schematic plan view of the display device according to this embodiment.

[0022] As shown in Figure 1, the display device 10 has a first substrate 102 and a second substrate 104, and the second substrate 104 includes a flexible printed circuit board 106 and an IC chip 108. The first substrate 102 and the second substrate 104 are arranged facing each other, and a display area 110 is provided in the region where the first substrate 102 and the second substrate 104 face each other. Outside the display area 110, the display device 10 further has a peripheral area 112 and a terminal area 114.

[0023] Multiple pixels 118 are arranged in the display area 110. A light-emitting diode 116 is placed in each pixel 118. The light-emitting diode 116 is electrically connected to multiple switching elements, multiple capacitors, and various wirings provided on the second substrate 104 (not shown).

[0024] A driver circuit 107 for controlling the light emission state of the light-emitting diodes 116 provided in each pixel 118 can be provided in the peripheral region 112. The driver circuit 107 controls the light emission state of the light-emitting diodes 116 via the aforementioned multiple switching elements, multiple capacitors, and various wiring. In addition, a terminal region 114 is provided at one end of the peripheral region 112 of the second substrate 104. Multiple terminals are provided in the terminal region 114. The flexible printed circuit board 106 is attached to the terminal region 114 and electrically connected to the multiple terminals. An IC chip 108 is mounted on the flexible printed circuit board 106. The IC chip 108 outputs a video signal. The video signal output from the IC chip 108 is transmitted via the flexible printed circuit board 106 to the driver circuit 107 provided on the second substrate 104.

[0025] Figure 2 shows an enlarged view of the pixel 118 on the first substrate 102 shown in Figure 1. Figure 2 is a schematic plan view of the pixel of a display device according to one embodiment of the present invention. Note that the first substrate 102 shown in Figure 1 is the top surface, and the first substrate 102 shown in Figure 2 is the bottom surface.

[0026] A light-emitting diode 116 is placed in each pixel 118. Figure 2 shows an example in which three light-emitting diodes 116 are provided in one pixel 118, but the example is not limited to this, and one light-emitting diode 116 may be provided in one pixel 118.

[0027] Pixel 118 includes a junction 120. The junction 120 forms a junction between the single crystal layer 122 and the first substrate 102, as will be described in detail later. The junction 120 may include multiple junctions 120, which are formed discontinuously and dispersed. Each of the multiple junctions 120 is spaced apart. The junction 120 is surrounded by a peripheral portion 140.

[0028] (Cross-sectional structure) Figure 3 shows a schematic cross-sectional view along the line A1-A2 shown in Figure 2. Figure 3 is a schematic cross-sectional view of a pixel of a display device according to one embodiment of the present invention. Note that in Figure 3, the first substrate 102, which was shown at the top in Figure 1, is shown at the bottom.

[0029] The first substrate 102 and the second substrate 104 are arranged facing each other. A single-crystal gallium nitride layer 122 is provided on the first substrate 102, and a junction 120 is provided between the first substrate 102 and the single-crystal gallium nitride layer 122. The first substrate 102, the single-crystal gallium nitride layer 122, and the junction 120 constitute a structure 124. A light-emitting diode 116 can be provided on the structure 124. The light-emitting diode 116 is placed between the first substrate 102 and the second substrate 104. In Figure 3, an example is shown in which the light-emitting diode 116 is sandwiched between the first substrate 102 and the second substrate 104, but the light-emitting diode 116 only needs to be placed on the first substrate 102, and the second substrate 104 does not need to be placed on the light-emitting diode 116. When the light-emitting diode 116 is placed on the first substrate, power to the light-emitting diode 116 is supplied separately, for example, by wire bonding.

[0030] The first substrate 102 is an amorphous substrate. An amorphous substrate is a non-crystalline substrate that does not have a crystalline structure. The first substrate 102 has a different coefficient of thermal expansion than the single-crystal gallium nitride layer 122. As the amorphous substrate, for example, a glass substrate, a quartz substrate, etc., can be used. Since the light emitted from the light-emitting diode 116 is transmitted through the first substrate 102, it is preferable to use an amorphous substrate with high transmittance of the light emitted from the light-emitting diode 116. In addition to a substrate similar to the first substrate 102, the second substrate 104 can be a flexible substrate such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate. Although not shown in detail, the second substrate 104 may be a so-called circuit board on which a circuit for driving the light-emitting diode 116 is formed.

[0031] The single crystal layer 122 can be made of a single crystal semiconductor or sapphire, as will be described in detail later. As the single crystal semiconductor, a single crystal of a group IV semiconductor or a group III-V compound semiconductor can be used. As the group III-V compound semiconductor single crystal, one of gallium nitride, indium gallium nitride, or aluminum gallium nitride can be selected. As the group IV semiconductor, silicon or gallium can be used. Furthermore, the single crystal layer 122 may also include a single crystal layer grown on a single crystal substrate such as the single crystal silicon substrate or sapphire substrate mentioned above.

[0032] A gap 126 is provided between the first substrate 102 and the single crystal layer 122, in addition to the joint portion 120. The gap 126 is a region where the single crystal layer 122 is not joined to the first substrate 102, and is formed by the peripheral portion 140 surrounding the joint portion 120. The provision of the gap 126 reduces the contact area between the first substrate 102 and the single crystal layer 122. Since the entire bottom surface of the single crystal layer 122 is not joined to the first substrate 102 or the joint portion 120, which have different coefficients of thermal expansion, and only a part of its bottom surface is joined to the joint portion 120 at a predetermined distance, thermal stress associated with temperature rise and fall in the joining process and subsequent manufacturing process, which will be described later, is mitigated. For example, in the film deposition process in the manufacturing process, film deposition is performed under rising temperature conditions, but when the temperature drops to room temperature after film deposition, thermal stress will occur at the joint between materials with different coefficients of thermal expansion. In this embodiment, by joining the first substrate 102 and the single crystal layer 122 via a joint portion 120 with a predetermined interval, the thermal stress can be effectively relieved compared to a configuration in which the entire bottom surface of the single crystal layer 122 is joined to the substrate.

[0033] As shown in Figure 2, the peripheral portion 140 is a region (space) sandwiched between the first substrate 102 and the single crystal layer 122, surrounding a plurality of discontinuously formed joints 120. Since the single crystal layer 122 is held in a floating state from the first substrate 102 by the joints 120, the peripheral portion 140 is connected to the space outside the single crystal layer 122. Therefore, if the pixel 118 is in air, the peripheral portion 140 is also filled with air. That is, an air layer is formed between the first substrate 102 and the single crystal layer 122. Furthermore, in a configuration in which the display device 10 is provided with a cover glass (not shown) and the pixel 118 is sealed with the cover glass, the peripheral portion 140 can be filled with nitrogen gas or an inert gas.

[0034] By forming an air layer, thermal stress caused by the process temperature during the formation of the light-emitting diode 116 and the transistor 20 (described later) can be alleviated. Specifically, during the cooling process from process temperature to room temperature, the entire structure 124 shrinks, and a difference in the thermal expansion coefficient between the first substrate 102 and the single-crystal layer 122 results in a difference in dimensions at room temperature. The stress generated by this dimensional difference is effectively alleviated by the formation of the air layer.

[0035] The formation of an air layer reduces the temperature difference between the surrounding temperature of the structure 124 and the temperature of the air layer. For example, when a light-emitting diode 116 is formed on the structure 124, the heat generated when the light-emitting diode 116 emits light causes the temperature around the light-emitting diode 116 or the structure 124, as well as the temperature of the structure 124, to rise. However, because the air layer is connected to the surrounding area of ​​the light-emitting diode 116 or the structure 124, the heat is diffused. This heat diffusion helps to equalize the temperature in the region where the light-emitting diode 116 or the structure 124 is formed.

[0036] Furthermore, it is preferable that the joint portion 120, which is formed discontinuously with respect to the single crystal layer 122, has a periodic structure. For example, the joint portion 120 may be formed with a constant period P. The period P of the joint portion 120 can be defined as the sum of the distance between adjacent joint portions 120 and the width d of the joint portion 120 (i.e., the distance from one end of one joint portion 120 to one end of another adjacent joint portion 120). For example, as shown in Figure 2, the period P of the joint portion 120 corresponds to the sum of the distance between adjacent joint portions 120-1 and 120-2 and the width d of the joint portion 120.

[0037] The joint portion 120 may have an upper surface 131 facing the first substrate 102 and a bottom surface 133 located on the opposite side of the upper surface 131 and facing the single crystal layer 122. The upper surface 131 functions as the bonding surface with the first substrate 102, and the bottom surface 133 functions as the bonding surface with the single crystal layer 122. The period P of the joint portion 120 is defined as the sum of the distance between adjacent joint portions 120-1 and 120-2 and the width d of the upper surface 131 forming the joint portion 120. The arrangement of the multiple joint portions 120 preferably satisfies the relationship 200d > P > d. Furthermore, the width d of the upper surface 131 is preferably several tens of mm > d > 100 nm. More preferably, the width d of the upper surface 131 is 60 mm > d > 100 nm, and even more preferably 30 mm > d > 100 nm. Furthermore, if the shape and area of ​​the top surface 131 are equivalent to those of the bottom surface 133, the width d of the top surface 131 can be read as the width d of the bottom surface.

[0038] The periodic arrangement of the joint portions 120 only needs to satisfy the above relationship, and may be, for example, a staggered arrangement as shown in Figure 4, or an aligned arrangement as shown in Figure 5. Figures 4 and 5 show examples of periodic arrangements of the joint portions 120, but the arrangement of the joint portions 120 can be a random arrangement rather than a periodic arrangement, as long as it does not deviate significantly from the above relationship or satisfies it. Figures 4 and 5 are plan views showing the first substrate 102 and joint portions 120 of the pixel shown in Figure 2, and the joint portion 120 shows the top surface 131 or the bottom surface 133.

[0039] The joint portions 120 are arranged such that the distance between the single crystal layer 122 and the first substrate 102 is uniform. Preferably, the joint portions 120 are located near the edges and in the center of the region where the single crystal layer 122 and the first substrate 102 overlap. If the region where the first substrate 102 and the single crystal layer 122 overlap is rectangular, as shown in Figure 4, for example, it is preferable that the joint portions 120 be located at the four corners and in the center of that region. Preferably, the joint portions 120 are located at least five locations in the region where the first substrate 102 and the single crystal layer 122 overlap. By arranging the joint portions 120 as described above, the single crystal layer 122 is stably bonded to the first substrate 102, and the flatness of the structure 124 relative to the first substrate 102 can also be ensured.

[0040] The joint portion 120 may be located not only near the edge and in the center of the region where the single crystal layer 122 and the first substrate 102 overlap, but also at multiple additional locations between the edge and the center of the region, as shown in Figure 5.

[0041] The joint portion 120 may have a cylindrical shape, as shown in Figures 3 to 5. The top surface 131 and bottom surface 133 of the joint portion 120 may be circular. The shape of the joint portion 120 is not limited to a cylindrical shape, but may also be a polygonal prism. Similarly, the shapes of the top surface 131 and bottom surface 133 are not limited to a circular shape, but may also be polygonal. The shapes of the top surface 131 and bottom surface 133 are preferably polygonal, close to a circle, and may, for example, be a polygon with six or more vertices. The joint portion 120 is not limited to a columnar shape, but may also be plate-shaped. The joint portion 120 may also be disc-shaped. In Figure 3, an example is shown in which the height h of the joint portion 120 is longer than the length d of the top surface 131 or bottom surface 133, but the height h of the joint portion 120 may be shorter than the length d of the top surface 131 or bottom surface 133. Here, the height h of the joint 120 can be the distance from the top surface 131 to the bottom surface 133 or the distance between the first substrate 102 and the single crystal layer 122.

[0042] The joint 120 may have a laminated structure. The laminated structure may include a layer 223 containing an intermetallic compound. As shown in FIG. 3, the laminated structure may have a structure in which a first layer 221 connected to the single crystal layer 122, a layer 223 containing an intermetallic compound, and a second layer 222 connected to the first substrate 102 are laminated. The layer 223 containing an intermetallic compound is an intermediate layer disposed between the first layer 221 and the second layer 222.

[0043] For the first layer 221 and the second layer 222, for example, a high-melting-point metal such as tungsten (W), titanium (Ti), or platinum (Pt) can be used. The first layer 221 and the second layer 222 can be formed, for example, by forming a film using physical vapor deposition (PVD), chemical vapor deposition (CVD), or a plating method, and then performing patterning.

[0044] As described above, the intermediate layer contains an intermetallic compound, and for the intermetallic compound, for example, a copper-tin alloy (Cu-Sn alloy) and a gold-indium alloy (Au-In alloy) can be used. The intermediate layer can be formed using TLP bonding (Transient Liquid Phase Diffusion Bonding).

[0045] The joint 120 may contain metal particles. For the metal particles, a material excellent in low-temperature sinterability can be used, and examples thereof include metal nanoparticles such as gold, silver, and copper. The joint 120 can be formed by placing a paste of metal particles by a printing method using a dispenser or a metal mask, followed by sintering.

[0046] Although details will be described later, the single crystal layer 122 is formed by bonding a single crystal layer crystal-grown on a single crystal substrate to the first substrate 102.

[0047] A light-emitting diode 116 may be provided on the single crystal layer 122. Specifically, the light-emitting diode 116 may be provided on a second surface 122B of the single crystal layer 122 opposite to a first surface 122F on which the joint 120 is provided. As shown in FIG. 3, the light-emitting diode 116 may be provided on the single crystal layer 122, and may also be provided on a structural body 124. The light-emitting diode 116 may include an n-type semiconductor layer 150, a light-emitting layer 152, a p-type semiconductor layer 154, an anode 156, a cathode 158, an anode bump 160, and a cathode bump 162. A laminated film in which the n-type semiconductor layer 150, the light-emitting layer 152, and the p-type semiconductor layer 154 are laminated in this order can be formed by using the single crystal layer 122 as a single crystal substrate and growing gallium nitride crystals from the single crystal layer 122. The second surface 122B of the single crystal layer 122 may serve as a crystal growth surface 122B.

[0048] As the light-emitting diode 116, for example, a red light-emitting diode, a green light-emitting diode, a blue light-emitting diode, or an ultraviolet light-emitting diode can be formed. There is no limitation on the size of the light-emitting diode, and minute light-emitting diodes called mini-LEDs or micro-LEDs can also be formed.

[0049] In one embodiment of the present invention, a micro-LED refers to an LED with a chip size of several micrometers or more and 100 μm or less, and a mini-LED refers to an LED with a chip size of 100 μm or more. According to one embodiment of the present invention, LEDs of any size can be used, and can be properly selected according to the application and form of the display device.

[0050] Figure 3 shows a structure in which the light-emitting diode 116 is provided as a flip-chip type LED chip, a cathode bump 162 is used to connect the cathode 158 to the second substrate 104, and an anode bump 160 is used to connect the anode 156 to the second substrate 104. The cathode bump 162 and anode bump 160 are electrically connected to a transistor (not shown) provided on the second substrate 104. This transistor is electrically connected to, for example, a driver circuit 107, and controls the light-emitting state of the light-emitting diode 116. The cathode bump 162 and anode bump 160 can be formed by plating, sputtering, deposition, or printing. Gold can be used as the material for the cathode bump 162 and anode bump 160, for example, but is not limited to this.

[0051] As explained above, the structure 124 includes a first substrate 102, a single crystal layer 122 on the first substrate 102, and a joint portion 120 between the first substrate 102 and the single crystal layer 122. The joint portion 120 is formed discontinuously and dispersed, so that the joint surface between the first substrate 102 and the single crystal layer 122 is not continuous. Because the joint surface is not continuous, the thermal stress caused by the thermal expansion coefficients of the single crystal layer 122 and the first substrate 102 when joining them is relieved. This relief of thermal stress suppresses the occurrence of defects such as cracks in the joint surface (mainly the single crystal layer 122) that occur when joining the single crystal layer 122 and the first substrate 102.

[0052] Furthermore, the process of thinning or thinning the single crystal layer, which has been carried out to countermeasures against warping and cracking of the substrate due to thermal stress caused by the thermal expansion coefficients of the single crystal layer 122 and the first substrate 102, can be omitted. By reducing the number of processes, the manufacturing cost of the light-emitting diode 116 or display device 10 using the structure 124 can be reduced.

[0053] Furthermore, in the light-emitting diode 116, the thermal stress caused by the thermal expansion coefficient between the single crystal layer 122 and the first substrate 102 during crystal growth of the light-emitting layer 152 on the single crystal layer 122 is mitigated by the presence of the structure 124. This mitigation of thermal stress suppresses the occurrence of defects such as cracks in the single crystal layer 122, the n-type semiconductor layer formed on the single crystal layer 122, the light-emitting layer 152, and the p-type semiconductor layer 154.

[0054] The light-emitting diode 116 and display device 10 having the structure 124 have few defects, and since the structure is adopted according to the size of the display area, it is possible to increase the area.

[0055] The above explanation has used a configuration in which the single crystal layer 122 is divided into pixels 118 as an example, but multiple pixels 118 may be formed on a single single crystal layer 122. With this configuration, a display device 10 equipped with a large number of pixels 118 can be efficiently manufactured.

[0056] In this embodiment, an example using the structure 124 in a display device 10 is shown, but the structure 124 can also be used in a transistor 20. Specifically, as shown in Figure 6, the structure 124 can be used in a transistor 20 by growing a crystal on the single crystal layer 122 to form a single crystal semiconductor layer 190. In addition to the semiconductor layer 190, the transistor 20 may have a gate insulating layer 192, a gate electrode 194, an insulating layer 196, an insulating layer 198, a source electrode 199-1, and a drain electrode 199-2. In Figure 6, the transistor 20 has a top gate structure, but it is not limited to this structure. The devices in which the structure 124 can be used are not limited to the display device 10 and the transistor 20. For example, the structure 124 can be used as a light source in a lighting device that utilizes a light-emitting diode 116. Furthermore, for example, the structure 124 can be used in a transistor 20 of an integrated circuit.

[0057] <Second Embodiment> This embodiment describes a method for manufacturing a structure according to one embodiment of the present invention. Here, we will describe a manufacturing method up to the point where the structure 124 is used in a light-emitting diode 116, a display device 10, or a semiconductor device. Figure 7 is a flowchart of the manufacturing method of the structure according to this embodiment. Figures 8 and 9 are schematic plan views of a single crystal layer according to one embodiment of the present invention. Figure 10 is a perspective view and a cross-sectional view showing a manufacturing method of a structure according to one embodiment of the present invention.

[0058] First, we will explain the process of the first substrate 102.

[0059] First, in step S10 of Figure 7, the first substrate 102 is prepared.

[0060] Next, in step S11 of Figure 7, the first substrate 102 is cleaned. For cleaning the first substrate 102, for example, cleaning with an alkaline cleaning solution may be performed. Any alkaline cleaning solution may be used, for example, a cleaning solution mainly composed of sodium hydroxide, sodium carbonate, or sodium phosphate may be used.

[0061] The first substrate 102 may be cleaned using an organic solvent. Alternatively, the first substrate 102 may be cleaned using both an alkaline cleaning solution and an organic solvent. Examples of organic solvents include acetone, methanol, and ethanol. When cleaning with an organic solvent, for example, the first substrate 102 may be cleaned with acetone, then methanol, and finally with pure water.

[0062] When a joint 120 formed by diffusion bonding such as TLP bonding is used in the structure 124, a bonding layer 120B may be formed on the first substrate 102 after step S11. A second layer 222 and an interface layer 180 are formed on the bonding layer 120B. The second layer 222 is formed on the first substrate 102 as described above. The interface layer 180 is formed by laminating on the second layer 222. For the interface layer 180, a metal that can become an intermetallic compound in the subsequent TLP bonding can be used. For example, Au can be used for the interface layer 180. The second layer 222 and the interface layer 180 should be patterned to match the pattern of the bonding layer 120A on the single crystal layer 122 shown in Figures 8 and 9. After forming the interface layer 180 on the first substrate 102, the first substrate 102 may be cleaned.

[0063] Next, we will explain the process for forming the single crystal layer 122.

[0064] First, in step S20 of Figure 7, a single crystal substrate 182 is prepared. The single crystal substrate 182 corresponds to the single crystal layer 122 of the structure 124 described above, and the same single crystal as the single crystal layer 122 can be used. Specifically, the single crystal substrate 182 can be a sapphire substrate, a silicon carbide single crystal substrate, a single crystal silicon substrate, a GaN template / sapphire substrate, a single crystal gallium nitride substrate, or SAM (ScAlMgO ４ A substrate or the like can be used. A bonding layer 120A is provided on the single crystal substrate 182. The single crystal gallium nitride layer 122 can be formed by any known method, for example, by methods such as MOCVD and HVPE.

[0065] Next, in step S21 of Figure 7, the single crystal substrate 182 is cut. Cutting the single crystal substrate 182 as shown in step S21 of Figure 10 makes it easier to align and arrange the single crystal substrate 182 on the first substrate 102. In Figure 10, an example is shown in which the cut single crystal substrates 182 are the same shape and size, but they do not have to be the same shape and size.

[0066] Furthermore, in step S22 of Figure 7, the single crystal substrate 182 is cleaned. For example, the single crystal substrate 182 can be cleaned using an organic solvent. Acetone and methanol can be used as organic solvents. For example, the single crystal substrate 182 can be cleaned with acetone and methanol in that order, and finally cleaned with pure water.

[0067] In step S20 of Figure 10, an example is shown in which a single-crystal substrate 182 on which a bonding layer 120A is formed is prepared. However, when a bonding portion 120 formed by diffusion bonding such as TLP bonding is used for the structure 124, the bonding layer 120A can be formed after step S22. The bonding layer 120A can be formed by a first layer 221 and an interface layer 181. As described above, the first layer 221 is formed on the single-crystal layer 122 using PVD, CVD, plating, etc. The interface layer 181 can be formed by laminating it on the first layer 221 using the same method as the first layer 221.

[0068] The interface layer 181 can be made of a metal that can form an intermetallic compound when bonded with the later interface layer 180. For example, the interface layer 181 is formed by laminating a layer containing In and a layer containing Au, with the layer containing In located on the single crystal layer 122 side. The first layer 221 and the interface layer 181 are preferably patterned on the single crystal substrate 182 in an aligned arrangement as shown in Figure 8, or in a staggered arrangement as shown in Figure 9. After forming the interface layer 181 on the single crystal layer 122, the first substrate 102 can be cleaned.

[0069] Finally, the single crystal layer 122 and the first substrate 102 are bonded together in step S30 of Figure 7. By bonding the single crystal layer 122 and the first substrate 102, the single crystal layer 122 on the single crystal substrate 182 is transferred onto the first substrate 102, and the structure 124 can be obtained.

[0070] As shown in step S30 of Figure 10, the single crystal layer 122 is placed on the first substrate 102 such that the bonding layer 120A of the single crystal layer 122 and the bonding layer 120B of the first substrate 102 face each other, and the first substrate 102 and the single crystal layer 122 are bonded together. In Figure 15, multiple single crystal layers 122 of single crystal substrates 182 are bonded to one first substrate 102, but there is no limit to the number of single crystal substrates 182. In Figure 15, an example is shown in which single crystal substrates 182 of the same shape and size are used for bonding, but single crystal substrates 182 of different shapes and sizes may also be used.

[0071] For bonding the first substrate 102 and the single crystal layer 122, known methods can be used, and as described above, bonding can be done using diffusion bonding or plating. When bonding using plating, a metal nanopaste can be pre-printed on the first substrate 102 or the single crystal layer 122 before step S30. When bonding using diffusion bonding, the interface layer 180 and the interface layer 181 are brought into contact, and the single crystal layer 122 and the first substrate 102 are heated at the melting temperature of the metal contained in the interface layer 180 and the interface layer 181. In addition to heating, pressurization may also be applied. Since the bonded portion 120 is formed discontinuously and dispersed, differential pressure is less likely to occur in the structure 124, and pressurization can be applied.

[0072] As described above, in this manufacturing method, by interposing a bonding portion 120 between the first substrate 102 and the single crystal layer 122 and transferring the single crystal layer 122 on the single crystal substrate 182 to the first substrate 102, thermal stress caused by the thermal expansion coefficient between the single crystal layer 122 and the first substrate 102 can be relieved, and a structure 124 with relieved internal stress can be obtained.

[0073] <Third Embodiment> (Reuse) This embodiment describes a method for reusing a structure according to one embodiment of the present invention. Here, a method is described in which the structure 124 is peeled off after it has been used in a display device 10 or a light-emitting diode 116, and the single crystal layer 122 is reused. Figure 11 is a schematic cross-sectional view showing a method for reusing a structure according to one embodiment of the present invention.

[0074] The structure 124 can be separated from the light-emitting diode 116 by performing a laser lift-off (LLO) process at the interface between the structure 124 and the light-emitting diode 116. Figure 11 shows the state in which the structure 124 has been separated by irradiating the second surface 122B with a laser such as an excimer laser or a solid-state laser. The separated structure 124 can be reused in a new display device 10 and light-emitting diode 116 by growing a semiconductor layer and a light-emitting layer again from the single crystal layer 122. The method for separating the light-emitting diode 116 from the structure 124 is not limited to LLO processing.

[0075] The embodiments described above as embodiments of the present invention can be combined and implemented as appropriate, insofar as they do not contradict each other. Furthermore, devices based on the display devices of each embodiment, in which a person skilled in the art has added, deleted, or modified components, or added, omitted, or modified processes, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0076] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention.

[0077] 10: Display device, 102: First substrate, 104: Second substrate, 106: Flexible printed circuit board, 107: Driver circuit, 108: Chip, 110: Display area, 112: Peripheral area, 114: Terminal area, 116: Light-emitting diode, 118: Pixel, 120: Junction, 120-1: Junction, 120-2: Junction, 120A: Junction layer, 120B: Junction layer, 122: Single crystal layer, 122B: Crystal growth surface, 122B: Second surface, 122F: First surface, 124: Structure, 126: Gap, 1 31: Top surface, 133: Bottom surface, 140: Peripheral part, 150: n-type semiconductor layer, 152: Light-emitting layer, 154: p-type semiconductor layer, 156: Anode, 158: Cathode, 160: Anode bump, 162: Cathode bump, 180: Interface layer, 181: Interface layer, 182: Single crystal substrate, 190: Semiconductor layer, 192: Gate insulating layer, 194: Gate electrode, 196: Insulating layer, 198: Insulating layer, 199-1: Source electrode, 199-2: Drain electrode, 221: First layer, 222: Second layer, 223: Layer

Claims

1. A structure comprising an amorphous substrate, a single crystal layer on the amorphous substrate, and a junction between the amorphous substrate and the single crystal layer, wherein the junction is formed discontinuously and dispersed.

2. The structure according to claim 1, further comprising a peripheral portion surrounding the junction between the amorphous substrate and the single crystal layer, wherein the peripheral portion forms a gap between the amorphous substrate and the single crystal layer.

3. The structure according to claim 2, wherein the peripheral portion is continuous between the amorphous substrate and the single crystal layer, forming an air layer.

4. The structure according to claim 1, wherein the joint includes a plurality of joints, and when P is the period during which the plurality of joints are arranged between the amorphous substrate and the single crystal layer, and d is the width of the joint, the relationship 200d > P > d is satisfied.

5. The structure according to claim 4, wherein the width d of the joint is 30 mm > d > 100 nm.

6. The structure according to claim 1, wherein the joint has a laminated structure, and the laminated structure has a layer containing an intermetallic compound.

7. The structure according to claim 1, wherein the joint portion includes metal particles.

8. The structure according to claim 1, wherein the bonding portions are arranged at least five times between the amorphous substrate and the single crystal layer.

9. The structure according to claim 1, wherein the joint is bonded to the single crystal layer on a first surface and to the amorphous substrate on a second surface opposite to the first surface.

10. The structure according to claim 1, wherein the single crystal layer comprises a single crystal semiconductor or sapphire.

11. The structure according to claim 10, wherein the single-crystal semiconductor comprises a single crystal of a group IV semiconductor or a group III-V compound semiconductor.

12. The structure according to claim 11, wherein the single crystal of the group III-V compound semiconductor is selected from gallium nitride, indium gallium nitride, and aluminum gallium nitride.

13. A light-emitting diode comprising the structure described in claim 1.

14. A display device comprising the light-emitting diode described in claim 10.

15. A lighting device comprising the light-emitting diode described in claim 10.

16. A transistor comprising the structure described in claim 1.

17. An integrated circuit comprising the transistor described in claim 16.

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