Imaging element, electronic device, and manufacturing method

Abstract

The present disclosure relates to an imaging element, an electronic device, and a manufacturing method with which it is possible to further widen a dynamic range. This imaging element is provided with: a first substrate on which a photoelectric conversion unit is provided; a second substrate stacked on the first substrate; and a capacitor structure configured from a semiconductor layer and a gate electrode so as to surround, via at least an insulating film, one side surface of the gate electrode and the semiconductor layer, the semiconductor layer constituting a transistor layer provided in an insulating layer of a wiring layer of the second substrate. This technology can be applied to, for example, an imaging element capable of HDR imaging.

Description

Image Sensor, Electronic Device, and Manufacturing Method

[0001] The present disclosure relates to an image sensor, an electronic device, and a manufacturing method, and particularly relates to an image sensor, an electronic device, and a manufacturing method that enable a wider dynamic range.

[0002] Conventionally, an image sensor capable of HDR (High Dynamic Range) imaging is configured to be able to switch conversion efficiency when converting charges by turning on / off the connection of an additional capacitor to an FD (Floating Diffusion) section to which charges are transferred from a photoelectric conversion section.

[0003] Patent Document 1 discloses an image sensor configured such that an additional capacitor is disposed via an interlayer insulating film from a silicon substrate on which a photoelectric conversion section and an FD section are formed, and includes a connection section that switches connection of the additional capacitor to the FD section.

[0004] Japanese Unexamined Patent Publication No. 2013-33896

[0005] In recent years, with the miniaturization of pixels, while additional capacitors for realizing HDR imaging have been reduced in size, there has been a demand for a wider dynamic range by increasing the charge storage capacity of the additional capacitors.

[0006] The present disclosure has been made in view of such circumstances, and aims to enable a wider dynamic range.

[0007] An image sensor according to one aspect of the present disclosure includes: a first substrate provided with a photoelectric conversion section; a second substrate stacked on the first substrate; and a capacitor structure formed of the semiconductor layer and the gate electrode, the capacitor structure surrounding at least one side surface of the semiconductor layer and the gate electrode, which constitute a transistor layer provided in an insulating layer of a wiring layer of the second substrate, with an insulating film interposed therebetween.

[0008] An electronic device according to one aspect of the present disclosure includes an image sensor having a first substrate on which a photoelectric conversion unit is provided, a second substrate laminated on the first substrate, and a capacitor structure composed of a semiconductor layer and a gate electrode such that a semiconductor layer constituting a transistor layer is provided in the insulating layer of the wiring layer of the second substrate, and one side of the gate electrode is surrounded by at least an insulating film.

[0009] One aspect of the manufacturing method of this disclosure includes forming a capacitor structure composed of a semiconductor layer and a gate electrode such that one side of the semiconductor layer and gate electrode constituting a transistor layer provided in an insulating layer of a wiring layer of a second substrate laminated on a first substrate on which a photoelectric conversion unit is provided is surrounded by at least an insulating film.

[0010] In one aspect of this disclosure, a capacitor structure is configured by a semiconductor layer and a gate electrode such that one side of the semiconductor layer and gate electrode constituting a transistor layer provided in the insulating layer of a wiring layer of a second substrate laminated on a first substrate on which a photoelectric conversion unit is provided is surrounded by at least an insulating film.

[0011] Figure 11 shows an example of the configuration of a pixel in a first embodiment of an image sensor to which this technology is applied. Figure 17 shows an example of the configuration of a first embodiment of an image sensor having the pixel shown in Figure 1. Figure 17 shows a second example of cross-sectional configuration of an image sensor having the pixels shown in Figure 17. Figure 17 shows a third example of cross-sectional configuration of an image sensor having the pixels shown in Figure 17. Figure 17 shows a first example of planar layout of the transistor layer of the pixels shown in Figure 17. Figure 17 shows a second example of planar layout of the transistor layer of the pixels shown in Figure 17. Figure 17 shows a third example of planar layout of the transistor layer of the pixels shown in Figure 17. Figure 17 shows a fourth example of planar layout of the transistor layer of the pixels shown in Figure 17. Figure 17 shows a first variation of circuit configuration of the pixels shown in Figure 17. Figure 17 shows a second variation of circuit configuration of the pixels shown in Figure 17. Figure 17 shows a third variation of circuit configuration of the pixels shown in Figure 17. Figure 27 shows a cross-sectional configuration example of an image sensor having the pixels shown in Figure 27. Figure 17 shows an example of configuration of the seventh embodiment of the pixels. Figure 27 shows an example of configuration of the eighth embodiment of the pixels. Figure 37 shows an example of configuration of the ninth embodiment of the pixels. Figure 47 shows an example of configuration of the tenth embodiment of the pixels. Figure 57 illustrates a method for manufacturing a capacitor structure. Figure 67 illustrates a method for manufacturing a capacitor structure.This is a diagram illustrating a method for manufacturing a capacitor structure. This is a diagram illustrating a method for manufacturing a capacitor structure. This is a diagram showing a first planar layout example of a pixel in the eleventh embodiment. This is a diagram showing a second planar layout example of a pixel in Figure 37. This is a diagram showing a third planar layout example of a pixel in Figure 37. This is a diagram showing a fourth planar layout example of a pixel in Figure 37. This is a diagram showing a fifth planar layout example of a pixel in Figure 37. This is a diagram showing a sixth planar layout example of a pixel in Figure 37. This is a diagram illustrating a first modified shape of the capacitor structure. This is a diagram illustrating a second modified shape of the capacitor structure. This is a diagram showing an example configuration of a pixel in the twelfth embodiment. This is a diagram showing the circuit configuration of a pixel in Figure 45. This is a block diagram showing an example configuration of an imaging device. This is a diagram showing an example of use using an image sensor.

[0012] The following describes in detail a specific embodiment of this technology, with reference to the drawings.

[0013] <First Pixel Configuration Example> Referring to Figures 1 to 12, a first embodiment of the configuration of pixels in an image sensor to which this technology is applied will be described.

[0014] Figure 1A shows a planar example of the semiconductor layer and gate electrode constituting the transistor layer of the pixel 11, while Figure 1B shows a cross-sectional example along the dashed line shown in Figure 1A.

[0015] As shown in Figure 1, the pixel 11 is constructed by providing a capacitor structure 35, along with an amplification transistor 31, a selection transistor 32, a reset transistor 33, and a connection transistor 34, on a transistor layer provided within an insulating film 21 that constitutes a wiring layer. Furthermore, semiconductor layers 41-1 to 41-4, gate electrodes 42-1 to 42-5, wiring 43-1 and 43-2, and electrodes 44-1 to 44-12 are provided within the insulating film 21.

[0016] The amplification transistor 31 is constructed such that the top surface and both sides of a trench-shaped semiconductor layer 41-1 are covered by a gate electrode 42-1 via an insulating film (not shown). An electrode 44-1 is provided to connect the gate electrode 42-1 to a wiring 43-1, and an electrode 44-2 is provided to connect to the semiconductor layer 41-1 which is the source side of the amplification transistor 31.

[0017] The selection transistor 32 is constructed such that the top surface and both sides of a trench-shaped semiconductor layer 41-1 are covered by a gate electrode 42-2 via an insulating film 45-1, as shown in Figure 1B. An electrode 44-3 is provided to connect to the gate electrode 42-2, and an electrode 44-4 is provided to connect to the semiconductor layer 41-1 that is the drain side of the selection transistor 32.

[0018] The reset transistor 33 is constructed such that the top surface and both sides of a trench-shaped semiconductor layer 41-2 are covered by a gate electrode 42-3 via an insulating film (not shown). An electrode 44-5 is provided to connect to the gate electrode 42-3, an electrode 44-6 is provided to connect to the semiconductor layer 41-2 which is the drain side of the reset transistor 33, and an electrode 44-7 is provided to connect the semiconductor layer 41-2 which is the source side of the reset transistor 33 to the wiring 43-1.

[0019] The connecting transistor 34 is constructed such that the top surface and both sides of a trench-shaped semiconductor layer 41-2 are covered by a gate electrode 42-4 via an insulating film 45-2, as shown in Figure 1B. An electrode 44-8 is provided to connect to the gate electrode 42-4, and an electrode 44-9 is provided to connect the semiconductor layer 41-2, which is the drain side of the connecting transistor 34, to the wiring 43-2.

[0020] The capacitor structure 35 is constructed such that the top surface and both sides of the trench-shaped semiconductor layers 41-3 and 41-4 are covered by a gate electrode 42-5 via insulating films 45-3 and 45-4, respectively, as shown in Figure 1B. An electrode 44-10 is provided to connect to the gate electrode 42-5, and electrodes 44-11 and 44-12 are provided to connect the semiconductor layers 41-3 and 41-4 to the wiring 43-2, respectively.

[0021] The capacitor structure 35 is configured such that the gate electrode 42-5 is connected to the drain power supply VDD via electrode 44-10, and the semiconductor layers 41-3 and 41-4 are connected to the semiconductor layer 41-2, which is the drain side of the connecting transistor 34, via electrodes 44-11 and 44-12, respectively. Therefore, the space between the top surface and both sides of the semiconductor layer 41-3 and the gate electrode 42-5, and the space between the top surface and both sides of the semiconductor layer 41-4 and the gate electrode 42-5, can be used as a charge storage capacitance for the charge supplied via the connecting transistor 34.

[0022] In a pixel 11 provided with a trench-shaped capacitor structure 35, both sides of the semiconductor layer 41-3 and semiconductor layer 41-4 can also be used as charge storage capacitances. Therefore, compared to a pixel provided with a planar capacitor structure, for example, it can store more charge.

[0023] Furthermore, the connecting transistor 34 is used to switch the conversion efficiency of the amplifying transistor 31 by, for example, switching the connection between the FD section 72 (see Figure 2) and the capacitor structure 35 on and off. For example, when the connecting transistor 34 is turned on, the capacitor structure 35 is connected to the FD section 72, increasing the charge storage capacity transferred from the photoelectric conversion section 71 (see Figure 2), and thus lowering the charge conversion efficiency of the amplifying transistor 31. On the other hand, when the connecting transistor 34 is turned off, the capacitor structure 35 is not connected to the FD section 72, decreasing the charge storage capacity transferred from the photoelectric conversion section 71 (see Figure 2), and thus increasing the charge conversion efficiency of the amplifying transistor 31.

[0024] Therefore, an image sensor 12 equipped with pixels 11 in this configuration can increase the charge storage capacity of the capacitor structure 35, resulting in the ability to perform HDR shooting with a wider dynamic range.

[0025] Referring to Figures 2 to 4, an example of the cross-sectional configuration of an image sensor 12 having pixels 11 will be described.

[0026] Figure 2 shows a first example of the cross-sectional configuration of the image sensor 12.

[0027] As shown in Figure 2, the image sensor 12 is constructed by joining a sensor substrate 51 and a logic substrate 52 at a joint surface (indicated by the thick dashed line in the figure). The image sensor 12 also employs a pixel-sharing structure in which multiple pixels 11 (in the illustrated example, two pixels 11-1 and 11-2) share an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a capacitor structure 35. Hereafter, the amplification transistor 31, selection transistor 32, reset transistor 33, and connection transistor 34 will be collectively referred to as pixel transistors.

[0028] The sensor substrate 51 is constructed by stacking a wiring layer 62 on a semiconductor layer 61. The semiconductor layer 61 is provided with a photoelectric conversion unit 71-1 for pixel 11-1, a photoelectric conversion unit 71-2 for pixel 11-2, an FD unit 72, a transfer transistor 73-1 for pixel 11-1, and a transfer transistor 73-2 for pixel 11-2. The transfer transistor 73-1 is constructed by providing a gate electrode 81-1 on the surface of the semiconductor layer 61, and the transfer transistor 73-2 is constructed by providing a gate electrode 81-2 on the surface of the semiconductor layer 61.

[0029] The logic board 52 is constructed by stacking wiring layers 63 on a semiconductor layer (not shown), and an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a capacitor structure 35 are provided within the insulating film 21 of the wiring layer 63.

[0030] Furthermore, the image sensor 12 is provided with a through electrode 46 connecting the sensor substrate 51 and the logic substrate 52. One end of the through electrode 46 is connected to the FD portion 72. The other end of the through electrode 46 is connected to the gate electrode 42-1 of the amplification transistor 31 via wiring 43-1 and electrode 44-1.

[0031] Thus, the image sensor 12 can be configured as a stacked structure in which a sensor substrate 51 and a logic substrate 52 are stacked, and the sensor substrate 51 and the logic substrate 52 are electrically connected using through electrodes 46.

[0032] Figure 3 shows a second example of the cross-sectional configuration of the image sensor 12.

[0033] As shown in Figure 3, the image sensor 12 is constructed by joining the front surface of the sensor substrate 51 and the back surface of the logic substrate 52 at a joint surface (indicated by the thick dashed line in the figure). Furthermore, the image sensor 12 employs a pixel-sharing structure in which multiple pixels 11 (in the illustrated example, two pixels 11-1 and 11-2) share a pixel transistor and capacitor structure 35.

[0034] The sensor substrate 51 is constructed by stacking a wiring layer 62 on a semiconductor layer 61. The semiconductor layer 61 is provided with a photoelectric conversion unit 71-1 for pixel 11-1, a photoelectric conversion unit 71-2 for pixel 11-2, an FD unit 72, a transfer transistor 73-1 for pixel 11-1, and a transfer transistor 73-2 for pixel 11-2. The transfer transistor 73-1 is constructed by providing a gate electrode 81-1 on the surface of the semiconductor layer 61, and the transfer transistor 73-2 is constructed by providing a gate electrode 81-2 on the surface of the semiconductor layer 61.

[0035] The logic board 52 is constructed by stacking wiring layers 63 on a semiconductor layer (not shown), and an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a capacitor structure 35 are provided within the insulating film 21 of the wiring layer 63.

[0036] In the image sensor 12, a connection pad 82 is provided on the bonding surface of the sensor substrate 51, and a connection pad 47 is provided on the bonding surface of the logic substrate 52, and the connection pads 82 and 47 are electrically and mechanically bonded (for example, Cu-Cu bonding). The connection pad 82 is connected to the FD section 72 via a connection structure 83 composed of electrodes and wiring. The connection pad 47 is connected to the gate electrode 42-1 of the amplification transistor 31 via a through electrode 46, wiring 43-1, and electrode 44-1.

[0037] Thus, the image sensor 12 has a stacked structure in which the front surface of the sensor substrate 51 and the back surface of the logic substrate 52 are joined and stacked, and the sensor substrate 51 and the logic substrate 52 can be configured to be electrically connected using the Cu-Cu junctions of the connection pads 82 and 47.

[0038] Figure 4 shows a third example of the cross-sectional configuration of the image sensor 12.

[0039] As shown in Figure 4, the image sensor 12 is constructed by joining the surface side of the sensor substrate 51 and the surface side of the logic substrate 52 at a joint surface (shown by the thick dashed line in the figure). Furthermore, the image sensor 12 employs a pixel sharing structure in which a pixel transistor and capacitor structure 35 are shared by multiple pixels 11 (in the illustrated example, two pixels 11-1 and 11-2).

[0040] The sensor substrate 51 is constructed by stacking a wiring layer 62 on a semiconductor layer 61. The semiconductor layer 61 is provided with a photoelectric conversion unit 71-1 for pixel 11-1, a photoelectric conversion unit 71-2 for pixel 11-2, an FD unit 72, a transfer transistor 73-1 for pixel 11-1, and a transfer transistor 73-2 for pixel 11-2. The transfer transistor 73-1 is constructed by providing a gate electrode 81-1 on the surface of the semiconductor layer 61, and the transfer transistor 73-2 is constructed by providing a gate electrode 81-2 on the surface of the semiconductor layer 61.

[0041] The logic substrate 52 is configured by laminating a wiring layer 63 on a semiconductor layer (not shown in the figure), and an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a capacitor structure 35 are provided in an insulating film 21 of the wiring layer 63.

[0042] In the image sensor 12, a connection pad 82 is provided on the bonding surface of the sensor substrate 51, and a connection pad 47 is provided on the bonding surface of the logic substrate 52. The connection pad 82 and the connection pad 47 are electrically and mechanically bonded (for example, Cu-Cu bonding). The connection pad 82 is connected to the FD portion 72 via a connection structure 83 constituted by an electrode and a wiring. The connection pad 47 is connected to the gate electrode 42-1 of the amplification transistor 31 via a connection structure 48 constituted by an electrode and a wiring, a wiring 43-1, and an electrode 44-1.

[0043] As described above, the image sensor 12 has a laminated structure in which the surface side of the sensor substrate 51 and the surface side of the logic substrate 52 are bonded and laminated, and can be configured such that the sensor substrate 51 and the logic substrate 52 are electrically connected by using Cu-Cu bonding between the connection pad 82 and the connection pad 47.

[0044] An example of the planar layout of the transistor layer of the pixel 11 will be described with reference to FIGS. 5 to 8. In FIGS. 5 to 8, the illustration of the wiring 43 is omitted, and the black circles shown in FIGS. 5 to 8 represent through electrodes used for contact with the sensor substrate 51.

[0045] FIG. 5 is a diagram showing a first planar layout example of the transistor layer of the pixel 11.

[0046] On the left side of FIG. 5, a first planar layout example of transistor layers of a plurality of pixels 11 arranged in an array on the sensor surface of the image sensor 12 (in the illustrated example, nine pixels 11 arranged in a 3×3 array) is shown. On the right side of FIG. 5, a first planar layout example of the transistor layer of one pixel 11 among the plurality of pixels 11 is shown.

[0047] In the first planar layout example shown in FIG. 5, for one pixel 11, an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a capacitor structure 35 are provided in the transistor layer.

[0048] As described above, the image sensor 12 can configure the transistor layer of the pixel 11 in the first planar layout example that does not employ a pixel sharing structure.

[0049] FIG. 6 is a diagram showing a second planar layout example of the transistor layer of the pixel 11.

[0050] On the left side of FIG. 6, a second planar layout example of the transistor layer of a plurality of pixels 11 arranged in an array on the sensor surface of the image sensor 12 (36 pixels 11 arranged in 6×6 in the illustrated example) is shown. On the right side of FIG. 6, a second planar layout example of the transistor layer of four pixels 11-1 to 11-4 arranged in 2×2 as an FD sharing unit among the plurality of pixels 11 is shown.

[0051] In the second planar layout example shown in FIG. 6, for four pixels 11-1 to 11-4, an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a capacitor structure 35 are provided in the transistor layer.

[0052] As described above, the image sensor 12 can configure the transistor layer of the pixel 11 in the second planar layout example that employs a 4-pixel sharing structure.

[0053] FIG. 7 is a diagram showing a third planar layout example of the transistor layer of the pixel 11.

[0054] On the left side of FIG. 7, a third planar layout example of the transistor layer of a plurality of pixels 11 arranged in an array on the sensor surface of the image sensor 12 (48 pixels 11 arranged in 6×8 in the illustrated example) is shown. On the right side of FIG. 7, a third planar layout example of the transistor layer of eight pixels 11-1 to 11-8 arranged in 2×4 as an FD sharing unit among the plurality of pixels 11 is shown.

[0055] In the third planar layout example shown in Figure 7, an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and capacitor structures 35-1 and 35-2 are provided on the transistor layer for eight pixels 11-1 to 11-8.

[0056] Thus, the image sensor 12 can be configured with a third planar layout example employing an eight-pixel shared structure, which allows for the formation of the transistor layer of the pixels 11. Furthermore, in the eight-pixel shared structure, there is ample space for arrangement in the transistor layer, so two capacitor structures 35-1 and 35-2 can be provided for the eight pixels 11-1 to 11-8, thereby doubling the charge storage capacity.

[0057] Figure 8 shows a fourth planar layout example of the transistor layer of pixel 11. In this fourth planar layout example, one pixel 11 (a so-called Dual PD (Photodiode)) is formed by a pair of L pixels and R pixels that are arranged adjacent to each other.

[0058] The left side of Figure 8 shows a fourth planar layout example of the transistor layer of multiple pixels 11 (in the illustrated example, 36 pixels 11 arranged in a 6x6 configuration) arranged in an array on the sensor surface of the image sensor 12. The right side of Figure 8 shows a fourth planar layout example of the transistor layer of four pixels 11-1 to 11-4, which are FD sharing units arranged in a 2x2 configuration.

[0059] In the fourth planar layout example shown in Figure 8, an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a capacitor structure 35 are provided on the transistor layer for four pixels 11-1 to 11-4.

[0060] Thus, the image sensor 12 can be configured in a fourth planar layout example employing a four-pixel shared structure, forming a transistor layer of pixels 11 composed of pairs of L pixels and R pixels.

[0061] Referring to Figures 9 to 12, variations in the circuit configuration of the pixel 11 and examples of the planar layout of the transistor layer of the pixel 11 in each variation will be explained. The black circles shown in Figures 9 to 12 represent through electrodes used for contact with the sensor substrate 51.

[0062] Figure 9A shows the circuit configuration of the first variation of pixel 11, and Figure 9B shows an example of a planar layout of the transistor layer of pixel 11 in the circuit configuration of the first variation.

[0063] As shown in Figure 9A, the pixel 11 is composed of an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, a capacitor structure 35, a photoelectric conversion unit 71, an FD unit 72, and a transfer transistor 73. As shown in Figure 9B, a four-pixel sharing structure is employed in which four pixels 11-1 to 11-4 share a pixel transistor, but Figure 9A shows the circuit configuration of a single pixel 11.

[0064] The photoelectric conversion unit 71 is connected to the FD unit 72 via a transfer transistor 73, and the FD unit 72 is connected to the gate terminal of the amplification transistor 31. The drain terminal of the amplification transistor 31 is connected to the drain power supply VDD, and the source terminal of the amplification transistor 31 is connected to the vertical signal line VSL via a selection transistor 32, to which a constant current source is connected. A reset transistor 33 and a connection transistor 34 are connected in parallel between the FD unit 72 and the drain power supply VDD, and a capacitor structure 35 is connected between the connection transistor 34 and the drain power supply VDD. Note that the drain power supply VDD connected to the capacitor structure 35 does not have to be at the same potential as the drain power supply VDD connected to the amplification transistor 31 and the reset transistor 33.

[0065] In the first variation of this connection configuration, the pixel 11 can switch the connection of the capacitor structure 35 to the FD section 72 via the connecting transistor 34.

[0066] Figure 10A shows a circuit configuration of a second variation of pixel 11, and Figure 10B shows an example of a planar layout of the transistor layer of pixel 11 in the circuit configuration of the second variation.

[0067] As shown in Figure 10A, the pixel 11 is composed of an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, a capacitor structure 35, a photoelectric conversion unit 71, an FD unit 72, and a transfer transistor 73. As shown in Figure 10B, a four-pixel shared structure is employed in which four pixels 11-1 to 11-4 share a pixel transistor, but Figure 10A shows the circuit configuration of a single pixel 11. Also, as shown in Figure 10B, the capacitor structure 35 is composed of a gate electrode 42-5a and a gate electrode 42-5b, with electrode 44-10a connected to gate electrode 42-5a and electrode 44-10b connected to gate electrode 42-5b.

[0068] The photoelectric conversion unit 71 is connected to the FD unit 72 via a transfer transistor 73, and the FD unit 72 is connected to the gate terminal of the amplification transistor 31. The drain terminal of the amplification transistor 31 is connected to the drain power supply VDD, and the source terminal of the amplification transistor 31 is connected to the vertical signal line VSL via a selection transistor 32, to which a constant current source is connected. A reset transistor 33 and a connection transistor 34 are connected in series between the FD unit 72 and the drain power supply VDD, and a capacitor structure 35 is connected between the connection point of the reset transistor 33 and the connection transistor 34 and the drain power supply VDD. The drain power supply VDD connected to the capacitor structure 35 does not have to be at the same potential as the drain power supply VDD connected to the amplification transistor 31 and the reset transistor 33.

[0069] In this second variation of the connection configuration, the pixel 11 can switch the connection of the capacitor structure 35 to the FD section 72 via the connecting transistor 34.

[0070] Figure 11A shows a circuit configuration of a third variation of the pixel 11, and Figure 11B shows an example of a planar layout of the transistor layer of the pixel 11 in the circuit configuration of the third variation. Figure 12 also shows an example of a cross-sectional configuration of an image sensor 12 equipped with a pixel 11 configured with the circuit configuration of the third variation.

[0071] As shown in Figure 11A, the pixel 11 is composed of an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, a capacitor structure 35, a photoelectric conversion unit 71, an FD unit 72, a transfer transistor 73, and an overflow gate 74. Note that the pixel 11 of the third variation circuit configuration does not employ a pixel sharing structure.

[0072] The photoelectric conversion unit 71 is connected to the FD unit 72 via a transfer transistor 73, and the FD unit 72 is connected to the gate terminal of the amplification transistor 31. The drain terminal of the amplification transistor 31 is connected to the drain power supply VDD, and the source terminal of the amplification transistor 31 is connected to the vertical signal line VSL via a selection transistor 32, to which a constant current source is connected. A reset transistor 33 and a connection transistor 34 are connected in parallel between the FD unit 72 and the drain power supply VDD, and a capacitor structure 35 is connected between the connection transistor 34 and the drain power supply VDD. Furthermore, an overflow gate 74 is connected between the photoelectric conversion unit 71 and the connection point of the connection transistor 34 and the capacitor structure 35. Note that the drain power supply VDD connected to the capacitor structure 35 does not have to be at the same potential as the drain power supply VDD connected to the amplification transistor 31 and the reset transistor 33.

[0073] In this third variation of the connection configuration, the pixel 11 can switch the connection of the capacitor structure 35 to the FD section 72 via the connecting transistor 34. Also, the charge that overflows from the photoelectric conversion section 71 is stored in the capacitor structure 35 via the overflow gate 74.

[0074] <Second Pixel Configuration Example> Referring to Figure 13, a second embodiment of the configuration example of a pixel in an image sensor to which this technology is applied will be described. In the pixel 11A shown in Figure 13, components common to the pixel 11 shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0075] Figure 13A shows a planar configuration example of the semiconductor layer and gate electrode constituting the transistor layer of pixel 11A, while Figure 13B shows a cross-sectional configuration example along the dashed line shown in Figure 13A.

[0076] As shown in Figure 13, the pixel 11A is configured by providing a capacitor structure 35A, along with an amplification transistor 31, a selection transistor 32, a reset transistor 33, and a connection transistor 34, in a transistor layer provided within the insulating film 21 that constitutes the wiring layer. The amplification transistor 31, selection transistor 32, reset transistor 33, and connection transistor 34 have an SOI (Silicon on Insulator) Fin structure and are configured in the same way as in Figure 1.

[0077] The capacitor structure 35A is constructed by surrounding the sides of multiple columnar semiconductor layers 41A (in the example shown in Figure 13A, twelve semiconductor layers 41A arranged in a 2x6 configuration are shown, but reference numerals other than those for the semiconductor layer 41A whose cross-section is shown in Figure 13B) with gate electrodes 42A via insulating film 45A, as shown in Figure 13B. Electrodes 44A are also provided to connect each semiconductor layer 41A to the wiring 43A. Specifically, a connection structure is used in which the upper surfaces of each semiconductor layer 41A are exposed without being covered by the gate electrodes 42A, and the electrodes 44A are connected to these upper surfaces from above.

[0078] The capacitor structure 35A is configured such that the gate electrode 42A is connected to the drain power supply VDD via the electrode 44-10, and each semiconductor layer 41A is connected to the semiconductor layer 41-2 which is the drain side of the connecting transistor 34 via the electrode 44A. Therefore, the capacitor structure 35A can use the space between the side surface of each semiconductor layer 41A and the gate electrode 42A as a charge storage capacitance for the charge supplied via the connecting transistor 34.

[0079] Thus, the pixel 11A is constructed by providing a capacitor structure 35A (i.e., a MOS (Metal Oxide Semiconductor) capacitor with an SOI Fin structure) on the transistor layer, which is composed of a plurality of columnar semiconductor layers 41A. With this configuration, the capacitor structure 35A of the pixel 11A can be formed in the same process as the SOI Fin structure pixel transistor, thus reducing the number of processes and increasing the charge storage capacity of the capacitor structure 35A.

[0080] <Third Pixel Configuration Example> Referring to Figure 14, a third embodiment of the configuration of a pixel in an image sensor to which this technology is applied will be described. In the pixel 11B shown in Figure 14, components common to the pixel 11 shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0081] Figure 14A shows a planar configuration example of the semiconductor layer and gate electrode constituting the transistor layer of pixel 11B, while Figure 14B shows a cross-sectional configuration example along the dashed line shown in Figure 14A.

[0082] As shown in Figure 14, the pixel 11B is constructed by providing a capacitor structure 35B, along with an amplification transistor 31, a selection transistor 32, a reset transistor 33, and a connection transistor 34, in a transistor layer provided within the insulating film 21 that constitutes the wiring layer. The amplification transistor 31, the selection transistor 32, the reset transistor 33, and the connection transistor 34 are constructed in a structure (Bulk Fin structure) in which the semiconductor layers 41B-1 and 41B-2 that constitute them are formed in a trench shape so as to protrude from the bulk silicon substrate.

[0083] The capacitor structure 35B is constructed by surrounding the sides of multiple columnar semiconductor layers 41B (in the example shown in Figure 14A, 12 semiconductor layers 41B arranged in a 2x6 configuration are shown, but reference numerals other than those for the semiconductor layer 41B whose cross-section is shown in Figure 14B are omitted) with gate electrodes 42B via insulating films 45B, as shown in Figure 14B. The capacitor structure 35B is constructed in a bulk fin structure in which the semiconductor layers 41B are formed in a columnar shape so as to protrude from a bulk silicon substrate. In addition, electrodes 44B are provided to connect each semiconductor layer 41B to the wiring 43B. That is, a connection structure is used in which the upper surfaces of each semiconductor layer 41B are exposed without being covered by the gate electrodes 42B, and the electrodes 44B are connected to their upper surfaces from above.

[0084] The capacitor structure 35B is configured such that the gate electrode 42B is connected to the drain power supply VDD via electrode 44-10, and each individual semiconductor layer 41B is connected to the semiconductor layer 41B-2, which is the drain side of the connecting transistor 34, via electrode 44B. Therefore, the space between the side surface of each semiconductor layer 41B and the gate electrode 42B can be used as a charge storage capacitance for the charge supplied via the connecting transistor 34. Furthermore, as shown in Figure 14B, the bottom surface of the gate electrode 42B is covered by a bulk silicon substrate which is the lower end portion of the semiconductor layer 41B via an insulating film 45B, and the space between the bottom surface of the gate electrode 42B and the bulk silicon substrate can also be used as a charge storage capacitance.

[0085] Thus, the pixel 11B is constructed by providing a capacitor structure 35B (i.e., a MOS capacitance of a bulk fin structure) on the transistor layer, which is composed of a plurality of columnar semiconductor layers 41B. With this configuration, the pixel 11B can further increase its charge storage capacity in proportion to the amount of charge that can be stored between the bottom surface of the gate electrode 42B and the bulk silicon substrate.

[0086] <Fourth Pixel Configuration Example> Referring to Figure 15, a fourth embodiment of the configuration example of a pixel in an image sensor to which this technology is applied will be described. In the pixel 11C shown in Figure 15, components common to the pixel 11 shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0087] Figure 15A shows a planar configuration example of the semiconductor layer and gate electrode constituting the transistor layer of pixel 11C, while Figure 15B shows a cross-sectional configuration example along the dashed line shown in Figure 15A.

[0088] As shown in Figure 15, the pixel 11C is constructed by providing a capacitor structure 35C, along with an amplification transistor 31, a selection transistor 32, a reset transistor 33, and a connection transistor 34, in a transistor layer provided within the insulating film 21 that constitutes the wiring layer. The amplification transistor 31, the selection transistor 32, the reset transistor 33, and the connection transistor 34 are constructed in a structure (Bulk Fin structure) in which the semiconductor layers 41C-1 and 41C-2 that constitute them are formed in a trench shape so as to protrude from the bulk silicon substrate.

[0089] The capacitor structure 35C is constructed by covering the top and side surfaces of multiple columnar semiconductor layers 41C (in the example shown in Figure 15A, 12 semiconductor layers 41C arranged in a 2x6 configuration are shown, but reference numerals other than those for the semiconductor layer 41C whose cross-section is shown in Figure 15B) with gate electrodes 42C via insulating films 45C, as shown in Figure 15B. The capacitor structure 35C is constructed in a bulk fin structure in which the semiconductor layers 41C are formed in a columnar shape so as to protrude from the bulk silicon substrate. Therefore, since the lower ends of each semiconductor layer 41C are connected by the bulk silicon substrate, one semiconductor layer 41C (the upper right semiconductor layer 41C in the illustrated example) can be connected to the wiring 43C via one electrode 44C, thereby reducing the wiring density.

[0090] The capacitor structure 35C is configured such that the gate electrode 42C is connected to the drain power supply VDD via electrode 44-10, and the semiconductor layer 41C is connected to the semiconductor layer 41C-2, which is the drain side of the connecting transistor 34, via electrode 44C. Therefore, the space between the top and side surfaces of each semiconductor layer 41C and the gate electrode 42C can be used as a charge storage capacitance for the charge supplied via the connecting transistor 34. Furthermore, as shown in Figure 15B, the bottom surface of the gate electrode 42C is covered by a bulk silicon substrate, which is the lower end portion of the semiconductor layer 41C, via an insulating film 45C, and the space between the bottom surface of the gate electrode 42C and the bulk silicon substrate can also be used as a charge storage capacitance.

[0091] Thus, the pixel 11C is constructed by providing a capacitor structure 35C (i.e., a MOS capacitance of a bulk fin structure) on the transistor layer, which is composed of a plurality of columnar semiconductor layers 41C. With this configuration, the pixel 11C can further increase its storage capacity by accumulating charge between the bottom surface of the gate electrode 42C and the bulk silicon substrate. Furthermore, since the upper surfaces of a plurality of semiconductor layers 41C other than the semiconductor layer 41C to which the electrode 44C is connected can be covered by the gate electrode 42C, charge can also be accumulated between the upper surfaces of these semiconductor layers 41C and the gate electrode 42C, thereby further increasing the storage capacity.

[0092] <Fifth Pixel Configuration Example> Referring to Figure 16, a fifth embodiment of the configuration example of a pixel in an image sensor to which this technology is applied will be described. In the pixel 11D shown in Figure 16, components common to the pixel 11 shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0093] Figure 16A shows a planar configuration example of the semiconductor layer and gate electrode constituting the transistor layer of pixel 11D, and Figure 16B shows a cross-sectional configuration example along the dashed line shown in Figure 16A.

[0094] As shown in Figure 16, the pixel 11D is configured such that a capacitor structure 35D is provided on a transistor layer within an insulating film 21 constituting the wiring layer, along with an amplifying transistor 31, a selection transistor 32, a reset transistor 33, and a connection transistor 34. The amplifying transistor 31, the selection transistor 32, the reset transistor 33, and the connection transistor 34 have an SOI Fin structure and are configured in the same way as in Figure 1.

[0095] The capacitor structure 35D is constructed by surrounding the sides of a plurality of columnar gate electrodes 42D (in the example shown in Figure 16A, 12 gate electrodes 42D arranged in a 2x6 configuration are shown, but reference numerals other than those for gate electrodes 42D whose cross-section is shown in Figure 16B) with a semiconductor layer 41D via an insulating film 45D, as shown in Figure 16B. Electrodes 44D are provided to connect each gate electrode 42D to a wiring 43D. Specifically, a connection structure is used in which the upper surfaces of each gate electrode 42D are exposed without being covered by the semiconductor layer 41D, and the electrodes 44D are connected to these upper surfaces from above. Additionally, an electrode 44-10 is provided to connect to the semiconductor layer 41D.

[0096] The capacitor structure 35D is configured such that the semiconductor layer 41D is connected to the drain power supply VDD via the electrode 44-10, and each gate electrode 42D is connected to the semiconductor layer 41-2 which is the drain side of the connecting transistor 34 via the electrode 44D. Therefore, the capacitor structure 35D can use the space between the side of each gate electrode 42D and the semiconductor layer 41D as a charge storage capacitance for the charge supplied via the connecting transistor 34.

[0097] Thus, the pixel 11D is constructed by providing a capacitor structure 35D (i.e., a MOS capacitance of an SOI Fin structure) on the transistor layer, which is composed of a plurality of columnar gate electrodes 42D. With this configuration, the pixel 11D can reduce the number of manufacturing steps, similar to the pixel 11A in Figure 13, and increase the charge storage capacity of the capacitor structure 35D.

[0098] <Sixth Pixel Configuration Example> Referring to Figures 17 to 28, a sixth embodiment of the configuration example of a pixel in an image sensor to which this technology is applied will be described. In Figures 17 to 28, components common to the pixel 11 shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0099] Figure 17A shows a planar configuration example of the semiconductor layer and gate electrode constituting the transistor layer of pixel 11E, and Figure 17B shows a cross-sectional configuration example along the dashed line shown in Figure 17A.

[0100] As shown in Figure 17, the pixel 11E is configured by providing a capacitor structure 35E, along with an amplification transistor 31, a selection transistor 32, a reset transistor 33, and a connection transistor 34, on a transistor layer provided within the insulating film 21 that constitutes the wiring layer. The amplification transistor 31, selection transistor 32, reset transistor 33, and connection transistor 34 are configured in the same way as in Figure 1.

[0101] The capacitor structure 35E is constructed by surrounding the sides of a plurality of columnar gate electrodes 42E (in the example shown in Figure 17A, 12 gate electrodes 42E arranged in a 2x6 configuration are shown, but reference numerals other than those for the gate electrodes 42E whose cross-section is shown in Figure 17B) with a semiconductor layer 41E via an insulating film 45E, as shown in Figure 17B. Furthermore, the upper end portion of the gate electrodes 42E is formed to cover the upper surface of the semiconductor layer 41E via the insulating film 45E. Therefore, since the capacitor structure 35E is configured such that each gate electrode 42E is connected at its upper end, each gate electrode 42E can be connected to the wiring 43E via a single electrode 44E, thereby reducing the wiring density.

[0102] The capacitor structure 35E is configured such that the semiconductor layer 41E is connected to the drain power supply VDD via the electrode 44-10, and the gate electrode 42E is connected to the semiconductor layer 41-2, which is the drain side of the connected transistor 34, via the electrode 44E. Therefore, the capacitor structure 35E can use the space between the side surface of each gate electrode 42E and the semiconductor layer 41E, and the space between the upper surface of the semiconductor layer 41E and the upper end portion of the gate electrode 42E, as a charge storage capacitance for the charge supplied via the connected transistor 34.

[0103] Thus, the pixel 11E is constructed by providing a capacitor structure 35E (i.e., a MOS capacitance of an SOI Fin structure) on the transistor layer, which is composed of a plurality of columnar gate electrodes 42E. With this configuration, the upper surface of the semiconductor layer 41E can be covered by the upper end portion of the gate electrodes 42E, and therefore, the storage capacitance can be further increased by the amount of charge that can be stored between the upper surface of the semiconductor layer 41E and the upper end portion of the gate electrodes 42E.

[0104] Referring to Figures 18 to 20, an example of the cross-sectional configuration of an image sensor 12E having pixels 11E will be described.

[0105] Figure 18 shows a first example of the cross-sectional configuration of the image sensor 12E. In the image sensor 12E shown in Figure 18, components common to the image sensor 12 shown in Figure 2 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0106] As shown in Figure 18, the sensor substrate 51 and the logic substrate 52E are joined together at a joint surface (shown by the thick dashed line in the figure), and the sensor substrate 51 is configured in the same way as in Figure 2. Furthermore, the image sensor 12E uses a pixel sharing structure in which multiple pixels 11E (in the illustrated example, two pixels 11E-1 and 11E-2) share a pixel transistor and a capacitor structure 35E.

[0107] The logic board 52E is constructed by stacking a wiring layer 63E on a semiconductor layer (not shown), and an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a capacitor structure 35E are provided within the insulating film 21 of the wiring layer 63E. In other words, the image sensor 12E has a different configuration from the image sensor 12 in Figure 2, in that a capacitor structure 35E is provided instead of the capacitor structure 35 in Figure 2.

[0108] Thus, the image sensor 12E can be configured to have a stacked structure in which a sensor substrate 51 and a logic substrate 52E are stacked, and the sensor substrate 51 and the logic substrate 52E are electrically connected using through electrodes 46.

[0109] Figure 19 shows a second example of the cross-sectional configuration of the image sensor 12E. In the image sensor 12E shown in Figure 19, components common to the image sensor 12 shown in Figure 3 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0110] As shown in Figure 19, the image sensor 12E is constructed by joining the front surface of the sensor substrate 51 and the back surface of the logic substrate 52E at a joint surface (shown by the thick dashed line in the figure), and the sensor substrate 51 is constructed in the same manner as in Figure 3. Furthermore, the image sensor 12E employs a pixel sharing structure in which multiple pixels 11E (in the illustrated example, two pixels 11E-1 and 11E-2) share a pixel transistor and capacitor structure 35E.

[0111] The logic board 52E is constructed by stacking a wiring layer 63E on a semiconductor layer (not shown), and an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a capacitor structure 35E are provided within the insulating film 21 of the wiring layer 63E. In other words, the image sensor 12E has a different configuration from the image sensor 12 in Figure 3, in that a capacitor structure 35E is provided instead of the capacitor structure 35 in Figure 3.

[0112] Thus, the image sensor 12E has a stacked structure in which the front surface of the sensor substrate 51 and the back surface of the logic substrate 52E are joined and stacked, and the sensor substrate 51 and the logic substrate 52E can be configured to be electrically connected using the Cu-Cu junctions of the connection pads 82 and 47.

[0113] Figure 20 shows a third example of the cross-sectional configuration of the image sensor 12E. In the image sensor 12E shown in Figure 20, components common to the image sensor 12 shown in Figure 4 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0114] As shown in Figure 20, the image sensor 12E is constructed by joining the surface side of the sensor substrate 51 and the surface side of the logic substrate 52E at a joint surface (shown by the thick dashed line in the figure), and the sensor substrate 51 is constructed in the same manner as in Figure 4. Furthermore, the image sensor 12E employs a pixel sharing structure in which multiple pixels 11E (in the illustrated example, two pixels 11E-1 and pixel 11E-2) share a pixel transistor and a capacitor structure 35E.

[0115] The logic board 52E is constructed by stacking a wiring layer 63E on a semiconductor layer (not shown), and an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a capacitor structure 35E are provided within the insulating film 21 of the wiring layer 63E. In other words, the image sensor 12E has a different configuration from the image sensor 12 in Figure 4, in that a capacitor structure 35E is provided instead of the capacitor structure 35 in Figure 4.

[0116] Thus, the image sensor 12E has a stacked structure in which the surface side of the sensor substrate 51 and the surface side of the logic substrate 52E are joined and stacked, and the sensor substrate 51 and the logic substrate 52E can be configured to be electrically connected using the Cu-Cu junctions of the connection pads 82 and 47.

[0117] Referring to Figures 21 to 24, an example of a planar layout of the transistor layer of the pixel 11E will be described. Note that in Figures 21 to 24, the wiring 43 is not shown, and the black circles shown in Figures 21 to 24 represent through electrodes used for contact with the sensor substrate 51.

[0118] Figure 21 shows a first planar layout example of the transistor layer of pixel 11E.

[0119] The left side of Figure 21 shows a first planar layout example of the transistor layer of multiple pixels 11E (in the illustrated example, nine pixels 11E arranged in a 3x3 configuration) that are arranged in an array on the sensor surface of the image sensor 12E. The right side of Figure 21 shows a first planar layout example of the transistor layer of one of the multiple pixels 11E.

[0120] In the first planar layout example shown in Figure 21, an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a capacitor structure 35E are provided in the transistor layer for each pixel 11E.

[0121] Thus, the image sensor 12E can constitute the transistor layer of the pixels 11E in a first planar layout example that does not employ a pixel sharing structure.

[0122] Figure 22 shows a second planar layout example of the transistor layer of pixel 11E.

[0123] On the left side of Figure 22, a second planar layout example of the transistor layer of multiple pixels 11E (in the illustrated example, 36 pixels 11E arranged in a 6x6 configuration) arranged in an array on the sensor surface of the image sensor 12E is shown. On the right side of Figure 22, a second planar layout example of the transistor layer of four pixels 11E-1 to 11E-4, which are FD sharing units arranged in a 2x2 configuration, is shown.

[0124] In the second planar layout example shown in Figure 22, an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a capacitor structure 35E are provided on the transistor layer for four pixels 11E-1 to 11E-4.

[0125] Thus, the image sensor 12E can be configured with a second planar layout example employing a four-pixel shared structure, thereby forming the transistor layer of the pixels 11E.

[0126] Figure 23 shows an example of a third planar layout of the transistor layer of pixel 11E.

[0127] On the left side of Figure 23, a third planar layout example of the transistor layer of multiple pixels 11E (48 pixels 11E arranged in a 6x8 configuration in the illustrated example) arranged in an array on the sensor surface of the image sensor 12E is shown. On the right side of Figure 23, a third planar layout example of the transistor layer of eight pixels 11E-1 to 11E-8, which are FD sharing units arranged in a 2x4 configuration, is shown.

[0128] In the third planar layout example shown in Figure 23, an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and capacitor structures 35E-1 and 35E-2 are provided on the transistor layer for eight pixels 11E-1 to 11E-8.

[0129] Thus, the image sensor 12E can be configured with a third planar layout example employing an eight-pixel shared structure, and the transistor layer of the pixels 11E can be formed in this way. Furthermore, in the eight-pixel shared structure, there is ample space for arrangement in the transistor layer, so two capacitor structures 35E-1 and 35E-2 can be provided for the eight pixels 11E-1 to 11E-8, thereby doubling the charge storage capacity.

[0130] Figure 24 shows a fourth planar layout example of the transistor layer of pixel 11E. In this fourth planar layout example, one pixel 11E (a so-called Dual PD) is formed by a pair of L pixels and R pixels that are arranged adjacent to each other.

[0131] On the left side of Figure 24, a fourth planar layout example of the transistor layer of multiple pixels 11E (in the illustrated example, 36 pixels 11E arranged in a 6x6 configuration) arranged in an array on the sensor surface of the image sensor 12E is shown. On the right side of Figure 24, a fourth planar layout example of the transistor layer of four pixels 11E-1 to 11E-4, which are FD sharing units arranged in a 2x2 configuration, is shown.

[0132] In the fourth planar layout example shown in Figure 24, an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a capacitor structure 35E are provided on the transistor layer for four pixels 11E-1 to 11E-4.

[0133] Thus, the image sensor 12E is a fourth planar layout example employing a four-pixel shared structure, and can constitute a transistor layer of pixels 11E composed of pairs of L pixels and R pixels.

[0134] Referring to Figures 25 to 28, variations in the circuit configuration of the pixel 11E and examples of the planar layout of the transistor layer of the pixel 11E in each variation will be explained. The black circles shown in Figures 25 to 28 represent through electrodes used for contact with the sensor substrate 51.

[0135] Figure 25A shows the circuit configuration of the first variation of pixel 11E, and Figure 25B shows an example of a planar layout of the transistor layer of pixel 11E in the circuit configuration of the first variation.

[0136] As shown in Figure 25A, the pixel 11E is composed of an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, a capacitor structure 35E, a photoelectric conversion unit 71, an FD unit 72, and a transfer transistor 73. As shown in Figure 25B, a four-pixel sharing structure is employed in which four pixels 11E-1 to 11E-4 share a pixel transistor, but Figure 25A shows the circuit configuration of a single pixel 11E.

[0137] The photoelectric conversion unit 71 is connected to the FD unit 72 via a transfer transistor 73, and the FD unit 72 is connected to the gate terminal of the amplification transistor 31. The drain terminal of the amplification transistor 31 is connected to the drain power supply VDD, and the source terminal of the amplification transistor 31 is connected to the vertical signal line VSL via a selection transistor 32, to which a constant current source is connected. A reset transistor 33 and a connection transistor 34 are connected in parallel between the FD unit 72 and the drain power supply VDD, and a capacitor structure 35E is connected between the connection transistor 34 and the drain power supply VDD. The drain power supply VDD connected to the capacitor structure 35E does not have to be at the same potential as the drain power supply VDD connected to the amplification transistor 31 and the reset transistor 33.

[0138] In the first variation of this connection configuration, the pixel 11E can switch the connection of the capacitor structure 35E to the FD section 72 via the connecting transistor 34.

[0139] Figure 26A shows the circuit configuration of a second variation of pixel 11E, and Figure 26B shows an example of a planar layout of the transistor layer of pixel 11E in the circuit configuration of the second variation.

[0140] As shown in Figure 26A, the pixel 11E is composed of an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, a capacitor structure 35E, a photoelectric conversion unit 71, an FD unit 72, and a transfer transistor 73. As shown in Figure 26B, a four-pixel shared structure is employed in which four pixels 11E-1 to 11E-4 share a pixel transistor, but Figure 26A shows the circuit configuration of a single pixel 11E. Also, as shown in Figure 26B, the capacitor structure 35E is composed of a gate electrode 42E-a and a gate electrode 42E-b, with electrode 44-10a connected to gate electrode 42E-a and electrode 44-10b connected to gate electrode 42E-b.

[0141] The photoelectric conversion unit 71 is connected to the FD unit 72 via a transfer transistor 73, and the FD unit 72 is connected to the gate terminal of the amplification transistor 31. The drain terminal of the amplification transistor 31 is connected to the drain power supply VDD, and the source terminal of the amplification transistor 31 is connected to the vertical signal line VSL via a selection transistor 32, to which a constant current source is connected. A reset transistor 33 and a connection transistor 34 are connected in series between the FD unit 72 and the drain power supply VDD, and a capacitor structure 35E is connected between the connection point of the reset transistor 33 and the connection transistor 34 and the drain power supply VDD. The drain power supply VDD connected to the capacitor structure 35E does not have to be at the same potential as the drain power supply VDD connected to the amplification transistor 31 and the reset transistor 33.

[0142] In this second variation of the connection configuration, the pixel 11E can switch the connection of the capacitor structure 35E to the FD section 72 via the connecting transistor 34.

[0143] Figure 27A shows a circuit configuration of a third variation of pixel 11E, and Figure 27B shows an example of a planar layout of the transistor layer of pixel 11E in the circuit configuration of the third variation. Figure 28 also shows an example of a cross-sectional configuration of an image sensor 12E equipped with pixel 11E configured with the circuit configuration of the third variation.

[0144] As shown in Figure 27A, the pixel 11E is configured to include an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, a capacitor structure 35E, a photoelectric conversion unit 71, an FD unit 72, a transfer transistor 73, and an overflow gate 74. Note that the pixel 11E of the third variation circuit configuration does not employ a pixel sharing structure.

[0145] The photoelectric conversion unit 71 is connected to the FD unit 72 via a transfer transistor 73, and the FD unit 72 is connected to the gate terminal of the amplification transistor 31. The drain terminal of the amplification transistor 31 is connected to the drain power supply VDD, and the source terminal of the amplification transistor 31 is connected to the vertical signal line VSL via a selection transistor 32, to which a constant current source is connected. A reset transistor 33 and a connection transistor 34 are connected in parallel between the FD unit 72 and the drain power supply VDD, and a capacitor structure 35E is connected between the connection transistor 34 and the drain power supply VDD. Furthermore, an overflow gate 74 is connected between the photoelectric conversion unit 71 and the connection point of the connection transistor 34 and the capacitor structure 35E. Note that the drain power supply VDD connected to the capacitor structure 35E does not have to be at the same potential as the drain power supply VDD connected to the amplification transistor 31 and the reset transistor 33.

[0146] In this third variation of the connection configuration, the pixel 11E can switch the connection of the capacitor structure 35E to the FD section 72 via the connecting transistor 34. In addition, the charge that overflows from the photoelectric conversion section 71 is stored in the capacitor structure 35E via the overflow gate 74.

[0147] <Seventh Pixel Configuration Example> Referring to Figure 29, a seventh embodiment of the configuration of a pixel in an image sensor to which this technology is applied will be described. In the pixel 11F shown in Figure 29, components common to the pixel 11 shown in Figure 1 and the pixel 11E shown in Figure 17 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0148] Figure 29A shows a planar configuration example of the semiconductor layer and gate electrode constituting the transistor layer of pixel 11F, while Figure 29B shows a cross-sectional configuration example along the dashed line shown in Figure 29A.

[0149] As shown in Figure 29, the pixel 11F is constructed by providing a capacitor structure 35F, along with an amplification transistor 31, a selection transistor 32, a reset transistor 33, and a connection transistor 34, in a transistor layer provided within the insulating film 21 that constitutes the wiring layer. The amplification transistor 31, the selection transistor 32, the reset transistor 33, and the connection transistor 34 are constructed in a structure (Bulk Fin structure) in which the semiconductor layers 41F-1 and 41F-2 that constitute them are formed in a trench shape so as to protrude from the bulk silicon substrate.

[0150] The capacitor structure 35F is constructed by covering the sides and bottom surfaces of a plurality of columnar gate electrodes 42F (in the example shown in Figure 29A, 12 gate electrodes 42F arranged in a 2x6 configuration are shown, but reference numerals other than those for the gate electrodes 42F whose cross-section is shown in Figure 29B) with a semiconductor layer 41F via an insulating film 45F, as shown in Figure 29B. For example, a gate electrode 42F can be provided in a recess formed by carving into the semiconductor layer 41F. In addition, electrodes 44F are provided to connect each gate electrode 42F to a wiring 43F. That is, a connection structure is used in which the upper surface of each gate electrode 42F is exposed and an electrode 44F is connected to each upper surface from above. Furthermore, an electrode 44-10 is provided to connect to the semiconductor layer 41F.

[0151] The capacitor structure 35F is configured such that the semiconductor layer 41F is connected to the drain power supply VDD via the electrode 44-10, and each gate electrode 42F is connected to the semiconductor layer 41F-2, which is the drain side of the connecting transistor 34, via the electrode 44F. Therefore, the capacitor structure 35F can use the space between the sides and bottom surfaces of each gate electrode 42F and the semiconductor layer 41F as a charge storage capacitance for the charge supplied via the connecting transistor 34.

[0152] Thus, the pixel 11F is constructed by providing a capacitor structure 35F (i.e., a MOS capacitance of a bulk fin structure) on the transistor layer, which is composed of a plurality of columnar gate electrodes 42F. With this configuration, the pixel 11F can increase the charge storage capacity in the capacitor structure 35F, and further increases the charge storage capacity by the bottom surface of the gate electrodes 42F.

[0153] <Example of the eighth pixel configuration> Referring to Figure 30, an example of the configuration of the eighth embodiment of a pixel in an image sensor to which this technology is applied will be described. In the pixel 11G shown in Figure 30, components common to the pixel 11 shown in Figure 1 and the pixel 11E shown in Figure 17 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0154] Figure 30A shows a planar configuration example of the semiconductor layer and gate electrode constituting the transistor layer of pixel 11G, and Figure 30B shows a cross-sectional configuration example along the dashed line shown in Figure 30A.

[0155] As shown in Figure 30, the pixel 11G is configured by providing a capacitor structure 35G, along with an amplification transistor 31, a selection transistor 32, a reset transistor 33, and a connection transistor 34, in a transistor layer provided within an insulating film 21 that constitutes a wiring layer. The amplification transistor 31, the selection transistor 32, the reset transistor 33, and the connection transistor 34 are configured in a structure (Bulk Fin structure) in which the semiconductor layers 41G-1 and 41G-2 that constitute them are formed in a trench shape so as to protrude from the bulk silicon substrate.

[0156] The capacitor structure 35G is constructed such that the sides and bottom surfaces of multiple columnar gate electrodes 42G (in the example shown in Figure 30A, 12 gate electrodes 42G arranged in a 2x6 configuration are shown, but reference numerals other than those for the gate electrodes 42G whose cross-section is shown in Figure 30B are omitted) are covered by a semiconductor layer 41G via an insulating film 45G, as shown in Figure 30B. Furthermore, the upper end portions of the gate electrodes 42G are formed to cover the upper surface of the semiconductor layer 41G via the insulating film 45G. Therefore, since the capacitor structure 35G is configured such that each gate electrode 42G is connected at its upper end, each gate electrode 42G can be connected to the wiring 43G via a single electrode 44G, thereby reducing the wiring density.

[0157] The capacitor structure 35G is configured such that the semiconductor layer 41G is connected to the drain power supply VDD via the electrode 44-10, and the gate electrode 42G is connected to the semiconductor layer 41G-2, which is the drain side of the connecting transistor 34, via the electrode 44G. Therefore, the capacitor structure 35G can use the space between the sides and bottom surfaces of each gate electrode 42G and the semiconductor layer 41G as a charge storage capacitance for the charge supplied via the connecting transistor 34.

[0158] Thus, the pixel 11G is constructed by providing a capacitor structure 35G (i.e., a bulk fin structure MOS capacitance) on the transistor layer, which is composed of a plurality of columnar gate electrodes 42G. With this configuration, the pixel 11G can cover the upper surface of the semiconductor layer 41G with the upper end portion of the gate electrode 42G, and the bottom surface of the gate electrode 42G with the semiconductor layer 41G. As a result, charge can be accumulated between the upper surface of the semiconductor layer 41G and the upper end portion of the gate electrode 42G, and between the bottom surface of the gate electrode 42G and the semiconductor layer 41G, thereby further increasing the charge storage capacity.

[0159] <Example of the ninth pixel configuration> Referring to Figure 31, an example of the configuration of the ninth embodiment of a pixel in an image sensor to which this technology is applied will be described. In the pixel 11H shown in Figure 31, components common to the pixel 11 shown in Figure 1 and the pixel 11E shown in Figure 17 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0160] Figure 31A shows a planar configuration example of the semiconductor layer and gate electrode constituting the transistor layer of pixel 11H, while Figure 31B shows a cross-sectional configuration example along the dashed line shown in Figure 31A.

[0161] As shown in Figure 31, the pixel 11H is configured such that a capacitor structure 35H is provided on a transistor layer within an insulating film 21 that constitutes a wiring layer, along with an amplification transistor 31, a selection transistor 32, a reset transistor 33, and a connection transistor 34. The amplification transistor 31, selection transistor 32, reset transistor 33, and connection transistor 34 are configured in the same way as in Figure 1.

[0162] The capacitor structure 35H is constructed such that the sides of multiple electrodes 44H (in the example shown in Figure 31A, twelve electrodes 44H arranged in a 2x6 configuration are shown, but reference numerals other than those for electrodes 44H whose cross-section is shown in Figure 31B are omitted) are each surrounded by a semiconductor layer 41H via an insulating film 45H, as shown in Figure 31B. Each individual electrode 44H is provided to be connected to a wiring 43H.

[0163] The capacitor structure 35H is configured such that the semiconductor layer 41H is connected to the drain power supply VDD via the electrode 44-10, and the electrode 44H is connected to the semiconductor layer 41-2 which is the drain side of the connecting transistor 34 via the wiring 43H. Therefore, the capacitor structure 35H can use the space between the side of each electrode 44H and the semiconductor layer 41H as a charge storage capacitance for the charge supplied via the connecting transistor 34.

[0164] Thus, the pixel 11H is constructed by providing a capacitor structure 35H, which is composed of a plurality of columnar electrodes 44H, on the transistor layer. With this configuration, the pixel 11H can increase the charge storage capacity of the capacitor structure 35H.

[0165] <Example of the 10th Pixel Configuration> Referring to Figure 32, an example of the configuration of a 10th embodiment of a pixel in an image sensor to which this technology is applied will be described. In the pixel 11J shown in Figure 32, components common to the pixel 11 shown in Figure 1 and the pixel 11E shown in Figure 17 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0166] Figure 32A shows a planar configuration example of the semiconductor layer and gate electrode constituting the transistor layer of pixel 11J, and Figure 32B shows a cross-sectional configuration example along the dashed line shown in Figure 32A.

[0167] As shown in Figure 32, the pixel 11J is configured such that a capacitor structure 35J is provided on a transistor layer within an insulating film 21 constituting the wiring layer, along with an amplifying transistor 31, a selection transistor 32, a reset transistor 33, and a connection transistor 34. The amplifying transistor 31, selection transistor 32, reset transistor 33, and connection transistor 34 are configured in the same way as in Figure 1.

[0168] The capacitor structure 35J is constructed by surrounding the sides of a plurality of columnar semiconductor layers 41J (in the example shown in Figure 32A, 12 semiconductor layers 41J arranged in a 2x6 configuration are shown, but reference numerals other than those for the semiconductor layers 41J whose cross-section is shown in Figure 32B) with gate electrodes 42J via insulating films 45J, as shown in Figure 32B. In addition, electrodes 44J are provided to connect each semiconductor layer 41J to the wiring 43J.

[0169] The capacitor structure 35J is configured such that the gate electrode 42J is connected to the drain power supply VDD via electrode 44-10, and each semiconductor layer 41J is connected to the semiconductor layer 41-2 which is the drain side of the connecting transistor 34 via electrode 44J. Therefore, the space between the side surface of each semiconductor layer 41J and the gate electrode 42J can be used as a charge storage capacitance for the charge supplied via the connecting transistor 34.

[0170] Furthermore, in the pixel 11J, the insulating film 45J constituting the capacitor structure 35J and the insulating film 45 constituting the pixel transistor are formed from different dielectric materials. For example, by using a dielectric material with a higher dielectric constant than the insulating film 45 constituting the pixel transistor for the insulating film 45J, the charge storage capacity of the capacitor structure 35J can be increased compared to a configuration in which the same dielectric material as the insulating film 45 constituting the pixel transistor is used, as in the embodiments described above.

[0171] Thus, the pixel 11J is constructed by providing a capacitor structure 35J (i.e., a MOS capacitance of an SOI Fin structure) made up of a plurality of columnar semiconductor layers 41J on the transistor layer. With this configuration, the pixel 11J can increase the charge storage capacity by forming the semiconductor layers 41J in a columnar shape, and by using a material with a high dielectric constant for the insulating film 45J.

[0172] Figures 33 to 36 illustrate the manufacturing method for the capacitor structure 35J provided in the pixel 11J shown in Figure 32.

[0173] In the first step, as shown in the first step of Figure 33, the insulating film 21 laminated on the semiconductor layer 41 is bonded to the sensor substrate 51. The thick dashed lines shown in Figures 33 to 36 represent the bonding surface with the sensor substrate 51, and the sensor substrate 51 will not be shown in the following explanation.

[0174] In the second step, the semiconductor layer 41 is thinned as shown in the second step of Figure 33.

[0175] In the third step, as shown in the third row of Figure 33, the semiconductor layer 41 is processed to form semiconductor layer 41-1, semiconductor layer 41-2, and semiconductor layer 41J. Then, ion implantation is performed on semiconductor layer 41-1 and semiconductor layer 41-2.

[0176] In the fourth step, as shown in the first step of Figure 34, an insulating film 45J is formed to cover semiconductor layers 41-1, 41-2, and 41J by depositing a material with a relatively high dielectric constant relative to semiconductor layer 41-1, semiconductor layer 41-2, and semiconductor layer 41J.

[0177] In the fifth step, as shown in the second step of Figure 34, the semiconductor layer 41J is protected with the resist 91 and the insulating film 45J covering the semiconductor layers 41-1 and 41-2 is peeled off.

[0178] In the sixth step, as shown in the third step of Figure 34, insulating films 45-1 and 45-2 are formed by depositing a material with a relatively low dielectric constant compared to semiconductor layers 41-1 and 41-2, respectively, thereby covering semiconductor layers 41-1 and 41-2. Then, the resist 91 is removed.

[0179] In the seventh step, as shown in the first step of Figure 35, a material that will become the gate electrode 42 is deposited on the entire surface of the insulating film 21 so that semiconductor layers 41-1, 41-2, and 41J are embedded.

[0180] In the eighth step, as shown in the second step of Figure 35, the material of the gate electrode 42, which was film-formed over its entire surface in the seventh step, is processed to form the gate electrode 42-1, gate electrode 42-2, and gate electrode 42J.

[0181] In the ninth step, as shown in the third row of Figure 35, the gate electrodes 42-1 and 42-2 are protected with resist 92.

[0182] In the tenth step, as shown in the first step of Figure 36, the gate electrode 42J is etched until the insulating film 45J covering the semiconductor layer 41J is exposed.

[0183] In the 11th step, as shown in the second step of Figure 36, an insulating film 21 is formed until it reaches a predetermined thickness.

[0184] In the twelfth step, as shown in the third step of Figure 36, electrode 44-1 is formed to connect to gate electrode 42-1, electrode 44-5 is formed to connect to gate electrode 42-2, electrode 44-10 is formed to connect to gate electrode 42J, and electrode 44J is formed to connect to semiconductor layer 41J. This forms the amplification transistor 31, reset transistor 33, and capacitor structure 35J.

[0185] By the manufacturing method described above, a pixel 11J can be manufactured in which the insulating film 45J constituting the capacitor structure 35J is made of a material with a higher dielectric constant than the insulating film 45 constituting the pixel transistor, which includes the amplification transistor 31 and the reset transistor 33.

[0186] <Example of the 11th Pixel Configuration> Referring to Figures 37 to 42, an example of the configuration of the 11th embodiment of a pixel in an image sensor to which this technology is applied will be described. In the pixel 11K shown in Figures 37 to 42, components common to the pixel 11 shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0187] Figure 37 shows a first planar layout example of 16 pixels 11K arranged in a 4x4 configuration on the transistor layer of a plurality of pixels 11K arranged in an array on the sensor surface of the image sensor 12K. In Figure 37, each rectangle separated by a dashed line represents a pixel 11K, and the same applies to Figures 38 to 42 described below.

[0188] In the pixels 11 of each embodiment described above, a pixel sharing structure was employed in which a FD sharing unit, in which multiple pixels 11 share the FD section 72 (and also share the pixel transistors after the FD section 72), and a capacitor sharing unit, in which multiple pixels 11 share the capacitor structure 35, coincided. In contrast, in pixel 11K, a pixel sharing structure is employed in which the FD sharing unit and the capacitor sharing unit are different.

[0189] In Figure 37, a dashed line is shown enclosing the pixels 11K that constitute the FD sharing unit 101, and a dashed line is shown enclosing the pixels 11K that constitute the capacitor sharing unit 102. The same applies to Figures 38 to 42, which will be explained below.

[0190] As shown in Figure 37, in the first planar layout example, FD sharing unit 101 is composed of four pixels 11K arranged in a 2x2 configuration, and capacitor sharing unit 102 is composed of eight pixels 11K arranged in a 2x4 configuration (rows x columns). Specifically, capacitor sharing unit 102-1 is composed of eight pixels 11K that make up the two leftmost FD sharing units 101-1 and FD sharing unit 101-3, which are arranged in the column direction, out of the four FD sharing units 101-1 to FD sharing units 101-4 arranged in a 2x2 configuration. Similarly, capacitor sharing unit 102-2 is composed of eight pixels 11K that make up the two rightmost FD sharing units 101-2 and FD sharing unit 101-4, which are arranged in the column direction, out of the four FD sharing units 101-1 to FD sharing units 101-4 arranged in a 2x2 configuration.

[0191] For example, the pixel transistors (amplifier transistor 31-1, selection transistor 32-1, reset transistor 33-1, and connection transistor 34-1) shared by four pixels 11K arranged in a 2x2 configuration that make up the FD sharing unit 101-1 are located in the two pixels 11K on the left side of the FD sharing unit 101-1. The pixel transistors (amplifier transistor 31-3, selection transistor 32-3, reset transistor 33-3, and connection transistor 34-3) shared by four pixels 11K arranged in a 2x2 configuration that make up the FD sharing unit 101-3 are located in the two pixels 11K on the left side of the FD sharing unit 101-3. And the capacitor structure 35K-1 shared by eight pixels 11K arranged in a 2x4 configuration that make up the capacitor sharing unit 102-1 is located in the four pixels 11K on the right side of the capacitor sharing unit 102-1.

[0192] Similarly, the pixel transistors (amplifier transistor 31-2, selection transistor 32-2, reset transistor 33-2, and connection transistor 34-2) shared by the four pixels 11K arranged in a 2x2 configuration that constitute the FD sharing unit 101-2 are located in the two pixels 11K on the left side of the FD sharing unit 101-2. The pixel transistors (amplifier transistor 31-4, selection transistor 32-4, reset transistor 33-4, and connection transistor 34-4) shared by the four pixels 11K arranged in a 2x2 configuration that constitute the FD sharing unit 101-4 are located in the two pixels 11K on the left side of the FD sharing unit 101-4. And the capacitor structure 35K-2 shared by the eight pixels 11K arranged in a 2x4 configuration that constitute the capacitor sharing unit 102-2 is located in the four pixels 11K on the right side of the capacitor sharing unit 102-2.

[0193] As described above, the image sensor 12K configured in the first planar layout example has a configuration that makes it easy to increase conversion efficiency by forming an FD shared unit 101 with four pixels 11K arranged in a 2x2 configuration. Furthermore, a large-capacity capacitor structure 35K corresponding to the size of the four pixels 11K arranged in the column direction can be used to address the need to reduce conversion efficiency.

[0194] In this way, by providing a wider capacitor sharing unit 102 than the FD sharing unit 101, the area occupied by the pixel transistors per FD sharing unit 101 can be reduced, the capacitance of the capacitor structure 35K can be increased, and a wider dynamic range can be supported.

[0195] In the first planar layout example shown in Figure 37, four pixels 11K arranged in a 2x2 configuration constitute an FD sharing unit 101, and eight pixels 11K arranged in a 2x4 configuration constitute a capacitor sharing unit 102. However, the configuration is not limited to this. For example, an FD sharing unit 101 can be made with mxn pixels 11K arranged in an mxn configuration, and a capacitor sharing unit 102 can be made with MxN pixels 11K arranged in an MxN configuration, as long as the relationship mxn is less than MxN (mxn < MxN) is satisfied.

[0196] Figure 38 shows a second planar layout example in the 11K pixel transistor layer.

[0197] As shown in Figure 38, in the second planar layout example, FD sharing unit 101 is composed of four pixels 11K arranged in a 2x2 configuration, and capacitor sharing unit 102 is composed of eight pixels 11K arranged in a 4x2 configuration (rows x columns). Specifically, capacitor sharing unit 102-1 is composed of eight pixels 11K that make up the two upper FD sharing units 101-1 and 101-2, which are arranged in the row direction, out of the four FD sharing units 101-1 to 101-4 arranged in a 2x2 configuration. Similarly, capacitor sharing unit 102-2 is composed of eight pixels 11K that make up the two lower FD sharing units 101-3 and 101-4, which are arranged in the row direction, out of the four FD sharing units 101-1 to 101-4 arranged in a 2x2 configuration.

[0198] For example, the pixel transistors (amplifier transistor 31-1, selection transistor 32-1, reset transistor 33-1, and connection transistor 34-1) shared by four pixels 11K arranged in a 2x2 configuration that make up the FD sharing unit 101-1 are located in the two pixels 11K on the left side of the FD sharing unit 101-1. The pixel transistors (amplifier transistor 31-2, selection transistor 32-2, reset transistor 33-2, and connection transistor 34-2) shared by four pixels 11K arranged in a 2x2 configuration that make up the FD sharing unit 101-2 are located in the two pixels 11K on the right side of the FD sharing unit 101-2. And the capacitor structure 35K-1 shared by eight pixels 11K arranged in a 4x2 configuration that make up the capacitor sharing unit 102-1 are located in the four pixels 11K arranged in a 2x2 configuration in the center of the capacitor sharing unit 102-1.

[0199] Similarly, the pixel transistors (amplifier transistor 31-3, selection transistor 32-3, reset transistor 33-3, and connection transistor 34-3) shared by the four pixels 11K arranged in a 2x2 configuration that constitute the FD sharing unit 101-3 are located in the two pixels 11K on the left side of the FD sharing unit 101-3. The pixel transistors (amplifier transistor 31-4, selection transistor 32-4, reset transistor 33-4, and connection transistor 34-4) shared by the four pixels 11K arranged in a 2x2 configuration that constitute the FD sharing unit 101-4 are located in the two pixels 11K on the right side of the FD sharing unit 101-4. And the capacitor structure 35K-2 shared by the eight pixels 11K arranged in a 2x4 configuration that constitute the capacitor sharing unit 102-2 are located in the four pixels 11K arranged in a 2x2 configuration in the center of the capacitor sharing unit 102-2.

[0200] As described above, the image sensor 12K configured in the second planar layout example can support a wider dynamic range, similar to the image sensor 12K in the first planar layout example shown in Figure 37.

[0201] Figure 39 shows a third planar layout example in the 11K pixel transistor layer.

[0202] As shown in Figure 39, in the third planar layout example, the FD sharing unit 101 is composed of four pixels 11K arranged in a 2x2 configuration, and the capacitor sharing unit 102 is composed of sixteen pixels 11K arranged in a 4x4 configuration. That is, the capacitor sharing unit 102 is composed of sixteen pixels 11K that make up four FD sharing units 101-1 to 101-4 arranged in a 2x2 configuration.

[0203] For example, the pixel transistors (amplifier transistor 31-1, selection transistor 32-1, reset transistor 33-1, and connection transistor 34-1) shared by four pixels 11K arranged in a 2x2 configuration that make up the FD sharing unit 101-1 are located in the two pixels 11K on the left side of the FD sharing unit 101-1. The pixel transistors (amplifier transistor 31-2, selection transistor 32-2, reset transistor 33-2, and connection transistor 34-2) shared by four pixels 11K arranged in a 2x2 configuration that make up the FD sharing unit 101-2 are located in the two pixels 11K on the right side of the FD sharing unit 101-2. Pixel transistors (amplifier transistor 31-3, selection transistor 32-3, reset transistor 33-3, and connection transistor 34-3) shared by four pixels 11K arranged in a 2x2 configuration that make up the FD sharing unit 101-3 are located in the two pixels 11K on the left side of the FD sharing unit 101-3. Pixel transistors (amplifier transistor 31-4, selection transistor 32-4, reset transistor 33-4, and connection transistor 34-4) shared by four pixels 11K arranged in a 2x2 configuration that make up the FD sharing unit 101-4 are located in the two pixels 11K on the right side of the FD sharing unit 101-4. Furthermore, a capacitor structure 35K shared by sixteen pixels 11K arranged in a 4x4 configuration that make up the capacitor sharing unit 102-1 is located in eight pixels 11K arranged in a 2x4 configuration in the center of the capacitor sharing unit 102-1.

[0204] As described above, the image sensor 12K configured in the third planar layout example can achieve a larger capacitance of the capacitor structure 35K than the image sensor 12K in the first planar layout example shown in Figure 37, and can also reduce the conversion efficiency, thereby enabling it to support an even wider dynamic range.

[0205] Figure 40 shows a fourth planar layout example in the 11K pixel transistor layer.

[0206] As shown in Figure 40, in the fourth planar layout example, the FD sharing unit 101 is composed of eight pixels 11K arranged in a 2x4 (row direction x column direction) configuration, and the capacitor sharing unit 102 is composed of sixteen pixels 11K arranged in a 4x4 configuration. That is, the capacitor sharing unit 102 is composed of sixteen pixels 11K that make up two FD sharing units 101-1 and FD sharing unit 101-2, which are arranged in a 2x1 (row direction x column direction) configuration.

[0207] For example, the pixel transistors (amplifier transistor 31-1, selection transistor 32-1, reset transistor 33-1, and connection transistor 34-1) shared by eight pixels 11K arranged in a 2x4 configuration that constitute the FD sharing unit 101-1 are located in the four pixels 11K on the left side of the FD sharing unit 101-1. The pixel transistors (amplifier transistor 31-2, selection transistor 32-2, reset transistor 33-2, and connection transistor 34-2) shared by eight pixels 11K arranged in a 2x4 configuration that constitute the FD sharing unit 101-2 are located in the four pixels 11K on the right side of the FD sharing unit 101-2. And the capacitor structure 35K shared by sixteen pixels 11K arranged in a 4x4 configuration that constitute the capacitor sharing unit 102 is located in eight pixels 11K arranged in a 2x4 configuration in the center of the capacitor sharing unit 102-1.

[0208] As described above, the image sensor 12K configured in the fourth planar layout example has more space for arranging pixel transistors compared to the first planar layout example in Figure 37, and can accommodate further miniaturization. Furthermore, similar to the third planar layout example in Figure 39, it can accommodate an even wider dynamic range.

[0209] Figure 41 shows a fifth planar layout example for the transistor layer of the pixels 11K. In this fifth planar layout example, similar to the first planar layout example in Figure 37 described above, an FD sharing unit 101 is formed by four pixels 11K arranged in a 2x2 configuration, and a capacitor sharing unit 102 is formed by eight pixels 11K arranged in a 2x4 configuration (rows x columns).

[0210] Furthermore, the pixel 11K used in the fifth planar layout example shown in Figure 41 is configured with five pixel transistors for each FD sharing unit 101, consisting of an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a second connection transistor 36. For example, the pixel 11K is configured to connect the FD section 72 and the wiring capacitor by the second connection transistor 36, and the charge generated in the pixel 11K can be stored in three stages of storage capacitors, with the conversion efficiency being variable for each stage. In other words, the charge generated in the pixel 11K can be stored in the FD section 72, in the FD section 72 and the wiring capacitor, or in the FD section 72, the wiring capacitor, and the capacitor structure 35K, and the conversion efficiency can be varied by switching between these.

[0211] As described above, the image sensor 12K configured in the fifth planar layout example allows for a wider range of dynamic range adjustment than the first planar layout example in Figure 37, by making the conversion efficiency variable. Of course, a configuration in which five or more transistors (for example, third and fourth connecting transistors) are provided as pixel transistors for each FD sharing unit 101 is also possible.

[0212] Figure 42 shows a sixth planar layout example in the 11K pixel transistor layer.

[0213] In the sixth planar layout example, similar to the first planar layout example in Figure 37 described above, the FD sharing unit 101 is composed of four pixels 11K arranged in a 2x2 configuration, and the capacitor sharing unit 102 is composed of eight pixels 11K arranged in a 2x4 configuration (rows x columns). Furthermore, the pixels 11K used in the sixth planar layout example are configured with five pixel transistors for each FD sharing unit 101, similar to the fifth planar layout example in Figure 41 described above, consisting of an amplification transistor 31, a selection transistor 32, a reset transistor 33, a connection transistor 34, and a second connection transistor 36.

[0214] Furthermore, the pixels 11K used in the sixth planar layout example are configured to have a second capacitor structure 37 for each FD sharing unit 101, the second capacitor structure 37 having a different charge storage capacity from the capacitor structure 35K. For example, the pixels 11K are configured to connect the FD section 72 and the second capacitor structure 37 by a second connecting transistor 36, and the charge generated in the pixels 11K can be stored in three stages of storage capacity, with the conversion efficiency being variable for each stage. In other words, the charge generated in the pixels 11K can be stored in the FD section 72, in the FD section 72 and the second capacitor structure 37, or in the FD section 72, the second capacitor structure 37, and the capacitor structure 35N, and the conversion efficiency can be varied by switching between these configurations.

[0215] As described above, the image sensor 12K configured in the sixth planar layout example allows for a wider range of dynamic range adjustment compared to the first planar layout example in Figure 37, by making the conversion efficiency variable.

[0216] <Modified Capacitor Structure> Modified capacitor structures of the capacitor structure 35 will be described with reference to Figures 43 and 44.

[0217] In the pixels 11 of each of the embodiments described above, a rectangular capacitor structure 35 was used, but the capacitor structure 35 is not limited to a rectangular shape.

[0218] Figure 43 shows an example of a planar layout of a pixel 11L employing the capacitor structure 35L of the first modified example.

[0219] As shown in Figure 43, the capacitor structure 35L can be formed in an L-shape in which two straight sections are connected at an angle of approximately 90 degrees via a single bend.

[0220] In the illustrated planar layout example, the FD sharing unit 101 and the capacitor sharing unit 102 are formed by eight pixels 11L arranged in a 2x4 configuration.

[0221] For example, the pixel transistors (amplifier transistor 31-1, selection transistor 32-1, reset transistor 33-1, and connection transistor 34-1) shared by the eight pixels 11L arranged in a 2x4 configuration that constitute the FD sharing unit 101-1 are located in the four pixels 11L arranged in a 2x2 configuration on the lower side of the FD sharing unit 101-1. The capacitor structure 35L-1 shared by the eight pixels 11L arranged in a 2x4 configuration that constitute the capacitor sharing unit 102-1 is located in three of the four pixels 11L arranged in a 2x2 configuration on the upper side of the capacitor sharing unit 102-1.

[0222] Similarly, the pixel transistors (amplifier transistor 31-2, selection transistor 32-2, reset transistor 33-2, and connection transistor 34-2) shared by the eight pixels 11L arranged in a 2x4 configuration that constitute the FD sharing unit 101-2 are located in the four pixels 11L arranged in a 2x2 configuration on the lower side of the FD sharing unit 101-2. The capacitor structure 35L-2 shared by the eight pixels 11L arranged in a 2x4 configuration that constitute the capacitor sharing unit 102-2 is located in three of the four pixels 11L arranged in a 2x2 configuration on the upper side of the capacitor sharing unit 102.

[0223] Furthermore, capacitor structure 35L-1 and capacitor structure 35L-2 are arranged so that their L-shapes are symmetrical to each other.

[0224] Figure 44 shows an example of a planar layout of pixels 11M employing a second modified capacitor structure 35M.

[0225] As shown in Figure 44, the capacitor structure 35M can be formed in a shape that surrounds a pixel transistor, with four straight sections connected at approximately 90-degree angles via three bent sections.

[0226] In the illustrated planar layout example, the FD sharing unit 101 and the capacitor sharing unit 102 are composed of four pixels 11M arranged in a 2x2 configuration.

[0227] For example, the pixel transistors (amplifier transistor 31-1, selection transistor 32-1, reset transistor 33-1, and connection transistor 34-1) shared by four pixels 11M arranged in a 2x2 configuration that constitute the FD sharing unit 101-1 are placed in the four pixels 11M arranged in a 2x2 configuration. The capacitor structure 35M-1 shared by four pixels 11M arranged in a 2x2 configuration that constitute the capacitor sharing unit 102-1 is placed in the four pixels 11M arranged in a 2x2 configuration in a shape that surrounds those pixel transistors.

[0228] Furthermore, FD sharing units 101-2 to 101-4 also have pixel transistors and capacitor structures 35M arranged in the same way as FD sharing unit 101-1.

[0229] As described above, the capacitor structure 35 can be formed in a shape that is more optimized for each layout in which the pixel transistor and the capacitor structure 35 are arranged.

[0230] <Example of the 12th Pixel Configuration> Referring to Figures 45 and 46, an example of the configuration of the 12th embodiment of a pixel in an image sensor to which this technology is applied will be described. In the pixel 11N shown in Figures 45 and 46, components common to the pixel 11 shown in Figure 1 are denoted by the same reference numerals, and their detailed explanations are omitted.

[0231] Figure 45 shows an example of a planar layout of the transistor layers of 16 pixels 11N arranged in a 4x4 configuration, among a plurality of pixels 11N arranged in an array on the sensor surface of the image sensor 12N. Figure 46 shows the circuit configuration of these 16 pixels 11N. In Figure 45, each rectangle separated by a dashed line represents a pixel 11N, dashed lines are shown enclosing the pixels 11N that constitute the FD sharing unit 101, and single-dash lines are shown enclosing the pixels 11N that constitute the capacitor sharing unit 102.

[0232] As shown in the planar layout example in Figure 45, the FD sharing unit 101 is composed of eight pixels 11N arranged in a 2x4 (row direction x column direction) configuration, and the capacitor sharing unit 102 is composed of sixteen pixels 11N arranged in a 4x4 configuration. That is, the capacitor sharing unit 102 is composed of sixteen pixels 11N that make up two FD sharing units 101-1 and FD sharing unit 101-2, which are arranged in a 2x1 (row direction x column direction) configuration.

[0233] Furthermore, the pixel 11N is provided with an amplification transistor 31-1, a selection transistor 32-1, a connection transistor 111-1, a connection transistor 112-1, and a connection transistor 113-1 for the FD sharing unit 101-1, and with an amplification transistor 31-2, a selection transistor 32-2, a connection transistor 111-2, a connection transistor 112-2, and a connection transistor 113-2 for the FD sharing unit 101-2, and is configured to share a reset transistor 33 and a connection transistor 34 in the capacitor sharing unit 102.

[0234] For example, the amplification transistor 31-1, selection transistor 32-1, connection transistor 111-1, connection transistor 112-1, and connection transistor 113-1, which are shared by the eight pixels 11N arranged in a 2x4 configuration that constitute the FD sharing unit 101-1, and the connection transistor 34, which is shared by the capacitor sharing unit 102, are arranged in the six pixels 11N arranged in a 2x3 configuration below the FD sharing unit 101-1. The amplification transistor 31-2, selection transistor 32-2, connection transistor 111-2, connection transistor 112-2, and connection transistor 113-2, which are shared by the eight pixels 11N arranged in a 2x4 configuration that constitute the FD sharing unit 101-2, and the reset transistor 33, which is shared by the capacitor sharing unit 102, are arranged in the six pixels 11N arranged in a 2x3 configuration below the FD sharing unit 101-2. Then, a capacitor structure 35N, shared by 16 pixels 11N arranged in a 4x4 grid that constitute the capacitor sharing unit 102, is placed in the two upper pixels 11N of capacitor sharing unit 102-1 and the two upper pixels 11N of capacitor sharing unit 102-2.

[0235] As shown in Figure 46, pixels 11N-1 to 11N-8 are connected to the FD section 72-1 via transfer transistors 73-1 to 73-8, respectively. Connecting transistors 111-1 and 112-1 are provided to connect the FD section 72-1 to the wiring capacitor 114-1. Connecting transistor 113-1 is provided to connect the wiring capacitor 114-1 to the capacitor structure 35N via connecting transistor 34. Therefore, the charge generated in pixels 11N-1 to 11N-8 can be stored in the three stages of storage capacitance, and the conversion efficiency can be varied for each stage. That is, the charge generated in pixels 11N-1 to 11N-8 can be stored in the FD section 72-1, in the FD section 72-1 and the wiring capacitor 114-1, or in the FD section 72-1, the wiring capacitor 114-1, and the capacitor structure 35N.

[0236] Similarly, as shown in Figure 46, pixels 11N-9 to 11N-16 are connected to the FD section 72-2 via transfer transistors 73-9 to 73-16, respectively, and connection transistors 111-2 and 112-2 are provided to connect the FD section 72-2 to the wiring capacitor 114-2. Connection transistor 113-2 is provided to connect the wiring capacitor 114-2 to the capacitor structure 35N via connection transistor 34. Therefore, the charge generated in pixels 11N-9 to 11N-16 can be stored in the three stages of storage capacitors, and the conversion efficiency can be varied for each. That is, the charge generated in pixels 11N-9 to 11N-16 can be stored in the FD section 72-2, in the FD section 72-2 and the wiring capacitor 114-2, or in the FD section 72-2, the wiring capacitor 114-2, and the capacitor structure 35N.

[0237] The image sensor 12N configured as described above can accommodate a wider dynamic range and allows for a greater range of adjustment. Furthermore, there is ample space for arranging the pixel transistors, enabling further miniaturization.

[0238] <Example of Electronic Device Configuration> The image sensor 12 described above can be applied to various electronic devices such as imaging systems like digital still cameras and digital video cameras, mobile phones equipped with imaging functions, or other devices equipped with imaging functions.

[0239] Figure 47 is a block diagram showing an example configuration of an imaging device mounted on an electronic device.

[0240] As shown in Figure 37, the imaging device 201 is configured to include an optical system 202, an image sensor 203, a signal processing circuit 204, a monitor 205, and a memory 206, and is capable of capturing still images and moving images.

[0241] The optical system 202 is composed of one or more lenses and guides the image light (incident light) from the subject to the image sensor 203, forming an image on the light-receiving surface (sensor part) of the image sensor 203.

[0242] The image sensor 203 is the same as the image sensor 12 described above. Electrons are accumulated in the image sensor 203 for a certain period of time, depending on the image formed on the light-receiving surface via the optical system 202. Then, a signal corresponding to the electrons accumulated in the image sensor 203 is supplied to the signal processing circuit 204.

[0243] The signal processing circuit 204 performs various signal processing operations on the pixel signals output from the image sensor 203. The image (image data) obtained by the signal processing circuit 204 is supplied to the monitor 205 for display or supplied to the memory 206 for storage (recording).

[0244] With the imaging device 201 configured in this way, by applying the image sensor 12 described above, it is possible to capture, for example, high-quality images with a wider dynamic range.

[0245] <Examples of Image Sensor Usage> Figure 48 shows an example of using the image sensor (imaging element) described above.

[0246] The image sensor described above can be used in various cases to sense light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0247] - Devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions. - Devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. - Devices used in home appliances such as TVs, refrigerators, and air conditioners that capture user gestures and allow device operation according to those gestures. - Devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception. - Devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition. - Devices used for beauty purposes, such as skin measuring devices that capture images of skin and microscopes that capture images of the scalp. - Devices used for sports purposes, such as action cameras and wearable cameras for sports use. - Devices used for agriculture, such as cameras that monitor the condition of fields and crops.

[0248] <Examples of Configuration Combinations> The technology can also take the following configurations: (1) An image sensor comprising: a first substrate on which a photoelectric conversion unit is provided; a second substrate laminated on the first substrate; and a capacitor structure composed of a semiconductor layer and a gate electrode such that one side of the semiconductor layer and gate electrode constituting a transistor layer provided in the insulating layer of the wiring layer of the second substrate are surrounded by at least an insulating film. (2) The image sensor according to (1) above, wherein the capacitor structure is configured such that the top surface and both sides of the trench-shaped semiconductor layer are covered by the gate electrode via the insulating film. (3) The image sensor according to (1) above, wherein the capacitor structure is configured such that the side of the columnar-shaped semiconductor layer is surrounded by the gate electrode via the insulating film. (4) The image sensor according to (3) above, wherein the pixel transistor provided on the transistor layer is an SOI (Silicon on Insulator) Fin structure, and electrodes are connected from above to each of the columnar-shaped semiconductor layers. (5) The image sensor according to (3) above, wherein the pixel transistors provided in the transistor layer have a bulk fin structure, and electrodes are connected from above to each of the columnar semiconductor layers. (6) The image sensor according to any one of (3) to (5) above, wherein the insulating film constituting the capacitor structure is the same or a different dielectric material as the insulating film constituting the pixel transistors provided in the transistor layer. (7) The image sensor according to (1) above, wherein the capacitor structure is configured such that the side surface of the columnar gate electrode is surrounded by the semiconductor layer via the insulating film. (8) The image sensor according to (7) above, wherein the pixel transistors provided in the transistor layer have an SOI (Silicon on Insulator) fin structure, and electrodes are connected from above to each of the columnar gate electrodes. (9) The image sensor according to (7) above, wherein the pixel transistors provided in the transistor layer have a bulk fin structure, and electrodes are connected from above to each of the columnar gate electrodes.(10) The image sensor according to any one of (7) to (9) above, wherein the insulating film constituting the capacitor structure is the same as or different from the insulating film constituting the pixel transistor provided in the transistor layer. (11) The image sensor according to any one of (1) to (10) above, wherein the relationship m × n is less than M × N for an FD sharing unit in which m × n pixels arranged in m × n share an FD (Floating Diffusion) portion and a capacitor sharing unit in which M × N pixels arranged in M ​​× N share the capacitor structure. (12) The image sensor according to any one of (1) to (11) above, wherein five or more transistors are provided as pixel transistors provided in the transistor layer for each FD sharing unit in which a plurality of pixels share an FD (Floating Diffusion) portion. (13) The image sensor according to (12) above, wherein a second capacitor structure having a different charge storage capacity from the capacitor structure is provided for each FD sharing unit. (14) The image sensor according to any one of (1) to (13) above, wherein the capacitor structure is formed in a shape in which two or more straight sections are connected via one or more bent sections. (15) An electronic device comprising an image sensor having a first substrate on which a photoelectric conversion section is provided, a second substrate laminated on the first substrate, and a capacitor structure composed of a semiconductor layer and a gate electrode such that one side of the semiconductor layer and gate electrode constituting a transistor layer provided in the insulating layer of the wiring layer of the second substrate is surrounded by at least an insulating film. (16) A method for manufacturing an image sensor, comprising forming a capacitor structure composed of a semiconductor layer and a gate electrode such that one side of the semiconductor layer and gate electrode constituting a transistor layer provided in the insulating layer of the wiring layer of the second substrate laminated on the first substrate on which a photoelectric conversion section is provided is surrounded by at least an insulating film.

[0249] It should be noted that this embodiment is not limited to the embodiment described above, and various modifications are possible without departing from the spirit of this disclosure. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also exist.

[0250] 11 Pixel, 12 Image sensor, 21 Insulating film, 31 Amplifying transistor, 32 Selecting transistor, 33 Reset transistor, 34 Connecting transistor, 35 Capacitor structure, 41 Semiconductor layer, 42 Gate electrode, 43 Wiring, 44 Electrode, 45 Insulating film, 46 Through electrode, 47 Connecting pad, 48 Connecting structure, 51 Sensor substrate, 52 Logic substrate, 61 Semiconductor layer, 62 Wiring layer, 63 Wiring layer, 71 Photoelectric conversion unit, 72 FD unit, 73 Transfer transistor, 81 Gate electrode, 82 Connecting pad, 83 Connecting structure

Claims

1. An image sensor comprising: a first substrate on which a photoelectric conversion unit is provided; a second substrate laminated on the first substrate; and a capacitor structure composed of a semiconductor layer and a gate electrode, such that a semiconductor layer constituting a transistor layer is provided within the insulating layer of the wiring layer of the second substrate, and one side of the gate electrode is surrounded by at least an insulating film.

2. The image sensor according to claim 1, wherein the capacitor structure is configured such that the upper surface and both sides of the trench-shaped semiconductor layer are covered by the gate electrode via the insulating film.

3. The image sensor according to claim 1, wherein the capacitor structure is configured such that the side surface of the columnar semiconductor layer is surrounded by the gate electrode via the insulating film.

4. The image sensor according to claim 3, wherein the pixel transistors provided in the transistor layer have an SOI (Silicon on Insulator) Fin structure, and electrodes are connected from above to each of the columnar semiconductor layers.

5. The image sensor according to claim 3, wherein the pixel transistors provided in the transistor layer have a bulk fin structure, and electrodes are connected from above to each of the columnar semiconductor layers.

6. The image sensor according to claim 3, wherein the insulating film constituting the capacitor structure is the same as or different from the insulating film constituting the pixel transistor provided in the transistor layer.

7. The image sensor according to claim 1, wherein the capacitor structure is configured such that the side surface of the columnar gate electrode is surrounded by the semiconductor layer via the insulating film.

8. The image sensor according to claim 7, wherein the pixel transistors provided in the transistor layer have an SOI (Silicon on Insulator) Fin structure, and electrodes are connected from above to each of the columnar gate electrodes.

9. The image sensor according to claim 7, wherein the pixel transistors provided in the transistor layer have a bulk fin structure, and electrodes are connected from above to each of the columnar gate electrodes.

10. The image sensor according to claim 7, wherein the insulating film constituting the capacitor structure is the same as or different from the insulating film constituting the pixel transistor provided in the transistor layer.

11. The image sensor according to claim 1, wherein the relationship m × n is less than M × N for an FD (Floating Diffusion) portion shared by m × n pixels arranged in an m × n pattern, and a capacitor sharing unit shared by M × N pixels arranged in an M × N pattern.

12. The image sensor according to claim 1, wherein five or more transistors are provided as pixel transistors in the transistor layer for each FD sharing unit that shares an FD (Floating Diffusion) portion with multiple pixels.

13. The image sensor according to claim 12, wherein a second capacitor structure having a charge storage capacity different from that of the capacitor structure is provided for each FD sharing unit.

14. The image sensor according to claim 1, wherein the capacitor structure is formed in a shape in which two or more straight sections are connected via one or more bent sections.

15. An electronic device comprising an image sensor having a first substrate on which a photoelectric conversion unit is provided, a second substrate laminated on the first substrate, and a capacitor structure composed of a semiconductor layer and a gate electrode such that a semiconductor layer constituting a transistor layer is provided within the insulating layer of the wiring layer of the second substrate, and one side of the gate electrode is surrounded by at least an insulating film.

16. A method for manufacturing an image sensor, comprising forming a capacitor structure composed of a semiconductor layer and a gate electrode such that one side of the semiconductor layer and gate electrode constituting a transistor layer provided in an insulating layer of a wiring layer of a second substrate laminated on a first substrate on which a photoelectric conversion unit is provided is surrounded by at least an insulating film.

Images