Electronic device and method for controlling same

Abstract

An electronic device is disclosed. The electronic device comprises: a communication interface; at least one accelerator for providing a computational resource; an integrated API including at least one function implemented in a preset format; a memory storing instructions; and at least one processor, wherein, when the instructions are executed individually or collectively by the at least one processor, the electronic device: when an application is executed, acquires information about an accelerator for executing the application, wherein the information about the accelerator includes type information of the accelerator; acquires, on the basis of the application, a function included in the integrated API and an operation order of the function; converts the function of the integrated API acquired on the basis of the type information of the accelerator into a function of a format corresponding to the type information of the accelerator; and executes the converted function to communicate with the accelerator.

Description

Electronic device and control method thereof

[0001] The present disclosure relates to an electronic device and a method for controlling the same, and more specifically, to an electronic device capable of performing communication between heterogeneous accelerators and a method for controlling the same.

[0002] A heterogeneous cluster system can represent connecting heterogeneous systems via an interconnect network to use them as homogeneous systems. Such a heterogeneous cluster system may include a processor and at least one accelerator capable of performing specific tasks faster than the processor. For example, the heterogeneous cluster system may include accelerators such as a GPU (Graphics Processing Unit) or an FPGA (Field Programmable Gate Array). The heterogeneous cluster system can perform communication between accelerators by controlling accelerators and network cards along the communication path.

[0003] In this case, if the accelerators within the heterogeneous cluster system are of different types, or if the software for controlling the accelerators and network cards is incompatible, smooth communication between the accelerators cannot be performed.

[0004] According to the present disclosure, an electronic device may include a communication interface, at least one accelerator for providing computational resources, a memory for storing instructions and an integrated API including at least one function implemented in a preset format, and at least one processor. When the instructions are executed individually or collectively by the at least one processor, the electronic device may, when an application is executed, obtain information about an accelerator for executing the application, the information about the accelerator includes type information of the accelerator, obtain a function included in the integrated API and the order of operation of the function based on the application, convert the function of the integrated API obtained based on the type information of the accelerator into a function in a format corresponding to the type information of the accelerator, and execute the converted function to communicate with the accelerator.

[0005] According to the present disclosure, information regarding the accelerator further includes size information of data to be transmitted or received to the accelerator, and the at least one accelerator may include a first accelerator and a second accelerator. When the instructions are executed individually or collectively by the at least one processor, the electronic device identifies whether Remote Direct Memory Access (RDMA) is supported between the first accelerator and the second accelerator, and if RDMA is not supported between the first accelerator and the second accelerator, it sets a buffer in the memory corresponding to the size information of the data, and based on the address of the set buffer, obtains a first function for transmitting data from the first accelerator to the memory and a second function for transmitting data from the memory to the second accelerator among the functions included in the integrated API.

[0006] When the above instructions are executed individually or collectively by the at least one processor, the electronic device may obtain a third function for transferring data from the first accelerator to the second accelerator among the functions included in the integrated API, if RDMA is supported between the first accelerator and the second accelerator.

[0007] When the above instructions are executed individually or collectively by the at least one processor, if RDMA is not supported between the first accelerator and the second accelerator, the electronic device may set a first buffer and a second buffer in the memory with a size corresponding to the size information of the data, and based on the first buffer address and the second buffer address, together obtain a first function for transferring data from the first accelerator to the memory and a second function for transferring data from the memory to the second accelerator among the functions included in the integrated API.

[0008] According to the present disclosure, the communication interface may include at least one network card for performing communication with an external electronic device. When the instructions are executed individually or collectively by the at least one processor, the electronic device may identify a first network card having the largest bandwidth with the accelerator among the at least one network cards, identify whether RDMA is supported between the accelerator and the first network card, and if RDMA is not supported between the accelerator and the first network card, set a buffer in the memory corresponding to the size information of the data, and based on the address of the set buffer, obtain a first function for transferring data from the accelerator to the memory and a fourth function for transferring data from the memory to the external electronic device through the first network card among the functions included in the integrated API.

[0009] If RDMA is supported between the accelerator and the first network card, the electronic device can obtain a fifth function among the functions included in the integrated API for transmitting data from the accelerator to the external electronic device through the first network card.

[0010] When the above instructions are executed individually or collectively by the at least one processor, the electronic device identifies a first network card having the largest bandwidth with the accelerator among the at least one network cards, identifies whether RDMA is supported between the accelerator and the first network card, and if RDMA is not supported between the accelerator and the first network card, sets a buffer in the memory corresponding to the size information of the data, and based on the set buffer address, obtains a sixth function for storing data received from an external electronic device in memory among the functions included in the integrated API, and a second function for transmitting data from the memory to the accelerator.

[0011] If RDMA is supported between the accelerator and the first network card, the electronic device can obtain a seventh function among the functions included in the integrated API for transmitting data received from the external electronic device through the first network card to the accelerator.

[0012] Meanwhile, a control method for an electronic device according to one or more embodiments of the present disclosure may include, when an application is executed, a step of obtaining information about an accelerator for executing the application; a step of obtaining a function included in an integrated API implemented in a preset format based on the application and a sequence of operations of the function; a step of converting a function of the integrated API obtained based on the accelerator type information included in the information about the accelerator into a function in a format corresponding to the accelerator type information; and a step of executing the converted function to perform communication with the accelerator.

[0013] According to the present disclosure, information regarding the accelerator may further include size information of data to be transmitted or received by the accelerator. The step of obtaining a function included in the integrated API and the operation sequence of the function may include: identifying whether Remote Direct Memory Access (RDMA) is supported between a first accelerator and a second accelerator within the electronic device; if RDMA is not supported between the first accelerator and the second accelerator, setting a buffer corresponding to the size information of the data in the memory of the electronic device; and, based on the set buffer address, obtaining a first function for transmitting data from the first accelerator to memory and a second function for transmitting data from the memory to the second accelerator among the functions included in the integrated API.

[0014] The step of obtaining the function included in the integrated API and the operation order of the function may further include the step of obtaining a third function for transmitting data from the first accelerator to the second accelerator among the functions included in the integrated API, if RDMA is supported between the first accelerator and the second accelerator.

[0015] According to the present disclosure, the step of obtaining a function included in the integrated API and the operation order of the function may include: identifying a first network card having the largest bandwidth among network cards in the electronic device with respect to the accelerator; identifying whether RDMA is supported between the accelerator and the first network card; if RDMA is not supported between the accelerator and the first network card, setting a buffer corresponding to the size information of the data in the memory of the electronic device; and, based on the set buffer address, obtaining a first function for transmitting data from the accelerator to the memory and a fourth function for transmitting data from the memory to an external electronic device through the first network card among the functions included in the integrated API.

[0016] The step of obtaining the functions included in the integrated API and the operation sequence of the functions may further include the step of obtaining a fifth function among the functions included in the integrated API for transmitting data from the accelerator to the external electronic device through the first network card, if RDMA is supported between the accelerator and the first network card.

[0017] According to the present disclosure, the step of obtaining a function included in the integrated API and the operation order of the function may include: identifying a first network card having the largest bandwidth among network cards in the electronic device with respect to the accelerator; identifying whether RDMA is supported between the accelerator and the first network card; if RDMA is not supported between the accelerator and the first network card, setting a buffer corresponding to the size information of the data in the memory of the electronic device; and, based on the set buffer address, obtaining a sixth function for storing data received from an external electronic device through the first network card in memory and a second function for transmitting data from the memory to the accelerator among the functions included in the integrated API.

[0018] The step of obtaining the functions included in the integrated API and the operation sequence of the functions may further include the step of obtaining a seventh function among the functions included in the integrated API for transmitting data received from the external electronic device through the first network card to the accelerator, if RDMA is supported between the accelerator and the first network card.

[0019] FIG. 1 is a drawing for illustrating a heterogeneous cluster system according to various embodiments of the present disclosure.

[0020] FIG. 2 is a block diagram illustrating the configuration of an electronic device according to various embodiments of the present disclosure.

[0021] FIGS. 3 and 4 are drawings for explaining the operation of an electronic device communicating with an accelerator according to various embodiments of the present disclosure.

[0022] FIGS. 5 to 8 are drawings for explaining the operation of an electronic device acquiring a communication API according to various embodiments of the present disclosure.

[0023] FIG. 9 is a diagram illustrating the operation of an electronic device implementing an integrated API according to various embodiments of the present disclosure.

[0024] FIGS. 10 to 13 are flowcharts for explaining a method of controlling an electronic device according to various embodiments of the present disclosure.

[0025] The terms used in this specification will be briefly explained, and the present disclosure will be described in detail.

[0026] The terms used in the embodiments of this disclosure have been selected to be as widely used as possible, taking into account their functions within this disclosure; however, these terms may vary depending on the intent of those skilled in the art, case law, the emergence of new technologies, etc. Additionally, in specific cases, terms have been arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant explanatory section of this disclosure. Therefore, terms used in this disclosure should be defined not merely by their names, but based on their meanings and the overall content of this disclosure.

[0027] In this specification, expressions such as “have,” “may have,” “include,” or “may include” indicate the presence of such features (e.g., numerical values, functions, operations, or components such as parts) and do not exclude the presence of additional features.

[0028] In the present disclosure, expressions such as “A or B,” “at least one of A or / and B,” or “one or more of A or / and B” may include all possible combinations of items listed together. For example, “A or B,” “at least one of A and B,” or “at least one of A or B” may refer to cases including (1) at least one A, (2) at least one B, or (3) both at least one A and at least one B.

[0029] Expressions such as "first," "second," "first," or "second" used in this specification may modify various components regardless of order and / or importance, and are used only to distinguish one component from another and do not limit said components.

[0030] Where it is stated that a component (e.g., Component 1) is "operatively or communicatively coupled with / to" or "connected to" another component (e.g., Component 2), it should be understood that the component may be directly connected to the other component or connected through the other component (e.g., Component 3).

[0031] The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "consisting of" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0032] In the present disclosure, a "module" or "part" performs at least one function or operation and may be implemented in hardware or software, or a combination of hardware and software. Additionally, a plurality of "modules" or a plurality of "parts" may be integrated into at least one module and implemented by at least one processor (not shown), except for a "module" or "part" that needs to be implemented in specific hardware.

[0033] An embodiment of the present disclosure will be described in more detail below with reference to the attached drawings.

[0034] FIG. 1 is a drawing for explaining a heterogeneous cluster system (10) according to various embodiments of the present disclosure.

[0035] A heterogeneous cluster system (10) may represent connecting heterogeneous electronic devices to a network so that they operate as if they were a single system. The electronic devices included in the heterogeneous cluster system (10) may include accelerators for rapidly performing specific operations. For example, the accelerators may include a GPU (Graphics Processing Unit), an FPGA (Field Programmable Gate Array), an NPU (Neural Processing Unit), etc. In order to perform communication between accelerators in the heterogeneous cluster system (10), the electronic device may execute instructions to the accelerators and network cards on the communication path using software (e.g., driver, runtime, etc.) for controlling the accelerators and communication interfaces (e.g., network card).

[0036] In this case, conventionally, communication between accelerators can be performed smoothly when the accelerators within the heterogeneous cluster system (10) are of the same type or when the control software is compatible. However, the heterogeneous cluster system (10) according to various embodiments of the present disclosure can perform communication between accelerators smoothly even when the types of accelerators are different or heterogeneous accelerators with incompatible control software are included.

[0037] Referring to FIG. 1, a heterogeneous cluster system (10) may include an electronic device (100) and a plurality of external electronic devices (101 to 10n). In this case, the electronic device (100) and the plurality of external electronic devices (101 to 10n) may be implemented as various types of devices such as smartphones, PDAs (personal digital assistants), tablet PCs, computers, notebooks, and laptop PCs. However, they are not limited thereto, and the electronic device (100) and the plurality of external electronic devices (101 to 10n) may include any device capable of performing computational functions. Additionally, the electronic device (100) and the plurality of external electronic devices (101 to 10n) may be referred to as computation nodes, nodes, etc.

[0038] The electronic device (100) and a plurality of external electronic devices (101 to 10n) can be connected to each other through a network. The electronic devices included in the heterogeneous cluster system (10) can be connected to other electronic devices through a network and can transmit and receive data with the electronic devices connected to the communication.

[0039] Through this, the heterogeneous cluster system (10) can implement a high-performance computing system capable of large-scale deep learning training or parallel computation.

[0040] FIG. 2 is a block diagram illustrating the configuration of an electronic device (100) according to various embodiments of the present disclosure.

[0041] According to FIG. 2, the electronic device (100) may include a communication interface (110), at least one accelerator (120), memory (130) and a processor (140).

[0042] The communication interface (110) is configured to perform communication with at least one external device. The communication interface (110) may include at least one wireless communication module, at least one wired communication module, etc. Each communication module may be implemented in the form of at least one hardware chip. The wireless communication module may include at least one module among a Wi-Fi module, a Bluetooth module, an infrared communication module, or other communication modules. In addition, the communication interface (110) may include at least one communication chip that performs communication according to various wireless communication standards such as Zigbee, 3G (3rd Generation), 3GPP (3rd Generation Partnership Project), LTE (Long Term Evolution), LTE-A (LTE Advanced), 4G (4th Generation), 5G (5th Generation), etc. The wired communication module may include, for example, at least one of a LAN (Local Area Network) module, an Ethernet module, a pair cable, a coaxial cable, a fiber optic cable, or an UWB (Ultra Wide-Band) module.

[0043] The communication interface (110) may include at least one network card for performing communication with external electronic devices (101 to 10n). The communication interface (110) is implemented in various forms such as this, and by performing communication with external electronic devices (101 to 10n), it can receive various data from external electronic devices (101 to 10n) or transmit data to external electronic devices (101 to 10n).

[0044] At least one accelerator (120) is configured to provide computational resources. Performing computations of high complexity, such as training a deep learning model, may require a significant amount of computation time. In this case, the processor (140) can reduce computation time by distributing computational data to the accelerator (120). The accelerator (120) may also perform specific tasks faster than the processor (140). The accelerator (120) may include a processor for performing computations and memory for storing computational data.

[0045] The memory (130) may be implemented as internal memory such as ROM (e.g., EEPROM (electrically erasable programmable read-only memory)) or RAM included in the processor (140), or it may be implemented as memory separate from the processor (140). Depending on the purpose of data storage, the memory (130) may be implemented as memory embedded in the electronic device (100) or as memory detachable from the electronic device (100). For example, data for operating the electronic device (100) may be stored in memory embedded in the electronic device (100), and data for the expansion function of the electronic device (100) may be stored in memory detachable from the electronic device (100).

[0046] Meanwhile, the memory embedded in the electronic device (100) may be implemented as at least one of volatile memory (e.g., DRAM (dynamic RAM), SRAM (static RAM), or SDRAM (synchronous dynamic RAM), non-volatile memory (e.g., OTPROM (one time programmable ROM), PROM (programmable ROM), EPROM (erasable and programmable ROM), EEPROM (electrically erasable and programmable ROM), mask ROM, flash ROM, flash memory (e.g., NAND flash or NOR flash), hard drive, or solid state drive (SSD), and the memory that is detachable from the electronic device (100) may be implemented in the form of a memory card (e.g., CF (compact flash), SD (secure digital), Micro-SD (micro secure digital), Mini-SD (mini secure digital), xD (extreme digital), MMC (multi-media card), etc.), or external memory that can be connected to a USB port (e.g., USB memory).

[0047] The memory (130) may store at least one instruction, data, program, etc., required for the operation of the electronic device (100) or the processor (140). For example, the memory (130) may store computational data received from at least one accelerator (120). Additionally, the memory (130) may store an operating system (O / S) for driving the electronic device (100). Furthermore, the memory (130) may store various software programs or applications for the operation of the electronic device (100) according to various embodiments of the present disclosure. Also, the memory (130) may include semiconductor memory such as flash memory or magnetic storage media such as a hard disk.

[0048] Specifically, various software modules for operating an electronic device (100) according to various embodiments of the present disclosure may be stored in the memory (130), and the processor (140) may control the operation of the electronic device (100) by executing the various software modules stored in the memory (130). That is, the memory (130) is accessed by the processor (140), and reading / writing / modifying / deleting / updating of data by the processor (140) may be performed.

[0049] The memory (130) may be implemented as a single memory that stores data generated in various operations according to the present disclosure, but is not limited thereto, and the memory (130) may be implemented to include a plurality of memories that each store different types of data or each store data generated in different stages.

[0050] Meanwhile, in the present disclosure, the term memory (130) may be used to include a storage unit, a ROM (not shown), a RAM (not shown) within a processor (140), or a memory card (not shown) (e.g., a micro SD card, a memory stick) mounted in an electronic device (100).

[0051] Additionally, memory (130) may store an Application Programming Interface (API). The API may include at least one function implemented in a preset format. The API will be described in more detail later.

[0052] The processor (140) is a component connected to each component of the electronic device (100) to control the overall operation of the electronic device (100). The processor (140) may be implemented as a digital signal processor (DSP) for processing digital signals, a microprocessor, an artificial intelligence (AI) processor, or a time controller (TCON). However, it is not limited thereto, and may include or be defined by one or more of a central processing unit (CPU), a micro controller unit (MCU), a micro processing unit (MPU), a controller, an application processor (AP), a communication processor (CP), or an ARM processor. Additionally, the processor (140) may be implemented as a System on Chip (SoC) or a large-scale integration (LSI) with built-in processing algorithms, or it may be implemented in the form of an application-specific integrated circuit (ASIC). Additionally, the processor (140) can perform various functions by executing computer executable instructions stored in memory (130). The processor (140) may be implemented as one or multiple units.

[0053] When an application is executed, the processor (140) can obtain information about an accelerator (120) for executing the application. For example, the information about the accelerator (120) may include at least one of type information of the accelerator (120), index information of the accelerator (120), memory address of the accelerator (120), and size information of data to be transmitted or received by the accelerator (120).

[0054] The processor (140) can obtain functions included in the integrated API and the order of operation of the functions based on the application. Based on the type information of the accelerator (120), the processor (140) can convert the functions of the integrated API obtained into functions in a format corresponding to the type information of the accelerator, and execute the converted functions to communicate with the accelerator (120).

[0055] For example, if the accelerator (120) is implemented as a GPU of company N, the processor (140) can convert the acquired function into a function corresponding to the format of company N and execute the converted function to communicate with the GPU of company N.

[0056] FIGS. 3 and 4 are drawings for explaining the operation of an electronic device communicating with an accelerator according to various embodiments of the present disclosure. For example, FIG. 3 is a drawing for explaining the operation of an electronic device (100) communicating with an accelerator (120) in a heterogeneous cluster system (10).

[0057] Referring to FIG. 3, an electronic device (100) may be connected to external electronic devices (101 to 10n) through an interconnect network (310) in a heterogeneous cluster system (10). Additionally, the electronic device (100) may include a communication interface (110), at least one accelerator (120), a memory (130), and a processor (140). In this case, the communication interface (110) may include at least one network card for communicating with external electronic devices (101 to 10n).

[0058] When there are multiple accelerators (120), the multiple accelerators (120) may be implemented of the same type, but as illustrated in FIG. 3, different types of accelerators (120) may be included. Also, although FIG. 3 only shows the first accelerator (121) and the second accelerator (122) among the multiple accelerators (120), the multiple accelerators (120) may include three or more accelerators (120). The accelerators (120) may be connected to a processor (140) or memory (130) through an interconnect network (320) within the electronic device (100).

[0059] Additionally, the accelerator (120) may include a network interface (330). If the accelerator (120) includes a network interface (330), the accelerator (120) may perform the operation of a network card. For example, if the accelerator (120) includes a network interface (330), the first accelerator (121) may directly transmit and receive computational data to and from the second accelerator (122), and the accelerator (120) may transmit and receive computational data to and from external electronic devices (101 to 10n).

[0060] FIG. 4 is a drawing for explaining in detail the operation of an electronic device according to various embodiments of the present disclosure communicating with an accelerator.

[0061] Referring to FIG. 4, the electronic device (100) may include a communication interface (110), at least one accelerator (120), and a memory (130). In FIG. 4, a processor (140) is omitted for convenience of explanation, but the processor (140) may be included in the electronic device (100) to control the operation of the electronic device (100) or to control the operation of each component included in the memory (130).

[0062] According to FIG. 4, the communication interface (110) may include a network card. Additionally, the memory (130) may store an application (410), a communication library (420), a runtime (431, 441) and a driver (432, 442), and an operating system (450) for controlling the operation of the electronic device (100). The processor (140) may transmit information about the acquired accelerator (120) to the communication library (420). The communication library (420) may be implemented as a shared library. For example, the electronic device (100) may compile the communication library (420) into a shared library using a conventional host compiler, and execute the communication library (420) by statically or dynamically linking it to the application when the application is executed.

[0063] The communication library (420) may include a communication algorithm (421), an integration API (422), and integration API implementation software (423). The communication library (420) may operate together with the application (410) on all electronic devices (100, 101 to 10n) within the heterogeneous cluster system (10). The processor (140) may obtain the integration API through the communication algorithm (421).

[0064] When the application (410) is executed, the communication algorithm (421) can obtain the functions included in the integrated API (422) and the order of operation of the functions based on the application (410). For example, the communication algorithm (421) can obtain the functions included in the integrated API (422) for a communication request input from the application (410) and determine the order of operation of the obtained functions.

[0065] The integrated API (422) may include at least one function implemented in a preset format. The integrated API (422) may include at least one function that performs various functions to control the accelerator (120) or the communication interface (110). The at least one function may include functions necessary to perform communication between accelerators (120) regardless of the type of accelerator (120). The integrated API implementation software (423) may implement the integrated API (422) using a runtime API for each accelerator (120).

[0066] The accelerator runtime (431) and accelerator driver (432) are configurations for controlling the accelerator (120). Additionally, the network card runtime (441) and network card driver (442) are configurations for controlling the communication interface (110). For example, the network card runtime (441) and network card driver (442) can control the network card included in the communication interface (110).

[0067] The integrated API (422) may include functions that perform the following functions. For example, function F1(A, X, Y, N) can transfer data from an accelerator (120) included in the electronic device (100) to memory (130). Specifically, function F1(A, X, Y, N) can copy data from memory addresses X to (X+N) of accelerator (120) A to memory (130) addresses Y to (Y+N). In function F1(A, X, Y, N), A represents the index of the accelerator (120), X represents the memory address of accelerator (120) A, Y represents the address of memory (130), and N represents the size of the data to be transferred from the accelerator (120) to memory (130).

[0068] Function F2(X, A, Y, N) can transfer data from memory (130) within the electronic device (100) to the accelerator (120). Specifically, function F2(X, A, Y, N) can copy data located at memory (130) addresses X to (X+N) to memory addresses Y to (Y+N) of accelerator (120) A. In function F2(X, A, Y, N), X represents the memory (130) address, A represents the index of the accelerator (120), Y represents the memory address of accelerator (120) A, and N represents the size of the data to be transferred from memory (130) to the accelerator (120).

[0069] Function F3(A, X, B, Y, N) can transmit data from the first accelerator (121) to the second accelerator (122) within the electronic device (100). Specifically, function F3(A, X, B, Y, N) can copy data located at memory addresses X to (X+N) of the first accelerator (121) A to memory addresses Y to (Y+N) of the second accelerator (122) B. In function F3(A, X, B, Y, N), A represents the index of the first accelerator (121) transmitting data, X represents the memory address of the first accelerator (121) A, B represents the index of the second accelerator (122) receiving data, Y represents the memory address of the second accelerator (122) B, and N represents the size of the data to be transmitted from the first accelerator (121) A to the second accelerator (122) B.

[0070] Function G1(X, C, D, N) can transmit data from memory (130) within an electronic device (100) to an external electronic device (101 to 10n). Specifically, function G1(X, C, D, N) can transmit data located at memory (130) addresses X to (X+N) to network card D of an external electronic device through a communication interface (110) (e.g., network card) C within the electronic device (100). In function G1(X, C, D, N), X represents the memory (130) address, C represents the index of the network card included in the communication interface (110), D represents the index of the network card included in the external electronic device (101 to 10n), and N represents the size of the data to be transmitted from memory (130) to the external electronic device (101 to 10n).

[0071] Function G2(C, D, X, N) can store data received from external electronic devices (101 to 10n) in memory (130). Specifically, function G2(C, D, X, N) can receive data transmitted from network card C of external electronic devices (101 to 10n) through network card D of electronic device (100) and store the received data in memory (130) addresses X to (X+N). In function G2(C, D, X, N), C represents the index of a network card within external electronic devices (101 to 10n), D represents the index of a network card within electronic device (100), X represents the address of memory (130) for storing data, and N represents the size of the data transmitted from external electronic devices (101 to 10n).

[0072] Function G3(A, X, C, D, N) can transmit data from an accelerator (120) within an electronic device (100) to an external electronic device (101 to 10n). Specifically, function G3(A, X, C, D, N) can transmit data located at memory addresses X to (X+N) of accelerator (120) A within the electronic device (100) to network card D of an external electronic device (101 to 10n) via network card C within the electronic device (100). In the function G3(A, X, C, D, N), A represents the index of the accelerator (120) within the electronic device (100), X represents the memory address of the accelerator (120) A, C represents the index of the network card within the electronic device (100), D represents the index of the network card of the external electronic device (101 to 10n), and N represents the size of the data to be transmitted from the accelerator (120) within the electronic device (100) to the external electronic device (101 to 10n).

[0073] Function G4(C, D, A, X, N) can transmit data received from external electronic devices (101 to 10n) to an accelerator (120) within the electronic device (100). Specifically, function G4(C, D, A, X, N) can receive data transmitted from network card C of the external electronic devices (101 to 10n) through network card D of the electronic device (100), and can store the received data in memory addresses X to (X+N) of accelerator A (120) within the electronic device (100). In function G4(C, D, A, X, N), C represents the index of a network card of an external electronic device (101 to 10n), D represents the index of a network card within an electronic device (100), A represents the index of an accelerator (120) within an electronic device (100), X represents the memory address of accelerator (120) A, and N represents the size of data transmitted from an external electronic device (101 to 10n) to an accelerator (120) within an electronic device (100).

[0074] FIGS. 5 to 8 are drawings for explaining the operation of an electronic device acquiring a communication API according to various embodiments of the present disclosure. For example, FIG. 5 is a drawing for explaining the operation of an electronic device (100) acquiring a communication API to perform communication between accelerators (120) when a heterogeneous accelerator (120) is located within the electronic device (100).

[0075] Referring to FIG. 5, when an application is executed, the electronic device (100) can obtain information about an accelerator (120) for executing the application based on the application (S510). The information about the accelerator (120) may include at least one of type information of the accelerator (120), index information of the accelerator (120), memory address of the accelerator (120), and size information of data to be transmitted. For example, when the accelerator (120) includes a first accelerator (121) and a second accelerator (122), the electronic device (100) can obtain index information of the first accelerator (121), memory address of the first accelerator (121), index information of the second accelerator (122), memory address of the second accelerator (122), and size information of data to be transmitted from the first accelerator (121) to the second accelerator (122) through the application.

[0076] The electronic device (100) can identify whether RDMA (Remote Direct Memory Access) is supported between the first accelerator (121) and the second accelerator (122) (S520).

[0077] Remote Direct Memory Access (RDMA) refers to the ability of a computing unit to directly access one memory from another without using an operating system. RDMA enables network adapters (e.g., network cards) to directly transfer data from a wired connection to memory or from memory to a wired connection, without the need to copy data between the operating system's memory and data buffers. This enables high-throughput, low-latency networking, and RDMA can be effectively utilized in environments such as large-scale parallel computer clusters.

[0078] If RDMA is not supported between the first accelerator (121) and the second accelerator (122), the electronic device (100) can set a buffer of size N corresponding to the data size information in memory (130) and store the set buffer address in Z (S531). Additionally, the electronic device (100) can perform communication between the first accelerator (121) and the second accelerator (122) by transmitting data from the first accelerator (121) to the set buffer and transmitting data from the buffer to the second accelerator (122). Specifically, the electronic device (100) can obtain a function F1 (A, X, Z, N) for transmitting data from the first accelerator (121) to memory (130) among the functions included in the integrated API based on the address of the set buffer (S532). Additionally, the electronic device can obtain a function F2 (Z, B, Y, N) for transmitting data from memory (130) to the second accelerator (122) among the functions included in the integrated API (S533).

[0079] In function F1(A, X, Z, N), A represents the index of the first accelerator (121), X represents the memory address of the first accelerator (121) A, Z represents the buffer address set in memory (130), and N represents the size of the data to be transmitted from the first accelerator (121) to the buffer. Additionally, in function F2(Z, B, Y, N), Z represents the buffer address set in memory (130), B represents the index of the second accelerator (122), Y represents the memory address of the second accelerator (122) B, and N represents the size of the data to be transmitted from the buffer to the second accelerator (122).

[0080] If RDMA is supported between the first accelerator (121) and the second accelerator (122), the electronic device (100) can perform communication between the first accelerator (121) and the second accelerator (122) by directly transmitting data from the first accelerator (121) to the second accelerator (122). Specifically, the electronic device (100) can obtain a function F3 (A, X, B, Y, N) for transmitting data from the first accelerator (121) to the second accelerator (122) among the functions included in the integrated API (S540). In the function F3(A, X, B, Y, N), A represents the index of the first accelerator (121) that transmits data, X represents the memory address of the first accelerator (121) A, B represents the index of the second accelerator (122) that receives data, Y represents the memory address of the second accelerator (122) B, and N represents the size of the data to be transmitted from the first accelerator (121) A to the second accelerator (122) B.

[0081] FIG. 6 is a diagram illustrating the operation of an electronic device (100) performing communication between heterogeneous accelerators (120). Specifically, FIG. 6 is a diagram illustrating the operation of an electronic device (100) setting a plurality of buffers in memory and using the plurality of buffers to perform communication between heterogeneous accelerators (120).

[0082] Referring to FIG. 6, if RDMA is not supported between heterogeneous accelerators (120), the electronic device (100) may set up a plurality of buffers corresponding to data size information in memory (130) to perform communication between the accelerators (120). For example, if RDMA is not supported between the first accelerator (121) and the second accelerator (122), the electronic device (100) may set up a first buffer and a second buffer with sizes corresponding to data size information M in memory (130) and store the buffer addresses in Z0 and Z1 (S610).

[0083] The electronic device (100) can obtain a function F1 (A, X, Z0, M) for transmitting data from the first accelerator (121) to the memory (130) among the functions included in the integrated API based on the address of the first buffer set (S620). In the function F1 (A, X, Z0, M), A represents the index of the first accelerator (121), X represents the memory address of A of the first accelerator (121), Z0 represents the address of the first buffer set in the memory (130), and M represents the size of the data to be transmitted from the first accelerator (121) to the first buffer.

[0084] The electronic device (100) can compare the size (N) of the data to be transmitted from the first accelerator (121) to the second accelerator (122) with the size (M) of the set buffer (S630). If the size (N) of the data to be transmitted is less than or equal to the size (M) of the set buffer, the electronic device (100) can obtain function F2 (Z0, B, Y, M) for transmitting data from memory (130) to the second accelerator (122) among the functions included in the integrated API (S641). If the size (N) of the data to be transmitted is less than or equal to the size (M) of the set buffer, all the data to be transmitted can be stored in the set buffer, so the electronic device (100) can transmit the data from memory (130) to the second accelerator (122) at once using function F2 (Z0, B, Y, M) and terminate without performing any further operations.

[0085] However, if the size (N) of the data to be transmitted is larger than the size (M) of the set buffer, the electronic device (100) may obtain, based on the addresses of the set first buffer and second buffer, a function F2 (Z0, B, Y, M) for transmitting data from memory (130) to the second accelerator (122) and a function F1 (A, X+M, Z1, M) for transmitting data from the first accelerator (121) to memory (130) together (S642). In function F2 (Z0, B, Y, M), Z0 represents the address of the first buffer set in memory (130), B represents the index of the second accelerator (122), Y represents the memory address of the second accelerator (122) B, and M represents the size of the data to be transmitted from the first buffer set in memory (130) to the second accelerator (122). In the function F1(A, X+M, Z1, M), A represents the index of the first accelerator (121), X+M represents the memory address of the first accelerator (121) A, Z1 represents the address of the second buffer set in memory (130), and M represents the size of the data to be transmitted from the first accelerator (121) to the second buffer.

[0086] The electronic device (100) can be set to increase the memory address of the first accelerator (121) A from X to X+M, increase the memory address of the second accelerator (122) B from Y to Y+M, and decrease the size N of the data to be transmitted from the first accelerator (121) to the second accelerator (122) to NM (S643). For example, since data transmission from the first accelerator (121) to the second accelerator (122) has been performed for a buffer size M from the initial data N to be transmitted from the first accelerator (121) to the second accelerator (122), the remaining data size to be transmitted can be set to NM.

[0087] Additionally, the electronic device (100) may obtain, based on the addresses of the set first buffer and second buffer, a function F2 (Z1, B, Y, M) for transmitting data from memory (130) to the second accelerator (122) and a function F1 (A, X+M, Z0, M) for transmitting data from the first accelerator (121) to memory (130), among the functions included in the integrated API.

[0088] Referring to FIG. 6, the electronic device (100) can compare the size (N) of the data to be transmitted with the size (M) of the set buffer (S650). In this case, the size (N) of the data to be transmitted may be the size of the data reduced by the buffer size M from the initial data to be transmitted from the first accelerator (121) to the second accelerator (122).

[0089] If the size (N) of the data to be transmitted is less than or equal to the size (M) of the set buffer, the electronic device (100) can obtain function F2 (Z1, B, Y, M) for transmitting data from memory (130) to the second accelerator (122) among the functions included in the integrated API (S661). Since all the data to be transmitted can be stored in the set buffer when the size (N) of the data to be transmitted is less than or equal to the size (M) of the set buffer, the electronic device (100) can transmit all the data from memory (130) to the second accelerator (122) using function F2 (Z1, B, Y, M) and terminate without performing any further operations.

[0090] However, if the size (N) of the data to be transmitted is larger than the size (M) of the set buffer, the electronic device (100) may obtain, based on the addresses of the set first buffer and second buffer, a function F2 (Z1, B, Y, M) for transmitting data from memory (130) to the second accelerator (122) and a function F1 (A, X+M, Z0, M) for transmitting data from the first accelerator (121) to memory (130) together (S662). In function F2 (Z1, B, Y, M), Z1 represents the address of the second buffer set in memory (130), B represents the index of the second accelerator (122), Y represents the memory address of the second accelerator (122) B, and M represents the size of the data to be transmitted from the second buffer set in memory (130) to the second accelerator (122). In the function F1(A, X+M, Z0, M), A represents the index of the first accelerator (121), X+M represents the memory address of the first accelerator (121) A, Z0 represents the address of the first buffer set in memory (130), and M represents the size of the data to be transmitted from the first accelerator (121) to the first buffer.

[0091] The electronic device (100) can be set to increase the memory address of the first accelerator (121) A from X to X+M, increase the memory address of the second accelerator (122) B from Y to Y+M, and decrease the size N of the data to be transmitted from the first accelerator (121) to the second accelerator (122) to NM (S663). For example, the size of the data to be transmitted can be set to NM because data transmission from the first accelerator (121) to the second accelerator (122) has been performed by a buffer size M from the remaining data N to be transmitted from the first accelerator (121) to the second accelerator (122).

[0092] Accordingly, since the initial data N to be transmitted from the first accelerator (121) to the second accelerator (122) is reduced by a buffer size M through steps S642 to S643 and by a buffer size M through steps S662 to S663, the size of the remaining data to be transmitted from the first accelerator (121) to the second accelerator (122) can be the size of the data reduced by 2M from the initial data to be transmitted.

[0093] The electronic device (100) can compare the size (N) of the remaining data to be transmitted from the first accelerator (121) to the second accelerator (122) with the size (M) of the set buffer, and repeat steps S641 through S663 based on the result of the comparison.

[0094] FIGS. 7 and 8 are drawings for explaining the operation of performing communication between heterogeneous accelerators when at least one accelerator for executing an application is located in an external electronic device. For example, FIG. 7 is a drawing for explaining the operation of transmitting data from an accelerator (120) within an electronic device (100) to an external electronic device (101 to 10n) when at least one accelerator for executing an application is located in an external electronic device (101 to 10n).

[0095] Referring to FIG. 7, when an application is executed, the electronic device (100) can obtain information about an accelerator (120) for executing the application based on the application (S710). For example, the electronic device (100) can obtain index information of the accelerator (120), the memory address of the accelerator (120), and information on the size of data to be transmitted from the accelerator (120) to an external electronic device (101 to 10n) through the application. In this case, if at least one accelerator for executing the application is located in the external electronic device (101 to 10n), the electronic device (100) may request information about the index information of the external accelerator and the memory address of the external accelerator from the external electronic device (101 to 10n).

[0096] When at least one accelerator for executing an application is located in an external electronic device (101 to 10n), the electronic device (100) can identify the bandwidth between the accelerator (120) within the electronic device (100) and at least one network card included in the communication interface (110), and can perform communication with the external electronic device using the first network card having the largest bandwidth among the identified bandwidths. For example, when the first accelerator (121) is located in the electronic device (100), the electronic device (100) can obtain information about the first accelerator (121) and the first network card having the largest bandwidth (S720), and can perform communication between the first accelerator (121) and the external electronic device using the first network card having the largest bandwidth.

[0097] The electronic device (100) may obtain information about an external accelerator located within the external electronic device (101 to 10n) and a network card having the largest bandwidth from the external electronic device (101 to 10n) (S730). For example, if an external accelerator for running an application is located in the first external electronic device (101), the electronic device (100) may request information about the external accelerator and a second network card having the largest bandwidth from the first external electronic device (101) and obtain information about the external accelerator and the second network card having the largest bandwidth from the first external electronic device (101).

[0098] In this case, the first external electronic device (101) can identify the bandwidth between the external accelerator and the network card within the first external electronic device (101), and can perform communication between the external accelerator and the electronic device (100) using the second network card having the largest bandwidth among the identified bandwidths.

[0099] When the electronic device (100) identifies the accelerator (120) and the first network card having the largest bandwidth, it can identify whether RDMA is supported between the accelerator (120) and the first network card (S740). If RDMA is not supported between the accelerator (120) and the first network card, the electronic device (100) can set a buffer in memory (130) corresponding to the size information of the data to be transferred from the accelerator (120) to the external electronic device, and store the buffer address in Z (S751). Based on the address of the set buffer, the electronic device (100) can obtain a function F1 (A, X, Z, N) for transferring data from the accelerator (120) to memory (130) among the functions included in the integrated API (S752). Additionally, the electronic device (100) can obtain a function G1 (Z, C, D, N) for transmitting data from memory (130) to an external electronic device (101 to 10n) through a first network card based on the address of a set buffer among the functions included in the integrated API (S753).

[0100] In function F1(A, X, Z, N), A represents the index of the accelerator (120), X represents the memory address of accelerator (120) A, Z represents the address of the buffer set in memory (130), and N represents the size of the data to be transmitted from the accelerator (120) to the buffer. In function G1(Z, C, D, N), Z represents the address of the buffer set in memory (130), C represents the index of the first network card included in the communication interface (110), D represents the index of the second network card included in the external electronic device (101 to 10n), and N represents the size of the data to be transmitted from the buffer of memory (130) to the external electronic device (101 to 10n).

[0101] If RDMA is supported between the accelerator (120) and the first network card, the electronic device (100) can obtain a function G3 (A, X, C, D, N) for transmitting data from the accelerator (120) to the external electronic device (101 to 10n) through the first network card among the functions included in the integrated API (S760). In the function G3 (A, X, C, D, N), A represents the index of the accelerator (120), X represents the memory address of accelerator (120) A, C represents the index of the first network card, D represents the index of the second network card of the external electronic device (101 to 10n), and N represents the size of the data to be transmitted from the accelerator (120) to the external electronic device (101 to 10n).

[0102] FIG. 8 is a diagram illustrating the operation of an electronic device (100) receiving data from an external electronic device (101 to 10n) when at least one accelerator for executing an application is located in an external electronic device (101 to 10n). Specifically, FIG. 8 is a diagram illustrating the operation of an electronic device (100) receiving data from an external electronic device (101 to 10n) and transmitting it to an accelerator (120) within the electronic device (100).

[0103] Referring to FIG. 8, when an application is executed, the electronic device (100) can obtain information about an accelerator (120) for executing the application based on the application (S810). For example, the electronic device (100) can obtain index information of the accelerator (120), memory address of the accelerator (120), and size information of data to be transmitted from the accelerator (120) to an external electronic device (101 to 10n) through the application.

[0104] When at least one accelerator for executing an application is located in an external electronic device (101 to 10n), the electronic device (100) can identify the bandwidth between the accelerator (120) within the electronic device (100) and at least one network card included in the communication interface (110), and obtain information about the first network card having the largest bandwidth among the identified bandwidths (S820).

[0105] The electronic device (100) can obtain information about an external accelerator located within the external electronic device (101 to 10n) and a network card having the largest bandwidth from the external electronic device (101 to 10n). For example, if an external accelerator for running an application is located in the first external electronic device (101), the electronic device (100) can request information about the external accelerator and a second network card having the largest bandwidth from the first external electronic device (101) and obtain information about the external accelerator and the second network card having the largest bandwidth from the first external electronic device (101) (S830).

[0106] When the electronic device (100) identifies the accelerator (120) and the first network card having the largest bandwidth, it can identify whether RDMA is supported between the accelerator (120) and the first network card (S840). If RDMA is not supported between the accelerator (120) and the first network card, the electronic device (100) can set a buffer in memory (130) corresponding to the size information of data to be received from external electronic devices (101 to 10n) to the accelerator (120), and store the buffer address in Z (S851). Based on the address of the set buffer, the electronic device (100) can obtain a function G2 (C, D, Z, N) among the functions included in the integrated API for storing data received from external electronic devices (101 to 10n) in memory (130) (S852). Additionally, the electronic device (100) can obtain a function F2 (Z, A, Y, N) for transmitting data from memory (130) to an accelerator (120) among the functions included in the integrated API based on the address of the set buffer (S853).

[0107] In function G2(C, D, Z, N), C represents the index of the second network card in the external electronic device (101 to 10n), D represents the index of the first network card in the electronic device (100), Z represents the buffer address of the memory (130) for storing data, and N represents the size of the data transmitted from the external electronic device (101 to 10n). Additionally, in function F2(Z, A, Y, N), Z represents the buffer address in the memory (130), A represents the index of the accelerator (120), Y represents the memory address of the accelerator (120) A, and N represents the size of the data to be transmitted from the memory (130) to the accelerator (120).

[0108] If RDMA is supported between the accelerator (120) and the first network card, the electronic device (100) can obtain a function G4 (C, D, A, Y, N) for transmitting data received from an external electronic device (101 to 10n) to the accelerator (120) within the electronic device (100) among the functions included in the integrated API (S860). In the function G4 (C, D, A, Y, N), C represents the index of the second network card of the external electronic device (101 to 10n), D represents the index of the first network card within the electronic device (100), A represents the index of the accelerator (120) within the electronic device (100), Y represents the memory address of the accelerator (120) A, and N represents the size of the data transmitted from the external electronic device (101 to 10n) to the accelerator (120) within the electronic device (100).

[0109] FIG. 9 is a diagram illustrating the operation of an electronic device implementing an integrated API according to various embodiments of the present disclosure. Specifically, FIG. 9 is a diagram illustrating the operation of an electronic device (100) converting an integrated API obtained based on application and accelerator type information into a format corresponding to the accelerator type information.

[0110] In FIG. 9, the left diagram shows the function of the integrated API obtained based on the application, and the right diagram shows the obtained integrated API implemented as a library corresponding to the accelerator type information.

[0111] Referring to FIG. 9, when an electronic device obtains an integrated API based on an application, it obtains type information of an accelerator (120) or network card, and can convert the function of the obtained integrated API into a format corresponding to the type information of the accelerator (120) or network card using integrated API implementation software (423).

[0112] FIGS. 10 to 13 are flowcharts for explaining a method of controlling an electronic device according to various embodiments of the present disclosure. For example, FIG. 10 is a diagram for explaining a method of an electronic device performing communication between heterogeneous accelerators.

[0113] According to FIG. 10, when an application is executed, the electronic device can obtain information about an accelerator for executing the application (S1010). For example, the information about the accelerator may include at least one of the type information of the accelerator, the index information of the accelerator, the memory address of the accelerator, and the size information of data to be transmitted or received by the accelerator. The accelerator may include a GPU (Graphics Processing Unit), an FPGA (Field Programmable Gate Array), a NPU (Neural Processing Unit), etc. The accelerator may also include a dedicated interconnect for performing communication. If the accelerator includes a dedicated interconnect, the electronic device can perform direct communication between accelerators or between the accelerator and a network card.

[0114] The electronic device can obtain functions included in an integrated API implemented in a preset format based on an application and the order of operation of the functions (S1020). Additionally, the electronic device can convert the functions of the acquired integrated API into functions in a format corresponding to the accelerator type information based on the accelerator type information included in the accelerator information (S1030).

[0115] When there are multiple accelerators, they may be implemented of the same type, or they may include accelerators from different manufacturers or of different types. If multiple accelerators are implemented of the same type, communication between them is smooth because software such as drivers and runtimes are compatible; however, if they are implemented of different types, communication between them may be difficult due to software incompatibility. Therefore, an electronic device can obtain functions of an integrated API implemented in a shared library format based on an application, and upon obtaining accelerator type information, convert the obtained functions of the integrated API into functions in a format corresponding to the accelerator type information.

[0116] For example, if the accelerator is of the GPU type of company N, the electronic device can convert the function of the acquired integrated API into the library format of company N. In addition, the electronic device can execute the converted function to communicate with the accelerator (S1040).

[0117] FIG. 11 is a diagram illustrating how an electronic device obtains a function included in an integrated API and the sequence of operations of the function when a heterogeneous accelerator is located within the electronic device.

[0118] According to FIG. 11, if the electronic device includes a first accelerator and a second accelerator, the electronic device can identify whether Remote Direct Memory Access (RDMA) is supported between the first accelerator and the second accelerator (S1110). RDMA can represent a function of directly accessing from one memory to another without using an operating system in the computing device. RDMA allows a network adapter (e.g., a network card) to directly transfer data from the wire to memory or from memory to the wire without the need to copy data between the memory and the data buffer of the operating system.

[0119] If RDMA is not supported between the first accelerator and the second accelerator, the electronic device may set a buffer in the electronic device's memory corresponding to the size information of the data (S1120). Based on the set buffer address, the electronic device may obtain a first function for transferring data from the first accelerator to memory and a second function for transferring data from memory to the second accelerator among the functions included in the integrated API (S1130). For example, the electronic device may obtain a function F1 (A, X, Z, N) for transferring data from the first accelerator to memory and a function F2 (Z, B, Y, N) for transferring data from memory to the second accelerator.

[0120] In function F1(A, X, Z, N), A represents the index of the first accelerator, X represents the memory address of the first accelerator, Z represents the address of the buffer set in memory, and N represents the size of the data to be transmitted from the first accelerator to the buffer. Additionally, in function F2(Z, B, Y, N), Z represents the address of the buffer set in memory, B represents the index of the second accelerator, Y represents the memory address of the second accelerator, and N represents the size of the data to be transmitted from the buffer to the second accelerator.

[0121] In this case, if RDMA is supported between the first accelerator and the second accelerator, the electronic device can perform communication between the first accelerator and the second accelerator by directly transmitting data from the first accelerator to the second accelerator. If RDMA is supported between the first accelerator and the second accelerator, the electronic device can obtain a third function among the functions included in the integrated API for transmitting data from the first accelerator to the second accelerator. For example, the electronic device can obtain a function F3(A, X, B, Y, N) among the functions included in the integrated API for transmitting data from the first accelerator to the second accelerator.

[0122] In the function F3(A, X, B, Y, N), A represents the index of the first accelerator transmitting data, X represents the memory address of the first accelerator, B represents the index of the second accelerator receiving data, Y represents the memory address of the second accelerator, and N represents the size of the data to be transmitted from the first accelerator to the second accelerator.

[0123] FIGS. 12 and 13 are diagrams illustrating a method for an electronic device to obtain a function included in an integrated API and the order of operation of the function when at least one accelerator for executing an application is located in an external electronic device. For example, FIG. 12 is a diagram illustrating a method for transmitting data from an accelerator within an electronic device to an external electronic device when at least one accelerator for executing an application is located in an external electronic device.

[0124] According to FIG. 12, the electronic device can identify a first network card having the largest bandwidth among network cards within the electronic device with respect to the accelerator (S1210). The electronic device can determine the first network card by obtaining a minimum value among the bandwidths of the links of the path connecting the accelerator and each network card, and by identifying the network card corresponding to the largest bandwidth among the obtained minimum bandwidths.

[0125] For example, if network cards A, B, and C are included within an electronic device, the electronic device can obtain a first minimum value, which is the smallest among the bandwidths of the links in the path connecting the accelerator and network card A. Additionally, the electronic device can obtain a second minimum value, which is the smallest among the bandwidths of the links in the path connecting the accelerator and network card B, and a third minimum value, which is the smallest among the bandwidths of the links in the path connecting the accelerator and network card C. Furthermore, the electronic device can determine a first network card by identifying the network card corresponding to the largest value among the first to third minimum values.

[0126] The electronic device can identify whether Remote Direct Memory Access (RDMA) is supported between the accelerator and the first network card (S1220). If RDMA is not supported between the accelerator and the first network card, the electronic device can set a buffer in its memory corresponding to the size information of the data (S1230). For example, if RDMA is not supported between the accelerator and the first network card, the electronic device can set a buffer of size N in its memory corresponding to the size information of the data to be transmitted from the accelerator to an external electronic device, and store the set buffer address in Z.

[0127] Based on a set buffer address, the electronic device may obtain a first function for transmitting data from an accelerator to memory within the electronic device and a fourth function for transmitting data from memory to an external electronic device through a first network card among the functions included in the integrated API (S1240). For example, the electronic device may obtain a function F1 (A, X, Z, N) for transmitting data from an accelerator to memory within the electronic device and a function G1 (Z, C, D, N) for transmitting data from memory to an external electronic device through a first network card.

[0128] In function F1(A, X, Z, N), A represents the index of the accelerator, X represents the memory address of the accelerator, Z represents the buffer address set in the memory of the electronic device, and N represents the size of the data to be transmitted from the accelerator to the buffer. In function G1(Z, C, D, N), Z represents the buffer address set in memory, C represents the index of the first network card, D represents the index of the network card included in the external electronic device, and N represents the size of the data to be transmitted from the buffer in the memory of the electronic device to the external electronic device.

[0129] In this case, if RDMA is supported between the accelerator and the first network card, the electronic device may obtain a fifth function among the functions included in the integrated API for transmitting data from the accelerator to an external electronic device through the first network card. For example, the electronic device may obtain a function G3(A, X, C, D, N) for transmitting data from the accelerator to an external electronic device through the first network card. In the function G3(A, X, C, D, N), A represents the index of the accelerator, X represents the memory address of the accelerator, C represents the index of the first network card, D represents the index of the network card of the external electronic device, and N represents the size of the data to be transmitted from the accelerator to the external electronic device.

[0130] FIG. 13 is a diagram illustrating a method for an electronic device to receive data from an external electronic device when at least one accelerator for running an application is located in an external electronic device.

[0131] According to FIG. 13, the electronic device can identify a first network card having the largest bandwidth among network cards within the electronic device with respect to the accelerator (S1310). The electronic device can determine the first network card by obtaining a minimum value among the bandwidths of the links of the path connecting the accelerator and each network card, and by identifying the network card corresponding to the largest bandwidth among the obtained minimum bandwidths.

[0132] The electronic device can identify whether RDMA is supported between the accelerator and the first network card (S1320). If RDMA is not supported between the accelerator and the first network card, the electronic device can set a buffer in its memory corresponding to the size information of the data (S1330). For example, if RDMA is not supported between the accelerator and the first network card, the electronic device can set a buffer of size N in its memory corresponding to the size information of the data to be received from an external electronic device to the accelerator, and store the set buffer address in Z.

[0133] Based on a set buffer address, the electronic device may obtain a sixth function for storing data received from an external electronic device via a first network card in memory and a second function for transmitting data from memory to an accelerator among the functions included in the integrated API (S1340). For example, the electronic device may obtain a function G2 (C, D, Z, N) for storing data received from an external electronic device via a first network card in memory within the electronic device. Additionally, the electronic device may obtain a function F2 (Z, A, Y, N) for transmitting data from memory within the electronic device to an accelerator.

[0134] In function G2(C, D, Z, N), C represents the index of a network card within an external electronic device, D represents the index of a first network card within an electronic device, Z represents the buffer address of memory for storing data, and N represents the size of data transmitted from the external electronic device. Additionally, in function F2(Z, A, Y, N), Z represents the buffer address within memory, A represents the index of the accelerator, Y represents the memory address of the accelerator, and N represents the size of data to be transmitted from memory to the accelerator.

[0135] In this case, if RDMA is supported between the accelerator and the first network card, the electronic device may obtain a seventh function among the functions included in the integrated API for transmitting data received from an external electronic device through the first network card to the accelerator. For example, if RDMA is supported between the accelerator and the first network card, the electronic device may obtain a function G4(C, D, A, Y, N) for transmitting data received from an external electronic device through the first network card to the accelerator within the electronic device. In function G4(C, D, A, Y, N), C represents the index of the network card of the external electronic device, D represents the index of the first network card within the electronic device, A represents the index of the accelerator within the electronic device, Y represents the memory address of the accelerator, and N represents the size of the data received from the external electronic device to the accelerator within the electronic device.

[0136] As such, the electronic device and the control method according to various embodiments of the present disclosure can perform communication between heterogeneous accelerators. Specifically, the electronic device and the control method according to various embodiments of the present disclosure can smoothly perform communication between accelerators of different manufacturers or accelerators of different types whose drivers and runtimes are incompatible.

[0137] Through this, the electronic device and the control method according to various embodiments of the present disclosure can maximize the utilization of the cluster's computational resources and perform large-scale computations by integrating accelerators from various manufacturers or different types of accelerators in a heterogeneous cluster system.

[0138] Meanwhile, according to the embodiments of the present disclosure, the various embodiments described above may be implemented as software containing instructions stored on a machine-readable storage medium (e.g., a computer). The machine may include an electronic device according to the disclosed embodiments, which is a device capable of calling instructions stored from the storage medium and operating according to the called instructions. When instructions are executed by a processor, the processor may perform a function corresponding to the instructions directly or by using other components under the control of the processor. Instructions may include code generated or executed by a compiler or an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, "non-transitory" means only that the storage medium does not contain a signal and is tangible, and does not distinguish whether data is stored semi-permanently or temporarily in the storage medium.

[0139] Additionally, according to one embodiment of the present disclosure, the method according to the various embodiments described above may be provided by being included in a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)) or an application store (e.g., Play Store). TMIt can be distributed online through ). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created on a storage medium such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0140] Additionally, each component (e.g., module or program) according to the various embodiments described above may be composed of a single or multiple entities, and some of the aforementioned sub-components may be omitted, or other sub-components may be further included in the various embodiments. Generally or additionally, some components (e.g., module or program) may be integrated into a single entity to perform the functions performed by each of the respective components prior to integration in the same or similar manner. The operations performed by the module, program, or other components according to the various embodiments may be executed sequentially, in parallel, iteratively, or heuristically, or at least some operations may be executed in a different order, omitted, or other operations added.

[0141] Although preferred embodiments of the present disclosure have been illustrated and described above, the present disclosure is not limited to the specific embodiments described above. It is understood that various modifications can be made by those skilled in the art without departing from the essence of the present disclosure as claimed in the claims, and such modifications should not be understood individually from the technical spirit or perspective of the present disclosure.

Claims

1. In an electronic device, Communication interface; At least one accelerator for providing computational resources; Memory for storing integrated APIs and instructions, including at least one function implemented in a preset format; and It includes at least one processor; and When the above instructions are executed individually or collectively by the at least one processor, the electronic device, When an application is executed, information about an accelerator for executing the application is obtained, and the information about the accelerator includes type information of the accelerator, and Based on the above application, obtain the functions included in the above integrated API and the order of operation of the functions, and Based on the type information of the accelerator, the function of the integrated API obtained is converted into a function in a format corresponding to the type information of the accelerator, and An electronic device that performs communication with the accelerator by executing the above-described converted function.

2. In Paragraph 1, The information regarding the accelerator further includes information on the size of the data to be transmitted or received by the accelerator, and The above at least one accelerator includes a first accelerator and a second accelerator, and When the above instructions are executed individually or collectively by the at least one processor, the electronic device, Identify whether RDMA (Remote Direct Memory Access) is supported between the first accelerator and the second accelerator, and If RDMA is not supported between the first accelerator and the second accelerator, a buffer corresponding to the size information of the data is set in the memory, and An electronic device that obtains, based on the address of a set buffer, a first function for transferring data from the first accelerator to memory and a second function for transferring data from the memory to the second accelerator among the functions included in the integrated API.

3. In Paragraph 2, When the above instructions are executed individually or collectively by the at least one processor, the electronic device, An electronic device that, when RDMA is supported between the first accelerator and the second accelerator, obtains a third function for transmitting data from the first accelerator to the second accelerator among the functions included in the integrated API.

4. In Paragraph 2, When the above instructions are executed individually or collectively by the at least one processor, the electronic device, If RDMA is not supported between the first accelerator and the second accelerator, a first buffer and a second buffer of a size corresponding to the size information of the data are set in the memory, and An electronic device that, based on the first buffer address and the second buffer address, together obtains a first function for transferring data from the first accelerator to memory and a second function for transferring data from the memory to the second accelerator among the functions included in the integrated API.

5. In Paragraph 1, The information regarding the accelerator further includes information on the size of the data to be transmitted or received by the accelerator, and The above communication interface includes at least one network card for performing communication with an external electronic device, and When the above instructions are executed individually or collectively by the at least one processor, the electronic device, Identifying a first network card having the largest bandwidth with the accelerator among the at least one network card, and Identify whether RDMA is supported between the above accelerator and the first network card, and If RDMA is not supported between the accelerator and the first network card, a buffer corresponding to the size information of the data is set in the memory, and An electronic device that obtains, based on the address of a set buffer, a first function for transmitting data from the accelerator to memory and a fourth function for transmitting data from the memory to an external electronic device through the first network card among the functions included in the integrated API.

6. In Paragraph 5, When the above instructions are executed individually or collectively by the at least one processor, the electronic device, An electronic device that, when RDMA is supported between the accelerator and the first network card, obtains a fifth function among the functions included in the integrated API for transmitting data from the accelerator to the external electronic device through the first network card.

7. In Paragraph 1, The information regarding the accelerator further includes information on the size of the data to be transmitted or received by the accelerator, and When the above instructions are executed individually or collectively by the at least one processor, the electronic device, Identifying a first network card having the largest bandwidth with the accelerator among the at least one network card, and Identify whether RDMA is supported between the above accelerator and the first network card, and If RDMA is not supported between the accelerator and the first network card, a buffer corresponding to the size information of the data is set in the memory, and An electronic device that obtains a sixth function for storing data received from an external electronic device in memory among the functions included in the integrated API based on a set buffer address, and a second function for transmitting data from the memory to the accelerator.

8. In Paragraph 7, When the above instructions are executed individually or collectively by the at least one processor, the electronic device, An electronic device that, when RDMA is supported between the accelerator and the first network card, obtains a seventh function among the functions included in the integrated API for transmitting data received from the external electronic device through the first network card to the accelerator.

9. A method for controlling an electronic device that performs communication between heterogeneous accelerators, When the application is executed, a step of obtaining information about an accelerator for executing the application; A step of obtaining functions included in an integrated API implemented in a preset format based on the above application and the order of operation of the functions; A step of converting a function of an integrated API obtained based on the accelerator type information included in the information regarding the accelerator into a function in a format corresponding to the accelerator type information; and A control method comprising the step of executing the converted function to communicate with the accelerator.

10. In Paragraph 9, The information regarding the accelerator further includes information on the size of the data to be transmitted or received by the accelerator, and The step of obtaining the functions included in the above-mentioned integrated API and the order of operation of the functions is, A step of identifying whether RDMA (Remote Direct Memory Access) is supported between the first accelerator and the second accelerator within the electronic device; If RDMA is not supported between the first accelerator and the second accelerator, the step of setting a buffer corresponding to the size information of the data in the memory of the electronic device; and A control method comprising the step of obtaining, based on a set buffer address, a first function for transferring data from the first accelerator to memory and a second function for transferring data from the memory to the second accelerator among the functions included in the integrated API.

11. In Paragraph 10, The step of obtaining the functions included in the above-mentioned integrated API and the order of operation of the functions is, A control method further comprising the step of obtaining a third function for transmitting data from the first accelerator to the second accelerator among the functions included in the integrated API when RDMA is supported between the first accelerator and the second accelerator.

12. In Paragraph 9, The information regarding the accelerator further includes information on the size of the data to be transmitted or received by the accelerator, and The step of obtaining the functions included in the above-mentioned integrated API and the order of operation of the functions is, A step of identifying a first network card having the largest bandwidth with the accelerator among network cards within the electronic device; A step of identifying whether RDMA is supported between the accelerator and the first network card; If RDMA is not supported between the accelerator and the first network card, the step of setting a buffer corresponding to the size information of the data in the memory of the electronic device; and A control method comprising the step of obtaining, based on a set buffer address, a first function for transmitting data from the accelerator to memory and a fourth function for transmitting data from the memory to an external electronic device through the first network card among the functions included in the integrated API.

13. In Paragraph 12, The step of obtaining the functions included in the above-mentioned integrated API and the order of operation of the functions is, A control method further comprising the step of obtaining a fifth function among the functions included in the integrated API for transmitting data from the accelerator to the external electronic device through the first network card when RDMA is supported between the accelerator and the first network card.

14. In Paragraph 9, The information regarding the accelerator further includes information on the size of the data to be transmitted or received by the accelerator, and The step of obtaining the functions included in the above-mentioned integrated API and the order of operation of the functions is, A step of identifying a first network card having the largest bandwidth with the accelerator among network cards within the electronic device; A step of identifying whether RDMA is supported between the accelerator and the first network card; If RDMA is not supported between the accelerator and the first network card, the step of setting a buffer corresponding to the size information of the data in the memory of the electronic device; and A control method comprising the step of obtaining, based on a set buffer address, a sixth function for storing data received from an external electronic device through the first network card in memory and a second function for transmitting data from the memory to the accelerator among the functions included in the integrated API.

15. In Paragraph 14, The step of obtaining the functions included in the above-mentioned integrated API and the order of operation of the functions is, A control method further comprising the step of obtaining a seventh function among the functions included in the integrated API for transmitting data received from the external electronic device through the first network card to the accelerator when RDMA is supported between the accelerator and the first network card.

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