Doherty amplifier with fast peak activation

Abstract

A Doherty amplifier with fast peak activation is disclosed. In one aspect, a Doherty amplifier uses a main path for primary signal boosting and a peak path when the main path amplifier starts to compress. A compression or saturation detector (238) may be used to detect when to turn on the peak path responsive to the detection of compression by the main path amplifier. To assist in activating the peak path synchronously with the compression, a pre-driver stage (248) with a self-expanding attribute may be provided. Digital control of the pre-driver stage (248) enables the pre-driver to bring the peak amplifier out of class C operation more readily, resulting in faster activation upon compression detection. Synchronous activation of the peak path enables more linear operation and better compliance with relevant wireless standards, thereby improving the end-user experience.

Description

DOHERTY AMPLIFIER WITH FAST PEAK ACTIVATIONPRIORITY APPLICATION

[0001] The present application is related to U.S. Provisional Patent Application Serial No. 63 / 772,922, filed on March 17, 2025, and entitled “DOHERTY AMPLIFIER WITH FAST PEAK ACTIVATION,” the contents of which are incorporated herein by reference in their entiretyBACKGROUNDI. Field of the Disclosure

[0002] The technology of the disclosure relates generally to Doherty amplifiers and, more particularly, to ways in which to improve activation of a peak path within a Doherty amplifier.II. Background

[0003] Computing devices abound in modem society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices mean that mobile communication devices have evolved from simple communication tools into sophisticated mobile entertainment centers, enabling enhanced user experiences. With the advent of the myriad functions available on such devices, there has been increased pressure to develop improved techniques that allow greater amounts of data to be sent through them. This pressure has led to evolving wireless standards that generally support higher frequencies. The use of these higher frequencies has necessitated innovation in the transceivers used to send such wireless signals, including the power amplifiers that boost signals to the desired levels for transmission under the new standards. Changes in the requirements placed on the power amplifiers provides room for innovation.SUMMARY

[0004] Aspects disclosed in the detailed description include Doherty amplifiers with fast peak activation. In particular, a Doherty amplifier uses a main path for primary signal boosting and a peak path when the main path amplifier starts to compress. A compressionor saturation detector may be used to detect when to turn on the peak path responsive to the detection of compression by the main path amplifier. To assist in activating the peak path synchronously with the compression, a pre-driver stage with a self-expanding attribute may be provided. Digital control of the pre-driver stage enables the pre-driver to bring the peak amplifier out of class C operation more readily, resulting in faster activation upon compression detection. Synchronous activation of the peak path enables more linear operation and better compliance with relevant wireless standards, thereby improving the end-user experience.

[0005] In this regard, in one aspect, a Doherty amplifier is disclosed. The Doherty amplifier includes an input node, a main path coupled to the input node, the main path comprising a main amplifier and a saturation detector configured to detect compression in an output signal of the main amplifier, and a summing node coupled to the main amplifier. The Doherty amplifier also includes a peak path coupled to the input node and the summing node, the peak path comprising a peak amplifier configured to provide a peak signal to the summing node for summation with the output signal of the main amplifier, a self-expanding pre-driver amplifier serially positioned between the input node and the peak amplifier, and a bias circuit coupled to the saturation detector and configured to provide a bias signal to the peak amplifier responsive to detected compression in the output signal of the main amplifier.

[0006] In another aspect, a communication device is disclosed. The communication device includes a transceiver configured to provide wireless communication and comprising an amplifier chain comprising a Doherty amplifier comprising an input node, a main path coupled to the input node, the main path comprising a main amplifier and a saturation detector configured to detect compression in an output signal of the main amplifier, and a summing node coupled to the main amplifier. The communication device also includes a peak path coupled to the input node and the summing node, the peak path comprising a peak amplifier configured to provide a peak signal to the summing node for summation with the output signal of the main amplifier, a self-expanding pre-driver amplifier serially positioned between the input node and the peak amplifier, and a bias circuit coupled to the saturation detector and configured to provide a bias signal to the peak amplifier responsive to detected compression in the output signal of the main amplifier.

[0007] In another aspect, a method for using a Doherty amplifier is disclosed. The method includes measuring compression associated with a main path of a main amplifier, responsive to detection of compression at the main amplifier, activating a peak path in the Doherty amplifier, and responsive to an input signal exceeding a threshold, using a selfexpanding pre-driver to ready the peak path for activation.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A is a block diagram of a conventional Doherty amplifier;

[0009] Figure IB is an expanded block diagram of a conventional Doherty amplifier with a saturation detector used to assist in turning on the peak path;

[0010] Figure 1C is a timing diagram showing activation of the main path and the peak path using the Doherty amplifier of Figure IB and the associated lag therebetween resulting from delays in the feedback of the saturation detector;

[0011] Figure 2 is a block diagram of a Doherty amplifier with self-expanding predriver stages added to the main path and peak path to facilitate fast peak path activation according to aspects of the present disclosure;

[0012] Figure 3 is a block diagram of a Doherty amplifier similar to Figure 2, but with an alternate placement for a saturation detector;

[0013] Figure 4 is an expanded block diagram of the Doherty amplifier of Figure 2 with additional details about the pre-driver stage and introducing the possibility of a hybrid amplifier chain using a mix of analog and digital implementations;

[0014] Figure 5 is a block diagram of the Doherty amplifier of Figure 4 with additional details about the digital control of aspects of the different stages;

[0015] Figure 6 is a block diagram of a main path of a Doherty amplifier with a parallel path amplifier used to modify a slope of the main path amplifier;

[0016] Figure 7A is a mixed circuit and block diagram of a bias circuit working with a power amplifier and having a relatively large time constant, which may occur in some implementations of a Doherty amplifier;

[0017] Figure 7B is a mixed circuit and block diagram showing a balanced bias approach, which reduces the time constant of a power amplifier;

[0018] Figure 7C is a mixed circuit and block diagram showing the balanced bias approach of Figure 7B applied to a differential path;

[0019] Figure 8 is a circuit diagram of a Doherty amplifier according to aspects of the present disclosure, with additional details about the bias circuit;

[0020] Figure 9 is a flowchart illustrating an exemplary process for fast activation of a peak path of a Doherty amplifier; and

[0021] Figure 10 is a block diagram of a mobile communication device that may include a Doherty amplifier with fast activation of a peak path, as described herein.DETAILED DESCRIPTION

[0022] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0023] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0024] It will be understood that when an element, such as a layer, region, or substrate, is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, no intervening elements are present. Likewise, it will be understood that when an element, such as a layer, region, or substrate, is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, no intervening elements are present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can bedirectly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected’’ or “directly coupled” to another element, no intervening elements are present.

[0025] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a," “an,” and “the” are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises," “comprising," “includes,” and / or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0028] In keeping with the above admonition regarding definitions, the present disclosure uses the term transceiver in a broad manner. Current industry literature uses “transceiver” in two ways. The first way uses transceiver broadly to refer to a plurality of circuits that send and receive signals. Exemplary circuits may include a baseband processor, an up / down conversion circuit, filters, amplifiers, couplers, and the like coupled to one or more antennas. A second way, used by some authors in the industry literature, treats the circuit positioned between a baseband processor and a power amplifier as a transceiver. This intermediate circuit may include the up / down conversion circuits, mixers, oscillators, filters, and the like, but generally does not include the power amplifiers. As used herein, the term transceiver is used in the first sense. Where relevantto distinguish between the two definitions, the terms “transceiver chain” and “transceiver circuit” are used respectively.

[0029] Additionally, to the extent that the tern “approximately” is used in the claims, it is herein defined to be within five percent (5%).

[0030] Aspects disclosed in the detailed description include Doherty amplifiers with fast peak activation. In particular, a Doherty amplifier uses a main path for primary signal boosting and a peak path when the main path amplifier starts to compress. A compression or saturation detector may be used to detect when to turn on the peak path responsive to the detection of compression by the main path amplifier. To assist in activating the peak path synchronously with the compression, a pre-driver stage with a self-expanding attribute may be provided. Digital control of the pre-driver stage enables the pre-driver to bring the peak amplifier out of class C operation more readily, resulting in faster activation upon compression detection. Synchronous activation of the peak path enables more linear operation and better compliance with relevant wireless standards, thereby improving the end-user experience.

[0031] Before addressing aspects of the present disclosure, a brief overview of a conventional Doherty amplifier is provided with reference to Figures 1A-1C, along with an explanation of how such conventional amplifiers may be inefficient for evolving communication standards. A discussion of aspects of the present disclosure begins below with reference to Figure 2.

[0032] In this regard, Figure 1 A illustrates a block diagram of a conventional Doherty amplifier 100. The Doherty amplifier 100 includes an input node 102 that receives an input signal and splits it into a main path 104 and a peak path 106 at a splitter node 108. The main path 104 includes a main amplifier 110 and a phase shift element 112, which, in most instances, imposes a ninety-degree phase shift to the signal on the main path 104. The peak path 106 includes an initial phase-shift element 114, which, in most instances, imposes a 90-degree phase shift on the signal on the peak path 106. This shifted signal is then selectively amplified by a peak amplifier 116. The signals from the main path 104 and the peak path 106 arc then summed at a summing node 118 and provided to an output node 120.

[0033] In operation, when a signal requires a relatively low gain, only the main path 104 is active. The peak amplifier 116 has negative gain or high impedance at these low-gain levels and does not materially contribute to the sum at the summing node 118.However, when the desired gain exceeds a predetermined level, the peak path 106 is turned on, and the peak amplifier 116 begins to contribute an amplified signal to the summing node 118.

[0034] In practice, the peak path 106 is turned on at the gain level where the main amplifier 110 begins to experience compression and exhibit non-linear behavior. Various schemes have been used over the years for determining when to turn on the peak path 106. One approach is better illustrated by the additional details in Figure IB.

[0035] In this regard, the main amplifier 110 may actually be a multi-stage amplifier with a driver amplifier 110D and an output amplifier 110O. A driver amplifier bias circuit 130 may provide a bias signal to the driver amplifier HOD through a ballast resistor 132. Similarly, an output amplifier bias circuit 134 may provide a bias signal to the output amplifier 110O through a second ballast resistor 136. A saturation detector 138 may be associated with the output amplifier 110O. As illustrated, the saturation detector 138 is coupled to an output of the output amplifier HOO before the phase shift element 112. The saturation detector 138 measures a metric and, from that metric, infers compression of the signal generated by the output amplifier 1100. Based on this detected event, a signal is provided to driver peak bias circuit 140 and / or output peak bias circuit 142. The driver peak bias circuit 140 provides a bias signal to peak driver amplifier 116D through a third ballast resistor 144, and the output peak bias circuit 142 provides a bias signal to peak output amplifier 1160 through a fourth ballast resistor 146. Optionally, the saturation detector 138 may also provide feedback to the driver amplifier bias circuit 130.

[0036] For low- and moderate-bandwidth modulations, the approach shown in Figure IB is adequate. However, more recent wireless standards may have bandwidth modulations above 100 MHz. This corresponds to a time window of a few nanoseconds or less. This becomes relevant because the signal from the saturation detector 138 to a bias circuit 130, 140, 142 may approach a nanosecond or more. Specifically, time delay (Td_satdet) may occur within the saturation detector 138. An additional delay may be present in the line between the saturation detector 138 and the bias circuits 130, 140, 142. Still further delay (Td_bias) exists within the bias circuits (as illustrated this is in the bias circuit 140, but each such bias circuit 130, 140, 142 will have similar delays). Still further delay (Td_bal) exists as a signal propagates across the ballast resistor (e.g., ballast resistor 144). Cumulatively, this delay may, as noted, exceed one nanosecond. This delay meansthat the activation of the peak path 106 is no longer synchronous with the compression detected by the saturation detector 138.

[0037] This delay is shown in Figure 1C, where the contribution of the main path 104 is shown by line 150, and that of the peak path 106 by line 152. The lines 150, 152 should be symmetrical, but as is readily apparent, the line 152 lags the center point of the line 150.

[0038] Exemplary aspects of the present disclosure include a self-expanding predriver stage that begins activating the peak path out of its normal class C just prior to an expected compression point, and then further boosts activation upon receipt of a signal from the saturation detector. This pre-activation helps offset delayed activation and keeps the activation of the peak path closer in time to the compression in the main path.

[0039] In this regard, Figure 2 illustrates a Doherty amplifier 200 with fast peak activation according to aspects of the present disclosure. The Doherty amplifier 200 includes an input node 202 that takes an input signal and splits the signal into a main path 204 and a peak path 206 at the splitter node 108. The main path 204 includes a main amplifier 210 and the phase shift element 112, which, in most instances, imposes a ninetydegree phase shift to the signal on the main path 204. The peak path 206 has the initial phase shift element 114, which in most instances imposes a ninety-degree phase shift to the signal on the peak path 206. This shifted signal is then selectively amplified by a peak amplifier 216. The signals from the main path 204 and the peak path 206 are then summed at a summing node 118 and provided to an output node 220.

[0040] A saturation detector 238 is positioned at an output of the main amplifier 210 and provides signals to the bias circuit 242 and optionally to a threshold feedback circuit 244. As with the Doherty amplifier 100, there may be a main driver amplifier 210D and a main output amplifier 2100, along with a peak driver amplifier 216D and a peak output amplifier 2160. A bias circuit 234 may operate with the main output amplifier 2100 as is well understood.

[0041] Aspects of the present disclosure add a main pre-driver amplifier 246 and a peak pre-driver amplifier 248. Both the pre-driver amplifiers 246, 248 arc self-expanding amplifiers that automatically provide an initial low gain, but after reaching a threshold begin providing a gain according to a predetermined slope. The pre-driver amplifier 246 is optional but may assist in making the operation more linear. Information from the saturation detector 238 may be used by the threshold feedback circuit 244 to adjust athreshold at which the gain begins to be applied. Because this self-expansion is not specifically tied to the compression of the main output amplifier 2100, it effectively serves as an open-loop kick to the Doherty amplifier 200 and allows the peak path 206 to be activated before the delayed compression detection signal.

[0042] Before addressing specifics, it should be appreciated that the saturation detector may be repositioned without departing from the present disclosure. Thus, as illustrated in Figure 3, a saturation detector 300 may be positioned in front of the main output amplifier 2100 in the Doherty amplifier 200’.

[0043] Note that the Doherty amplifier 200 may be split across two (or more) dice. Such splitting may allow differences in technologies to be leveraged. For example, most output amplifiers rely on an analog III-V semiconductor technology, such as gallium arsenide (GaAs), to achieve the desired gain levels. However, the self-expanding amplifiers may be implemented digitally in a complementary metal-oxide-semiconductor (CMOS) technology (e.g., silicon or silicon-on-insulator (Sol)).

[0044] Thus, as illustrated in Figure 4, a first CMOS die 400 may include the predriver amplifiers 246, 248, and replace the initial phase shift element 114 with a programmable phase element 404, while a second GaAs die 402 includes the main amplifier 210 and the peak amplifier 216. Digital to analog converters (DACs) 406(1)-406(N) may receive values from registers (not shown) responsive to a control circuit 408 and may be used to program the phase element 404 to a desired phase adjustment. Likewise, the DACs 406(1 )-406(N) may control the gain, threshold, and slope of the predriver amplifiers 246, 248. That is, the initial gain (low) may be programmed by the DACs 406(1 )-406(N); the threshold at which the gain changes may be programmed, and the slope with which the gain changes may be programmed.

[0045] To further assist in programmability of the pre-driver amplifiers 246, 248, each pre-driver amplifier 246, 248 may have a class-B amplifier and a class-C amplifier that are summed. The control circuit 408 effectively controls when the class-C amplifiers are turned on and the slope steepness using the DACs 406(l)-406(N).

[0046] Additionally, the Doherty amplifier 200, the DACs 406(l)-406(N) may also have values for the thresholds and slopes of the other amplifiers 2160 and 216D as shown by graphs 500( l)-500(3) in Figure 5.

[0047] Note that the pre-driver amplifier 246 may have reached a gain that is undesirably high. To offset this, an additional parallel amplifier 600, illustrated in Figure6, may be subtracted from a primary amplifier 602. Both the primary amplifier 602 and the additional parallel amplifier 600 may be self-expanding and may have different thresholds and / or different slopes, such that the subtraction only takes place for large signals.

[0048] Tangential to the present disclosure, but helpful in providing linear behavior for the Doherty amplifier 200 of the present disclosure, is a realization that is illustrated in Figure 7A. Specifically, when the bias circuit 242 biases the peak output amplifier 2160, the signal goes through a ballast resistor 700 to a base of the peak output amplifier 2160. The base is also coupled to the driver amplifier 216D through a capacitor 702 (Cac). Changes in the bias signal create charging and discharging currents in the capacitor 702. The time constant is a function of the capacitance and the resistance of the ballast resistor 700. In some cases, this time constant may be long enough to reduce efficiency.

[0049] Aspects of the present disclosure solve this problem by balancing the current applied to both sides of the capacitor, as shown in Figure 7B, where the bias circuit 242 provides current on both sides of the capacitor 702 through a bootstrap element 704 (which may be a resistor (illustrated) or an inductor (not shown)). Because of the balanced approach, the capacitor 702 floats with the bias signal and does not charge / discharge, and the time constant is greatly reduced.

[0050] This concept may be extended to a differential Doherty amplifier 750 as shown in Figure 7C. The bias circuit 242 is coupled to the bases of amplifiers 752, 754 through ballast resistors 756, 758, respectively. The ballast resistors 756, 758 are also coupled to coupling capacitors 760, 762, respectively. To provide the balance, the bias circuit is also coupled to the other sides of the coupling capacitors 760, 762 through a transformer 764, and through coils 766, 768 of the transformer 764.

[0051] Figure 8 illustrates additional details about the bias circuit 242 and the saturation detector 238, and how current minors may be used to provide a desired bias responsive to the detected compression. Other circuits could be used.

[0052] Figure 9 is a flowchart of a process 900 for using the Doherty amplifier 200 of the present disclosure. Specifically, an input signal is provided (block 902) at the input node 202. The control circuit 408 detects if the input signal is above a threshold (block 904). If the criteria are not met, the process iterates and continues to measure the input signal. However, when those criteria are met, the control circuit 408 activates the predriver gain for peak path 206 (block 906) using the pre-driver amplifier 248. Thesaturation detector 238 detects compression (block 908) at the output amplifier 2100. Responsive to detecting compression, the peak path 206 is activated with the bias circuit 242 (block 910).

[0053] The Doherty amplifiers with fast peak activation according to aspects disclosed herein may be provided in or integrated into any processor-based device that uses amplifiers. Thus, devices that include transceivers and wireless transceivers in particular are well-suited to incorporate the amplifiers made according to the present disclosure. Examples, without limitation, include a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

[0054] Figure 10 is a schematic diagram of an exemplary communication device 1000 wherein the Doherty amplifiers with fast peak path activation can be provided. Herein, the communication device 1000 can be any type of communication device, such as those listed above as well as access points, base stations (e.g., eNB or gNB), and any other type of wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, Ultra-wideband (UWB), and near field communications.

[0055] More particularly, the communication device 1000 will generally include a control system 1002, a baseband processor 1004, transmit circuitry 1006, receive circuitry 1008, antenna switching circuitry 1010, multiple antennas 1012, and user interface circuitry 1014. In a non-limiting example, the control system 1002 can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In this regard, the control system 1002 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 1008 receives radio frequency signals via the antennas1012 and through the antenna switching circuitry 1010 from one or more base stations. A low noise amplifier, which in theory could be a Doherty amplifier according to aspects of the present disclosure, and a filter of the receive circuitry 1008 cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0056] The baseband processor 1004 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. The baseband processor 1004 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0057] For transmission, the baseband processor 1004 receives digitized data, which may represent voice, data, or control information, from the control system 1002, which it encodes for transmission. The encoded data is output to the transmit circuitry 1006, where a digital-to- analog converter(s) (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier, which can be a Doherty amplifier according to the present disclosure, will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 1012 through the antenna switching circuitry 1010. The multiple antennas 1012 and the replicated transmit and receive circuitries 1006, 1008 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0058] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions,commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0059] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

AMENDED CLAIMSreceived by the International Bureau on 21 July 2026 (21.07.2026)What is claimed is:

1. (Previously Presented) A Doherty amplifier comprising:an input node;a main path coupled to the input node, the main path comprising;a main amplifier comprising a main driver amplifier and a main output amplifier, anda saturation detector configured to detect compression in an output signal of the main amplifier;a summing node coupled to the main amplifier; anda peak path coupled to the input node and the summing node, the peak path comprising:a peak amplifier comprising a peak driver amplifier and a peak output amplifier, the peak amplifier configured to provide a peak signal to the summing node for summation with the output signal of the main amplifier;a self-expanding pre-driver amplifier serially positioned between the input node and the peak amplifier, wherein the self-expanding pre-driver amplifier comprises a first Class-B amplifier and a second Class-C amplifier positioned in parallel and summed such that an initial low gain is provided until a threshold is reached, after which a gain is provided according to a predetermined slope; anda bias circuit coupled to the saturation detector and configured to provide a bias signal to the peak amplifier responsive to detected compression in the output signal of the main amplifier.

2. (Original) The Doherty amplifier of claim 1, wherein the self-expanding predriver amplifier comprises a complementary metal oxide semiconductor (CMOS) amplifier.

3. (Original) The Doherty amplifier of claim 2, wherein the main amplifier comprises a gallium arsenide (GaAs) amplifier.

4. (Original) The Doherty amplifier of claim 1, wherein the saturation detector is positioned between the input node and the main amplifier such that the saturation detector measures an input signal for the main amplifier.

5. (Original) The Doherty amplifier of claim 1, wherein the saturation detector is positioned between the main amplifier and the summing node such that the saturation detector measures the output signal of the main amplifier.

6. (Original) The Doherty amplifier of claim 1, further comprising a main bias circuit coupled to the main amplifier.

7. (Original) The Doherty amplifier of claim 1, wherein the self-expanding predriver amplifier comprises a first Class-B amplifier and a second Class-C amplifier positioned in parallel and summed.

8. (Original) The Doherty amplifier of claim 1, further comprising a digital control circuit configured to set a gain, threshold, and slope for the self-expanding predriver amplifier.

9. (Original) The Doherty amplifier of claim 8, further comprising a digital-to-analog converter (DAC) coupled to the digital control circuit and providing a value to the self-expanding pre-driver amplifier.

10. (Original) The Doherty amplifier of claim 1, further comprising a coupling capacitor associated with the peak amplifier, wherein the bias circuit is coupled to both sides of the coupling capacitor.

11. (Original) The Doherty amplifier of claim 1, wherein the main amplifier is a single-ended amplifier.

12. (Original) The Doherty amplifier of claim 1, wherein the main amplifier is a differential amplifier.

13. (Previously Presented) A communication device comprising:a transceiver configured to provide wireless communication and comprising: an amplifier chain comprising a Doherty amplifier comprising:an input node;a main path coupled to the input node, the main path comprising:a main amplifier comprising a main driver amplifier and a main output amplifier, anda saturation detector configured to detect compression in an output signal of the main amplifier;a summing node coupled to the main amplifier; anda peak path coupled to the input node and the summing node, the peak path comprising:a peak amplifier comprising a peak driver amplifier and a peak output amplifier, the peak amplifier configured to provide a peak signal to the summing node for summation with the output signal of the main amplifier;a self-expanding pre-driver amplifier serially positioned between the input node and the peak amplifier, wherein the self-expanding pre-driver amplifier comprises a first Class-B amplifier and a second Class-C amplifier positioned in parallel and summed such that an initial low gain is provided until a threshold is reached, after which a gain is provided according to a predetermined slope; anda bias circuit coupled to the saturation detector and configured to provide a bias signal to the peak amplifier responsive to detected compression in the output signal of the main amplifier.

14. (Original) The communication device of claim 13 comprising a mobile communication device.

15. (Previously Presented) A method for using a Doherty amplifier comprising:measuring compression associated with a main path of a main amplifier comprising a main driver amplifier and a main output amplifier;responsive to detection of compression at the main amplifier, activating a peak path comprising a peak driver amplifier and a peak output amplifier in the Doherty amplifier; andresponsive to an input signal exceeding a threshold, using a self-expanding predriver to ready the peak path for activation, wherein the self-expanding pre-driver amplifier comprises a first Class-B amplifier and a second Class-C amplifier positioned in parallel and summed such that an initial low gain is provided until a threshold is reached, after which a gain is provided according to a predetermined slope.

16. (Original) The method of claim 15, wherein measuring comprises measuring an output of the main amplifier.

17. (Original) The method of claim 15, wherein measuring comprises measuring an input of the main amplifier.

18. (Original) The method of claim 15, wherein activating the peak path comprises using a bias circuit to bias a peak amplifier.

19. (Original) The method of claim 15, further comprising shifting a signal in the peak path ninety degrees.

20. (Original) The method of claim 15, further comprising summing signals from the peak path and the main path.STATEMENT UNDER ARTICLE 19(1) Claims 1, 13, and 15 are amended.All other claims remain unchanged.The basis for this amendment is claim 7, paragraphs 0039-0041. If you have any questions, please do not hesitate to contact me.

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