Affine bilateral matching merge mode for video coding

Abstract

A method of decoding video data includes generating, for a current block coded in affine mode, a candidate list that includes bi-prediction affine motion information of one or more candidate blocks, refining the bi-prediction affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information, and decoding the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether a BDOF enabling condition is satisfied.

Description

Qualcomm Ref. No. 2503663 WO 1 / 67AFFINE BILATERAL MATCHING MERGE MODE FOR VIDEO CODING

[0001] This application claims priority to U.S. Provisional Patent Application No.63 / 773,935, filed March 18, 2025, the entire content of which is incorporated by reference.TECHNICAL FIELD

[0002] This disclosure relates to video encoding and video decoding.BACKGROUND

[0003] Digital video capabilities can be incorporated into a wide range of devices, including digital televisions, digital direct broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, e-book readers, digital cameras, digital recording devices, digital media players, video gaming devices, video game consoles, cellular or satellite radio telephones, so-called “smart phones,” video teleconferencing devices, video streaming devices, and the like. Digital video devices implement video coding techniques, such as those described in the standards defined by MPEG-2, MPEG-4, ITU-T H.263, ITU-T H.264 / MPEG-4, Part 10, Advanced Video Coding (AVC), ITU-T H.265 / High Efficiency Video Coding (HEVC), ITU-T H.266 / Versatile Video Coding (VVC), and extensions of such standards, as well as proprietary video codecs / formats such as AOMedia Video 1 (AVI) that was developed by the Alliance for Open Media. The video devices may transmit, receive, encode, decode, and / or store digital video information more efficiently by implementing such video coding techniques.

[0004] Video coding techniques include spatial (intra-picture) prediction and / or temporal (inter-picture) prediction to reduce or remove redundancy inherent in video sequences. For block-based video coding, a video slice (e.g., a video picture or a portion of a video picture) may be partitioned into video blocks, which may also be referred to as coding tree units (CTUs), coding units (CUs) and / or coding nodes. Video blocks in an intracoded (I) slice of a picture are encoded using spatial prediction with respect to reference samples in neighboring blocks in the same picture. Video blocks in an inter-coded (P or B) slice of a picture may use spatial prediction with respect to reference samples in neighboring blocks in the same picture or temporal prediction with respect to reference1616-639WO01Qualcomm Ref. No. 2503663 WO 2 / 67samples in other reference pictures. Pictures may be referred to as frames, and reference pictures may be referred to as reference frames.SUMMARY

[0005] In general, this disclosure describes techniques for inter prediction in video codecs, such as for affine motion prediction. In affine mode, control point motion vectors (CPMVs) of a current block are used to determine per-pixel or subblock motion vectors. The per-pixel or subblock motion vectors identify samples that can be used to generate a prediction signal. In addition to affine mode, bidirectional optical flow (BDOF) and motion vector refinement techniques can be used to refine the prediction signal with BDOF and / or to refine the motion vector using the motion vector refinement techniques.

[0006] This disclosure provides example techniques for affine bilateral matching merge mode that allows for selection between per-pixel or subblock affine, potentially with motion vector refinement, and affine BDOF. In affine bilateral matching merge, a merge candidate list stores bi-prediction affine motion information (e.g., motion information of two motion vectors that can be used to generate a bi-prediction signal) of previously encoded or decoded blocks (e.g., candidate blocks). With the example techniques, rather than always defaulting to affine BDOF or per-pixel or subblock affine, a video encoder or video decoder may determine whether certain criteria are satisfied to select affine BDOF or per-pixel or subblock affine. In some examples, a candidate that is used to determine the motion vectors may indicate whether affine BDOF or per-pixel or subblock affine is used.

[0007] In this manner, the example techniques may improve the operation of affine mode encoding and decoding. For instance, with the example techniques, a video encoder and video decoder may generate a prediction signal in affine mode that better estimates the samples in the current block. Accordingly, the residual information (e.g., difference between current block and prediction signal) that is signaled may be reduced, which results in bandwidth efficiencies.

[0008] In one example, this disclosure describes a method of decoding video data, the method comprising generating, for a current block coded in affine mode, a candidate list that includes bi-prediction affine motion information of one or more candidate blocks, refining the bi-prediction affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information, and decoding the current block using the refined affine motion information based on performing per-pixel 1616-639WO01Qualcomm Ref. No. 2503663 WO 3 / 67or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether a BDOF enabling condition is satisfied.

[0009] In one example, this disclosure describes a device for decoding video data, the device comprising one or more memories configured to store the video data, and processing circuitry coupled to the one or more memories, the processing circuitry being configured to generate, for a current block coded in affine mode, a candidate list that includes bi-prediction affine motion information of one or more candidate blocks, refine the bi-prediction affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information, and decode the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether a BDOF enabling condition is satisfied.

[0010] In one example, this disclosure describes a device for encoding video data, the device comprising one or more memories configured to store the video data, and processing circuitry coupled to the one or more memories, the processing circuitry being configured to generate, for a current block coded in affine mode, a candidate list that includes bi-prediction affine motion information of one or more candidate blocks, refine the bi-prediction affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information, and encode the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether a BDOF enabling condition is satisfied.

[0011] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description, drawings, and claims.BRIEF DESCRIPTION OF DRAWINGS

[0012] FIG. 1 is a block diagram illustrating an example video encoding and decoding system that may perform the techniques of this disclosure.

[0013] FIG. 2 is a block diagram illustrating an example video encoder that may perform the techniques of this disclosure.

[0014] FIG. 3 is a block diagram illustrating an example video decoder that may perform the techniques of this disclosure.1616-639WO01Qualcomm Ref. No. 2503663 WO 4 / 67

[0015] FIG. 4 is a flowchart illustrating an example method for encoding a current block in accordance with the techniques of this disclosure.

[0016] FIG. 5 is a flowchart illustrating an example method for decoding a current block in accordance with the techniques of this disclosure.

[0017] FIGS. 6A and 6B are conceptual diagrams illustrating examples for affine mode.

[0018] FIG. 7 is a flowchart illustrating an example method of operation in accordance with one or more examples described in this disclosure.DETAILED DESCRIPTION

[0019] In video coding, a video encoder and a video decoder perform similar operations to determine a prediction signal for a current block. An example video encoding and decoding technique is affine mode. In affine mode, a current block includes a plurality of control point motion vectors (CPMVs), such as motion vectors that extend from comers of the current block. Using the CPMVs and based on the coordinates of samples in the current block, the video encoder and the video decoder may determine per-pixel or subblock motion vectors. Using the motion vectors (per-pixel or subblock), the video encoder and the video decoder may determine a prediction signal for each pixel or each subblock. The prediction signal may be previously encoded or decoded sample values, possibly with additional refinement.

[0020] In affine mode, the video encoder may determine residual information indicative of the difference between the prediction signal and samples in the current block, and signal the residual information. The video decoder may receive the residual information and reconstruct the current block by adding the residual information back to the prediction signal.

[0021] In some examples, the video encoder and the video decoder may determine the CPMVs for the current block or the motion vectors for the pixels or subblocks of the current block based on CPMVs or motion vectors of previously encoded or decoded blocks (e.g., candidate blocks). The video encoder and the video decoder may generate a candidate list (e.g., merge candidate list) that includes motion information (e.g., motion vectors) of one or more candidate blocks. The video encoder may signal an index and the video decoder may receive the index into the candidate list to determine the candidate block whose motion information should be used to determine the motion vectors for the current block.1616-639WO01Qualcomm Ref. No. 2503663 WO 5 / 67

[0022] In one or more examples, the candidate list may store bi-prediction affine motion information. Bi-prediction affine motion information may refer to two motion vectors. For instance, some of the candidate blocks may be encoded or decoded where the prediction signals for these candidate blocks is derived from two different set of samples (e.g., with weighted average) identified using two different motion vectors. These two different motion vectors for the candidate blocks may form the bi-prediction affine motion information for the candidate block.

[0023] There may be further updates to affine coding techniques to improve performance. One example is using bidirectional optical flow (BDOF). In BDOF, the video encoder and the video decoder may refine the bi-prediction signal (e.g., a prediction signal generated from two different set of samples using two different motion vectors) and generate motion refinement. BDOF, such as the motion refinement techniques, may be extended to affine providing for an affine BDOF.

[0024] Another example of improving performance of affine mode is decoder side motion vector refinement (DMVR). In DMVR, the video encoder and the video decoder refine a motion vector to identify samples that better approximate the current block. DMVR may be extended to affine mode for refining the motion vectors used in affine mode providing for affine DMVR.

[0025] In some cases, when an affine merge candidate satisfies the affine DMVR condition (e.g., affine DMVR is available for the candidate block), the candidate block typically also meets the affine BDOF condition (e.g., affine BDOF is available for the candidate block). In some of these cases, BDOF for affine coded block may be performed instead of per-pixel or subblock based affine motion compensation. Per-pixel or subblock based affine motion compensation may mean determining a prediction signal on a pixel-by-pixel basis or subblock-by-subblock basis. That is, motion compensation may refer to the video encoder or the video decoder determining the prediction signal. However, BDOF for affine coded block might not always provide the best prediction signal.

[0026] In accordance with one or more examples, an affine bilateral matching merge mode is described, such that the merge candidate list includes bi-prediction affine motion information for one or more candidate blocks. A video encoder or video decoder may refine (e.g., using affine DMVR) the affine motion information in some examples. Given the affine refined affine motion or even if no refinement, the video encoder or video decoder may apply per-pixel or subblock based motion compensation and affine BDOF is not applied (e.g., independent of whether BDOF enabling condition is satisfied). That 1616-639WO01Qualcomm Ref. No. 2503663 WO 6 / 67is, even if the conditions for when BDOF is to be applied are satisfied, the video encoder and the video decoder may still perform per-pixel or subblock based motion compensation that bypasses BDOF so that per-pixel or subblock based motion compensation that bypasses BDOF is applied independent of whether BDOF enabling condition is satisfied. In some examples, the inverse may be performed such as for the affine refined affine motion or even if no refinement, the video encoder and the video decoder may not apply per-pixel or subblock based motion compensation and apply affine BDOF.

[0027] In some examples, whether per-pixel or subblock based motion compensation is applied or whether affine BDOF is applied may be based on the candidate block that is selected from the candidate list. In some examples, the video encoder and the video decoder may construct multiple candidate lists. If the candidate block is present in more than one candidate list, then the video encoder or the video decoder may select per-pixel or subblock based motion compensation and not affine BDOF, or vice-versa.

[0028] In this way, the example techniques may improve the quality of the prediction signal such that the residual values indicative of the difference between the prediction signal and the current block is smaller (e.g., the values of the prediction signal are approximately the same as the values of the samples of the current block). Since the video encoder signals the residual information (e.g., residual values) and smaller values of residual values tend to require fewer bits, the example techniques may promote efficient bandwidth utilization.

[0029] FIG. 1 is a block diagram illustrating an example video encoding and decoding system 100 that may perform the techniques of this disclosure. The techniques of this disclosure are generally directed to coding (encoding and / or decoding) video data. In general, video data includes any data for processing a video. Thus, video data may include raw, unencoded video, encoded video, decoded (e.g., reconstructed) video, and video metadata, such as signaling data.

[0030] As shown in FIG. 1, system 100 includes a source device 102 that provides encoded video data to be decoded and displayed by a destination device 116, in this example. In particular, source device 102 provides the video data to destination device 116 via a computer-readable medium 110. Source device 102 and destination device 116 may be or include any of a wide range of devices, such as desktop computers, notebook (i.e., laptop) computers, mobile devices, tablet computers, set-top boxes, telephone handsets such as smartphones, televisions, cameras, display devices, digital media players, video gaming consoles, video streaming device, broadcast receiver devices, or 1616-639WO01Qualcomm Ref. No. 2503663 WO 7 / 67the like. In some cases, source device 102 and destination device 116 may be equipped for wireless communication, and thus may be referred to as wireless communication devices.

[0031] In the example of FIG. 1, source device 102 includes video source 104, memory 106, video encoder 200, and output interface 108. Destination device 116 includes input interface 122, video decoder 300, memory 120, and display device 118. In accordance with this disclosure, video encoder 200 of source device 102 and video decoder 300 of destination device 116 may be configured to apply the techniques for affine mode encoding and decoding. Thus, source device 102 represents an example of a video encoding device, while destination device 116 represents an example of a video decoding device. In other examples, a source device and a destination device may include other components or arrangements. For example, source device 102 may receive video data from an external video source, such as an external camera. Likewise, destination device 116 may interface with an external display device, rather than include an integrated display device.

[0032] System 100 as shown in FIG. 1 is merely one example. In general, any digital video encoding and / or decoding device may perform techniques for affine mode encoding and decoding. Source device 102 and destination device 116 are merely examples of such coding devices in which source device 102 generates coded video data for transmission to destination device 116. This disclosure refers to a “coding” device as a device that performs coding (encoding and / or decoding) of data. Thus, video encoder 200 and video decoder 300 represent examples of coding devices, in particular, a video encoder and a video decoder, respectively. In some examples, source device 102 and destination device 116 may operate in a substantially symmetrical manner such that each of source device 102 and destination device 116 includes video encoding and decoding components. Hence, system 100 may support one-way or two-way video transmission between source device 102 and destination device 116, e.g., for video streaming, video playback, video broadcasting, or video telephony.

[0033] In general, video source 104 represents a source of video data (i.e., raw, unencoded video data) and provides a sequential series of pictures (also referred to as “frames”) of the video data to video encoder 200, which encodes data for the pictures. Video source 104 of source device 102 may include a video capture device, such as a video camera, a video archive containing previously captured raw video, and / or a video feed interface to receive video from a video content provider. As a further alternative, video source 104 1616-639WO01Qualcomm Ref. No. 2503663 WO 8 / 67may generate computer graphics-based data as the source video, or a combination of live video, archived video, and computer-generated video. In each case, video encoder 200 encodes the captured, pre-captured, or computer-generated video data. Video encoder 200 may rearrange the pictures from the received order (sometimes referred to as “display order”) into a coding order for coding. Video encoder 200 may generate a bitstream including encoded video data. Source device 102 may then output the encoded video data via output interface 108 onto computer-readable medium 110 for reception and / or retrieval by, e.g., input interface 122 of destination device 116.

[0034] Memory 106 of source device 102 and memory 120 of destination device 116 represent general purpose memories. In some examples, memories 106, 120 may store raw video data, e.g., raw video from video source 104 and raw, decoded video data from video decoder 300. Additionally or alternatively, memories 106, 120 may store software instructions executable by, e.g., video encoder 200 and video decoder 300, respectively. Although memory 106 and memory 120 are shown separately from video encoder 200 and video decoder 300 in this example, it should be understood that video encoder 200 and video decoder 300 may also include internal memories for functionally similar or equivalent purposes. Furthermore, memories 106, 120 may store encoded video data, e.g., output from video encoder 200 and input to video decoder 300. In some examples, portions of memories 106, 120 may be allocated as one or more video buffers, e.g., to store raw, decoded, and / or encoded video data.

[0035] Computer-readable medium 110 may represent any type of medium or device capable of transporting the encoded video data from source device 102 to destination device 116. In one example, computer-readable medium 110 represents a communication medium to enable source device 102 to transmit encoded video data directly to destination device 116 in real-time, e.g., via a radio frequency network or computer-based network. Output interface 108 may modulate a transmission signal including the encoded video data, and input interface 122 may demodulate the received transmission signal, according to a communication standard, such as a wireless communication protocol. The communication medium may include any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network, such as a local area network, a wide-area network, or a global network such as the Internet. The communication medium may include routers, switches, base stations, or any other1616-639WO01Qualcomm Ref. No. 2503663 WO 9 / 67equipment that may be useful to facilitate communication from source device 102 to destination device 116.

[0036] In some examples, source device 102 may output encoded data from output interface 108 to storage device 112. Similarly, destination device 116 may access encoded data from storage device 112 via input interface 122. Storage device 112 may include any of a variety of distributed or locally accessed data storage media such as a hard drive, Blu-ray discs, DVDs, CD-ROMs, flash memory, volatile or non-volatile memory, or any other suitable digital storage media for storing encoded video data.

[0037] In some examples, source device 102 may output encoded video data to file server 114 or another intermediate storage device that may store the encoded video data generated by source device 102. Destination device 116 may access stored video data from file server 114 via streaming or download.

[0038] File server 114 may be any type of server device capable of storing encoded video data and transmitting that encoded video data to the destination device 116. File server 114 may represent a web server (e.g., for a website), a server configured to provide a file transfer protocol service (such as File Transfer Protocol (FTP) or File Delivery over Unidirectional Transport (FLUTE) protocol), a content delivery network (CDN) device, a hypertext transfer protocol (HTTP) server, a Multimedia Broadcast Multicast Service (MBMS) or Enhanced MBMS (eMBMS) server, and / or a network attached storage (NAS) device. File server 114 may, additionally or alternatively, implement one or more HTTP streaming protocols, such as Dynamic Adaptive Streaming over HTTP (DASH), HTTP Live Streaming (HLS), Real Time Streaming Protocol (RTSP), HTTP Dynamic Streaming, or the like.

[0039] Destination device 116 may access encoded video data from file server 114 through any standard data connection, including an Internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., digital subscriber line (DSL), cable modem, etc.), or a combination of both that is suitable for accessing encoded video data stored on file server 114. Input interface 122 may be configured to operate according to any one or more of the various protocols discussed above for retrieving or receiving media data from file server 114, or other such protocols for retrieving media data.

[0040] Output interface 108 and input interface 122 may represent wireless transmitters / receivers, modems, wired networking components (e.g., Ethernet cards), wireless communication components that operate according to any of a variety of IEEE 1616-639WO01Qualcomm Ref. No. 2503663 WO 10 / 67802.11 standards, or other physical components. In examples where output interface 108 and input interface 122 include wireless components, output interface 108 and input interface 122 may be configured to transfer data, such as encoded video data, according to a cellular communication standard, such as 4G, 4G-LTE (Long-Term Evolution), LTE Advanced, 5G, or the like. In some examples where output interface 108 includes a wireless transmitter, output interface 108 and input interface 122 may be configured to transfer data, such as encoded video data, according to other wireless standards, such as an IEEE 802.11 specification, an IEEE 802.15 specification (e.g., ZigBee™), a Bluetooth™ standard, or the like. In some examples, source device 102 and / or destination device 116 may include respective system-on-a-chip (SoC) devices. For example, source device 102 may include an SoC device to perform the functionality attributed to video encoder 200 and / or output interface 108, and destination device 116 may include an SoC device to perform the functionality attributed to video decoder 300 and / or input interface 122.

[0041] The techniques of this disclosure may be applied to video coding in support of any of a variety of multimedia applications, such as over-the-air television broadcasts, cable television transmissions, satellite television transmissions, Internet streaming video transmissions, such as dynamic adaptive streaming over HTTP (DASH), digital video that is encoded onto a data storage medium, decoding of digital video stored on a data storage medium, or other applications.

[0042] Input interface 122 of destination device 116 receives an encoded video bitstream from computer-readable medium 110 (e.g., a communication medium, storage device 112, file server 114, or the like). The encoded video bitstream may include signaling information defined by video encoder 200, which is also used by video decoder 300, such as syntax elements having values that describe characteristics and / or processing of video blocks or other coded units (e.g., slices, pictures, groups of pictures, sequences, or the like). Display device 118 displays decoded pictures of the decoded video data to a user. Display device 118 may represent any of a variety of display devices such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

[0043] Although not shown in FIG. 1, in some examples, video encoder 200 and video decoder 300 may each be integrated with an audio encoder and / or audio decoder (e.g., audio codec), and may include appropriate MUX-DEMUX units, or other hardware and / or software, to handle multiplexed streams including both audio and video in a 1616-639WO01Qualcomm Ref. No. 2503663 WO 11 / 67common data stream. Example audio codecs may include AAC, AC-3, AC-4, ALAC, ALS, AMBE, AMR, AMR-WB (G.722.2), AMR-WB+, aptx (various versions), ATRAC, BroadVoice (BV16, BV32), CELT, Enhanced AC-3 (E-AC-3), EVS, FLAC, G.711, G.722, G.722.1, G.722.2 (AMR-WB). G.723.1, G.726, G.728, G.729, G.729.1, GSM-FR, HE-AAC, iLBC, iSAC, LA Lyra, Monkey's Audio, MP1, MP2 (MPEG-1, 2 Audio Layer II), MP3, Musepack, Nellymoser Asao, OptimFROG, Opus, Sac, Satin, SBC, SILK, Siren 7, Speex, SVOPC, True Audio (TTA), TwinVQ, USAC, Vorbis (Ogg), WavPack, and Windows Media Audio.

[0044] Video encoder 200 and video decoder 300 each may be implemented as any of a variety of suitable encoder and / or decoder circuitry that includes a processing system, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware or any combinations thereof. When the techniques are implemented partially in software, a device may store instructions for the software in a suitable, non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Each of video encoder 200 and video decoder 300 may be included in one or more encoders or decoders, either of which may be integrated as part of a combined encoder / decoder (CODEC) in a respective device. A device including video encoder 200 and / or video decoder 300 may implement video encoder 200 and / or video decoder 300 in processing circuitry such as an integrated circuit and / or a microprocessor. Such a device may be a wireless communication device, such as a cellular telephone, or any other type of device described herein.

[0045] Video encoder 200 and video decoder 300 may operate according to a video coding standard, such as ITU-T H.265, also referred to as High Efficiency Video Coding (HEVC) or extensions thereto, such as the multi-view and / or scalable video coding extensions. Alternatively, video encoder 200 and video decoder 300 may operate according to other proprietary or industry standards, such as ITU-T H.266, also referred to as Versatile Video Coding (VVC). In other examples, video encoder 200 and video decoder 300 may operate according to a proprietary video codec / format, such as AOMedia Video 1 (AVI), extensions of AVI, and / or successor versions of AVI (e.g., AV2). In other examples, video encoder 200 and video decoder 300 may operate according to other proprietary formats or industry standards. The techniques of this disclosure, however, are not limited to any particular coding standard or format. In 1616-639WO01Qualcomm Ref. No. 2503663 WO 12 / 67general, video encoder 200 and video decoder 300 may be configured to perform the techniques of this disclosure in conjunction with any video coding techniques that use affine mode.

[0046] In general, video encoder 200 and video decoder 300 may perform block-based coding of pictures. The term “block” generally refers to a structure including data to be processed (e.g., encoded, decoded, or otherwise used in the encoding and / or decoding process). For example, a block may include a two-dimensional matrix of samples of luminance and / or chrominance data. In general, video encoder 200 and video decoder 300 may code video data represented in a YUV (e.g., Y, Cb, Cr) format. That is, rather than coding red, green, and blue (RGB) data for samples of a picture, video encoder 200 and video decoder 300 may code luminance and chrominance components, where the chrominance components may include both red hue and blue hue chrominance components. In some examples, video encoder 200 converts received RGB formatted data to a YUV representation prior to encoding, and video decoder 300 converts the YUV representation to the RGB format. Alternatively, pre- and post-processing units (not shown) may perform these conversions.

[0047] This disclosure may generally refer to coding (e.g., encoding and decoding) of pictures to include the process of encoding or decoding data of the picture. Similarly, this disclosure may refer to coding of blocks of a picture to include the process of encoding or decoding data for the blocks, e.g., prediction and / or residual coding. An encoded video bitstream generally includes a series of values for syntax elements representative of coding decisions (e.g., coding modes) and partitioning of pictures into blocks. Thus, references to coding a picture or a block should generally be understood as coding values for syntax elements forming the picture or block.

[0048] HEVC defines various blocks, including coding units (CUs), prediction units (PUs), and transform units (TUs). According to HEVC, a video coder (such as video encoder 200) partitions a coding tree unit (CTU) into CUs according to a quadtree structure. That is, the video coder partitions CTUs and CUs into four equal, nonoverlapping squares, and each node of the quadtree has either zero or four child nodes. Nodes without child nodes may be referred to as “leaf nodes,” and CUs of such leaf nodes may include one or more PUs and / or one or more TUs. The video coder may further partition PUs and TUs. For example, in HEVC, a residual quadtree (RQT) represents partitioning of TUs. In HEVC, PUs represent inter-prediction data, while TUs represent1616-639WO01Qualcomm Ref. No. 2503663 WO 13 / 67residual data. CUs that are intra-predicted include intra-prediction information, such as an intra-mode indication.

[0049] As another example, video encoder 200 and video decoder 300 may be configured to operate according to VVC. According to VVC, a video coder (such as video encoder 200) partitions a picture into a plurality of CTUs. Video encoder 200 may partition a CTU according to a tree structure, such as a quadtree-binary tree (QTBT) structure or Multi-Type Tree (MTT) structure. The QTBT structure removes the concepts of multiple partition types, such as the separation between CUs, PUs, and TUs of HEVC. A QTBT structure includes two levels: a first level partitioned according to quadtree partitioning, and a second level partitioned according to binary tree partitioning. A root node of the QTBT structure corresponds to a CTU. Leaf nodes of the binary trees correspond to CUs.

[0050] In an MTT partitioning structure, blocks may be partitioned using a quadtree (QT) partition, a binary tree (BT) partition, and one or more types of triple tree (TT) (also called ternary tree (TT)) partitions. A triple or ternary tree partition is a partition where a block is split into three subblocks. In some examples, a triple or ternary tree partition divides a block into three subblocks without dividing the original block through the center. The partitioning types in MTT (e.g., QT, BT, and TT), may be symmetrical or asymmetrical.

[0051] When operating according to the AVI codec, video encoder 200 and video decoder 300 may be configured to code video data in blocks. In AVI, the largest coding block that can be processed is called a superblock. In AVI, a superblock can be either 128x128 luma samples or 64x64 luma samples. However, in successor video coding formats (e.g., AV2), a superblock may be defined by different (e.g., larger) luma sample sizes. In some examples, a superblock is the top level of a block quadtree. Video encoder 200 may further partition a superblock into smaller coding blocks. Video encoder 200 may partition a superblock and other coding blocks into smaller blocks using square or nonsquare partitioning. Non-square blocks may include N / 2xN, NxN / 2, N / 4xN, and NxN / 4 blocks. Video encoder 200 and video decoder 300 may perform separate prediction and transform processes on each of the coding blocks.

[0052] AVI also defines a tile of video data. A tile is a rectangular array of superblocks that may be coded independently of other tiles. That is, video encoder 200 and video decoder 300 may encode and decode, respectively, coding blocks within a tile without using video data from other tiles. However, video encoder 200 and video decoder 300 may perform filtering across tile boundaries. Tiles may be uniform or non-uniform in1616-639WO01Qualcomm Ref. No. 2503663 WO 14 / 67size. Tile-based coding may enable parallel processing and / or multi-threading for encoder and decoder implementations.

[0053] In some examples, video encoder 200 and video decoder 300 may use a single QTBT or MTT structure to represent each of the luminance and chrominance components, while in other examples, video encoder 200 and video decoder 300 may use two or more QTBT or MTT structures, such as one QTBT / MTT structure for the luminance component and another QTBT / MTT structure for both chrominance components (or two QTBT / MTT structures for respective chrominance components). Video encoder 200 and video decoder 300 may be configured to use quadtree partitioning, QTBT partitioning, MTT partitioning, superblock partitioning, or other partitioning structures.

[0054] In some examples, a CTU includes a coding tree block (CTB) of luma samples, two corresponding CTBs of chroma samples of a picture that has three sample arrays, or a CTB of samples of a monochrome picture or a picture that is coded using three separate color planes and syntax structures used to code the samples. A CTB may be an NxN block of samples for some value of N such that the division of a component into CTBs is a partitioning. A component is an array or single sample from one of the three arrays (luma and two chroma) that compose a picture in 4:2:0, 4:2:2, or 4:4:4 color format or the array or a single sample of the array that compose a picture in monochrome format. In some examples, a coding block is an MxN block of samples for some values of M and N such that a division of a CTB into coding blocks is a partitioning.

[0055] The blocks (e.g., CTUs or CUs) may be grouped in various ways in a picture. As one example, a brick may refer to a rectangular region of CTU rows within a particular tile in a picture. A tile may be a rectangular region of CTUs within a particular tile column and a particular tile row in a picture. A tile column refers to a rectangular region of CTUs having a height equal to the height of the picture and a width specified by syntax elements (e.g., such as in a picture parameter set). A tile row refers to a rectangular region of CTUs having a height specified by syntax elements (e.g., such as in a picture parameter set) and a width equal to the width of the picture.

[0056] In some examples, a tile may be partitioned into multiple bricks, each of which may include one or more CTU rows within the tile. A tile that is not partitioned into multiple bricks may also be referred to as a brick. However, a brick that is a true subset of a tile may not be referred to as a tile. The bricks in a picture may also be arranged in a slice. A slice may be an integer number of bricks of a picture that may be exclusively 1616-639WO01Qualcomm Ref. No. 2503663 WO 15 / 67contained in a single network abstraction layer (NAL) unit. In some examples, a slice includes either a number of complete tiles or only a consecutive sequence of complete bricks of one tile.

[0057] This disclosure may use “NxN” and “N by N” interchangeably to refer to the sample dimensions of a block (such as a CU or other video block) in terms of vertical and horizontal dimensions, e.g., 16x16 samples or 16 by 16 samples. In general, a 16x16 CU will have 16 samples in a vertical direction (y = 16) and 16 samples in a horizontal direction (x = 16). Likewise, an NxN CU generally has N samples in a vertical direction and N samples in a horizontal direction, where N represents a nonnegative integer value. The samples in a CU may be arranged in rows and columns. Moreover, CUs need not necessarily have the same number of samples in the horizontal direction as in the vertical direction. For example, CUs may include NxM samples, where M is not necessarily equal toN.

[0058] Video encoder 200 encodes video data for CUs representing prediction and / or residual information, and other information. The prediction information indicates how the CU is to be predicted in order to form a prediction block for the CU. The residual information generally represents sample-by-sample differences between samples of the CU prior to encoding and the prediction block.

[0059] To predict a CU, video encoder 200 may generally form a prediction block for the CU through inter-prediction or intra-prediction. Inter-prediction generally refers to predicting the CU from data of a previously coded picture, whereas intra-prediction generally refers to predicting the CU from previously coded data of the same picture. To perform inter-prediction, video encoder 200 may generate the prediction block using one or more motion vectors. Video encoder 200 may generally perform a motion search to identify a reference block that closely matches the CU, e.g., in terms of differences between the CU and the reference block. Video encoder 200 may calculate a difference metric using a sum of absolute difference (SAD), sum of squared differences (SSD), mean absolute difference (MAD), mean squared differences (MSD), or other such difference calculations to determine whether a reference block closely matches the current CU. In some examples, video encoder 200 may predict the current CU using uni-directional prediction or bidirectional prediction.

[0060] Some examples of VVC also provide an affine motion compensation mode, which may be considered an inter-prediction mode. In affine motion compensation mode, video encoder 200 may determine two or more motion vectors that represent non-translational 1616-639WO01Qualcomm Ref. No. 2503663 WO 16 / 67motion, such as zoom in or out, rotation, perspective motion, or other irregular motion types.

[0061] To perform intra-prediction, video encoder 200 may select an intra-prediction mode to generate the prediction block. Some examples of VVC provide sixty-seven intraprediction modes, including various directional modes, as well as planar mode and DC mode. In general, video encoder 200 selects an intra-prediction mode that describes neighboring samples to a current block (e.g., a block of a CU) from which to predict samples of the current block. Such samples may generally be above, above and to the left, or to the left of the current block in the same picture as the current block, assuming video encoder 200 codes CTUs and CUs in raster scan order (left to right, top to bottom).

[0062] Video encoder 200 encodes data representing the prediction mode for a current block. For example, for inter-prediction modes, video encoder 200 may encode data representing which of the various available inter-prediction modes is used, as well as motion information for the corresponding mode. For uni-directional or bidirectional inter-prediction, for example, video encoder 200 may encode motion vectors using advanced motion vector prediction (AMVP) or merge mode. Video encoder 200 may use similar modes to encode motion vectors for affine motion compensation mode.

[0063] AVI includes two general techniques for encoding and decoding a coding block of video data. The two general techniques are intra prediction (e.g., intra frame prediction or spatial prediction) and inter prediction (e.g., inter frame prediction or temporal prediction). In the context of AVI, when predicting blocks of a current frame of video data using an intra prediction mode, video encoder 200 and video decoder 300 do not use video data from other frames of video data. For most intra prediction modes, video encoder 200 encodes blocks of a current frame based on the difference between sample values in the current block and predicted values generated from reference samples in the same frame. Video encoder 200 determines predicted values generated from the reference samples based on the intra prediction mode.

[0064] Following prediction, such as intra-prediction or inter-prediction of a block, video encoder 200 may calculate residual data for the block. The residual data, such as a residual block, represents sample by sample differences between the block and a prediction block for the block, formed using the corresponding prediction mode. Video encoder 200 may apply one or more transforms to the residual block, to produce transformed data in a transform domain instead of the sample domain. For example, video encoder 200 may apply a discrete cosine transform (DCT), an integer transform, a wavelet 1616-639WO01Qualcomm Ref. No. 2503663 WO 17 / 67transform, or a conceptually similar transform to residual video data. Additionally, video encoder 200 may apply a secondary transform following the first transform, such as a mode-dependent non-separable secondary transform (MDNSST), a signal dependent transform, a Karhunen-Loeve transform (KLT), or the like. Video encoder 200 produces transform coefficients following application of the one or more transforms.

[0065] As noted above, following any transforms to produce transform coefficients, video encoder 200 may perform quantization of the transform coefficients. Quantization generally refers to a process in which transform coefficients are quantized to possibly reduce the amount of data used to represent the transform coefficients, providing further compression. By performing the quantization process, video encoder 200 may reduce the bit depth associated with some or all of the transform coefficients. For example, video encoder 200 may round an zz-bit value down to an m-bit value during quantization, where n is greater than m. In some examples, to perform quantization, video encoder 200 may perform a bitwise right-shift of the value to be quantized.

[0066] Following quantization, video encoder 200 may scan the transform coefficients, producing a one-dimensional vector from the two-dimensional matrix including the quantized transform coefficients. The scan may be designed to place higher energy (and therefore lower frequency) transform coefficients at the front of the vector and to place lower energy (and therefore higher frequency) transform coefficients at the back of the vector. In some examples, video encoder 200 may utilize a predefined scan order to scan the quantized transform coefficients to produce a serialized vector, and then entropy encode the quantized transform coefficients of the vector. In other examples, video encoder 200 may perform an adaptive scan. After scanning the quantized transform coefficients to form the one-dimensional vector, video encoder 200 may entropy encode the one-dimensional vector, e.g., according to context-adaptive binary arithmetic coding (CABAC). Video encoder 200 may also entropy encode values for syntax elements describing metadata associated with the encoded video data for use by video decoder 300 in decoding the video data.

[0067] To perform CABAC, video encoder 200 may assign a context within a context model to a symbol to be transmitted. The context may relate to, for example, whether neighboring values of the symbol are zero-valued or not. The probability determination may be based on a context assigned to the symbol.

[0068] Video encoder 200 may further generate syntax data, such as block-based syntax data, picture-based syntax data, and sequence-based syntax data, to video decoder 300, 1616-639WO01Qualcomm Ref. No. 2503663 WO 18 / 67e.g., in a picture header, a block header, a slice header, or other syntax data, such as a sequence parameter set (SPS), picture parameter set (PPS), or video parameter set (VPS). Video decoder 300 may likewise decode such syntax data to determine how to decode corresponding video data.

[0069] In this manner, video encoder 200 may generate a bitstream including encoded video data, e.g., syntax elements describing partitioning of a picture into blocks (e.g., CUs) and prediction and / or residual information for the blocks. Ultimately, video decoder 300 may receive the bitstream and decode the encoded video data.

[0070] In general, video decoder 300 performs a reciprocal process to that performed by video encoder 200 to decode the encoded video data of the bitstream. For example, video decoder 300 may decode values for syntax elements of the bitstream using CAB AC in a manner substantially similar to, albeit reciprocal to, the CABAC encoding process of video encoder 200. The syntax elements may define partitioning information for partitioning of a picture into CTUs, and partitioning of each CTU according to a corresponding partition structure, such as a QTBT structure, to define CUs of the CTU. The syntax elements may further define prediction and residual information for blocks (e.g., CUs) of video data.

[0071] The residual information may be represented by, for example, quantized transform coefficients. Video decoder 300 may inverse quantize and inverse transform the quantized transform coefficients of a block to reproduce a residual block for the block. Video decoder 300 uses a signaled prediction mode (intra- or inter-prediction) and related prediction information (e.g., motion information for inter-prediction) to form a prediction block for the block. Video decoder 300 may then combine the prediction block and the residual block (on a sample-by-sample basis) to reproduce the original block. Video decoder 300 may perform additional processing, such as performing a deblocking process to reduce visual artifacts along boundaries of the block.

[0072] Any of the video encoding or video decoding processes described above may be performed using a neural network (NN). Additionally or alternatively, a neural network may be trained to efficiently compress video data without necessarily separately performing prediction and residual coding. Studies have shown that embedding neural networks into the hybrid video coding framework of video encoder 200 and video decoder 300 can improve compression efficiency. Neural networks may be used for intra prediction and inter prediction to improve the prediction efficiency. NN-based in-loop filtering and / or post-filtering have also performed well in heuristic testing.1616-639WO01Qualcomm Ref. No. 2503663 WO 19 / 67

[0073] For example, video encoder 200 and video decoder may use one or more NN-based filters for existing filters, such as deblocking filters, sample adaptive offset (SAO), and / or adaptive loop filtering (ALF). NN-based filters can also be applied exclusively, where NN-based filters are designed to replace all of the existing filters. Additionally or alternatively, NN-based filters may be designed to supplement, enhance, or replace any or all of the other filters.

[0074] In some examples, an NN-based filter may be a convolutional neural network (CNN)-based filter with multiple layers. An NN-based filtering process may take reconstructed samples as inputs, and may add the intermediate outputs back to the inputs to refine the input samples. The NN-based filter may use all color components (e.g., Y, U, and V, or Y, Cb, and Cr) as inputs 172 to exploit cross-component correlations. Different color components may share the same filters (including network structure and model parameters) or each component may have its own specific filters.

[0075] The filtering process can also be generalized as follows:7?'(i,j)=^(bj) + NN_filter_residual_output R')

[0076] Here, R(i, j) represents a reconstructed sample at position (i, j) in the picture, R’(i, j) represents the filtered version of the reconstructed sample, and NN filter residual output(R) represents the intermediate samples discussed above that are calculated by the NN filter. The model structure and model parameters of NN-based filter(s) can be pre-defined and be stored at video encoder 200 and video decoder 300. The filters can also be signaled in the bitstream.

[0077] In some examples, an NN-based filter may include a series of feature extraction layers, followed by an output convolution. The feature extraction layers may include a 3x3 convolution (conv) layer followed by a parametric rectified linear unit (PReLU) layer. The convolutional layer applies a convolution operation to the input data, which involves a filter or kernel processing the input data (e.g., the reconstruction samples) in a sliding window fashion and computing dot products at each position. The convolution operation essentially captures local patterns within the input data. For example, in the context of image processing, these patterns could be edges, textures, or other visual features. The filter or kernel is a small matrix of weights that gets updated during the training process. By sliding this filter across the input data (or feature map from a previous layer) and computing the dot product at each position, the convolutional layer creates a feature map that encodes spatial hierarchies and patterns detected in the input. The output of a convolutional layer is a set of feature maps, each corresponding to 1616-639WO01Qualcomm Ref. No. 2503663 WO 20 / 67one filter, capturing different aspects of the input data. This layer helps the neural network to learn increasingly complex and abstract features as the data passes through deeper layers of the network.

[0078] The PReLU layer is an activation function used in neural networks, and is a variant of the ReLU (Rectified Linear Unit) activation function. As described above, the convolution layer outputs feature maps, each corresponding to one filter, representing detected features in the input. Following the convolution layer, the PReLU layer applies the PReLU activation function to each element of the feature maps produced by the convolution layer. For positive values, the PReLU layer acts like a standard ReLU, passing the value through. For negative values, instead of setting them to zero (e.g., as ReLU does), the PReLU layer allows a small, linear, negative output. This keeps neurons of the NN active and maintains the gradient flow, which can be beneficial for learning in deep networks.

[0079] When NN-based filtering is applied in video coding, the whole video signal (pixel data) may be split into multiple processing units (e.g., 2D blocks), and each processing unit can be processed separately or be combined with other information associated with this block of pixels. For example, a processing unit may be a frame, a slice / tile, a CTU, or any pre-defined or signaled shapes and sizes. Typically, NN-based filtering is performed on reconstructed blocks of video data. Here, reconstructed blocks and samples may refer to both decoded blocks produced by video decoder 300, as well blocks reconstructed in a reconstruction loop of video encoder 200.

[0080] To further improve the performance of NN-based filtering, different types of input data can be processed jointly to produce the filtered output. Input data may include, but is not limited to, reconstruction pixels / samples, prediction pixels / samples, pixels / samples after the loop filter(s), partitioning structure information, deblocking parameters (e.g., boundary strength (BS)), quantization parameter (QP) values, slice or picture types, or a filters applicability or coding modes map. Input data can be provided at different granularities. Luma reconstruction and prediction samples may be provided at the original resolution, whereas chroma samples may be provided at lower resolution, e.g. for 4:2:0 representation, or can be up-sampled to the Luma resolution to achieve per-pixel representation. Similarly, QP, BS, partitioning, or coding mode information can be provided at lower resolution, including cases with a single value per frame, slice or processing block (e.g. QP). In other examples, QP, BS, partitioning, or coding mode information can be expanded (e.g., replicated) to achieve per-pixel / sample representation.1616-639WO01Qualcomm Ref. No. 2503663 WO 21 / 67

[0081] To further improve the performance of NN-based filtering, multi-mode solutions can be used. For example, for each processing unit, video encoder 200 may select a mode from a set of modes based on rate-distortion optimization and signal the selected mode in the bit-stream. The different modes may include different NN models, different values that may be used as the input information of the NN models, etc. In one example, video encoder 200 and video decoder 300 may use an NN-based filtering solution with multiple modes based on a single NN model by using different QP values as input to the NN model for different modes.

[0082] This disclosure may generally refer to “signaling” certain information, such as syntax elements. The term “signaling” may generally refer to the communication of values for syntax elements and / or other data used to decode encoded video data. That is, video encoder 200 may signal values for syntax elements in the bitstream. In general, signaling refers to generating a value in the bitstream. As noted above, source device 102 may transport the bitstream to destination device 116 substantially in real time, or not in real time, such as might occur when storing syntax elements to storage device 112 for later retrieval by destination device 116.

[0083] In accordance with the techniques of this disclosure, video encoder 200 and video decoder 300 may encode and decode a current block using affine bilateral matching merge mode. As described in more detail, video encoder 200 and video decoder 300 may generate a candidate list that includes bi-prediction affine motion information of one or more candidate blocks, and encode or decode a current block based on affine motion information for at least a candidate block of the one or more candidate blocks. In some examples, motion vector refinement techniques may be used. In some examples, video encoder 200 and video decoder 300 may select between performing per-pixel or subblock based motion compensation to the current block in affine mode or performing affine bidirectional optical flow (BDOF) in affine mode.

[0084] The following describes affine motion model. An affine motion model can be described as, in equation 1 :vx= ax + by + evy= ex + dy + f

[0085] In the above equation, (vx, vy) is the motion vector at the coordinate (x,y), and a, b, c, d, e, and f are the six parameters. This affine motion model is referred to as 6-parameters affine motion model. In a typical video coder, a picture is partitioned into blocks for block-based coding. The affine motion model for a block can also be described 1616-639WO01Qualcomm Ref. No. 2503663 WO 22 / 67by the 3 motion vectors (MVs) v0= (vOx,vOy), vx= (vlx,vly), and v2= (v2x,v2y) at three different locations that are not in the same line. The three locations are usually referred to as control points, the three motion vectors are referred to as control-point motion vectors (CPMVs). In the case when the three control points are at the three corners of the block, the affine motion can be described as, in equation 2:(fix fox) (f2x fox)blkWXblkHy V°x(fly—f Oy)blkWwherein blkW and blkH are the width and height of the block.

[0086] FIGS. 6A and 6B are conceptual diagram illustrating examples for affine mode. FIG. 6A illustrates an example where the three control points are at the three comers of block 600A. FIG. 6B illustrates an example where four control points are at the four corners of block 600B.

[0087] A simplified 4-parameters affine model (for zoom and rotational motion) is described as, in equation 3 :vx= ax — by + evy= bx + ay + f

[0088] Similarly, the simplified 4-parameters affine model for a block can be described by 2 CPMVs v0= (Ox> f oy) and v = (vlx,vly) at the 2 comers of the block. The motion field is then described as, in equation 4:(fix fox) (fly foy)Xy + vblkW blkHOx(vly- VOy) (fix “ f Ox)blkWx +blkHy + v°y

[0089] The following describes subblock based affine motion compensation. Given an affine motion model for a block, different motion vectors can be derived for each pixel in the block. Therefore, motion compensation can be performed in pixel-by-pixel (e.g., per-pixel). However, to reduce the complexity, subblock based motion compensation is usually adopted, wherein the block is partitioned into multiple subblocks (that have smaller block size) and each subblock is associated with one motion vector for motion compensation (e.g., to identify a prediction signal for that subblock). The motion vector for each subblock is derived using the representative coordinate of the subblock. Typically, the center position is used. In one example, the block is partitioned into nonoverlapping subblocks. The block width is blkW, block height is blkH, the subblock width1616-639WO01Qualcomm Ref. No. 2503663 WO 23 / 67is sbW and subblock height is sbH, then there is blkH / sbH rows of subblocks and blkW / sbW subblocks in each row. For a six parameter affine motion model, the motion vector for the subblock (referred to as subblock MV) at ith row (0<=i<blkW / sbW) and jth (0<=j<bl kH / sbH) column is derived as, in equation 5:

[0090] Representing the affine model by control point motion vectors (CPMVs) instead of the conventional model parameters was adopted in VVC AMC to take the advantage of the existing prediction and the block merging techniques for MV coding. A 4-parameter affine model is represented by two CPMVs and a 6-parameter affine model is represented by three CPMVs, as described above.

[0091] The following describes overlapped block motion compensation (OBMC). In ECM (enhanced compression model), an inter prediction tool called OBMC is included. The tool operates on a subblock (4x4) basis, since the minimum unit for storing motion information is currently 4x4. For a subblock, in OBMC, video encoder 200 or video decoder 300 use motion information of neighboring block or subblock to the current block to adjust the prediction samples that are generated from the current motion information associated with the current subblock.

[0092] In one example, assume the current subblock is associated with a set of motion information mvA, the prediction sample block (e.g., initial prediction signal) generated using the motion information set mvA is denoted as predA. The block that is adjacent to the left boundary of the current subblock is associated with another set of motion information mvB. When the set of motion information mvA and mvB is determined to be different, OBMC generates another prediction sample block predB using the motion information mvB based on the current subblock position. The final prediction samples (e.g., final prediction signal) that are adjacent to the left boundary of the current subblock would be a blend of the corresponding prediction samples in predA and predB.

[0093] The OBMC can operate at subblocks adjacent to the CU boundary or inner subblocks (inside the current CU) adjacent to a subblock boundary. The inner subblocks are present when the CU are coded using subblock based prediction method, for example, affine, subblock based temporal motion vector prediction (sbTMVP), decoder-side motion refinement (DMVR), or bidirectional optical flow (BDOF) based subblock motion1616-639WO01Qualcomm Ref. No. 2503663 WO 24 / 67derivation. The OBMC can be viewed as a tool to smooth out sample value difference between boundaries.

[0094] The following describes bidirectional optical flow. Bidirectional optical flow (BDOF) is used to refine the bi-prediction signal of luma samples in a CU at the 4^4 subblock level. The BDOF mode is based on the optical flow concept, which assumes that the motion of an object is smooth. For each 4x4 subblock, a motion refinement is calculated by minimizing the difference between the L0 and LI prediction samples. The motion refinement is then used to adjust the bi-predicted sample values in the 4x4 subblock. The following steps are applied in the BDOF process.

[0095] First, the horizontal and vertical gradients, k = 0,1, ofthe two prediction signals are computed by directly calculating the difference between two neighboring samples, i.e.,ediction signal in list k, k = 0,1, and shiftl is calculated based on the luma bit depth, bitDepth, as shift 1 is set to be equal to 6.

[0096] Then, the auto- and cross-correlation of the gradients,15S2, S3, S5and S6, are calculated aswherewhere Q. is a 6x6 window around the 4x4 subblock, the value of shift2 is set to be equal to 4, and the value of shift3 is set to be equal to 1.1616-639WO01Qualcomm Ref. No. 2503663 WO 25 / 67

[0097] The motion refinement (vx,vy) is then derived using the cross- and autocorrelation terms using the following:Where, thB'I0= 1 « 4. [■] is the floor function.

[0098] Based on the motion refinement and the gradients, the following adjustment is calculated for each sample in the 4^4 subblock:

[0099] The BDOF samples of the CU are calculated by adjusting the bi-prediction samples as follows:Wherein, shift5 is set equal to Max(3, 15 - BitDepth) and the variable oo^setis set equal to (1 « (shifts— 1)).

[0100] These values are selected such that the multipliers in the BDOF process do not exceed 15-bit, and the maximum bit- width of the intermediate parameters in the BDOF process is kept within 32-bit.

[0101] BDOF is used to refine the bi-prediction signal of a CU at the 4x4 subblock level. BDOF is applied to a CU if it satisfies all the following conditions (e.g., BDOF enabling condition is satisfied):a. The CU is coded using “true” bi-prediction mode, i.e., one of the two reference pictures is prior to the current picture in display order and the other is after the current picture in display orderb. The CU is not coded using affine mode or the ATMVP merge mode c. CU has more than 64 luma samplesd. Both CU height and CU width are larger than or equal to 8 luma samples e. BCW weight index indicates equal weightf. WP is not enabled for the current CUg. CIIP mode is not used for the current CU

[0102] Although above describes that BDOF may not be available for affine mode, there may be some instances where BDOF or at least some results from BDOF may be used in affine mode. The following describes BDOF for affine coded blocks. JVET-AF0159,1616-639WO01Qualcomm Ref. No. 2503663 WO 26 / 67entitled “EE2-3.6: Affine subblock BDOF refinement,” proposes to apply BDOF to refine subblock MV (motion vector) for an affine coded block. When an affine coded block meets the BDOF enabling condition, subblock MC (motion compensation) is applied with BDOF refinement per subblock. The refined MVs are stored for future block MV prediction. An affine coded block, e.g. affine regular merge mode, affine BM merge mode, affine AMVP mode, derives MVs for each 4^4 subblock from the affine model. The BDOF process starts with the 4x4 subblocks grouping with identical MVs. The first iteration of BDOF MV refinement is processed in 8x8 subblock grid as in EMC-10.0. When the grouped subblock size is less than 256, the second iteration of BDOF MV refinement is processed in 4x4 subblock grid, and otherwise in 8x8 subblock grid. When the grouped subblock size is 4xN or Nx4, the first iteration of BDOF MV refinement is bypassed. The BDOF enabling condition may be the same as ECM-10.0, e.g., two reference pictures have equal POC distance to the current picture, and equal weight prediction.

[0103] The following describes adaptive per-pixel motion compensation for affine coded block. JVET-AC0158, entitled “EE2-2.5: Pixel based affine motion compensation,” proposes to change the minimum affine subblock size from 4x4 to 1x1 for both luma and chroma components, 1x1 subblock size allows pixel based affine MC. When affine subblock width or height is smaller than 4, PROF is disabled. For affine merge mode, OBMC flag is inherited from neighbor affine block. For regular inter AMVP the OBMC flag is enabled without signaling, and OBMC is disabled for SCC classes by existed SPS flag. Minimum affine subblock size is set to 1x1 for luma component when OBMC is not applied, and minimum subblock size may always be set to 1x1 for chroma components.

[0104] The following describes decoder side motion vector refinement (DMVR) for affine merge mode. The affine DMVR design can be summarized in the following steps:a. Divide the current block into subblocks.b. Generate initial motion vectors (of both prediction directions) for each subblock (subblock motion fields) according to the initial affine motion model.c. Loop over each subblock, calculate subblock bilateral matching cost for all possible offsets.d. For each possible offset, accumulate the subblock bilateral matching cost to generate the bilateral matching cost corresponding to the entire block.1616-639WO01Qualcomm Ref. No. 2503663 WO 27 / 67e. Determine the best offset by selecting the one with minimum bilateral matching cost corresponding to the entire block.

[0105] During this search and refinement loop, video encoder 200 and video decoder 300 may test various small offsets applied to the CPMVs. For example, the search may include integer pixel offsets such as -1, 0, and +1. Following the integer search, video encoder 200 and video decoder 300 may determine sub-pixel offsets, such as +0.3 pixels, using parametric error surface estimation to further refine the motion vectors without performing additional image matching.

[0106] In this way, the subblock motion fields may be generated only once instead of for each candidate offset. In some examples, video encoder 200 and video decoder 300 calculate the bilateral matching cost as a sum of absolute differences between prediction samples derived from a first reference list (List 0) and a second reference list (List 1). This cost calculation may be represented as Cost = Sum(|PredL0(subblock) -PredLl(subblock)|), where the summation is performed over the subblocks of the current block. If the affine model rotates the block, the List 0 and List 1 prediction blocks may be rotated versions of each other, and the refined Control Point Motion Vectors (CPMVs) may be selected to minimize this cost, thereby making the two warped blocks appear substantially identical.

[0107] The subblock size in the above process is decided based on the affine parameters. Affine parameters reflect the per pixel motion vector change in an affine coded block. Generally, a larger subblock size is used when the affine parameters is small and vice versa.

[0108] Given the offset and initial motion vectors (generated in step b), the candidate motion vectors can be derived. Pre-interpolation is applied to generate predictors for all possible offsets in one step, which reduces the complexity. Bilinear interpolation is used instead of 8-tap (6-tap, or 12-tap) interpolation filters that are typically used for final motion compensation. Parametric error surface based sub-pixel offsets estimation may also be applied after step e) to generate the sub-pixel offset.

[0109] In JVET-AB0112, entitled “EE2-2.6: DMVR for affine merge coded blocks,” affine DMVR that follows the above-mentioned procedures are proposed. In JVET-AB0177, entitled “EE2-related: Sub-block processing for affine DMVR,” certain simplification aspect is added. For example, instead of using each of the subblock in affine DMVR, only a sub-set of subblocks are used. Regression based affine merge candidate derivation method is further applied based on the affine DMVR search results.1616-639WO01Qualcomm Ref. No. 2503663 WO 28 / 67

[0110] In JVET-AB0178, entitled “EE2 -related: Control-point motion vector refinement for Affine DMVR,” a CPMV based affine DMVR search method is proposed. Given initial control-point motion vectors initCpMvLXfcpIdx] with cpIdx=O..numCpMv - 1, wherein the numCpMv is the number of CPMVs of the current affine coding block. The proposed method can be described in the following steps:a. For each control point, perform bilateral matching for a block that is centered by the control points to derive the refined CPMVs bmRefinedCpMvLxfcpIdx] .b. Loop over combinations of initCpMvLXfcpIdx] and bmRefinedCpMvLxfcpIdx], derive a best set of CPMVs that minimize the bilateral matching cost of the current block.c. Iteratively further refine the CPMVs to minimize the bilateral matching cost of the current block. In each iteration, one CPMV is refined while the others are fixed.[OHl] The following describes alternative affine merge list for adaptive affine decoder side motion vector refinement. In U.S. Patent Publication No. 2024 / 0179342, a separate affine merge list may be used which may only consist of affine merge candidates that meet the affine DMVR conditions. After affine merge list is constructed, those candidates that meet the adaptive affine DMVR conditions may be added to a separate list which may be only used for adaptive affine DMVR process. By excluding those candidates that are either uni -predicted or do not satisfy the adaptive affine DMVR conditions, potentially the merge index to be signaled may be smaller and hence signaling overhead can be reduced.

[0112] There may be some issues with affine mode techniques. When an affine merge candidate (e.g., candidate block) meets the affine DMVR condition (e.g., affine DMVR enabling condition is satisfied), typically the candidate (e.g., candidate block) also meets the affine BDOF condition (e.g., BDOF enabling condition is satisfied). Therefore, BDOF for affine coded block may be performed instead of per-pixel or subblock based affine MC (motion compensation). However, BDOF for affine coded block may not always provide the best prediction (e.g., prediction signal).

[0113] In accordance with one or more examples, an affine bilateral matching merge mode is described, such that the merge candidate list contains bi-prediction affine motion information and affine DMVR is performed to refine the affine motion. This affine bilateral matching merge mode is a different merge mode than existing merge modes. 1616-639WO01Qualcomm Ref. No. 2503663 WO 29 / 67

[0114] In one or more examples, given the affine refined affine motion, per-pixel or subblock based motion compensation is applied and affine BDOF is not applied. The same candidate may exist in another merge list for a different merge mode. Affine BDOF may be applied if the candidate meets the affine BDOF condition. In one example, both affine motion in both reference lists simultaneously are used as in regular affine DMVR.

[0115] In accordance with the techniques of this disclosure, video decoder 300 may generate, for a current block coded in affine mode, a candidate list that includes biprediction affine motion information of one or more candidate blocks. Video decoder 300 may refine the affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information. Video decoder 300 may decode the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether a BDOF enabling condition is satisfied.

[0116] Such techniques of the disclosure may be considered as altering the decision logic typically employed in advanced video codecs (such as VVC or ECM) by decoupling the mandatory linkage between high-precision affine motion and optical flow adjustments. As explained above, in existing approaches, when an affine coded block satisfies the specific conditions required for BDOF (e.g., true bi-prediction, sufficient block size, equal weights, etc.), video decoder 300 may always apply BDOF (e.g., video decoder 300 is required to apply BDOF). While BDOF generally improves prediction quality by refining the optical flow between reference pictures, BDOF relies on the assumption that motion is smooth and linear. However, affine motion often involves complex, non-linear deformations such as rotation, zooming, and shearing. In some cases, the optical flow adjustments calculated by BDOF may introduce artifacts or “over-correct” the prediction, resulting in a less accurate signal than the pure geometric affine compensation.

[0117] By utilizing the affine bilateral matching merge mode described herein, video decoder 300 gains the flexibility to utilize high-precision, refined affine motion vectors (e.g., via bilateral matching) while explicitly skipping the optical flow refinement step. For instance, the disclosure describes example techniques of applying per-pixel or subblock based motion compensation where affine BDOF is not applied (e.g., bypass BDOF) independent of whether BDOF enabling condition is satisfied. Accordingly, even if the criterion for enabling BDOF is met (e.g., the block being bi-predicted, the block size being 8x8 or larger, and the reference pictures being equidistant), video decoder 300 may be configured to bypass the BDOF process (e.g., no apply BDOF) if the affine 1616-639WO01Qualcomm Ref. No. 2503663 WO 30 / 67bilateral matching merge mode is selected. This allows video decoder 300 to generate a prediction signal based on pure geometric affine compensation when such a signal provides better reconstruction quality than a BDOF-adjusted signal.

[0118] As an example to illustrate the example techniques, a current block may represent a rotating wheel with complex texture. The current block may be coded using 6-parameter affine motion and have valid bi-prediction reference pictures, thereby satisfying the standard BDOF enabling conditions (e.g., CU size > 64 luma samples, not using CIIP, etc.). In some example decoders, satisfying these conditions would automatically trigger the BDOF process, which might attempt to smooth the flow between the rotating textures in a way that blurs the sharp edges of the wheel spokes. However, using the techniques of this disclosure, video decoder 300 identifies that the current block is coded using the affine bilateral matching merge mode. Despite the BDOF conditions being fully satisfied (e.g., the “flag” for BDOF capability is technically true), video decoder 300 overrides this default behavior. Instead, video decoder 300 may apply the refined affine motion vectors to perform per-pixel or subblock motion compensation directly and bypass BDOF (e.g., BDOF is not applied), preserving the sharp geometric rotation without the optical flow smoothing.

[0119] In another example, video decoder 300 may determine that a candidate block selected from the merge list has bi-prediction affine motion information. Video decoder 300 first refines this motion information using decoder side motion vector refinement (DMVR). That is, refining the affine motion information may include refining the affine motion information using DMVR.

[0120] As an example, video decoder 300 may employ bilateral matching to derive refined control point motion vectors (CPMVs) that minimize the matching cost between the two reference lists. This refinement may increase the accuracy of the affine model (e.g., the rotation and zoom parameters). Once refined, video decoder 300 may proceed to motion compensation. Even though the block might be a large 32x32 block with equal weight prediction (a perfect candidate for BDOF), video decoder 300 performs standard subblock-based affine motion compensation (e.g., on 4x4 subblocks) or per-pixel motion compensation (e.g., on 1x1 pixels) and strictly skips the BDOF calculation steps (e.g., gradient calculation, motion refinement derivation).

[0121] Furthermore, video decoder 300 may receive information indicating an index in the merge candidate list that identifies the bi-prediction affine motion information of the candidate block. This signaling effectively serves as a switch, allowing video encoder 200 1616-639WO01Qualcomm Ref. No. 2503663 WO 31 / 67to explicitly direct video decoder 300 to use this specific mode, where BDOF is bypassed despite being available. This empowers video encoder 200 to make a rate-distortion optimization decision: it can test the prediction error with BDOF (using a standard affine merge mode) and without BDOF (using the affine bilateral matching merge mode). If the version without BDOF yields a lower residual, video encoder 200 may indicate that affine bilateral matching merge mode is to be used and signal the index for the affine bilateral matching merge mode, and video decoder 300 may reconstruct the block by refining the affine motion and then bypassing BDOF, regardless of the eligibility of the block for optical flow refinement.

[0122] In some examples, in the affine bilateral matching merge mode, affine BDOF may be always applied for motion compensation. If the same candidate exists in another merge list for a different merge mode, the per-pixel or subblock based motion compensation may be performed instead of affine BDOF.

[0123] In some examples, video decoder 300 may construct the candidate list as a first candidate list specifically for the affine bilateral matching merge mode. As part of the general decoding process, video decoder 300 may construct a second merge candidate list for a merge mode different than the affine bilateral matching merge mode. This second merge mode may be, for instance, a standard affine merge mode or an inter-merge mode. Inter-merge mode may be a conventional merge mode where motion information from a neighboring inter-predicted blocks is used as motion information for current block. This second list includes a set of motion information available for standard decoding processes where BDOF may typically be applied.

[0124] In some examples, video decoder 300 may determine that the refined affine motion information (derived for the affine bilateral matching merge mode) is the same as at least one motion information included in the set of motion information in the second merge candidate list. This situation creates a unique decision point. In some techniques, if a candidate exists in a standard merge list and satisfies BDOF conditions, the decoder may automatically apply BDOF. However, in accordance with one or more examples described in this disclosure, video decoder 300 may decode the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses BDOF (e.g., BDOF is skipped) independent of whether the BDOF enabling condition is satisfied, and further based on the refined affine motion information being the same as at least one motion information in the set of motion information in the second merge candidate list.1616-639WO01Qualcomm Ref. No. 2503663 WO 32 / 67

[0125] This capability may provide advantages in coding efficiency by offering video encoder 200 a granular “switch” for BDOF. Even though the same motion candidate exists in the standard list (where it would be subject to BDOF), video encoder 200 may cause video decoder 300 to use the “clean,” geometric-only version of that candidate by signaling that the affine bilateral matching merge mode is enabled. This allows the example techniques to support a candidate that is “BDOF-capable” but to deliberately use it in a “BDOF-disabled” manner when the optical flow refinement may have lower prediction quality (e.g., in complex rotation scenarios where optical flow assumptions fail).

[0126] To further illustrate the flexibility of the example techniques, consider the processing of a second block. Video decoder 300 may generate, for a second block coded in the affine mode, a second candidate list that includes bi-prediction affine motion information of a second set of one or more candidate blocks. Unlike the current block described above, video decoder 300 decodes this second block using the bi-prediction affine motion information of a second candidate block from this set based on performing affine BDOF. Accordingly, this disclosure describes various example coding techniques for the affine bilateral matching merge mode: one techniques utilizes high-precision affine motion while bypassing BDOF even if the candidate is BDOF-eligible, and another technique that takes full advantage of affine BDOF.

[0127] Some high level syntax, SPS level, PPS level, picture level or slice level flag might be used to indicate whether the affine bilateral matching merge mode is used. At CU level, a flag is signaled to indicate if a CU uses this mode for coding.

[0128] Accordingly, in some examples, video decoder 300 receives a syntax parameter indicating that an affine bilateral matching merge mode is enabled. This syntax parameter serves as a high-level control or a specific block-level indicator that dictates the operational state of video decoder 300 regarding the affine bilateral matching merge mode. In response to the syntax element indicating that the affine bilateral matching merge mode is enabled, video decoder 300 may proceed to decode the current block based on performing per-pixel or subblock based motion compensation that bypasses BDOF independent of whether a BDOF enabling condition is satisfied.

[0129] This signaling mechanism may allow video decoder 300 to distinguish between a standard affine merge mode (where BDOF is mandatory if conditions are met) and the affine bilateral matching merge mode (where BDOF is prohibited). Without this explicit syntax parameter, video decoder 300 may default to existing standards that couple affine 1616-639WO01Qualcomm Ref. No. 2503663 WO 33 / 67motion with BDOF, thereby negating the benefits of the purely geometric affine prediction described in this disclosure. By receiving this parameter, video decoder 300 may be informed to switch its motion compensation path to the “BDOF -bypass” logic, if needed, ensuring that the refined affine motion vectors are applied directly to the prediction samples without optical flow modification.

[0130] It should be noted that in some examples, video decoder 300 may always apply BDOF such as in an alternative design. In this alternative design, in the affine bilateral matching merge mode, affine BDOF is always applied for motion compensation. If the same candidate exists in another merge list for a different merge mode, the per-pixel or subblock based motion compensation is performed instead of affine BDOF.

[0131] In accordance with the techniques of this disclosure, video decoder 300 may receive this syntax parameter that the current block is coded using affine bilateral matching merge mode at various levels of the video coding hierarchy. For instance, video decoder 300 may receive the syntax parameter in a sequence parameter set (SPS), a picture parameter set (PPS), at a picture level (e.g., in a picture header), or at a slice level (e.g., in a slice header). Additionally, video decoder 300 may receive a flag at the block level (e.g., a coding unit (CU) level flag or a merge index) indicating the specific usage for the current block.

[0132] This hierarchical signaling structure may offer advantages regarding coding efficiency and complexity management. For example, by signaling the enablement of the affine bilateral matching merge mode at the SPS or PPS level, video encoder 200 can enable or disable the tool for an entire video sequence or picture based on the profile, tier, or level constraints of the decoder, or based on the global characteristics of the content (e.g., screen content versus natural video). If the high-level flag indicates the affine bilateral matching merge mode is disabled, video decoder 300 does not need to parse for block-level flags or indices related to this mode, thereby saving processing cycles and reducing the bit overhead of the bitstream.

[0133] Conversely, if the high-level syntax enables the mode, the block-level signaling provides granular control. Video encoder 200 can selectively apply the affine bilateral matching merge mode only to those specific CUs where rotational or zoom motion is complex enough that BDOF artifacts would degrade quality, while leaving other CUs in the same slice to use standard BDOF. This adaptive capability ensures that video decoder 300 always utilizes the optimal reconstruction method — either "Refined Affine + BDOF"1616-639WO01Qualcomm Ref. No. 2503663 WO 34 / 67or "Refined Affine Only" — for every specific region of the image, maximizing the overall video quality while minimizing the residual data that must be transmitted.

[0134] The following are some additional example techniques, video encoder 200 and video decoder 300 may be configured to generate a candidate list that includes biprediction affine motion information of one or more candidate blocks, and refine the affine motion information (e.g., using DMVR) for at least a candidate block of the one or more candidate blocks to generate refined affine motion information. Video encoder 200 may encode and video decoder 300 may decode a current block based on performing at least one of per-pixel or subblock based motion compensation to the current block using the refined affine motion information.

[0135] The current block may be considered as a first block and the one or more candidate blocks comprises a first set of one or more candidate blocks. Video encoder 200 and video decoder 300 may generate a first merge candidate list and a second merge candidate list for a second block, the first merge candidate list and the second merge candidate list including bi-prediction affine motion information of a second set of one or more candidate blocks. Video encoder 200 and video decoder 300 may determine that a candidate block used for encoding or decoding the second block is present in both the first merge candidate list and the second merge candidate list. In this example, video encoder 200 may encode and video decoder 300 may decode the second block based on performing affine bidirectional optical flow (BDOF).

[0136] In some examples, video encoder 200 and video decoder 300 may generate a candidate list that includes bi-prediction affine motion information of one or more candidate blocks, and determine the bi-prediction affine motion information for at least one candidate block of the one or more candidate blocks. Video encoder 200 may encode and video decoder 300 may decode a current block based on performing affine bidirectional optical flow (BDOF) using the determined bi-prediction affine motion information for the at least one candidate block.

[0137] In some examples, video encoder 200 and video decoder 300 may generate a candidate list that includes bi-prediction affine motion information of one or more candidate blocks, and determine the bi-prediction affine motion information for at least one candidate block of the one or more candidate blocks. Video encoder 200 may encode and video decoder 300 may decode a current block based on performing at least one of per-pixel or subblock based motion compensation to the current block using the biprediction affine motion information of the at least one candidate block.1616-639WO01Qualcomm Ref. No. 2503663 WO 35 / 67

[0138] FIG. 2 is a block diagram illustrating an example video encoder 200 that may perform the techniques of this disclosure. FIG. 2 is provided for purposes of explanation and should not be considered limiting of the techniques as broadly exemplified and described in this disclosure. For purposes of explanation, this disclosure describes video encoder 200 according to the techniques of VVC and HEVC. However, the techniques of this disclosure may be performed by video encoding devices that are configured to other video coding standards and video coding formats, such as AVI and successors to the AVI video coding format.

[0139] In the example of FIG. 2, video encoder 200 includes video data memory 230, mode selection unit 202, residual generation unit 204, transform processing unit 206, quantization unit 208, inverse quantization unit 210, inverse transform processing unit 212, reconstruction unit 214, filter unit 216, decoded picture buffer (DPB) 218, and entropy encoding unit 220. Any or all of video data memory 230, mode selection unit 202, residual generation unit 204, transform processing unit 206, quantization unit 208, inverse quantization unit 210, inverse transform processing unit 212, reconstruction unit 214, filter unit 216, DPB 218, and entropy encoding unit 220 may be implemented in one or more processors or in processing circuitry. For instance, the units of video encoder 200 may be implemented as one or more circuits or logic elements as part of hardware circuitry, or as part of a processor, ASIC, or FPGA. Moreover, video encoder 200 may include additional or alternative processors or processing circuitry to perform these and other functions.

[0140] Video data memory 230 is an example of a memory system that may store video data to be encoded by the components of video encoder 200. Video encoder 200 may receive the video data stored in video data memory 230 from, for example, video source 104 (FIG. 1). DPB 218 is an example of a memory system that may act as a reference picture memory that stores reference video data for use in prediction of subsequent video data by video encoder 200. Video data memory 230 and DPB 218 may each be formed by any of a variety of one or more memory devices or memory units, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. Video data memory 230 and DPB 218 may be provided by the same memory device or separate memory devices. In various examples, video data memory 230 may be on-chip with other components of video encoder 200, as illustrated, or off-chip relative to those components.1616-639WO01Qualcomm Ref. No. 2503663 WO 36 / 67

[0141] In this disclosure, reference to video data memory 230 should not be interpreted as being limited to memory internal to video encoder 200, unless specifically described as such, or memory external to video encoder 200, unless specifically described as such. Rather, reference to video data memory 230 should be understood as reference memory that stores video data that video encoder 200 receives for encoding (e.g., video data for a current block that is to be encoded). Memory 106 of FIG. 1 may also provide temporary storage of outputs from the various units of video encoder 200.

[0142] The various units of FIG. 2 are illustrated to assist with understanding the operations performed by video encoder 200. The units may be implemented as fixed-function circuits, programmable circuits, or a combination thereof. Fixed-function circuits refer to circuits that provide particular functionality, and are preset on the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks, and provide flexible functionality in the operations that can be performed. For instance, programmable circuits may execute software or firmware that cause the programmable circuits to operate in the manner defined by instructions of the software or firmware. Fixed-function circuits may execute software instructions (e.g., to receive parameters or output parameters), but the types of operations that the fixed-function circuits perform are generally immutable. In some examples, one or more of the units may be distinct circuit blocks (fixed-function or programmable), and in some examples, one or more of the units may be integrated circuits.

[0143] Video encoder 200 may include arithmetic logic units (ALUs), elementary function units (EFUs), digital circuits, analog circuits, and / or programmable cores, formed from programmable circuits. In examples where the operations of video encoder 200 are performed using software executed by the programmable circuits, memory 106 (FIG. 1) may store the instructions (e.g., object code) of the software that video encoder 200 receives and executes, or another memory within video encoder 200 (not shown) may store such instructions.

[0144] Video data memory 230 is configured to store received video data. Video encoder 200 may retrieve a picture of the video data from video data memory 230 and provide the video data to residual generation unit 204 and mode selection unit 202. Video data in video data memory 230 may be raw video data that is to be encoded.

[0145] Mode selection unit 202 includes a motion estimation unit 222, a motion compensation unit 224, and an intra-prediction unit 226. Mode selection unit 202 may include additional functional units to perform video prediction in accordance with other 1616-639WO01Qualcomm Ref. No. 2503663 WO 37 / 67prediction modes. As examples, mode selection unit 202 may include a palette unit, an intra-block copy unit (which may be part of motion estimation unit 222 and / or motion compensation unit 224), an affine unit, a linear model (LM) unit, or the like.

[0146] Mode selection unit 202 generally coordinates multiple encoding passes to test combinations of encoding parameters and resulting rate-distortion values for such combinations. The encoding parameters may include partitioning of CTUs into CUs, prediction modes for the CUs, transform types for residual data of the CUs, quantization parameters for residual data of the CUs, and so on. Mode selection unit 202 may ultimately select the combination of encoding parameters having rate-distortion values that are better than the other tested combinations.

[0147] Video encoder 200 may partition a picture retrieved from video data memory 230 into a series of CTUs, and encapsulate one or more CTUs within a slice. Mode selection unit 202 may partition a CTU of the picture in accordance with a tree structure, such as the MTT structure, QTBT structure, superblock structure, or the quad-tree structure described above. As described above, video encoder 200 may form one or more CUs from partitioning a CTU according to the tree structure. Such a CU may also be referred to generally as a “video block” or “block.”

[0148] In general, mode selection unit 202 also controls the components thereof (e.g., motion estimation unit 222, motion compensation unit 224, and intra-prediction unit 226) to generate a prediction block for a current block (e.g., a current CU, or in HEVC, the overlapping portion of a PU and a TU). For inter-prediction of a current block, motion estimation unit 222 may perform a motion search to identify one or more closely matching reference blocks in one or more reference pictures (e.g., one or more previously coded pictures stored in DPB 218). In particular, motion estimation unit 222 may calculate a value representative of how similar a potential reference block is to the current block, e.g., according to sum of absolute difference (SAD), sum of squared differences (SSD), mean absolute difference (MAD), mean squared differences (MSD), or the like. Motion estimation unit 222 may generally perform these calculations using sample-by-sample differences between the current block and the reference block being considered. Motion estimation unit 222 may identify a reference block having a lowest value resulting from these calculations, indicating a reference block that most closely matches the current block.

[0149] Motion estimation unit 222 may form one or more motion vectors (MVs) that defines the positions of the reference blocks in the reference pictures relative to the 1616-639WO01Qualcomm Ref. No. 2503663 WO 38 / 67position of the current block in a current picture. Motion estimation unit 222 may then provide the motion vectors to motion compensation unit 224. For example, for unidirectional inter-prediction, motion estimation unit 222 may provide a single motion vector, whereas for bidirectional inter-prediction, motion estimation unit 222 may provide two motion vectors. Motion compensation unit 224 may then generate a prediction block using the motion vectors. For example, motion compensation unit 224 may retrieve data of the reference block using the motion vector. As another example, if the motion vector has fractional sample precision, motion compensation unit 224 may interpolate values for the prediction block according to one or more interpolation filters. Moreover, for bidirectional inter-prediction, motion compensation unit 224 may retrieve data for two reference blocks identified by respective motion vectors and combine the retrieved data, e.g., through sample-by-sample averaging or weighted averaging.

[0150] When operating according to the AVI video coding format, motion estimation unit 222 and motion compensation unit 224 may be configured to encode coding blocks of video data (e.g., both luma and chroma coding blocks) using translational motion compensation, affine motion compensation, overlapped block motion compensation (OBMC), and / or compound inter-intra prediction.

[0151] As another example, for intra-prediction, or intra-prediction coding, intraprediction unit 226 may generate the prediction block from samples neighboring the current block. For example, for directional modes, intra-prediction unit 226 may generally mathematically combine values of neighboring samples and populate these calculated values in the defined direction across the current block to produce the prediction block. As another example, for DC mode, intra-prediction unit 226 may calculate an average of the neighboring samples to the current block and generate the prediction block to include this resulting average for each sample of the prediction block.

[0152] When operating according to the AVI video coding format, intra-prediction unit 226 may be configured to encode coding blocks of video data (e.g., both luma and chroma coding blocks) using directional intra prediction, non-directional intra prediction, recursive filter intra prediction, chroma-from-luma (CFL) prediction, intra block copy (IBC), and / or color palette mode. Mode selection unit 202 may include additional functional units to perform video prediction in accordance with other prediction modes.

[0153] Mode selection unit 202 provides the prediction block to residual generation unit 204. Residual generation unit 204 receives a raw, unencoded version of the current block from video data memory 230 and the prediction block from mode selection unit 202.1616-639WO01Qualcomm Ref. No. 2503663 WO 39 / 67Residual generation unit 204 calculates sample-by-sample differences between the current block and the prediction block. The resulting sample-by-sample differences define a residual block for the current block. In some examples, residual generation unit 204 may also determine differences between sample values in the residual block to generate a residual block using residual differential pulse code modulation (RDPCM). In some examples, residual generation unit 204 may be formed using one or more subtractor circuits that perform binary subtraction.

[0154] In examples where mode selection unit 202 partitions CUs into PUs, each PU may be associated with a luma prediction unit and corresponding chroma prediction units. Video encoder 200 and video decoder 300 may support PUs having various sizes. As indicated above, the size of a CU may refer to the size of the luma coding block of the CU and the size of a PU may refer to the size of a luma prediction unit of the PU. Assuming that the size of a particular CU is 2Nx2N, video encoder 200 may support PU sizes of 2Nx2N or NxN for intra prediction, and symmetric PU sizes of 2Nx2N, 2NxN, Nx2N, NxN, or similar for inter prediction. Video encoder 200 and video decoder 300 may also support asymmetric partitioning for PU sizes of 2NxnU, 2NxnD, nLx2N, and nRx2N for inter prediction.

[0155] In examples where mode selection unit 202 does not further partition a CU into PUs, each CU may be associated with a luma coding block and corresponding chroma coding blocks. As above, the size of a CU may refer to the size of the luma coding block of the CU. The video encoder 200 and video decoder 300 may support CU sizes of 2Nx2N, 2NxN, orNx2N.

[0156] For other video coding techniques such as an intra-block copy mode coding, an affine-mode coding, and linear model (LM) mode coding, as some examples, mode selection unit 202, via respective units associated with the coding techniques, generates a prediction block for the current block being encoded. In some examples, such as palette mode coding, mode selection unit 202 may not generate a prediction block, and instead generate syntax elements that indicate the manner in which to reconstruct the block based on a selected palette. In such modes, mode selection unit 202 may provide these syntax elements to entropy encoding unit 220 to be encoded.

[0157] As described above, residual generation unit 204 receives the video data for the current block and the corresponding prediction block. Residual generation unit 204 then generates a residual block for the current block. To generate the residual block, residual1616-639WO01Qualcomm Ref. No. 2503663 WO 40 / 67generation unit 204 calculates sample-by-sample differences between the prediction block and the current block.

[0158] Transform processing unit 206 applies one or more transforms to the residual block to generate a block of transform coefficients (referred to herein as a “transform coefficient block”). Transform processing unit 206 may apply various transforms to a residual block to form the transform coefficient block. For example, transform processing unit 206 may apply a discrete cosine transform (DCT), a directional transform, a Karhunen-Loeve transform (KLT), or a conceptually similar transform to a residual block. In some examples, transform processing unit 206 may perform multiple transforms to a residual block, e.g., a primary transform and a secondary transform, such as a rotational transform. In some examples, transform processing unit 206 does not apply transforms to a residual block.

[0159] When operating according to AVI, transform processing unit 206 may apply one or more transforms to the residual block to generate a block of transform coefficients (referred to herein as a “transform coefficient block”). Transform processing unit 206 may apply various transforms to a residual block to form the transform coefficient block. For example, transform processing unit 206 may apply a horizontal / vertical transform combination that may include a discrete cosine transform (DCT), an asymmetric discrete sine transform (ADST), a flipped ADST (e.g., an ADST in reverse order), and an identity transform (IDTX). When using an identity transform, the transform is skipped in one of the vertical or horizontal directions. In some examples, transform processing may be skipped.

[0160] Quantization unit 208 may quantize the transform coefficients in a transform coefficient block, to produce a quantized transform coefficient block. Quantization unit 208 may quantize transform coefficients of a transform coefficient block according to a quantization parameter (QP) value associated with the current block. Video encoder 200 (e.g., via mode selection unit 202) may adjust the degree of quantization applied to the transform coefficient blocks associated with the current block by adjusting the QP value associated with the CU. Quantization may introduce loss of information, and thus, quantized transform coefficients may have lower precision than the original transform coefficients produced by transform processing unit 206.

[0161] Inverse quantization unit 210 and inverse transform processing unit 212 may apply inverse quantization and inverse transforms to a quantized transform coefficient block, respectively, to reconstruct a residual block from the transform coefficient block.1616-639WO01Qualcomm Ref. No. 2503663 WO 41 / 67Reconstruction unit 214 may produce a reconstructed block corresponding to the current block (albeit potentially with some degree of distortion) based on the reconstructed residual block and a prediction block generated by mode selection unit 202. For example, reconstruction unit 214 may add samples of the reconstructed residual block to corresponding samples from the prediction block generated by mode selection unit 202 to produce the reconstructed block.

[0162] Filter unit 216 may perform one or more filter operations on reconstructed blocks. For example, filter unit 216 may perform deblocking operations to reduce blockiness artifacts along edges of CUs. Operations of filter unit 216 may be skipped, in some examples.

[0163] When operating according to AVI, filter unit 216 may perform one or more filter operations on reconstructed blocks. For example, filter unit 216 may perform deblocking operations to reduce blockiness artifacts along edges of CUs. In other examples, filter unit 216 may apply a constrained directional enhancement filter (CDEF), which may be applied after deblocking, and may include the application of non-separable, non-linear, low-pass directional filters based on estimated edge directions. Filter unit 216 may also include a loop restoration filter, which is applied after CDEF, and may include a separable symmetric normalized Wiener filter or a dual self-guided filter.

[0164] Video encoder 200 stores reconstructed blocks in DPB 218. For instance, in examples where operations of filter unit 216 are not performed, reconstruction unit 214 may store reconstructed blocks to DPB 218. In examples where operations of filter unit 216 are performed, filter unit 216 may store the filtered reconstructed blocks to DPB 218. Motion estimation unit 222 and motion compensation unit 224 may retrieve a reference picture from DPB 218, formed from the reconstructed (and potentially filtered) blocks, to inter-predict blocks of subsequently encoded pictures. In addition, intra-prediction unit 226 may use reconstructed blocks in DPB 218 of a current picture to intra-predict other blocks in the current picture.

[0165] In general, entropy encoding unit 220 may entropy encode syntax elements received from other functional components of video encoder 200. For example, entropy encoding unit 220 may entropy encode quantized transform coefficient blocks from quantization unit 208. As another example, entropy encoding unit 220 may entropy encode prediction syntax elements (e.g., motion information for inter-prediction or intramode information for intra-prediction) from mode selection unit 202. Entropy encoding unit 220 may perform one or more entropy encoding operations on the syntax elements, 1616-639WO01Qualcomm Ref. No. 2503663 WO 42 / 67which are another example of video data, to generate entropy-encoded data. For example, entropy encoding unit 220 may perform a context-adaptive variable length coding (CAVLC) operation, a CABAC operation, a variable-to-variable (V2V) length coding operation, a syntax-based context-adaptive binary arithmetic coding (SB AC) operation, a Probability Interval Partitioning Entropy (PIPE) coding operation, an Exponential-Golomb encoding operation, or another type of entropy encoding operation on the data. In some examples, entropy encoding unit 220 may operate in bypass mode where syntax elements are not entropy encoded.

[0166] Video encoder 200 may output a bitstream that includes the entropy encoded syntax elements needed to reconstruct blocks of a slice or picture. In particular, entropy encoding unit 220 may output the bitstream.

[0167] In accordance with AVI, entropy encoding unit 220 may be configured as a symbol -to- symbol adaptive multi-symbol arithmetic coder. A syntax element in AVI includes an alphabet of N elements, and a context (e.g., probability model) includes a set of N probabilities. Entropy encoding unit 220 may store the probabilities as n-bit (e.g., 15-bit) cumulative distribution functions (CDFs). Entropy encoding unit 220 may perform recursive scaling, with an update factor based on the alphabet size, to update the contexts.

[0168] The operations described above are described with respect to a block. Such description should be understood as being operations for a luma coding block and / or chroma coding blocks. As described above, in some examples, the luma coding block and chroma coding blocks are luma and chroma components of a CU. In some examples, the luma coding block and the chroma coding blocks are luma and chroma components ofaPU.

[0169] In some examples, operations performed with respect to a luma coding block need not be repeated for the chroma coding blocks. As one example, operations to identify a motion vector (MV) and reference picture for a luma coding block need not be repeated for identifying a MV and reference picture for the chroma blocks. Rather, the MV for the luma coding block may be scaled to determine the MV for the chroma blocks, and the reference picture may be the same. As another example, the intra-prediction process may be the same for the luma coding block and the chroma coding blocks.

[0170] Video encoder 200 represents an example of a device configured to encode video data including a memory configured to store video data, and one or more processing units implemented in circuitry and configured to perform the example techniques described in 1616-639WO01Qualcomm Ref. No. 2503663 WO 43 / 67this disclosure. In accordance with the techniques of this disclosure, video encoder 200 may operate to select the optimal encoding mode for a current block, which may include selecting the affine bilateral matching merge mode. Video encoder 200 may generate, for a current block coded in affine mode, a candidate list that includes bi-prediction affine motion information of one or more candidate blocks. To ensure the highest precision for the motion information before making a mode decision, video encoder 200 may refine the affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information. In some examples, video encoder 200 performs this refinement using decoder side motion vector refinement (DMVR), utilizing bilateral matching to derive updated control point motion vectors (CPMVs) that minimize distortion between reference lists.

[0171] Once the motion is refined, video encoder 200 may determine whether to encode the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether a BDOF enabling condition is satisfied. This determination is typically part of a rate-distortion optimization (RDO) process. Video encoder 200 may test the coding cost (e.g., a Lagrangian cost function based on rate and distortion) of encoding the block using standard affine merge (where BDOF is applied if conditions are met) versus the affine bilateral matching merge mode (where BDOF is strictly bypassed).

[0172] If video encoder 200 determines that the prediction signal generated by the refined affine motion without BDOF results in a lower cost (e.g., because the motion is purely rotational and BDOF introduces unwanted smoothing artifact), video encoder 200 selects the affine bilateral matching merge mode. Video encoder 200 then encodes the current block using this mode and signals the necessary syntax elements (e.g., syntax parameter that indicates that affine bilateral matching merge mode is enabled and a merge index) to instruct video decoder 300 to use the refined affine motion and to bypass BDOF (e.g., so that the reconstruction at video decoder 300 matches the prediction signal selected by video encoder 200).

[0173] FIG. 3 is a block diagram illustrating an example video decoder 300 that may perform the techniques of this disclosure. FIG. 3 is provided for purposes of explanation and is not limiting on the techniques as broadly exemplified and described in this disclosure. For purposes of explanation, this disclosure describes video decoder 300 according to the techniques of VVC and HEVC. However, the techniques of this 1616-639WO01Qualcomm Ref. No. 2503663 WO 44 / 67disclosure may be performed by video coding devices that are configured to other video coding standards.

[0174] In the example of FIG. 3, video decoder 300 includes coded picture buffer (CPB) memory 320, entropy decoding unit 302, prediction processing unit 304, inverse quantization unit 306, inverse transform processing unit 308, reconstruction unit 310, filter unit 312, and DPB 314. Any or all of CPB memory 320, entropy decoding unit 302, prediction processing unit 304, inverse quantization unit 306, inverse transform processing unit 308, reconstruction unit 310, filter unit 312, and DPB 314 may be implemented in one or more processors or in processing circuitry. For instance, the units of video decoder 300 may be implemented as one or more circuits or logic elements as part of hardware circuitry, or as part of a processor, ASIC, or FPGA. Moreover, video decoder 300 may include additional or alternative processors or processing circuitry to perform these and other functions.

[0175] Prediction processing unit 304 includes motion compensation unit 316 and intraprediction unit 318. Prediction processing unit 304 may include additional units to perform prediction in accordance with other prediction modes. As examples, prediction processing unit 304 may include a palette unit, an intra-block copy unit (which may form part of motion compensation unit 316), an affine unit, a linear model (LM) unit, or the like. In other examples, video decoder 300 may include more, fewer, or different functional components.

[0176] When operating according to AVI, motion compensation unit 316 may be configured to decode coding blocks of video data (e.g., both luma and chroma coding blocks) using translational motion compensation, affine motion compensation, OBMC, and / or compound inter-intra prediction, as described above. Intra-prediction unit 318 may be configured to decode coding blocks of video data (e.g., both luma and chroma coding blocks) using directional intra prediction, non-directional intra prediction, recursive filter intra prediction, CFL, IBC, and / or color palette mode, as described above.

[0177] CPB memory 320 is an example of a memory system that may store video data, such as an encoded video bitstream, to be decoded by the components of video decoder 300. The video data stored in CPB memory 320 may be obtained, for example, from computer-readable medium 110 (FIG. 1). CPB memory 320 may include a CPB that stores encoded video data (e.g., syntax elements) from an encoded video bitstream. Also, CPB memory 320 may store video data other than syntax elements of a coded picture, such as temporary data representing outputs from the various units of video decoder 300.1616-639WO01Qualcomm Ref. No. 2503663 WO 45 / 67DPB 314 is an example of a memory system that generally stores decoded pictures, which video decoder 300 may output and / or use as reference video data when decoding subsequent data or pictures of the encoded video bitstream. CPB memory 320 and DPB 314 may each be formed by any of a variety of memory devices or memory units, such as DRAM, including SDRAM, MRAM, RRAM, or other types of memory devices. CPB memory 320 and DPB 314 may be provided by the same memory device or separate memory devices. In various examples, CPB memory 320 may be on-chip with other components of video decoder 300, or off-chip relative to those components.

[0178] Additionally or alternatively, in some examples, video decoder 300 may retrieve coded video data from memory 120 (FIG. 1). That is, memory 120 may store data as discussed above with CPB memory 320. Likewise, memory 120 may store instructions to be executed by video decoder 300, when some or all of the functionality of video decoder 300 is implemented in software to be executed by processing circuitry of video decoder 300.

[0179] The various units shown in FIG. 3 are illustrated to assist with understanding the operations performed by video decoder 300. The units may be implemented as fixed-function circuits, programmable circuits, or a combination thereof. Similar to FIG. 2, fixed-function circuits refer to circuits that provide particular functionality, and are preset on the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks, and provide flexible functionality in the operations that can be performed. For instance, programmable circuits may execute software or firmware that cause the programmable circuits to operate in the manner defined by instructions of the software or firmware. Fixed-function circuits may execute software instructions (e.g., to receive parameters or output parameters), but the types of operations that the fixed-function circuits perform are generally immutable. In some examples, one or more of the units may be distinct circuit blocks (fixed-function or programmable), and in some examples, one or more of the units may be integrated circuits.

[0180] Video decoder 300 may include ALUs, EFUs, digital circuits, analog circuits, and / or programmable cores formed from programmable circuits. In examples where the operations of video decoder 300 are performed by software executing on the programmable circuits, on-chip or off-chip memory may store instructions (e.g., object code) of the software that video decoder 300 receives and executes.1616-639WO01Qualcomm Ref. No. 2503663 WO 46 / 67

[0181] Entropy decoding unit 302 may receive encoded video data from the CPB and entropy decode the video data to reproduce syntax elements. Prediction processing unit 304, inverse quantization unit 306, inverse transform processing unit 308, reconstruction unit 310, and filter unit 312 may generate decoded video data based on the syntax elements extracted from the bitstream.

[0182] In general, video decoder 300 reconstructs a picture on a block-by-block basis. Video decoder 300 may perform a reconstruction operation on each block individually (where the block currently being reconstructed, i.e., decoded, may be referred to as a “current block”).

[0183] Entropy decoding unit 302 may entropy decode syntax elements defining quantized transform coefficients of a quantized transform coefficient block, as well as transform information, such as a quantization parameter (QP) and / or transform mode indication(s). Inverse quantization unit 306 may use the QP associated with the quantized transform coefficient block to determine a degree of quantization and, likewise, a degree of inverse quantization for inverse quantization unit 306 to apply. Inverse quantization unit 306 may, for example, perform a bitwise left-shift operation to inverse quantize the quantized transform coefficients. Inverse quantization unit 306 may thereby form a transform coefficient block including transform coefficients.

[0184] After inverse quantization unit 306 forms the transform coefficient block, inverse transform processing unit 308 may apply one or more inverse transforms to the transform coefficient block to generate a residual block associated with the current block. For example, inverse transform processing unit 308 may apply an inverse DCT, an inverse integer transform, an inverse Karhunen-Loeve transform (KLT), an inverse rotational transform, an inverse directional transform, or another inverse transform to the transform coefficient block.

[0185] Furthermore, prediction processing unit 304 generates a prediction block according to prediction information syntax elements that were entropy decoded by entropy decoding unit 302. For example, if the prediction information syntax elements indicate that the current block is inter-predicted, motion compensation unit 316 may generate the prediction block. In this case, the prediction information syntax elements may indicate a reference picture in DPB 314 from which to retrieve a reference block, as well as a motion vector identifying a location of the reference block in the reference picture relative to the location of the current block in the current picture. Motion compensation unit 316 may generally perform the inter-prediction process in a manner 1616-639WO01Qualcomm Ref. No. 2503663 WO 47 / 67that is substantially similar to that described with respect to motion compensation unit 224 (FIG. 2).

[0186] As another example, if the prediction information syntax elements indicate that the current block is intra-predicted, intra-prediction unit 318 may generate the prediction block according to an intra-prediction mode indicated by the prediction information syntax elements. Again, intra-prediction unit 318 may generally perform the intraprediction process in a manner that is substantially similar to that described with respect to intra-prediction unit 226 (FIG. 2). Intra-prediction unit 318 may retrieve data of neighboring samples to the current block from DPB 314.

[0187] Reconstruction unit 310 may reconstruct the current block using the prediction block and the residual block. For example, reconstruction unit 310 may add samples of the residual block to corresponding samples of the prediction block to reconstruct the current block.

[0188] Filter unit 312 may perform one or more filter operations on reconstructed blocks. For example, filter unit 312 may perform deblocking operations to reduce blockiness artifacts along edges of the reconstructed blocks. Operations of filter unit 312 are not necessarily performed in all examples.

[0189] Video decoder 300 may store the reconstructed blocks in DPB 314. For instance, in examples where operations of filter unit 312 are not performed, reconstruction unit 310 may store reconstructed blocks to DPB 314. In examples where operations of filter unit 312 are performed, filter unit 312 may store the filtered reconstructed blocks to DPB 314. As discussed above, DPB 314 may provide reference information, such as samples of a current picture for intra-prediction and previously decoded pictures for subsequent motion compensation, to prediction processing unit 304. Moreover, video decoder 300 may output decoded pictures (e.g., decoded video) from DPB 314 for subsequent presentation on a display device, such as display device 118 of FIG. 1.

[0190] In this manner, video decoder 300 represents an example of a video decoding device including a memory configured to store video data, and one or more processing units implemented in circuitry and configured to perform the example techniques described in this disclosure. In accordance with the techniques of this disclosure, a device for decoding video data, such as video decoder 300, includes one or more memories (e.g., CPB memory 320, DPB 314) configured to store the video data, and processing circuitry coupled to the one or more memories. The processing circuitry of video decoder 300 may be configured to generate, for a current block coded in affine mode, a candidate list that 1616-639WO01Qualcomm Ref. No. 2503663 WO 48 / 67includes bi-prediction affine motion information of one or more candidate blocks. The processing circuitry of video decoder 300 may be configured to refine the affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information. In one or more examples, the processing circuitry of video decoder 300 may be configured to decode the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether a BDOF enabling condition is satisfied.

[0191] This configuration allows the device to address issues where mandatory BDOF application degrades prediction quality for complex non-linear motion. By having the processing circuitry explicitly bypass BDOF even when the condition is satisfied (e.g., for a bi-predicted block with equal weights), the processing circuitry may preserve the structural integrity of the block (e.g., sharp edges during rotation) without unwanted smoothing from optical flow.

[0192] In some examples, to refine the affine motion information, the processing circuitry of video decoder 300 may be configured to refine the affine motion information using decoder side motion vector refinement (DMVR). This provides the advantage of increasing the precision of the control point motion vectors (CPMVs) without requiring additional signaling bits, as the refinement is derived from the video data itself via bilateral matching.

[0193] The processing circuitry of video decoder 300 may also be configured to receive information indicating an index in the merge candidate list that identifies the bi-prediction affine motion information of the candidate block. This allows video encoder 200 to efficiently signal the selection of the affine bilateral matching merge mode with minimal overhead.

[0194] In some examples, the processing circuitry of video decoder 300 is configured to construct a first candidate list for an affine bilateral matching merge mode and a second merge candidate list for a merge mode different than the affine bilateral matching merge mode (e.g., affine merge mode or inter-merge mode). The second merge candidate list includes a set of motion information. The processing circuitry of video decoder 300 may be configured to determine that the refined affine motion information is same as at least one motion information in the set of motion information in the second merge candidate list. In such example, the processing circuitry of video decoder 300 may decode the current block using the refined affine motion information based on performing per-pixel 1616-639WO01Qualcomm Ref. No. 2503663 WO 49 / 67or subblock based motion compensation that bypasses BDOF independent of whether BDOF enabling condition is satisfied and based on the refined affine motion information being same as at least one motion information in the set of motion information in the second merge candidate list. In this manner, the affine bilateral matching merge mode provides a unique motion candidate that is distinct from standard merge candidates, thereby enriching the pool of available predictors and improving coding efficiency.

[0195] Furthermore, the processing circuitry of video decoder 300 may be configured to receive a syntax parameter indicating that an affine bilateral matching merge mode is enabled. In response to this syntax element, the processing circuitry of video decoder 300 may decode the current block based on performing per-pixel or subblock based motion compensation that bypasses BDOF. The processing circuitry may receive this syntax parameter in a sequence parameter set (SPS), picture parameter set (PPS), at a picture level, or slice level. This hierarchical signaling provides the advantage of flexibility, allowing video encoder 200 to enable or disable the tool based on the complexity constraints of video decoder 300 or the properties of the video sequence.

[0196] To demonstrate the flexibility of video decoder 300, the current block may be a first block, and the processing circuitry of video decoder 300 may be configured to generate, for a second block coded in the affine mode, a second candidate list that includes bi-prediction affine motion information of a second set of one or more candidate blocks. The processing circuitry of video decoder 300 may decode this second block using the biprediction affine motion information of a second candidate block from this second set based on performing affine BDOF. This illustrates that video decoder 300 may support multiple operation examples for the affine bilateral matching merge mode (e.g., one with BDOF bypass (for the first block) and one with BDOF application (for the second block)).

[0197] To decode the current block, the processing circuitry of video decoder 300 may be configured to determine a prediction signal based on the refined affine motion information (e.g., which may be the same prediction signal that video encoder 200 generates), receive information indicative of residual information indicative of a difference between the prediction signal and samples in the current block, and decode the current block based on the prediction signal and the residual information. This way, the final reconstructed block accurately reflects the original video content by correcting the geometric prediction with the transmitted residual data.

[0198] FIG. 4 is a flowchart illustrating an example method for encoding a current block in accordance with the techniques of this disclosure. The current block may be or include 1616-639WO01Qualcomm Ref. No. 2503663 WO 50 / 67a current CU. Although described with respect to video encoder 200 (FIGS. 1 and 2), it should be understood that other devices may be configured to perform a method similar to that of FIG. 4.

[0199] In this example, video encoder 200 initially predicts the current block (400). For example, video encoder 200 may form a prediction block for the current block. Video encoder 200 may then calculate a residual block for the current block (402). To calculate the residual block, video encoder 200 may calculate a difference between the original, unencoded block and the prediction block for the current block. Video encoder 200 may then transform the residual block and quantize transform coefficients of the residual block (404). Next, video encoder 200 may scan the quantized transform coefficients of the residual block (406). During the scan, or following the scan, video encoder 200 may entropy encode the transform coefficients (408). For example, video encoder 200 may encode the transform coefficients using CAVLC or CAB AC. Video encoder 200 may then output the entropy encoded data of the block (410).

[0200] FIG. 5 is a flowchart illustrating an example method for decoding a current block of video data in accordance with the techniques of this disclosure. The current block may be or include a current CU. Although described with respect to video decoder 300 (FIGS.1 and 3), it should be understood that other devices may be configured to perform a method similar to that of FIG. 5.

[0201] Video decoder 300 may receive entropy encoded data for the current block, such as entropy encoded prediction information and entropy encoded data for transform coefficients of a residual block corresponding to the current block (500). Video decoder 300 may entropy decode the entropy encoded data to determine prediction information for the current block and to reproduce transform coefficients of the residual block (502). Video decoder 300 may predict the current block (504), e.g., using an intra- or interprediction mode as indicated by the prediction information for the current block, to calculate a prediction block for the current block. Video decoder 300 may then inverse scan the reproduced transform coefficients (506), to create a block of quantized transform coefficients. Video decoder 300 may then inverse quantize the transform coefficients and apply an inverse transform to the transform coefficients to produce a residual block (508). Video decoder 300 may ultimately decode the current block by combining the prediction block and the residual block (510).

[0202] FIG. 7 is a flowchart illustrating an example method of operation in accordance with one or more examples described in this disclosure. Video decoder 300 (e.g., via 1616-639WO01Qualcomm Ref. No. 2503663 WO 51 / 67processing circuitry) may be configured to perform the example method of FIG. 7. The example techniques include generating, for a current block coded in affine mode, a candidate list that includes bi-prediction affine motion information of one or more candidate blocks (700) . The candidate list may be constructed using various techniques for affine merge candidates.

[0203] As illustrated in FIG. 7, the example techniques include refining the affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information (702). In some examples, to refine the affine motion information, the processing circuitry of video decoder 300 may be configured to refine the affine motion information using decoder side motion vector refinement (DMVR). This refinement allows for precise application of the geometric transformation.

[0204] The example techniques include decoding the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether a BDOF enabling condition is satisfied (704). By bypassing BDOF independent of the enabling condition (e.g., even if the block size and weights satisfy BDOF requirements), the processing circuitry of video decoder 300 preserves the purely geometric affine prediction.

[0205] In some examples, the processing circuitry of video decoder 300 is configured to receive information indicating an index in the merge candidate list that identifies the biprediction affine motion information of the candidate block. In some examples, to construct the candidate list, the processing circuitry of video decoder 300 is configured to construct a first candidate list for an affine bilateral matching merge mode. The processing circuitry of video decoder 300 is further configured to construct a second merge candidate list for a merge mode different than the affine bilateral matching merge mode (e.g., an affine merge mode or an inter-merge mode), where the second merge candidate list includes a set of motion information. In these examples, to decode the current block, the processing circuitry of video decoder 300 may be configured to determine that the refined affine motion information is same as at least one motion information in the set of motion information in the second merge candidate list. The processing circuitry of video decoder 300 may decode the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses BDOF independent of whether BDOF enabling condition is satisfied and based on the refined 1616-639WO01Qualcomm Ref. No. 2503663 WO 52 / 67affine motion information being same as at least one motion information in the set of motion information in the second merge candidate list.

[0206] In some examples, the processing circuitry of video decoder 300 is configured to receive a syntax parameter indicating that an affine bilateral matching merge mode is enabled. In this case, to decode the current block, the processing circuitry of video decoder 300 may be configured to, in response to the syntax element indicating that the affine bilateral matching merge mode is enabled, decode the current block based on performing per-pixel or subblock based motion compensation that bypasses BDOF independent of whether the BDOF enabling condition is satisfied. The processing circuitry of video decoder 300 may be configured to receive the syntax parameter in a sequence parameter set (SPS), picture parameter set (PPS), at a picture level, or slice level.

[0207] In some examples, the current block is a first block, the candidate list is a first list, and the one or more candidate blocks are a first set of one or more candidate blocks. The processing circuitry of video decoder 300 may be configured to generate, for a second block coded in the affine mode, a second candidate list that includes bi-prediction affine motion information of a second set of one or more candidate blocks. The processing circuitry may be configured to decode the second block using the bi-prediction affine motion information of a second candidate block of the second set of one or more candidate blocks based on performing affine BDOF.

[0208] In one or more examples, to decode the current block, the processing circuitry of video decoder 300 may be configured to determine a prediction signal based on the refined affine motion information, and receive information indicative of residual information indicative of a difference between the prediction signal and samples in the current block. The processing circuitry of video decoder 300 may decode the current block based on the prediction signal and the residual information.

[0209] The following numbered clauses illustrate one or more aspects of the devices and techniques described in this disclosure.

[0210] Clause 1A. A method of encoding or decoding video data, the method comprising: generating a candidate list that includes bi-prediction affine motion information of one or more candidate blocks; refining the affine motion information for at least a candidate block of the one or more candidate blocks to generate refined affine motion information; and encoding or decoding a current block based on performing at1616-639WO01Qualcomm Ref. No. 2503663 WO 53 / 67least one of per-pixel or subblock based motion compensation to the current block using the refined affine motion information.

[0211] Clause 2 A. The method of clause 1 A, wherein refining the affine motion information comprises refining the affine motion information using decoder side motion vector refinement (DMVR).

[0212] Clause 3A. The method of any of clauses 1A and 2A, wherein encoding or decoding the current block based on performing at least one of per-pixel or subblock based motion compensation to the current block using the refined affine motion information comprises encoding or decoding a current block based on performing at least one of per-pixel or subblock based motion compensation to the current block using the refined affine motion information in a condition where the candidate block is not present in another candidate list.

[0213] Clause 4A. The method of any of clauses 1 A-3A, wherein encoding or decoding the current block based on performing at least one of per-pixel or subblock based motion compensation to the current block using the refined affine motion information comprises: determining a prediction signal based on the refined affine motion information; determining residual information indicative of a difference between the prediction signal and samples in the current block; and encoding or decoding the current block based on the residual information.

[0214] Clause 5A. The method of clause 4A, wherein encoding or decoding comprises decoding the current block, wherein determining the residual information comprises receiving information indicative of the residual information, and wherein decoding the current block comprises adding the residual information to the prediction signal.

[0215] Clause 6A. The method of clause 5A, further comprising: receiving information indicative of an index into the candidate list to identify the candidate block.

[0216] Clause 7A. The method of clause 4A, wherein encoding or decoding comprises encoding the current block, wherein encoding the current block comprises signaling information indicative of the residual information.

[0217] Clause 8A. The method of clause 7A, further comprising: signaling information indicative of an index into the candidate list to identify the candidate block.

[0218] Clause 9A. The method of any of clauses 1 A-8A, wherein the candidate list is a merge candidate list.1616-639WO01Qualcomm Ref. No. 2503663 WO 54 / 67

[0219] Clause 10 A. The method of any of clauses 1A-9A, wherein the current block comprises a first block and the one or more candidate blocks comprises a first set of one or more candidate blocks, the method further comprising: generating a first merge candidate list and a second merge candidate list for a second block, the first merge candidate list and the second merge candidate list including bi-prediction affine motion information of a second set of one or more candidate blocks; determining that a candidate block used for encoding or decoding the second block is present in both the first merge candidate list and the second merge candidate list; and encoding or decoding the second block based on performing affine bidirectional optical flow (BDOF).

[0220] Clause 11 A. The method of clause 10A, wherein encoding or decoding the second block based on performing affine BDOF comprises encoding or decoding the second block based on performing affine BDOF in a condition where the candidate block used for encoding or decoding the second block satisfies an affine BDOF condition.

[0221] Clause 12A. The method of any of clauses 1A-11A, wherein generating the candidate list comprises generating the candidate list in a condition where a syntax element indicates that affine bilateral matching merge mode is used.

[0222] Clause 13 A. A method of encoding or decoding video data, the method comprising: generating a candidate list that includes bi-prediction affine motion information of one or more candidate blocks; determining the bi-prediction affine motion information for at least one candidate block of the one or more candidate blocks; and encoding or decoding a current block based on performing affine bidirectional optical flow (BDOF) using the determined bi-prediction affine motion information for the at least one candidate block.

[0223] Clause 14. The method of clause 13A, wherein the current block comprises a first block and the one or more candidate blocks comprise a first set of one or more candidate blocks, the method further comprising: generating a first merge candidate list and a second merge candidate list for a second block, the first merge candidate list and the second merge candidate list including bi-prediction affine motion information of a second set of one or more candidate blocks; determining that a second candidate block used for encoding or decoding the second block is present in both the first merge candidate list and the second merge candidate list; and encoding or decoding the second block based on performing at least one of per-pixel or subblock based motion compensation to the second block using the bi-prediction affine motion information for the second candidate block.1616-639WO01Qualcomm Ref. No. 2503663 WO 55 / 67

[0224] Clause 15 A. A method of encoding or decoding video data, the method comprising: generating a candidate list that includes bi-prediction affine motion information of one or more candidate blocks; determining the bi-prediction affine motion information for at least one candidate block of the one or more candidate blocks; and encoding or decoding a current block based on performing at least one of per-pixel or subblock based motion compensation to the current block using the bi-prediction affine motion information of the at least one candidate block.

[0225] Clause 16A. The method of clause 15 A, wherein the current block comprises a first block and the one or more candidate blocks comprise a first set of one or more candidate blocks, the method further comprising: generating a first merge candidate list and a second merge candidate list for a second block, the first merge candidate list and the second merge candidate list including bi-prediction affine motion information of a second set of one or more candidate blocks; determining that a second candidate block used for encoding or decoding the second block is present in both the first merge candidate list and the second merge candidate list; and encoding or decoding the second block based on performing affine bidirectional optical flow (BDOF) using the bi-prediction affine motion information for the second candidate block.

[0226] Clause 17 A. A device for encoding or decoding video data, the device comprising: one or more memories configured to store the video data; and processing circuitry coupled to the one or more memories and configured to perform the method of any one or combination of clauses 1A-16A.

[0227] Clause 18 A. The device of clause 17A, further comprising a display configured to display decoded video data.

[0228] Clause 19 A. The device of any of clauses 17A and 18 A, wherein the device comprises one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set-top box.

[0229] Clause 20A. The device of any of clauses 17A-19A, wherein the device comprises a video decoder.

[0230] Clause 21 A. The device of any of clauses 17A-20A, wherein the device comprises a video encoder.

[0231] Clause 22A. A computer-readable storage medium having stored thereon instructions that, when executed, cause one or more processors to perform the method of any one or combination of clauses 1A-16A.1616-639WO01Qualcomm Ref. No. 2503663 WO 56 / 67

[0232] Clause 23 A. A device for encoding or decoding video data, the device comprising means for performing the method of any of claims 1 A-16A.

[0233] Clause IB. A method of decoding video data, the method comprising generating, for a current block coded in affine mode, a candidate list that includes bi-prediction affine motion information of one or more candidate blocks, refining the bi-prediction affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information, and decoding the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether a BDOF enabling condition is satisfied.

[0234] Clause 2B. The method of Clause IB, wherein refining the bi-prediction affine motion information comprises refining the bi-prediction affine motion information using decoder side motion vector refinement (DMVR).

[0235] Clause 3B. The method of any of Clauses 1B-2B, further comprising receiving information indicating an index in the candidate list that identifies the bi-prediction affine motion information of the candidate block.

[0236] Clause 4B. The method of any of Clauses 1B-3B, wherein constructing the candidate list comprises constructing a first candidate list for an affine bilateral matching merge mode, the method further comprising constructing a second merge candidate list for a merge mode different than the affine bilateral matching merge mode, the second merge candidate list including a set of motion information, wherein decoding the current block comprises determining that the refined affine motion information is same as at least one motion information in the set of motion information in the second merge candidate list, and decoding the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses BDOF independent of whether BDOF enabling condition is satisfied and based on the refined affine motion information being same as at least one motion information in the set of motion information in the second merge candidate list.

[0237] Clause 5B. The method of Clause 4B, wherein the merge mode different than the affine bilateral matching merge mode includes one of an affine merge mode or an intermerge mode.

[0238] Clause 6B. The method of any of Clauses 1B-5B, further comprising receiving a syntax element indicating that an affine bilateral matching merge mode is enabled, wherein decoding the current block comprises, in response to the syntax element 1616-639WO01Qualcomm Ref. No. 2503663 WO 57 / 67indicating that the affine bilateral matching merge mode is enabled, decoding the current block based on performing per-pixel or subblock based motion compensation that bypasses BDOF independent of whether BDOF enabling condition is satisfied.

[0239] Clause 7B. The method of Clause 6B, wherein receiving the syntax element comprises receiving the syntax element in a sequence parameter set (SPS), picture parameter set (PPS), at a picture level, slice level, or block level.

[0240] Clause 8B. The method of any of Clauses 1B-7B, wherein the current block is a first block, the candidate list is a first list, the one or more candidate blocks are a first set of one or more candidate blocks, the candidate block is a first candidate block, the method further comprising generating, for a second block coded in the affine mode, a second candidate list that includes bi-prediction affine motion information of a second set of one or more candidate blocks, and decoding the second block using the bi-prediction affine motion information of a second candidate block of the second set of one or more candidate blocks based on performing affine BDOF.

[0241] Clause 9B. The method of any of Clauses 1B-8B, wherein decoding the current block comprises determining a prediction signal based on the refined affine motion information, receiving information indicative of residual information indicative of a difference between the prediction signal and samples in the current block, and decoding the current block based on the prediction signal and the residual information.

[0242] Clause 10B. A device for decoding video data, the device comprising one or more memories configured to store the video data, and processing circuitry coupled to the one or more memories, the processing circuitry being configured to generate, for a current block coded in affine mode, a candidate list that includes bi-prediction affine motion information of one or more candidate blocks, refine the bi-prediction affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information, and decode the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether BDOF enabling condition is satisfied.

[0243] Clause 11B. The device of Clause 10B, wherein to refine the bi-prediction affine motion information, the processing circuitry is configured to refine the bi-prediction affine motion information using decoder side motion vector refinement (DMVR).1616-639WO01Qualcomm Ref. No. 2503663 WO 58 / 67

[0244] Clause 12B. The device of any of Clauses 10B-11B, wherein the processing circuitry is configured to receive information indicating an index in the candidate list that identifies the bi-prediction affine motion information of the candidate block.

[0245] Clause 13B. The device of any of Clauses 10B-12B, wherein to construct the candidate list, the processing circuitry is configured to construct a first candidate list for an affine bilateral matching merge mode, wherein the processing circuitry is configured to construct a second merge candidate list for a merge mode different than the affine bilateral matching merge mode, the second merge candidate list including a set of motion information, and wherein to decode the current block, the processing circuitry is configured to determine that the refined affine motion information is same as at least one motion information in the set of motion information in the second merge candidate list, and decode the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses BDOF independent of whether BDOF enabling condition is satisfied and based on the refined affine motion information being same as at least one motion information in the set of motion information in the second merge candidate list.

[0246] Clause 14B. The device of Clause 13B, wherein the merge mode different than the affine bilateral matching merge mode includes one of an affine merge mode or an inter-merge mode.

[0247] Clause 15B. The device of any of Clauses 10B-14B, wherein the processing circuitry is configured to receive a syntax element indicating that an affine bilateral matching merge mode is enabled, wherein to decode the current block, the processing circuity is configured to, in response to the syntax element indicating that the affine bilateral matching merge mode is enabled, decode the current block based on performing per-pixel or subblock based motion compensation that bypasses BDOF independent of whether BDOF enabling condition is satisfied.

[0248] Clause 16B. The device of Clause 15B, wherein to receive the syntax element, the processing circuitry is configured to receive the syntax element in a sequence parameter set (SPS), picture parameter set (PPS), at a picture level, or slice level.

[0249] Clause 17B. The device of any of Clauses 10B-16B, wherein the current block is a first block, the candidate list is a first list, the one or more candidate blocks are a first set of one or more candidate blocks, the candidate block is a first candidate block, and wherein the processing circuitry is configured to generate, for a second block coded in the affine mode, a second candidate list that includes bi-prediction affine motion 1616-639WO01Qualcomm Ref. No. 2503663 WO 59 / 67information of a second set of one or more candidate blocks, and decode the second block using the bi-prediction affine motion information of a second candidate block of the second set of one or more candidate blocks based on performing affine BDOF.

[0250] Clause 18B. The device of any of Clauses 10B-17B, wherein to decode the current block, the processing circuitry is configured to determine a prediction signal based on the refined affine motion information, receive information indicative of residual information indicative of a difference between the prediction signal and samples in the current block, and decode the current block based on the prediction signal and the residual information.

[0251] Clause 19B. A device for encoding video data, the device comprising one or more memories configured to store the video data, and processing circuitry coupled to the one or more memories, the processing circuitry being configured to generate, for a current block coded in affine mode, a candidate list that includes bi-prediction affine motion information of one or more candidate blocks, refine the bi-prediction affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information, and encode the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether BDOF enabling condition is satisfied.

[0252] Clause 20B. The device of Clause 19B, wherein to refine the bi-prediction affine motion information, the processing circuitry is configured to refine the bi-prediction affine motion information using decoder side motion vector refinement (DMVR).

[0253] It is to be recognized that depending on the example, certain acts or events of any of the techniques described herein can be performed in a different sequence, may be added, merged, or left out altogether (e.g., not all described acts or events are necessary for the practice of the techniques). Moreover, in certain examples, acts or events may be performed concurrently, e.g., through multi-threaded processing, interrupt processing, or multiple processors, rather than sequentially.

[0254] In one or more examples, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to a tangible medium such as data storage media, or communication media including any medium that facilitates transfer of a computer program from one place to 1616-639WO01Qualcomm Ref. No. 2503663 WO 60 / 67another, e.g., according to a communication protocol. In this manner, computer-readable media generally may correspond to (1) tangible computer-readable storage media which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code and / or data structures for implementation of the techniques described in this disclosure. A computer program product may include a computer-readable medium.

[0255] By way of example, and not limitation, such computer-readable storage media may include one or more of RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but are instead directed to non-transitory, tangible storage media. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0256] Instructions may be executed by one or more processors, such as one or more DSPs, general purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuitry. Accordingly, the terms “processor” and “processing circuitry,” as used herein may refer to any of the foregoing structures or any other structure suitable for implementation of the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and / or software modules configured for encoding and decoding, or incorporated in a combined codec. Also, the techniques could be fully implemented in one or more circuits or logic elements.1616-639WO01Qualcomm Ref. No. 2503663 WO 61 / 67

[0257] The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set). Various components, modules, or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require realization by different hardware units. Rather, as described above, various units may be combined in a codec hardware unit or provided by a collection of interoperative hardware units, including one or more processors as described above, in conjunction with suitable software and / or firmware.

[0258] Various examples have been described. These and other examples are within the scope of the following claims.1616-639WO01

Claims

Qualcomm Ref. No. 2503663 WO 62 / 67WHAT IS CLAIMED IS:

1. A method of decoding video data, the method comprising:generating, for a current block coded in affine mode, a candidate list that includes bi-prediction affine motion information of one or more candidate blocks; refining the bi-prediction affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information; and decoding the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether BDOF enabling condition is satisfied.

2. The method of claim 1, wherein refining the bi-prediction affine motion information comprises refining the bi-prediction affine motion information using decoder side motion vector refinement (DMVR).

3. The method of claim 1, further comprising receiving information indicating an index in the candidate list that identifies the bi-prediction affine motion information of the candidate block.

4. The method of claim 1, wherein constructing the candidate list comprises constructing a first candidate list for an affine bilateral matching merge mode, the method further comprising constructing a second merge candidate list for a merge mode different than the affine bilateral matching merge mode, the second merge candidate list including a set of motion information, wherein decoding the current block comprises:determining that the refined affine motion information is same as at least one motion information in the set of motion information in the second merge candidate list; anddecoding the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses BDOF independent of whether BDOF enabling condition is satisfied and based on the refined affine motion information being same as at least one motion information in the set of motion information in the second merge candidate list.1616-639WO01Qualcomm Ref. No. 2503663 WO 63 / 675. The method of claim 4, wherein the merge mode different than the affine bilateral matching merge mode includes one of an affine merge mode or an inter-merge mode.

6. The method of claim 1, further comprising:receiving a syntax element indicating that an affine bilateral matching merge mode is enabled,wherein decoding the current block comprises, in response to the syntax element indicating that the affine bilateral matching merge mode is enabled, decoding the current block based on performing per-pixel or subblock based motion compensation that bypasses BDOF independent of whether BDOF enabling condition is satisfied.

7. The method of claim 6, wherein receiving the syntax element comprises receiving the syntax element in a sequence parameter set (SPS), picture parameter set (PPS), at a picture level, slice level, or block level.

8. The method of claim 1, wherein the current block is a first block, the candidate list is a first list, the one or more candidate blocks are a first set of one or more candidate blocks, the candidate block is a first candidate block, the method further comprising:generating, for a second block coded in the affine mode, a second candidate list that includes bi-prediction affine motion information of a second set of one or more candidate blocks; anddecoding the second block using the bi-prediction affine motion information of a second candidate block of the second set of one or more candidate blocks based on performing affine BDOF.

9. The method of claim 1, wherein decoding the current block comprises:determining a prediction signal based on the refined affine motion information; receiving information indicative of residual information indicative of a difference between the prediction signal and samples in the current block; and decoding the current block based on the prediction signal and the residual information.1616-639WO01Qualcomm Ref. No. 2503663 WO 64 / 6710. A device for decoding video data, the device comprising:one or more memories configured to store the video data; andprocessing circuitry coupled to the one or more memories, the processing circuitry being configured to:generate, for a current block coded in affine mode, a candidate list that includes bi-prediction affine motion information of one or more candidate blocks;refine the bi-prediction affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information; anddecode the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether BDOF enabling condition is satisfied.

11. The device of claim 10, wherein to refine the bi-prediction affine motion information, the processing circuitry is configured to refine the bi-prediction affine motion information using decoder side motion vector refinement (DMVR).

12. The device of claim 10, wherein the processing circuitry is configured to receive information indicating an index in the candidate list that identifies the bi-prediction affine motion information of the candidate block.

13. The device of claim 10, wherein to construct the candidate list, the processing circuitry is configured to construct a first candidate list for an affine bilateral matching merge mode, wherein the processing circuitry is configured to construct a second merge candidate list for a merge mode different than the affine bilateral matching merge mode, the second merge candidate list including a set of motion information, and wherein to decode the current block, the processing circuitry is configured to:determine that the refined affine motion information is same as at least one motion information in the set of motion information in the second merge candidate list; anddecode the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses BDOF 1616-639WO01Qualcomm Ref. No. 2503663 WO 65 / 67independent of whether BDOF enabling condition is satisfied and based on the refined affine motion information being same as at least one motion information in the set of motion information in the second merge candidate list.

14. The device of claim 13, wherein the merge mode different than the affine bilateral matching merge mode includes one of an affine merge mode or an inter-merge mode.

15. The device of claim 10, wherein the processing circuitry is configured to:receive a syntax element indicating that an affine bilateral matching merge mode is enabled,wherein to decode the current block, the processing circuity is configured to, in response to the syntax element indicating that the affine bilateral matching merge mode is enabled, decode the current block based on performing per-pixel or subblock based motion compensation that bypasses BDOF independent of whether BDOF enabling condition is satisfied.

16. The device of claim 15, wherein to receive the syntax element, the processing circuitry is configured to receive the syntax element in a sequence parameter set (SPS), picture parameter set (PPS), at a picture level, or slice level.

17. The device of claim 10, wherein the current block is a first block, the candidate list is a first list, the one or more candidate blocks are a first set of one or more candidate blocks, the candidate block is a first candidate block, and wherein the processing circuitry is configured to:generate, for a second block coded in the affine mode, a second candidate list that includes bi-prediction affine motion information of a second set of one or more candidate blocks; anddecode the second block using the bi-prediction affine motion information of a second candidate block of the second set of one or more candidate blocks based on performing affine BDOF.1616-639WO01Qualcomm Ref. No. 2503663 WO 66 / 6718. The device of claim 10, wherein to decode the current block, the processing circuitry is configured to:determine a prediction signal based on the refined affine motion information; receive information indicative of residual information indicative of a difference between the prediction signal and samples in the current block; anddecode the current block based on the prediction signal and the residual information.

19. A device for encoding video data, the device comprising:one or more memories configured to store the video data; andprocessing circuitry coupled to the one or more memories, the processing circuitry being configured to:generate, for a current block coded in affine mode, a candidate list that includes bi-prediction affine motion information of one or more candidate blocks;refine the bi-prediction affine motion information for a candidate block of the one or more candidate blocks to generate refined affine motion information; andencode the current block using the refined affine motion information based on performing per-pixel or subblock based motion compensation that bypasses bidirectional optical flow (BDOF) independent of whether BDOF enabling condition is satisfied.

20. The device of claim 19, wherein to refine the bi-prediction affine motion information, the processing circuitry is configured to refine the bi-prediction affine motion information using decoder side motion vector refinement (DMVR).1616-639WO01

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