Method of making solid state device using nanoimprint lithography

Abstract

A method of making a photonic device includes forming at least one photonic device layer over a substrate, forming a nanoimprint lithography resist layer over the at least one photonic device layer, imprinting the nanoimprint lithography resist layer using a nanoimprint lithography template to form a patterned nanoimprint lithography resist layer having a first pattern, and patterning the at least one photonic device layer to include the first pattern.

Description

Attorney Docket No. 35113-0405WOMETHOD OF MAKING SOLID STATE DEVICE USING NANOIMPRINT LITHOGRAPHYRELATED APPLICATIONSThis application claims the benefit of priority from U.S. Provisional Application No.63 / 773,053, filed March 17, 2025; the entire contents of which is herein incorporated by reference.FIELD

[0001] The present invention relates to methods of making solid state devices using different lithographic patterning techniques to form a nanoimprint lithography template, and using the template to pattern a solid state device layer in a solid state photonic, electronic, and / or hybrid devices.BACKGROUND

[0002] Integrated circuits - photonic, electronic, hybrid, and others - are growing increasingly complex. Often, it is desirable to co-integrate different technologies or chip topologies at a chip or wafer level. There are currently several methods being used to achieve multi-part integration in solid state devices. Such methods may include, for example, die-to-wafer bonding and wafer-to-wafer bonding. However, these methods may not provide satisfactory results in some cases. In particular, for photonic integrated circuits (photonic ICs) there may be a high optical loss penalty when transitioning between different substrates / interposers / chips. Furthermore, some methods may provide improved line edge roughness (LER) but at the cost of design flexibility. Other method exhibit good line critical dimension uniformity (CDU) control but exhibit poor space control.SUMMARY

[0003] An aspect of the present disclosure includes a method of making a photonic device, comprising: forming at least one photonic device layer over a substrate; forming a nanoimprint lithography resist layer over the at least one photonic device layer; imprinting the nanoimprint lithography resist layer using a nanoimprint lithography template to form aAttorney Docket No. 35113-0405WOpatterned nanoimprint lithography resist layer having a first pattern; and patterning the at least one photonic device layer to include the first pattern.

[0004] Another aspect of the present disclosure includes a method of making a nanoimprint lithography template, comprising forming a first resist layer over at least one hard mask layer located over a template substrate; exposing and developing the first resist layer to form a patterned first resist layer; forming a second resist layer over the at least one hard mask layer; exposing and developing the second resist layer to form a patterned second resist layer; patterning the at least one hard mask layer using the patterned first resist layer and the patterned second resist layer in one or more patterning steps to form at least one patterned hard mask layer; and patterning the template substrate using the at least one patterned hard mask layer as a mask.BRIEF DESCRIPTION OF THE DRAWINGS

[0005] For a better understanding of the various described embodiments, reference should be made to the Detailed Description below, in conjunction with the following drawings in which like reference numerals refer to corresponding parts throughout the Figures.

[0006] FIG. 1 is a plan view (e.g., top view) of a solid state device according to one or more embodiments.

[0007] FIG. 2 illustrates a detailed plan view of region of the solid state device in FIG. 1 according to one or more embodiments.

[0008] FIG. 3 A illustrates a vertical cross-sectional view of the first sidewall of the first die according to one or more embodiments.

[0009] FIG. 3B illustrates a vertical cross-sectional view of the second sidewall of the second die according to one or more embodiments.

[0010] FIG. 4 illustrates a vertical cross-sectional view along the line A-A' in FIG. 2 according to one or more embodiments.

[0011] FIG. 5 illustrates a detailed plan view (e.g., top-down view) of the stitching region according to one or more embodiments.

[0012] FIG. 6A illustrates an intermediate structure including the first dies and second dies on the substrate according to one or more embodiments.Attorney Docket No. 35113-0405WO

[0013] FIG. 6B illustrates an intermediate structure including a first reticle (stitching reticle) over the substrate according to one or more embodiments.

[0014] FIG. 6C illustrates the solid state device including the first stitching regions and the second stitching regions according to one or more embodiments.

[0015] FIG. 7 is a flow chart illustrating a method of dividing different areas of a single patterning level into sub-reticle fields and integrating them to form a complete exposure on a wafer according to one or more embodiments.

[0016] FIG. 8 is a flow chart illustrating a method of decomposing an incoming design into sub-reticles, applying stitch-aware optical proximity correction, and fabricating individual masks according to one or more embodiments.

[0017] FIG. 9 is a flow chart illustrating a method of forming a solid state device using sequential application of multiple patterning techniques, including multi-exposure, sidewall image transfer, and extreme ultraviolet (EUV) lithography, according to one embodiment.

[0018] FIGS. 10A - 10E are perspective views of steps in the multi-exposure patterning technique, according to one or more embodiments.

[0019] FIG. 11 is a flow chart illustrating steps in a method of forming a nanoimprint lithography template in accordance with one embodiment.

[0020] FIG. 12 is a flow chart illustrating steps in a method of device wafer patterning using nanoimprint lithography in accordance with various embodiments.

[0021] FIG. 13 is a flow chart illustrating steps in a method of forming a nanoimprint lithography template in accordance with an alternative embodiment.

[0022] FIG. 14 is a simplified schematic diagram illustrating an optical switch, according to various embodiments.

[0023] FIG. 15 is a schematic diagram of a pre-fabricated wafer including stacked layers, according to various embodiments.

[0024] FIG. 16A is a simplified schematic diagram illustrating a cross section of a waveguide structure that shows the direction of an induced electric field, according to various embodiments.

[0025] FIG. 16B is a simplified schematic diagram illustrating a cross section of a waveguide structure, according to various embodiments.Attorney Docket No. 35113-0405WO

[0026] FIG. 17 is a simplified schematic diagram showing a top view of a waveguide structure, according to various embodiments.

[0027] FIG. 18 is a schematic illustration of patterning a barium titanate layer using a hard mask layer as a mask.DETAILED DESCRIPTION

[0028] The drawings are not necessarily drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The same reference numerals refer to the same element or a similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition.

[0029] Various embodiments of the present disclosure are directed using different lithographic patterning techniques to pattern the same device layer, such as a device layer in a solid state photonic, electronic, and / or hybrid devices. Various embodiments allow for the creation of complex patterns in one or more hard masks using two or more different patterning techniques, such as lithography-lithography-etch (i.e., “litho-litho-etch” (LLE)), litho-etch-litho-etch (LELE), sidewall image transfer (also referred to as self-aligned double patterning (SADP)), litho-freeze-litho-etch (LFLE) and / or EUV lithography. The hard mask patterns are then transferred to the same underlying optical, electronic or hybrid device level layer or layers. This approach may ensure precise control over the patterning process, particularly on boundary regions between masks, and provide production of solid state devices with high functionality and performance.

[0030] Various embodiments include methods of fabricating a solid state device which may include applying a first patterning technique to a resist (e.g., photoresist) layer located over a one or more hard masks. The one or more hard masks comprise one or more hard mask layer located over device layers formed on substrate, such as a semiconductor (e.g., silicon) wafer or a silicon on insulator wafer. In one embodiment, the first patterning technique may include multiple exposures of the resist layer to create a first pattern, such asAttorney Docket No. 35113-0405WOperforming a first exposure operation on the resist layer to form an initial pattern, and performing one or more subsequent exposure operations on the resist layer, resulting in the first pattern. The methods may further include developing the resist layer and etching the underlying hard mask to transfer the first pattern into a first hard mask (HM1). The methods may further include applying a second patterning technique, such as the SADP technique, to the same or different resist layer located over the patterned first hard mask to the wafer, and etching the resulting pattern into the first hard mask (HM1) or a second hard mask (HM2). The methods may further include applying a third patterning technique to the same or different resist layer, such as the EUV lithography technique to create a resist pattern, and etching the resist pattern into one of the first hard mask (HM1), the second hard mask (HM2), or an additional (e.g., third) hard mask (HMn). The methods may conclude by transferring all patterns from the first hard mask (HM1), the optional second hard mask (HM2), and / or the optional additional hard mask (HMn) into one or more device layers (e.g., at least one optical, electronic, or hybrid device layer) on the substrate (e.g., wafer).

[0031] FIG. 1 is a plan view (e.g., top view) of a solid state device 100 according to one or more embodiments. As illustrated in FIG. 1, the solid state device 100 may include a substrate 105. The substrate 105 may include, for example, a semiconductor wafer (e.g., silicon wafer). The solid state device 100 may also include one or more first dies 110 (e.g., first primary dies, first die 110) and one or more second dies 120 (e.g., second primary dies, second die 120). The first dies 110 and the second dies 120 may be formed (e.g., grown layer by layer and patterned by a suitable patterning method, etc.) on the substrate 105.

[0032] The first dies 110 may have a first die type. The second dies 120 may have a second die type that is different than the first die type. Each of the first dies 110 and the second dies 120 may include, for example, a photonic IC die, an electronic IC die, a hybrid IC die (e.g., a die including both photonic and electronic elements), or another type of IC die.

[0033] The first dies 110 and second dies 120 may be organized on the substrate 105 into a regular array. In at least one embodiment, about half of the total dies (e.g., the total number of first dies 110 and second dies 120) in the solid state device 100 may include the first dies 110 and the other half may include the second dies 120. In at least one embodiment, the first dies 110 and the second dies 120 may be altematingly formed in the x-direction and altematingly formed in the y-direction. The solid state device 100 may include one or more first stitching regions 130 between a first die 110 and a second die 120 and extendingAttorney Docket No. 35113-0405WOlongitudinally in the y-direction. The solid state device 100 may include one or more second stitching regions 140 between a first die 110 and a second die 120 and extending longitudinally in the x-direction.

[0034] FIG. 2 illustrates a detailed plan view of region 190 of the solid state device 100 in FIG. 1 according to one or more embodiments. As illustrated in FIG. 2, the first die 110 may include a first sidewall 111 and the second die 120a may include a second sidewall 122. The first sidewall 111 of the first die 110 may face the second sidewall 122 of the second die 120a. A first stitching region 130 (e.g., horizontal stitching region) may be located between the first sidewall 111 of the first die 110 and the second sidewall 122 of the second die 120a. In addition, the first die 110 may include a third sidewall 113 and the second die 120b (e.g., third die) may include a fourth sidewall 124. The third sidewall 113 of the first die 110 may face the fourth sidewall 124 of the second die 120b. A second stitching region 140 (e.g., vertical stitching region) may be located between the third sidewall 113 of the first die 110 and the fourth sidewall 124 of the second die 120b.

[0035] FIG. 3 A illustrates a vertical cross-sectional view of the first sidewall 111 of the first die 110 according to one or more embodiments. As illustrated in FIG. 3 A, at the first sidewall 111, the first die 110 may include a substrate layer Illa (e.g., silicon layer). An oxide layer 111b (e.g., buried oxide layer (BOX)) may be located on the substrate layer 1 Ila. The oxide layer 111b may include, for example, silicon dioxide and may serve as a bottom cladding layer. One or more optical waveguides 111c (e.g., channel waveguide) may be located on the oxide layer 11 lb. The optical waveguides 111c may include, for example, a semiconductor material (e.g., silicon, germanium, etc.). Alternatively, the optical waveguides 111c may include an insulating material, such as silicon nitride instead of or in addition to the semiconductor material. An optional blocking layer 11 Id may be located on the optical waveguides 111c. The blocking layer 11 Id may include, for example, a silicide layer, such as nickel silicide. An upper cladding layer 11 le (e.g., silicon dioxide) may be formed on the oxide layer 111b over the optical waveguides 111c and the blocking layer 11 Id. A conductive contact 11 If may be formed in the upper cladding layer 11 le and contact the blocking layer 11 Id. The conductive contact 11 If may include a metal material such as tungsten. Other metals are within the contemplated scope of disclosure.

[0036] A first interconnect layer Illg (e.g., a metal layer or metal trace) may be formed on the upper cladding layer 11 le. An interlayer dielectric layer (IDL) 11 Ih may be formedAttorney Docket No. 35113-0405WOon the first interconnect layer Illg. The IDL 11 Ih may include silicon dioxide, although other dielectric materials are within the contemplated scope of disclosure. A second interconnect layer 11 Ij (e.g., a metal layer or metal trace) may be formed on the IDL 11 Ih and connected to the first interconnect layer 111g by a conductive via Illi (e.g., a metal via) formed in the IDL 11 Ih. Each of the first interconnect layer Illg, conductive via Illi and second interconnect layer 11 Ij may include copper or a copper alloy, although other metals and metal alloys are within the contemplated scope of disclosure.

[0037] FIG. 3B illustrates a vertical cross-sectional view of the second sidewall 122 of the second die 120 according to one or more embodiments. As illustrated in FIG. 3B, at the second sidewall 122, the second die 120 may have a structure that is substantially similar in some respects to the structure of the first sidewall 111 of the first die 110. In particular, at the second sidewall 122, the second die 120 may include a substrate layer 122a similar to the substrate layer 1 Ila, an oxide layer 122b similar to the oxide layer 11 lb, an upper cladding layer 122e similar to upper cladding layer 11 le, a conductive contact 122f similar to conductive contact 11 If, a first interconnect layer 122g similar to first interconnect layer 111g, an IDL 122h similar to IDL 11 Ih, a second interconnect layer 122j similar to second interconnect layer 11 Ij, and a conductive via 122i similar to conductive via Illi.

[0038] As further illustrated in FIG. 3B, the second die 120 at the second sidewall 122 may have a structure that is different in some respects from the structure of the first sidewall 111 of the first die 110. In particular, the optical waveguide 122c at the second sidewall 122 of the second die 120 may different and / or located in a different location than the optical waveguides 111c at the first sidewall 111 of the first die 110. In addition, the second sidewall 122 of the second die 120 may not include a blocking layer corresponding to the blocking layer 11 Id in the first sidewall 111 of the first die 110.

[0039] Thus, a configuration (e.g., structure) of the first sidewall 111 of the first die 110 may be dissimilar to a configuration of the second sidewall 122 of the second die 120.However, there is at least one inactive (e.g., non-critical) layer that is common to both the first sidewall 111 and the second sidewall 122. For example, inactive BEOL layers, such as the first interconnect layer Illg and first interconnect layer 122g, the conductive via Illi and the conductive via 122i, and second interconnect layer 11 Ij and second interconnect layer 122j, are common to both the first sidewall 111 and the second sidewall 122. In another example, inactive (e.g., non-critical) MOL layers, such as the conductive contacts 11 If andAttorney Docket No. 35113-0405WOthe conductive contacts 122f, are common to both the first sidewall 111 and the second sidewall 122. Additionally, other non-critical layers, such as waveguide 111c and waveguide 122c may be common to both the first sidewall 111 and the second sidewall 122. Stitching can occur between one or more of first interconnect layer Illg and first interconnect layer 122g, the second interconnect layer 11 Ij and second interconnect layer 122j, or the optical waveguide 111c and optical waveguide 122c.

[0040] FIG. 4 illustrates a vertical cross-sectional view along the line A-A' in FIG. 2 according to one or more embodiments. The line A-A' with respect to the first die 110 and the second die 120 is also illustrated FIGS. 3A and 3B, respectively.

[0041] As illustrated in FIG. 4, the second die 120 may be located on the substrate 105 adjacent to the first die 110. In particular, the first sidewall 111 of the first die 110 may face the second sidewall 122 of the second die 120, with a gap G formed between the first sidewall 111 and the second sidewall 122. A dielectric encapsulation layer 150 (e.g., silicon dioxide) may be formed on the first die 110 and second die 120 and in the gap G.

[0042] As further illustrated in FIG. 4, the first stitching region 130 may include the first sidewall 111 of the first die 110, the gap G, and the second sidewall 122 of the second die 120. The first stitching region 130 may further include a stitching layer 131 on the dielectric encapsulation layer 150. The stitching layer 131 may extend across the gap G in the x-direction. The first stitching region 130 may also include a stitching via 132 in the encapsulation layer 150 and connecting the stitching layer 131 to the second interconnect layer 11 Ij (first non-critical layer) in the first die 110, and a stitching via 132 in the encapsulation layer 150 and connecting the stitching layer 131 to the second interconnect layer 122j (second non-critical layer) in the second die 120. The stitching layer 131 and the stitching vias 132 may together constitute a stitching structure 135 (first stitch portion). Each of the stitching layer 131 and the stitching vias 132 may include copper or a copper alloy, although other conductive materials, such as metals and metal alloys are within the contemplated scope of disclosure. An upper dielectric layer 160 (e.g., silicon dioxide) may be formed on the encapsulation layer 150 and on the stitching layer 131. Optionally, the respective waveguides 111c and 122c may also be stitched together across the respective first and second die.

[0043] FIG. 5 illustrates a detailed plan view (e.g., top-down view) of the stitching region 130 according to one or more embodiments. The upper dielectric layer 160 has been omittedAttorney Docket No. 35113-0405WOfrom FIG. 5 for ease of explanation. As illustrated in FIG. 5, the stitching region 130 may include a plurality of stitching structures 135. In particular, the plurality of stitching structures 135 may be formed along the length of the stitching region 130 in the y-direction.

[0044] It should also be noted that the second stitching region 140 in FIGS. 1 and 2 may have a configuration that is substantially similar to the configuration of the first stitching region 130. In particular, the second stitching region 140 may include a plurality of stitching structures (second stitch portions) that are substantially similar to the stitching structures 135.

[0045] FIGS. 6A-6C illustrate a method of forming the solid state device 100 according to one or more embodiments. In particular, FIG. 6A illustrates an intermediate structure including the first dies 110 and second dies 120 on the substrate 105 according to one or more embodiments.

[0046] As illustrated in FIG. 6 A, the first dies 110 may be aligned in the x-direction with second dies 120 and also aligned in the y-direction with second dies 120, so as to form a regular array on the substrate 105. In other words, the first dies 110 may alternate with the second dies 120 in both the x-direction and the y-direction. In particular, the first dies 110 and second dies 120 may be aligned on the substrate 105 so that the common inactive (e.g. non-critical) layer at a first sidewall 111 of the first die 110 may therefore be substantially aligned with the common inactive (e.g., non-critical) layer at the second sidewall 122 of the second die 120. The encapsulation layer 150 (see FIG. 4) may then be formed on the first dies 110 and second dies 120.

[0047] FIG. 6B illustrates an intermediate structure including a first reticle 600 (stitching reticle) located over the substrate 105 according to one or more embodiments. While the stitching reticle 600 is shown as covering the area entire substrate 105, it should be noted that the stitching reticle 600 may have an area smaller than the entire substrate 105, and be moved in the x and / or y directions above the substrate 105 during exposure. A photoresist layer (not shown) may be formed on the encapsulation layer 150, and over the first dies 110 and the second dies 120. The photoresist layer may then be patterned using the first reticle 600 as a mask. The first reticle 600 may be used to expose a photoresist layer for forming the first stitching region 130 and / or the second stitching region 140. The exposed photoresist layer is then developed to form a patterned photoresist layer. An etching step may then be performed in order to etch the encapsulation layer 150 so as to form via openings for the stitching vias 132 using the patterned photoresist layer as a mask. The first dies 110 and second dies 120Attorney Docket No. 35113-0405WOmay also be etched at this point as needed to form the stitching structures 135 (see FIGS. 4 and 5). A metal layer (e.g., copper layer) may then be formed on the encapsulation layer 150 and in the via openings, so as to form the stitching vias 132. The metal layer may then be patterned by a photolithographic process so as to form the stitching layer 131. The upper dielectric layer 160 may then be formed on the encapsulation layer 150 and the stitching layer 131.

[0048] It should be noted that in the forming of the first stitching region 130 and / or second stitching region 140, the same photoresist layer may be exposed sequentially in one or more first stitching regions 130 and / or second stitching regions 140. Further, another photoresist layer used in patterning of the active (e.g., critical) layers in the first dies 110 and the second dies 120 may be exposed simultaneously in all of the first dies 110 and the second dies 120, or may be expose sequentially in one or more of the first dies 110 and the second dies 120. Furthermore, a plurality of the inactive (e.g., non-critical) layers in the first dies 110 and the second dies 120 may be formed using the same or similar process steps. Each of the first dies 110 and the second dies 120 may have unique designs at active (e.g., critical) layers and can have unique mask patterns and lithographic exposure conditions for the active layers.

[0049] Further, each of the first dies 110 may be stitched to the one or more second dies 120 using the reticle 600. In particular, the same reticle 600 (e.g., the same horizontal and / or vertical stitching reticle) may be used to form the first stitching regions 130 and second stitching regions 140 at the interfaces between the first dies 110 and second dies 120 (e.g., at the chip interfaces). In at least one embodiment, a small number of new masks (e.g., about 2-5 new masks) for each reticle may be used to form the active layers in the respective dies. However, it may be unnecessary to use a full additional mask set which may require up to 30 masks or more. In at least one embodiment, one or more first dies 110 may be stitched to the one or more second dies 120 using the same horizontal and / or vertical stitching reticle at the interfaces between the first dies 110 and second dies 120 (e.g., at the chip interfaces).

[0050] FIG. 6C illustrates the solid state device 100 including the first stitching regions 130 and the second stitching regions 140 according to one or more embodiments. As illustrated in FIG. 6C, the solid state device 100 may include the first stitching regions 130 and the second stitching regions 140 that may be formed by the reticle 600.Attorney Docket No. 35113-0405WO

[0051] Some embodiments may include a stitching method that divides different areas of a single patterning level (e.g., the same device layer level) into sub-reticle fields, referred to as RX_n. Each sub-reticle field may be developed on a separate reticle substrate (i.e., on separate reticles) using the same different patterning techniques. These fields may be stitched together to form a single, unified patterning level in a resist layer over the substrate, providing the integration of diverse functionalities within a single solid state device (e.g., within the same integrated circuit).

[0052] FIG. 7 illustrates a litho-litho-etch (LLE) method of dividing different areas of a single patterning level into sub-reticle fields and integrating them to form a complete exposure of a resist over a substrate. FIG. 7 also illustrates that each sub-reticle field may be exposed sequentially to achieve a unified patterning level.

[0053] In one embodiment, each sub-reticle field (i.e., the respective mask pattern 712, 714, 716 for each respective reticle 702, 704, 706) may be formed using a specific patterning technique suited to its functional requirements. In one embodiment, a solid state device may comprise an optical quantum computer solid state device which may include a “Sources” section 720 containing one or more optical sources, such as solid state lasers, an “Optical Network” section 722, such a network of solid state optical waveguides, optical delay lines and switching devices (e.g., solid state interferometers), and a “Detector” section 724, such as a solid state superconductor wire located adjacent to a solid state optical waveguide. The superconductor wire loses its superconductivity which increases its resistance when a photon passes through the adjacent optical waveguide and heats the superconducting wire. Thus, the superconductor wire may be used as a part of a solid state electronic detector to detect the passing photon provided to the detector section from the optical network section.

[0054] The first reticle 702 may contain the mask pattern 712 for the “Sources” section 720. In one embodiment, this mask pattern 712 may be formed using an advanced patterning technique, such as a multi-beam mask writer technique. The second reticle 704 may contain the mask pattern 714 for the “Optical Network” section 722. In one embodiment, this mask pattern 714 may be formed using a laser writer technique for precise optical delay line mask pattern formation. The third reticle 706 may contain the mask pattern 716 for the “Detector” section 724. In one embodiment, this mask pattern 716 may be formed using a variableshaped electron beam patterning technique for optical waveguide fabrication near the superconductor wire of the detector. The mask patterns 712, 714, 716 may comprise aAttorney Docket No. 35113-0405WOpattern of a radiation (e.g., optical or UV) opaque material, such as a chromium, located on a radiation transparent reticle substrate, such as a quartz or glass substrate. Thus, the reticles 702, 704, 706 may comprise photolithography exposure masks.

[0055] The sub-reticle fields 712, 714, 716 on different reticles 702, 704, 706 may be stitched onto a single level by applying a resist layer over the device substrate, sequentially exposing the resist layer through all the reticles, and developing resist layer for a particular device patterning level. This process provides seamless integration of the individual sections of the solid state device using a reticle stitching method.

[0056] Referring back to FIG. 7, the first Exposure RX_1 730 may be used to expose the resist layer through the first sub-reticle field on the first reticle 702 containing the “Sources” section mask pattern 712. In other words, radiation (e.g., optical, UV, etc. radiation) is irradiated onto the resist layer located over the substrate through the first reticle 702.

[0057] The second exposure RX_2732 may be used expose the resist layer through the second sub-reticle field on the second reticle 704 containing the “Optical Network” section mask pattern 714.

[0058] The third exposure RX_3 734 may be used expose the resist layer through the third sub-reticle field on the third reticle 706 containing the “Detector” section mask pattern 716.

[0059] These sub-reticle fields may be stitched together to form a single, unified patterning level in the resist layer located over the substrate. The complete RX exposure 708 is the result of the first, second and third exposures that integrates the sources section 720, the optical network section 722, and the detector section 724 exposures through the respective mask patterns 712, 714, 716. This unified exposure 708 ensures that each solid state device section, exposed through different reticles which may be formed using different patterning techniques, is aligned and functions cohesively within the IC.

[0060] FIG. 8 illustrates a detailed process flow for fabricating a solid state device using multiple patterning techniques in accordance with some embodiments.

[0061] In block 802, the process begins with decomposing an incoming design into subreticles (e.g., first, second and third reticles 702, 704 and 706 illustrated in FIG. 7) based on the preferred mask manufacturing technique, labeled as "xx_n." As described above, the techniques include the multi-beam mask writer technique, the laser write technique, the variable-shaped electron beam patterning technique, etc. this operation may help ensure theAttorney Docket No. 35113-0405WOdesign is divided into manageable sections that may be individually processed using different patterning techniques.

[0062] Block 804 assigns the sub-reticle fields to various mask writers according to their specific requirements. These mask writers include a laser writer, a variable-shaped beam (VSB) writer, a multi-beam mask writer, and / or other suitable mask-writing technologies. Each mask writer is selected based on the preferred mask manufacturing technology for the specific sub-reticle field.

[0063] In block 806, stitch-aware optical proximity correction (OPC) is conducted. This operation may include adjusting the mask pattern designs to account for distortions that may occur during the patterning process. These operations may help ensure the patterns align correctly when the sub-reticle fields are stitched together.

[0064] In block 808, stitching designs are added to combine the fields. This operation may integrate the individual sub-reticle fields into a coherent design, preparing them for seamless stitching during exposure of the resist layer on the substrate.

[0065] In block 810, individual mask patterns 712, 714, 716 for each sub-reticle field are fabricated. These mask patterns may be used to transfer the corrected and integrated patterns onto the resist layer located over the substrate using various lithographic techniques.

[0066] In block 812, a ZL mask may formed by exposure to radiation, such as from a laser illuminator, and then etching if "xx" is the first product (i.e., device) level, such as RX.

[0067] In block 814, the device layers are formed over the substrate (e.g., wafer) until the single "xx" layer or layers that requires patterning are formed. The device layers may be deposited using any suitable solid state deposition methods and may optionally be patterned by lithography and etching.

[0068] In block 816, the substrate may coated with the photoresist layer in track to prepare it for the subsequent exposure operations. This coating operation may include applying a resist layer by spin coating or another suitable method over the device layers (e.g., the “xx” device layer) located over the substrate.

[0069] In block 820, the resist layer is sequentially exposed through the sub-reticle fields (xx_l, xx_2, ..., xx_n) using the exposure steps 732, 734 and 736 described above with respect to FIG. 7. This sequential exposure may help ensure that the patterns corresponding to different device sections 720, 722, 724 are accurately transferred to the resist layer while maintaining the precise alignment and pattern integrity.Attorney Docket No. 35113-0405WO

[0070] In block 822, the resist layer may be developed and the underlying hard mask and / or device layer(s) are etched using the patterned (i.e., developed) resist layer as a mask. This operation may include developing the exposed resist to reveal the pattern and etching the underlying layers to transfer the pattern into the underlying layers. The steps in blocks 820 and 822 correspond to the above described litho-litho-etch (LLE) method.

[0071] FIG. 9 illustrates a method of using multiple patterning techniques to fabricate a solid state device in accordance with some embodiments. This method may include sequentially applying different patterning techniques to achieve complex and precise patterns on a wafer. Each patterning technique may be tailored to the IC’s specific functional requirements.

[0072] In block 902, the process may begin with the application of Patterning Technique 1, exemplified by a multi-exposure process. The multi-exposure process may comprise part of the litho-litho-etch (LLE) process described above with respect to FIG. 7 and block 820 of FIG. 8). This technique may include multiple exposures of a first resist layer to create a desired pattern, starting with an initial exposure and followed by additional exposures of the first resist layer to complete the pattern.

[0073] In block 904, following the multiple exposures, the first resist layer may be developed to form a patterned first resist layer. The exposed portions of at least one layer underlying the patterned first resist layer are etched using the patterned first resist layer as a mask. For example, exposed portions of a first hard mask layer (HM1) may be etched using the patterned first photoresist layer as a mask. The first hard mask layer may comprise an insulating material (e.g., silicon oxide, silicon oxide, aluminum oxide, etc.), a conductive material (e.g., a metal nitride, such as titanium nitride, or a metal, such as Ti, W, Ta, Al, etc.), or a semiconductor material (e.g., polysilicon). The patterned first photoresist layer is then removed from the first hard mask layer using ashing or selective etching.

[0074] In block 906, Patterning Technique 2, exemplified by a sidewall image transfer method (e.g., the self-aligned double patterning (SADP) method), may be applied. As shown in FIG. 10A, this technique may include forming device layers 1003 over the substrate (e.g., wafer) 1002, forming a hard mask layer 1004 over the device layers 1003 and forming a second photoresist layer 1006 over a hard mask layer 1004. The device layers 1003 may comprise insulating, semiconductor and / or conductive layers of a photonic, electronic or hybrid device. The hard mask layer 1004 may comprise the above described first hard maskAttorney Docket No. 35113-0405WOlayer or another hard mask layer located below the first hard mask layer. If the hard mask layer 1004 comprises the first hard mask layer, then it may also include a pattern formed in block 904 that is located in another area of the hard mask layer 1004 that is not shown in FIG.10A. If the hard mask layer 1004 comprises a second hard mask layer, then it may be exposed in an opening in the overlying first hard mask layer which is not shown in FIG. 10A. The second photoresist layer 1006 is exposed through another photomask (e.g., reticle) and then developed to form the mandrel pattern shown in FIG. 10 A.

[0075] Referring to FIG. 10B, a spacer material layer 1008 is formed over and between the mandrel pattern in the patterned second photoresist layer 1006. The spacer material layer 1008 may comprise any suitable sidewall spacer material, such as an insulating material, for example silicon oxide or silicon nitride.

[0076] Referring to FIG. 10C, the spacer material layer 1008 is anisotropically etched using a sidewall spacer etch process to form sidewall spacers 1010 on sidewalls of the mandrel pattern in the second patterned photoresist layer 1006.

[0077] Referring to FIG. 10D, the second patterned photoresist layer 1006 is selectively removed relative to the sidewall spacers 1010 by ashing or selective etching to leave spaces 1012 between the sidewall spacers 1010. This forms a sidewall spacer 1010 pattern over the first hard mask layer 1004.

[0078] In block 908 of FIG. 9, the sidewall spacer 1010 pattern may be used as a mask to etch the underlying hard mask layer 1004 to form a patterned hard mask layer 1014. The patterned hard mask layer 1014 may comprise remaining portions of the first hard mask layer or a second hard mask layer. The sidewalls spacers 1010 may then be removed by selective etching or retained in the final device.

[0079] In block 910 of FIG. 9, patterning Technique N, exemplified by extreme ultraviolet (EUV) Lithography, may be applied. This technique may include forming a third resist layer over the patterned hard mask layer 1014 and exposing the third resist layer to EUV radiation followed by developing the exposed third resist layer to create a third resist pattern on the patterned hard mask layer 1014.

[0080] In block 912, the third resist pattern defined during the EUV exposure may be etched into the pattered hard mask layer 1014 or into an underlying hard mask layer. In other words, the patterned third resist layer is used as a mask to etch the first, second or n-th hardAttorney Docket No. 35113-0405WOmask layer (e.g., HM1, HM2, ... HMN). Thus, one or more patterned hard mask layers are located over the device layers on the substrate 1002 after the steps in block 912.

[0081] In block 914, all patterns from the at least one patterned hard mask layer 1014 (e.g., HM1, HM2, and / or HMN) are transferred into the device layers on the substrate 1002. In other words, at least one patterned hard mask layer 1014 is used as a mask to etch one or more underlying device layers on the substrate 1002.

[0082] In block 916, the substrate may continue through the remaining process flow, which may include additional operations, such as deposition of additional device layers, etching of various device layers, and / or planarization of various layers to complete the solid state device.

[0083] This sequential method of multiple patterning techniques may allow for complex and precise patterns on a wafer. Integrating multi-exposure, sidewall image transfer, and EUV lithography enhances the versatility, performance, and precision of ICs. Each section of the IC is optimized for specific functional requirements, leading to superior overall performance.

[0084] While exemplary sequential LLE, SADP and EUV patterning techniques are described above, one or more of LFLE, LELE or SADP with self-aligned cut masks (or block masks) may be used instead of or in addition to the patterning techniques illustrated in FIG. 9. A cut mask includes a rectangular feature at the end of linear patterns. The LELE process differs from the SADP process is that the initial resist pattern 1006 is chemically frozen, and a second resist layer rather than the sidewall spacer layer 1008 is formed over the initial resist pattern 1006. The second resist layer is lithographically patterned, and both the resist patterns are used to etch the underlying hard mask layer 1004 during the same etching step. Furthermore, the LLE, SADP and EUV patterning techniques may be carried out in a different order than that shown in FIG. 9.

[0085] In an alternative embodiment, the method shown in FIG. 7 may be used to pattern different photoresist layers over different device areas of the substrate using different patterning techniques. For example, a first technique is used to pattern the first photoresist layer over a first one of the radiation source region 720, the optical network region 722, and the detector region 724; a second technique is used to pattern the second photoresist layer over a second one of the radiation source region, the optical network region, and the detectorAttorney Docket No. 35113-0405WOregion; and the third technique is used to pattern the third photoresist layer over a third one of the radiation source region, the optical network region, and the detector region.

[0086] By leveraging multiple patterning techniques, the embodiment methods allow for the creation of complex and precise patterns tailored to the specific functional requirements of the solid state devices This co-integration is particularly beneficial for producing advanced quantum computer solid state devices incorporating photonic, electronic, and hybrid components.

[0087] FIGS. 11 and 12 illustrate process steps for fabricating a solid state device using nanoimprint lithography in accordance with some embodiments. The process flow may include multiple exposures of a photoresist followed by patterning the underlying substrate (e.g., wafer or another mold material) to form a template, such as the above described LELE, LLE, LFLE, SADP and / or EUV patterning techniques. Nanoimprint lithography may be useful, for example, to eliminate or reduce the use of complex lithography passes on routine wafer patterning runs.

[0088] FIG. 11 illustrates process steps for forming a master template (i.e., an imprint mold or stamp). The master template may be formed using high-resolution lithographic techniques, such as electron beam lithography, LELE, LLE, LFLE, SADP and / or EUV lithography, to provide sub-lithographic feature dimensions. The generated template may then serve as a patterning tool (i.e., an imprint mold or stamp with a pattern of protrusions and recesses) for imprinting resists on device wafers, allowing for high-precision replication of features with improved uniformity and reduced process variability. Alternatively, the master template may be used to generate additional die-level or wafer-level templates which are used to imprint resists on device wafers.

[0089] The master template generation process may begin with the deposition of a resist layer over a template substrate, followed by exposure using a high-resolution lithography technique. The exposed resist pattern may then be developed and transferred into the underlying template substrate through an etching process, forming a durable imprint mold. In some embodiments, a working template may be replicated from the master template to extend the template’s lifetime and facilitate high-volume manufacturing. The master template may be designed to include alignment marks and stitching features that provide accurate overlay of successive patterning steps, improving process control and integration with subsequent nanoimprint lithography exposures.Attorney Docket No. 35113-0405WO

[0090] In block 1102, the process begins with multiple exposures 1102a, 1102b, 1102n of a resist (e.g., photoresist) coated over the template substrate. The template substrate may comprise any substrate that may be used as a nanoimprint lithography template (i.e., an imprint mold). In one embodiment, the template substrate may comprise a semiconductor substrate, such as a silicon or a compound semiconductor material wafer. In another embodiment, the template substrate may comprise an optically transparent substrate, such as quartz, fused silicon or an optically transparent polymer (e.g., a polydimethylsiloxane “PDMS”) substrate. These exposures define the high-resolution features of the master template, which will later be replicated using nanoimprint lithography. Each exposure may correspond to a distinct patterning pass, allowing for precise definition of complex structures. The exposures may be performed using high-resolution lithography techniques such as electron beam lithography, extreme ultraviolet (EUV) lithography, or deep ultraviolet (DUV) lithography, depending on the required feature dimensions and critical design parameters.

[0091] In some embodiments, the multiple exposures may be used to generate different feature types on the master template. For example, one exposure may define primary device structures, such as waveguides or transistor gates, while another exposure may form alignment marks, stitching features, or metrology structures. The exposures may be performed sequentially with intermediate resist processing steps, for example, to help with accurate pattern placement and minimize overlay errors.

[0092] Additionally, the use of multiple exposures permits the incorporation of advanced patterning techniques, such as litho-freeze-litho-etch (LFLE), litho-etch-litho-etch (LELE), litho-litho-etch (LLE) or SADP, to enhance feature resolution beyond the limitations of single-patterning processes. These techniques may involve freezing or curing intermediate resist layers to preserve prior patterning results while introducing new structures in subsequent exposures. Once the exposures are completed, the resist pattern is developed, and the features are transferred into the master template substrate through an etching process.

[0093] In block 1104, the exposed resist is developed to form a patterned resist. After the multiple exposures in block 1102 are completed, the resist undergoes a development process to selectively remove the exposed or unexposed regions, depending on whether a positive or a negative resist is used. The development step forms the mask pattern that will be etched into template substrate.Attorney Docket No. 35113-0405WO

[0094] The patterned resist is then used as a mask to etch features into exposed portions of the underlying template substrate to form the master template for nanoimprint lithography. The etching process may comprise a dry etching process, such as reactive ion etching (RIE) or inductively coupled plasma (ICP) etching. The choice of etch chemistry and process parameters may be made for a high-fidelity pattern transfer while maintaining aspect ratio control and minimizing line edge roughness (LER). In some embodiments, an intermediate hard mask layer located between the resist and the template substrate may be used to improve pattern fidelity and enhance etch selectivity between the resist and the template substrate.

[0095] Once the etching is complete, any remaining resist material is stripped using ashing or selective etching to expose the final master template features. The resulting master template includes nanoscale patterns (i.e., protrusions and recesses), which are then used for subsequent nanoimprint lithography steps. The master template may also incorporate alignment marks and stitching features to facilitate integration with other patterning techniques or multi-step imprinting processes.

[0096] In some embodiments, additional post-etch treatments such as plasma surface modification or anti-adhesion layer deposition may be applied to enhance the durability of the master template and improve release properties during the imprinting process. These treatments may help to extend the template’s lifetime and ensure consistent pattern transfer across multiple wafers during high-volume manufacturing.

[0097] In one embodiment shown in block 1106, a die-level nanoimprint lithography (NIL) template is formed. This template is designed for pattern replication at the die scale. The die-level NIL template may have the same size as a die to be formed on the device wafer. In one embodiment, the die-level NIL template may be diced from the master template. In another embodiment, the template substrate may comprise a portion of a semiconductor wafer or a small transparent substrate having the same size as the die-level NIL template. In yet another embodiment, the die-level NIL template may be fabricated by transferring the etched features of the master template onto a durable, reusable material suitable for high-precision imprinting.

[0098] The formation of the die-level NIL template typically involves the deposition of a replication material, such as a polymer, fused glass or quartz, onto the master template, followed by a softening process during which the replication material flows into the recesses in the etched features in the master template, such that a contact surface of the replicationAttorney Docket No. 35113-0405WOmaterial includes nanoscale patters that are the inverse of the etched features of the master template. The replication material is then hardened or cured to preserve the nanoscale patterns. Thermoplastic imprint materials or UV-curable polymer imprint materials may be used, depending on the specific NIL process. Once hardened (e.g., by cooling) or cured (e.g., by UV curing), the replicated die-level template is separated from the master template and may be inspected for fidelity, which may be useful for accurate reproduction of critical dimensions and alignment marks.

[0099] Die-level NIL templates may be useful, for example, for applications requiring high-resolution features in localized regions of a device wafer. These templates provide precise patterning of individual dies, allowing for device-specific optimizations in solid state device fabrication. In some embodiments, multiple die-level templates may be formed from a single master template to facilitate parallel processing and extend the lifetime of the master template.

[0100] In another embodiment shown in block 1108, a wafer-level nanoimprint lithography (NIL) template is formed. This template is designed for large-area pattern replication, covering an entire wafer in a single imprinting step. Unlike the die-level NIL template, which is used to pattern individual dies on a device wafer, the wafer-level template is used during simultaneous NIL patterning of multiple dies or large-scale integrated structures on the entire device wafer.

[0101] In one embodiment, the master template formed in block 1104 is used as the wafer-level NIL template. In another embodiment, the wafer-level NIL template may be formed by scaling up the die-level imprinting process. The master template is coated with the above described replication material. The replication material is softened and then either hardened or cured, either thermally or via UV exposure, to form the wafer-level NIL template. The resulting wafer-scale NIL template retains the intricate nanoscale features of the master template while providing high-throughput patterning across an entire wafer.

[0102] Wafer-level NIL templates may be useful, for example, for advanced semiconductor and photonic integrated circuit (PIC) manufacturing, where precise alignment and feature uniformity across large areas are desired. These templates may incorporate stitching regions that facilitate seamless integration of patterns across adjacent reticle fields, ensuring continuity in multi-patterning processes. In some embodiments, the wafer-level NILAttorney Docket No. 35113-0405WOtemplate may also include alignment fiducial (e.g., alignment) marks and overlay correction marks to enhance accuracy during subsequent processing steps.

[0103] The process of FIG. 11 allows for flexibility in nanoimprint lithography applications by permitting fabrication of either die-level or wafer-level NIL templates. Dielevel templates provide precision for localized patterning, while wafer-level templates provide scalable, high-throughput manufacturing with consistent feature replication.

[0104] FIG. 12 illustrates steps for device wafer processing using nanoimprint lithography (NIL). Once the master template and / or optional corresponding nanoimprint lithography templates (either die-level or wafer-level templates) have been generated, these templates are used to transfer nanoscale patterns onto device wafers. The use of NIL during fabrication provides solid-state devices with high-resolution features while reducing the complexity associated with conventional multi-patterning lithography techniques.

[0105] The device wafer processing method includes sequence in which the NIL template is used to imprint patterns into a nanoimprint resist layer located over the wafer. The imprinted resist serves as a mask for subsequent etching steps, transferring the pattern into the underlying device layers. Compared to traditional photolithography, NIL can achieve sub-lithographic resolution without requiring advanced optics or multiple lithographic exposures, making it particularly useful for semiconductor and photonic device manufacturing.Additionally, NIL facilitates large-area patterning and integration of stitching and multi-layer alignment, to enhance design flexibility and device performance. For example, the die-level NIL template may be used for die level replication where intra-field stitching is conducted, while the wafer-level NIL template may be used for complex reticle to reticle stitching.

[0106] The process flow in FIG. 12 illustrates the application of NIL to pattern device wafers, including nanoimprint resist deposition, imprinting, pattern transfer, and postprocessing to provide high-fidelity feature replication. The process begins with the preparation of the device wafer surface, which may include cleaning, planarization, and the deposition of an adhesion-promoting layer to optimize resist adhesion. A nanoimprint resist layer is then applied over the device wafer using spin coating, spray coating, or other deposition methods tailored for NIL compatibility. The resist material is typically selected based on its mechanical properties, etch resistance, and compatibility with the subsequent processing steps.Attorney Docket No. 35113-0405WO

[0107] Once the resist is applied, the device wafer is brought into contact with the nanoimprint lithography template. Depending on whether a die-level or a wafer-level NIL template is used, the imprint process may involve localized (i.e., die-by-die) or full-wafer pattern transfer. The NIL template is pressed into the nanoimprint resist to form a pattern of protrusions and recesses in the nanoimprint resist which corresponds to the inverse of the patten of protrusions and recesses in the NIL template. The imprinting may be performed under controlled pressure for uniform resist deformation, followed by curing through ultraviolet (UV) radiation exposure or thermal annealing to harden the patterned resist.

[0108] For device wafers than need large-scale patterning beyond a single imprint field, stitching techniques may be used to align and merge adjacent imprint regions. This may be useful, for example, so that complex device structures spanning multiple imprint fields maintain design continuity without visible artifacts at the stitching boundaries. Stitch-aware optical proximity correction (OPC) and overlay correction marks may be used to compensate for minor misalignment between imprint passes.

[0109] After imprinting, the device wafer may undergo a resist patterning process to remove any residual resist in recessed areas, followed by an etching step to pattern an underlying hard mask or device layer using the remaining portions of the NIL resist as an etch mask. In some embodiments, additional pre-etch treatments, such as resist reflow or chemical trimming, may be applied to refine feature dimensions in the resist and enhance process uniformity.

[0110] In one embodiment, the result of the NIL and etch process of FIG. 12 is a stitched single layer 'xx,' where complex nanoscale patterns are seamlessly integrated across the device wafer. This layer may serve as a foundation for subsequent patterning steps of a multilayer device fabrication process while maintaining precise feature alignment.

[0111] In block 1202, the device wafer is processed until the stitched single layer 'xx' is formed over the device wafer.

[0112] In block 1204, the wafer is coated with the nanoimprint lithography resist in preparation for the imprinting process. The NIL resist serves as the pattern-transfer medium, capturing the nanoscale features from the imprint template and subsequently acting as a mask for pattern transfer into underlying layers. The coating process typically begins with wafer surface preparation to remove contaminants, improve adhesion, and ensure uniform resist coverage. The process may include a dehydration bake to eliminate moisture, followed by theAttorney Docket No. 35113-0405WOapplication of an adhesion promoter, such as hexamethyldisilazane (HMDS) to enhance resist adhesion to the device wafer surface.

[0113] The NIL resist is then deposited over the device wafer using one of several coating methods, depending on process specification and resist material properties. Examples of deposition techniques include spin coating, spray coating, slot-die coating or blade coating.

[0114] After resist deposition, the device wafer may undergo a soft bake step to remove residual solvents and improve resist stability before imprinting. The bake conditions (temperature and duration) may be controlled to prevent premature resist crosslinking while maintaining the appropriate viscosity for pattern deformation during imprinting.

[0115] The coated resist layer exhibits the rheological properties to facilitate high-fidelity pattern replication while maintaining sufficient etch resistance for subsequent transfer steps. In some embodiments, the NIL resist may be a thermoplastic material that softens under heat and solidifies upon cooling, or a UV-curable polymer that undergoes crosslinking upon exposure to ultraviolet radiation. If a UV-curable NIL resist is used, then the template may comprise a UV transparent substrate, such as fused glass or quartz. Once the device wafer is fully coated with the NIL resist, it is ready for the imprinting process, where a nanoimprint template will be used to transfer the desired pattern into the resist layer.

[0116] In block 1206, nanoimprint lithography is performed to transfer the nanoscale pattern from the imprint template into the NIL resist layer coated over the device wafer. This step defines the device features with high resolution and minimal feature distortion.

[0117] The NIL process begins by bringing the above described nanoimprint lithography template (either the die-level template or the wafer-level template) into controlled contact with the resist-coated device wafer. The imprint template contains the inverse of the desired nanoscale pattern and is aligned to the wafer’s existing structures using alignment marks and overlay control systems. An imprinting technique may be employed based on the type of NIL process, for example, thermal nanoimprint lithography (T-NTL) or ultraviolet nanoimprint lithography (UV-NIL).

[0118] During the NIL process, precise control of imprint pressure and template separation may be used to reduce or prevent defects such as resist voids, pattern collapse, or distortions at the nanoscale. To facilitate a clean release of the template from the resist, an anti-adhesion coating may be applied to the template surface, reducing the likelihood of defects due to resist sticking.Attorney Docket No. 35113-0405WO

[0119] For large-area patterning, multiple imprint fields may be stitched together to form a seamless pattern across the device wafer using the die-level NIL template. Stitching features incorporated into the die-level NIL template design help maintain alignment and ensure continuity across adjacent imprint regions.

[0120] After imprinting, any residual resist layer remaining in the pattern recesses may be removed using an etch-back process which reduces the thickness of the resist to ensure that the underlying layer (e.g., layer xx on the device wafer) is exposed between remaining patterned resist portions for subsequent processing. The device wafer is then ready for pattern transfer into the hard mask or device layer (e.g., layer xx) using an etching step.

[0121] By utilizing NIL, high-resolution patterns can be defined (e.g., with sub- 10 nm precision) while eliminating the need for complex multiple exposure steps associated with conventional photolithography. This process may improve manufacturing efficiency and allows for the integration of advanced device architectures in photonic and electronic devices.

[0122] In block 1208, an etch process is performed to transfer the patterned features from the patterned nanoimprint lithography resist layer into the underlying hard mask or device layer. The etching process typically begins with a descum step, in which a mild oxygen plasma or reactive ion etching (RIE) process removes any residual NIL resist material remaining at the base of the imprinted features. The underlying substrate is fully exposed, preventing or reducing incomplete pattern transfer.

[0123] Once the NIL resist has been fully patterned, a pattern transfer etch is performed using an anisotropic etching technique, such as reactive ion etching (RIE), inductively coupled plasma (ICP) etching, or atomic layer etching (ALE). The choice of etch chemistry depends on the materials involved in the NIL process. For example, fluorine-based etches (e.g., CF4, SFe) may be used for silicon-based layers, while chlorine- or bromine-based etches (e.g., CL, BCE) may be used for III-V semiconductor materials or perovskite materials (e.g., barium titanate, strontium titanate or barium strontium titanate layers of an optical interferometer). Alternatively or additionally, an isotropic wet etching step may be performed using an acid (e.g., hydrofluoric acid, nitric acid, their combination, etc.).

[0124] After the etch process is complete, the remaining NIL resist is stripped using a solvent-based wet strip or an oxygen plasma ashing process, leaving behind the final patterned structure in the device layer or the hard mask layer. If the hard mask layer is present, then it is used as a mask to etch the underlying device layer during the same orAttorney Docket No. 35113-0405WOdifferent etch process. Following etching, additional post-processing steps may be performed, depending on the specific device architecture and fabrication requirements. These may include deposition of additional functional layers, chemical mechanical planarization (CMP) or annealing.

[0125] If the NIL process is part of a multi-layer fabrication method, additional NIL patterning and etching cycles may be performed to define structures at different levels of the device stack. In some embodiments, NIL may be combined with conventional photolithography, extreme ultraviolet (EUV) lithography, or self-aligned patterning techniques to achieve further reductions in feature sizes and improve overlay accuracy.

[0126] FIG. 13 illustrates steps in a method of forming a nanoimprint lithography template in accordance with an alternative embodiment. The process may include multiple patterning schemes beyond simple multi-exposure techniques to define complex NIL template structures on the template substrate with high precision. Thus, the complex structures are formed in the template using multiple patterning schemes once, followed by using the template (or a derived die-level or wafer-level NIL template) to pattern plural device wafers using NIL without the need to use the multiple patterning schemes during processing of plural device wafers. The method steps of FIG. 13 may be similar to the method steps shown in FIG. 9, except that the method steps in FIG. 13 are used to pattern the NIL template rather than a device layer as in FIG. 9.

[0127] In block 1302, the process may begin with the application of Patterning Technique 1, exemplified by a multi-exposure process of a first photoresist layer located over at least one hard mask layer located over the above described template substrate. The multi-exposure process may comprise part of the litho-litho-etch (LLE) process described above with respect to FIG. 7 and block 820 of FIG. 8). This technique may include multiple exposures of a first photoresist layer to create a desired pattern, starting with an initial exposure and followed by additional exposures of the first resist layer to complete the pattern.

[0128] In block 1304, following the multiple exposures, the first photoresist layer may be developed to form a patterned first photoresist layer. The exposed portions of at least one hard mask layer underlying the patterned first photoresist layer are etched using the patterned first photoresist layer as a mask. For example, exposed portions of a first hard mask layer (HM1) may be etched using the patterned first photoresist layer as a mask. The first hard mask layer may comprise an insulating material (e.g., silicon oxide, silicon oxide, aluminumAttorney Docket No. 35113-0405WOoxide, amorphous carbon, etc.), a conductive material (e.g., a metal nitride, such as titanium nitride, or a metal, such as Ti, W, Ta, Al, etc.), or a semiconductor material (e.g., polysilicon). The patterned first photoresist layer is then removed from the first hard mask layer using ashing or selective etching.

[0129] In block 1306, Patterning Technique 2, exemplified by a sidewall image transfer method (e.g., the self-aligned double patterning (SADP) method), may be applied. The SADP method is described above with respect to FIGS. 10A to 10E. However, in this embodiment, the substrate 1002 comprises the NIL template substrate rather than a device wafer. In this embodiment, the device layers 1003 may be omitted. The SADP method forms the sidewall spacer 1010 pattern over the first hard mask layer 1004, as shown in FIG.10D.

[0130] In block 1308 of FIG. 13, the sidewall spacer 1010 pattern may be used as a mask to etch the underlying hard mask layer 1004 to form a patterned hard mask layer 1014. The patterned hard mask layer 1014 may comprise remaining portions of the first hard mask layer or a second hard mask layer. The sidewalls spacers 1010 may then be removed by selective etching or retained in the final NIL template.

[0131] In block 1310 of FIG. 13, patterning Technique N, exemplified by extreme ultraviolet (EUV) Lithography, may be applied. This technique may include forming a third photoresist layer over the patterned hard mask layer 1014 shown in FIG. 10E and exposing the third photoresist layer to EUV radiation followed by developing the exposed third photoresist layer to create a third photoresist pattern on the patterned hard mask layer 1014.

[0132] In block 1312, the third photoresist pattern defined during the EUV exposure may be etched into the pattered hard mask layer 1014 or into an underlying hard mask layer. In other words, the patterned third photoresist layer is used as a mask to etch the first, second or n-th hard mask layer (e.g., HM1, HM2, ... HMN). Thus, one or more patterned hard mask layers are located over the device layers on the template substrate 1002 after the steps in block 1312.

[0133] In block 1314, all patterns from the at least one patterned hard mask layer 1014 (e.g., HM1, HM2, and / or HMN) are transferred into a final underlying hard mask layer, which will serve as the etch mask for defining features in the template substrate.

[0134] In blocks 1316 and 1318, the final hard mask layer is used as a mask during etching of the template substrate to form the master template, as described above. The finalAttorney Docket No. 35113-0405WOhard mask may be removed from the master template by selective etching or it may be retained as part of the master template. As described above with respect to steps 1106 and 1108 of FIG. 11, the master template may comprise either the die-level NIL template in step 1316 or the wafer-level NIL template in step 1318. Alternatively, the master template may be used to form either the die-level NIL template in step 1316 or the wafer-level NIL template in step 1318, as described above with respect to steps 1106 and 1108 of FIG. 11.

[0135] Once the die-level and wafer-level NIL templates are formed, they are ready for integration into the nanoimprint lithography -based manufacturing process, where they will be used to directly pattern device wafers using NIL. The process then advances to device waferlevel processing, where these templates are employed to define the imprint resist pattern used as a mask to during etching of a device layer located over the device wafer, as described above with respect to FIG. 12.

[0136] According to some embodiments, the device layer may comprise a photonic device layer of a photonic device. The photonic device may utilize electro-optic effects, such as free carrier induced refractive index variation in semiconductors, the Pockels effect, and / or the DC Kerr effect to implement modulation and / or switching of optical signals. Thus, embodiments are applicable to both modulators, in which the transmitted light is modulated either ON or OFF, or light is modulated with a partial change in transmission percentage, as well as optical 4es, in which the transmitted light is output on a first output (e.g., waveguide) or a second output (e.g., waveguide) or an optical switch with more than two outputs, as well as more than one input. Thus, embodiments of this disclosure are applicable to a variety of system configurations including an M(input) x N(output) systems that utilize the methods, devices, and techniques discussed herein. Some embodiments also relate to electro-optic phase shifter devices, also referred to herein as phase adjustment sections, which may be employed within switches or modulators.

[0137] FIG. 14 is a simplified schematic diagram illustrating an optical switch, according to various embodiments. Referring to FIG. 14, the switch 1 includes two inputs: Input 1 and Input 2 as well as two outputs: Output 1 and Output 2. As an example, the inputs and outputs of switch 1 may be implemented as optical waveguides configured to support single mode or multimode optical beams. As an example, switch 1 may be implemented as a Mach-Zehnder interferometer coupled with a set of 50 / 50 beam splitters 5 and 7, respectively. As illustrated in FIG. 14, Input 1 and Input 2 are optically coupled to a first 50 / 50 beam splitter 5, alsoAttorney Docket No. 35113-0405WOreferred to as a directional coupler, which receives light from the Input 1 or Input 2 and, through evanescent coupling in the 50 / 50 beam splitter, directs 50% of the input light from Input 1 into waveguide 10 and 50% of the input light from Input 1 into waveguide 112.Concurrently, first 50 / 50 beam splitter 5 directs 50% of the input light from Input 2 into waveguide 10 and 50% of the input light from Input 2 into waveguide 12. Considering only input light from Input 1, the input light is split evenly between waveguides 10 and 12.

[0138] Mach-Zehnder interferometer 20 includes phase adjustment section 22. Voltage Vo may be applied across the waveguide in phase adjustment section 22 such that it may have an index of refraction in phase adjustment section 22 that is controllably varied. Because light in waveguides 10 and 12 may still have a well-defined phase relationship (e.g., they may be in-phase, 180° out-of-phase, etc.) after propagation through the first 50 / 50 beam splitter 5, phase adjustment in phase adjustment section 22 may introduce a predetermined phase difference between the light propagating in waveguides 30 and 32. The phase relationship between the light propagating in waveguides 30 and 32 may cause output light to be present at Output 1 (e.g., light beams are in-phase) or Output 2 (e.g., light beams are out of phase), thereby providing switch functionality as light is directed to Output 1 or Output 2 as a function of the voltage Vo applied at the phase adjustments section 22. Although a single active arm is illustrated in FIG. 14, in other embodiments both arms of the Mach-Zehnder interferometer may include phase adjustment sections.

[0139] As illustrated in FIG. 14, electro-optic switch technologies, in comparison to all-optical switch technologies, use an applied electrical bias (e.g., Vo in FIG. 14) across the active region of the switch to produce optical variation. The electric field and / or current that is induced by application of this voltage bias causes changes in one or more optical properties of the active region, such as the index of refraction or absorbance. Although a Mach-Zehnder interferometer implementation is illustrated in FIG. 14, the disclosure is not limited to this particular switch architecture and other phase adjustment devices are included within the scope of this disclosure, including ring resonator designs, Mach-Zehnder modulators, generalized Mach-Zehnder modulators, and the like.

[0140] The optical switch illustrated in FIG. 14 may include a waveguide structure that has been patterned from a wafer. FIG. 15 illustrates an example wafer that may be received from a wafer manufacturer and etched according to embodiments described herein, toAttorney Docket No. 35113-0405WOproduce the waveguide structure. FIG. 15 illustrates a cross section of a first wafer including a layer stack that may be received as part of a fabrication process for various devices described herein, according to various embodiments. As illustrated, a first insulating substrate layer 202 may be (optionally) disposed beneath a seed layer 204, which is disposed beneath an electro-optic layer 206, which is (optionally) disposed beneath an electrode layer 208, which is (optionally) disposed beneath a second insulating substrate layer 210.Alternatively, the electrode layer 208 may be located between the electro-optic layer 206 and the first insulating substrate layer 202. While FIG. 15 illustrates that each of the five layers 202 to 210 are present, any one or more of these layers may be absent, in various embodiments. In other words, the first wafer may be of various types depending on the specific fabrication method to be employed, and the seed layer, electrode layer, and second substrate layer may be optionally present or not present, as desired. One or more of the layers illustrated in FIG. 15 may be etched to produce an electro-optical component, according to embodiments described herein.

[0141] Each of the layers of the wafer may be of any of a variety of types of materials. For example, the electrode layer 208 may include a conducting material such as a metal, or alternatively they may be composed of a semiconductor material. In various embodiments, the electrode layer may include one of gallium arsenide (GaAs), an aluminum gallium arsenide (AlGaAs) / GaAs heterostructure, an indium gallium arsenide (InGaAs) / GaAs heterostructure, zinc oxide (ZnO), zinc sulfide (ZnS), indium oxide (InO), doped silicon, strontium titanate (STO), doped STO, barium titanate (BTO), barium strontium titanate (BST), hafnium oxide, lithium niobite, zirconium oxide, titanium oxide, graphene oxide, tantalum oxide, lead zirconium titanate (PZT), lead lanthanum zirconium titanate (PLZT), strontium barium niobate (SBN), aluminum oxide, aluminum oxide, doped variants or solid solutions thereof, or a two-dimensional electron gas. For embodiments where the electrode layer may include doped STO, the STO may be either niobium doped or lanthanum doped, or include vacancies, according to various embodiments.

[0142] In various embodiments, the electro-optic layer 206 may include one or more of STO, BTO, BST, hafnium oxide, lithium niobite, zirconium oxide, titanium oxide, graphene oxide, tantalum oxide, PZT, PLZT, SBN, aluminum oxide, aluminum oxide, or doped variants or solid solutions thereof. The electro-optic layer may be composed of a transparentAttorney Docket No. 35113-0405WOmaterial having an index of refraction that is larger than an index of refraction of the first and second insulating substrate layers, in some embodiments.

[0143] FIG. 16A is a simplified schematic diagram illustrating a cross section of an example completed waveguide structure, where the direction of the induced electric field is illustrated with arrows, according to some embodiments. The waveguide structure illustrated in FIG. 16A may be fabricated from the wafer illustrated in FIG. 15 by performing etching techniques of embodiments described herein. FIG. 16A illustrates two electrical contacts, and each electrical contact includes a lead (330 and 332) connected to an electrode (340 and 342). It is noted that, as used herein, the term “electrode” refers to a device component that directly couples to the waveguide structure (e.g., to alter the voltage drop across the waveguide structure and actuate a photonic switch). Further, the term “lead” may refer to a backend structure that couples the electrodes to other components of the device (e.g., the leads may couple the electrodes to a controllable voltage source), but the leads are isolated from and do not directly couple to the waveguide structure. In some embodiments, the leads may be composed of a metal (e.g., copper, gold, etc.), or alternatively, a semiconductor material.

[0144] As illustrated, FIG. 16A illustrates a photonic device including first and second cladding layers, 310 and 312, on either side of the waveguide. It is noted that the terms “first” and “second” are meant simply to distinguish between the two cladding layers, and, for example, the term “first cladding layer” may refer to the cladding layer on either side of the waveguide.

[0145] FIG. 16A further illustrates a slab layer 320 including a first material that is coupled to the first electrode of the first electrical contact and the second electrode of the second electrical contact. In some embodiments, the waveguide structure further includes a ridge portion 351 composed of the first material (or a different material) and coupled to the slab layer, where the ridge portion is disposed between the first electrical contact and the second electrical contact.

[0146] As illustrated in FIG. 16 A, the small arrows show the induced electric field direction which generally points along the positive x-direction through the electrodes of the device. The electric field curves in a convex manner both above and below the electrodes, as illustrated. Furthermore, the large arrow 350 pointing in the positive x-direction illustratesAttorney Docket No. 35113-0405WOthe direction of polarization of an optical mode that may travel through the slab layer and the waveguide.

[0147] FIG. 16B illustrates an architecture where the ridge portion of the waveguide structure 351 is disposed on the top side of the slab layer and extends into a first cladding layer 312, the first electrode and the second electrode are coupled to the slab layer on the bottom side of the slab layer opposite the top side. As illustrated, the combination of the ridge portion and the slab layer has a first thickness 362 greater than a second thickness 360 of the slab layer alone 320, and the excess of the first thickness relative to the second thickness extends into the first cladding layer 312 on the top side of the slab layer 320. As illustrated in FIG. 16B, the first electrode 340 and the second electrode 342 may be coupled to the slab layer 320 on the bottom side of the slab layer opposite the top side. Further, the first electrical contact 330 may be coupled to the first electrode 340 by penetrating through the slab layer 320 from the top side of the slab layer to the bottom side of the slab layer, and the second electrical contact 332 may be coupled to the second electrode 342 by penetrating through the slab layer 320 from the top side of the slab layer to the bottom side of the slab layer.

[0148] FIG. 17 is a top-down view of a photonic phase-shifter architecture of FIGS. 16A and 16B, which may be patterned according to embodiments described herein. As illustrated, the phase-shifter may include first 430 and second 432 leads, first 440 and second 442 electrodes, a slab (e.g., waveguide) layer 420, and a ridge portion of the waveguide structure 451.

[0149] FIG. 18 illustrates an etching method (e.g., ion milling, which is also known as ion beam etching) method for etching BTO (i.e., BaTiCh) electro-optic layer 520. The BTO layer 520 may be patterned by ion beam etching using argon using a hard mask layer 522, such as a silicon oxide hard mask layer 522. During ion milling, argon ions are accelerated towards the BTO layer 520 surface and physically break off barium and titanium atoms. These atoms are then pumped out through the exhaust. Alternatively, the BTO layer 520 may be etched using wet and / or dry chemical etching methods.

[0150] The following are examples of various exemplary embodiments.

[0151] An embodiment of the present disclosure includes a method of making a photonic device, comprising: forming at least one photonic device layer over a substrate; forming aAttorney Docket No. 35113-0405WOnanoimprint lithography resist layer over the at least one photonic device layer; imprinting the nanoimprint lithography resist layer using a nanoimprint lithography template to form a patterned nanoimprint lithography resist layer having a first pattern; and patterning the at least one photonic device layer to include the first pattern.

[0152] According to any one or more embodiments above, the patterning the at least one photonic device layer comprises etching the at least one photonic device layer using the patterned nanoimprint lithography resist layer as a mask, followed by removing the patterned nanoimprint lithography resist layer.

[0153] According to any one or more embodiments above, the method further comprises forming a hard mask layer over the at least one photonic device layer, wherein the nanoimprint lithography resist layer is formed over the hard mask layer; patterning the hard mask layer using the patterned nanoimprint lithography resist layer as a mask to form a patterned hard mask layer having the first pattern; removing the patterned nanoimprint lithography resist layer; and patterning the at least one photonic device layer using the patterned hard mask layer as a mask.

[0154] According to any one or more embodiments above, the at least one photonic device layer comprises a waveguide layer.

[0155] According to any one or more embodiments above, the at least one photonic device layer comprises a barium titanate or barium strontium titanate layer of a Mach-Zehnder interferometer.

[0156] According to any one or more embodiments above, the nanoimprint lithography template is a die-level template.

[0157] According to any one or more embodiments above, the nanoimprint lithography template is a wafer-level template.

[0158] According to any one or more embodiments above, the nanoimprint lithography template is formed by: forming a first resist layer over at least one hard mask layer located over a template substrate; exposing and developing the first resist layer to form a patterned first resist layer; forming a second resist layer over the at least one hard mask layer; exposing and developing the second resist layer to form a patterned second resist layer; patterning the at least one hard mask layer using the patterned first resist layer and the patterned second resist layer in one or more patterning steps to form at least one patterned hard mask layer; and patterning the template substrate using the at least one patterned hard mask layer as a mask.Attorney Docket No. 35113-0405WO

[0159] According to any one or more embodiments above, the nanoimprint lithography template is formed by a litho-litho-etch (LLE) technique, a litho-etch-litho-etch (LELE) technique, a self-aligned double patterning (SADP) technique, or a litho-freeze-litho-etch (LFLE) technique.

[0160] According to any one or more embodiments above, the nanoimprint lithography template is formed by a combination of at least one of a litho-litho-etch (LLE) technique, a litho-etch-litho-etch (LELE) technique, or a litho-freeze-litho-etch (LFLE) technique in combination with at least one of a self-aligned double patterning (SADP) technique or an extreme ultraviolet (EUV) lithography technique.

[0161] Another embodiment of the present disclosure includes a method of making a nanoimprint lithography template, comprising forming a first resist layer over at least one hard mask layer located over a template substrate; exposing and developing the first resist layer to form a patterned first resist layer; forming a second resist layer over the at least one hard mask layer; exposing and developing the second resist layer to form a patterned second resist layer; patterning the at least one hard mask layer using the patterned first resist layer and the patterned second resist layer in one or more patterning steps to form at least one patterned hard mask layer; and patterning the template substrate using the at least one patterned hard mask layer as a mask.

[0162] According to any one or more embodiments above, the nanoimprint lithography template is formed by a litho-litho-etch (LLE) technique in which the patterned first resist layer is hard baked after being exposed and developed; the second resist layer is formed over the at least one hard mask layer and over the hard baked patterned first resist layer; and the at least one hard mask layer is patterned in one patterning step using the patterned first resist layer and the patterned second resist layer as a mask.

[0163] According to any one or more embodiments above, the nanoimprint lithography template is formed by a litho-etch-litho-etch (LELE) technique in which: the at least one hard mask layer comprises an upper hard mask layer overlying a lower hard mask layer; the upper hard mask layer is patterned using the patterned first resist layer as a mask followed by removal of the patterned first resist layer; and the lower hard mask layer is patterned using the patterned second resist layer and the patterned upper hard mask layer after removal of the patterned first resist layer.Attorney Docket No. 35113-0405WO

[0164] According to any one or more embodiments above, the nanoimprint lithography template is formed by a litho-freeze-litho-etch (LFLE) technique in which: the patterned first resist layer is frozen by chemical modification after being exposed and developed; the second resist layer is formed over the at least one hard mask layer and over the frozen patterned first resist layer; and the at least one hard mask layer is patterned in one patterning step using the patterned first resist layer and the patterned second resist layer as a mask.

[0165] According to any one or more embodiments above, the nanoimprint lithography template is formed by a combination of at least one of a litho-litho-etch (LLE) technique, a litho-etch-litho-etch (LELE) technique, or a litho-freeze-litho-etch (LFLE) technique in combination with at least one of a self-aligned double patterning (SADP) technique or an extreme ultraviolet (EUV) lithography technique.

[0166] The preceding description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

Attorney Docket No. 35113-0405WOCLAIMS1. A method of making a photonic device, comprising:forming at least one photonic device layer over a substrate;forming a nanoimprint lithography resist layer over the at least one photonic device layer;imprinting the nanoimprint lithography resist layer using a nanoimprint lithography template to form a patterned nanoimprint lithography resist layer having a first pattern; and patterning the at least one photonic device layer to include the first pattern.

2. The method of claim 1, wherein the patterning the at least one photonic device layer comprises etching the at least one photonic device layer using the patterned nanoimprint lithography resist layer as a mask, followed by removing the patterned nanoimprint lithography resist layer.

3. The method of claim 1, further comprising:forming a hard mask layer over the at least one photonic device layer, wherein the nanoimprint lithography resist layer is formed over the hard mask layer;patterning the hard mask layer using the patterned nanoimprint lithography resist layer as a mask to form a patterned hard mask layer having the first pattern;removing the patterned nanoimprint lithography resist layer; andpatterning the at least one photonic device layer using the patterned hard mask layer as a mask.

4. The method of claim 1, wherein the at least one photonic device layer comprises a waveguide layer.

5. The method of claim 1, wherein the at least one photonic device layer comprises a barium titanate or barium strontium titanate layer of a Mach-Zehnder interferometer.

6. The method of claim 1, wherein the nanoimprint lithography template is a die-level template.Attorney Docket No. 35113-0405WO7. The method of claim 1, wherein the nanoimprint lithography template is a wafer-level template.

8. The method of claim 1, wherein the nanoimprint lithography template is formed by:forming a first resist layer over at least one hard mask layer located over a template substrate;exposing and developing the first resist layer to form a patterned first resist layer; forming a second resist layer over the at least one hard mask layer;exposing and developing the second resist layer to form a patterned second resist layer;patterning the at least one hard mask layer using the patterned first resist layer and the patterned second resist layer in one or more patterning steps to form at least one patterned hard mask layer; andpatterning the template substrate using the at least one patterned hard mask layer as a mask.

9. The method of claim 1, wherein the nanoimprint lithography template is formed by a litho-litho-etch (LLE) technique, a litho-etch-litho-etch (LELE) technique, a self-aligned double patterning (SADP) technique, or a litho-freeze-litho-etch (LFLE) technique.

10. The method of claim 1, wherein the nanoimprint lithography template is formed by a combination of at least one of a litho-litho-etch (LLE) technique, a litho-etch-litho-etch (LELE) technique, or a litho-freeze-litho-etch (LFLE) technique in combination with at least one of a self-aligned double patterning (SADP) technique or an extreme ultraviolet (EUV) lithography technique.IL A method of making a nanoimprint lithography template, comprising:forming a first resist layer over at least one hard mask layer located over a template substrate;exposing and developing the first resist layer to form a patterned first resist layer; forming a second resist layer over the at least one hard mask layer;Attorney Docket No. 35113-0405WOexposing and developing the second resist layer to form a patterned second resist layer;patterning the at least one hard mask layer using the patterned first resist layer and the patterned second resist layer in one or more patterning steps to form at least one patterned hard mask layer; andpatterning the template substrate using the at least one patterned hard mask layer as a mask.

12. The method of claim 11, wherein the nanoimprint lithography template is formed by a litho-litho-etch (LLE) technique in which:the patterned first resist layer is hard baked after being exposed and developed; the second resist layer is formed over the at least one hard mask layer and over the hard baked patterned first resist layer; andthe at least one hard mask layer is patterned in one patterning step using the patterned first resist layer and the patterned second resist layer as a mask.

13. The method of claim 11, wherein the nanoimprint lithography template is formed by a litho-etch-litho-etch (LELE) technique in which:the at least one hard mask layer comprises an upper hard mask layer overlying a lower hard mask layer;the upper hard mask layer is patterned using the patterned first resist layer as a mask followed by removal of the patterned first resist layer; andthe lower hard mask layer is patterned using the patterned second resist layer and the patterned upper hard mask layer after removal of the patterned first resist layer.

14. The method of claim 11, wherein the nanoimprint lithography template is formed by a litho-freeze-litho-etch (LFLE) technique in which:the patterned first resist layer is frozen by chemical modification after being exposed and developed;the second resist layer is formed over the at least one hard mask layer and over the frozen patterned first resist layer; andAttorney Docket No. 35113-0405WOthe at least one hard mask layer is patterned in one patterning step using the patterned first resist layer and the patterned second resist layer as a mask.

15. The method of claim 11, wherein the nanoimprint lithography template is formed by a combination of at least one of a litho-litho-etch (LLE) technique, a litho-etch-litho-etch (LELE) technique, or a litho-freeze-litho-etch (LFLE) technique in combination with at least one of a self-aligned double patterning (SADP) technique or an extreme ultraviolet (EUV) lithography technique.

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