Flared through-hole showerhead and pressure matching undercoat

Abstract

Methods of forming an undercoat on one or more surfaces of a showerhead where the undercoat pressure is equal to, or greater than, the film pressure (e.g., >15 torr or >18 torr) and apparatus with a showerhead having through-holes with a conical frustrum portion and an undercoat disposed on at least a portion of an inner surface of the conical frustrum portion.

Description

Attorney Docket No. LAM1P105WO / 12165-1WOFLARED THROUGH-HOLE SHOWERHEAD AND PRESSURE MATCHING UNDERCOAT RELATED APPLICATION(S)

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.BACKGROUND

[0002] Semiconductor manufacturing includes various processes performed on semiconductor wafers such as deposition, etching, and other treatments. Some exemplary processes include chemical vapor deposition (CVD), chemically enhanced plasma vapor deposition (CEPVD), plasma enhanced chemical vapor deposition (PECVD), sputtering physical vapor deposition (PVD), atomic layer deposition (ALD), thermal ALD (T-ALD), and plasma enhanced ALD (PEALD). Examples of other processes include etching (e.g., chemical etching, plasma etching, reactive ion etching, etc.) and cleaning procedures.

[0003] Atomic layer deposition (ALD) is a technique for depositing a thin film on substrates such as semiconductor wafers through sequential and self-limiting surface reactions. In ALD, film growth is controlled by self-terminating gas-solid surface reactions which enable precise control over thickness and uniformity of films over large areas. This precise control can be advantageous when depositing films in complex shapes such as in 3D-NAND structures. Certain ALD procedures involve flowing a single precursor across the substrate whereupon the precursor adsorbs onto the substrate forming a single-molecule thick layer of material. Through repeated exposure to the precursor over multiple cycles, a thin film of a stack of material layers is gradually formed on the surface of the substrate. Thermal ALD (T-ALD) is carried out in a heated processing chamber where heat is used to drive the reactions.

[0004] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.Attorney Docket No. LAM1P105WO / 12165-1WOSUMMARY

[0005] Certain embodiments pertain to apparatus for facilitating semiconductor processing operations. The apparatus includes a base portion defining a plenum, a faceplate, and an undercoat. The faceplate includes a plurality of through-holes in fluidic communication with the plenum. Each of the through-holes includes a conical frustum portion having a first end with a first diameter and a second end with a second diameter greater than the first diameter. The second end is at a surface of the faceplate configured to face a substrate during operation. The undercoat is disposed on at least a portion of an inner surface of the conical frustum portion of each of the through-holes.

[0006] Certain embodiments pertain to methods that form one or more layers of a first material of an undercoat on one or more surfaces of a showerhead in a semiconductor processing chamber. The one or more layers are formed while the semiconductor processing chamber is at an undercoat pressure. The methods also receive a substrate at a pedestal in the semiconductor processing chamber. The methods also form one or more layers of the first material of a film on the substrate while the semiconductor processing chamber is at a film pressure. The undercoat pressure is equal to, or greater than, the film pressure. In one embodiment, the film pressure is at least 15 torr. In one embodiment, the film pressure is at least 18 torr.

[0007] Certain embodiments pertain to semiconductor fabrication apparatus. The semiconductor fabrication apparatus includes a semiconductor processing chamber having one or more process stations located therewithin. The semiconductor fabrication apparatus also includes a pedestal in each of the one or more process stations, each pedestal configured to support a substrate during operation. The semiconductor fabrication apparatus also includes a showerhead above the pedestal in each of the one or more process stations. The showerhead includes a base portion defining a plenum. The showerhead also includes a faceplate with a plurality of through-holes in fluidic communication with the plenum. Each of the through-holes comprising a conical frustum portion having a first end and a second end with a larger diameter than the first end. The second end is at a surface of the faceplate facing the substrate during operation. The showerhead also includes an undercoat disposed on at least on a portion of an inner surface of the conical frustum portion of each of the through-holes. The semiconductor fabrication apparatus also includes a gas distribution system in fluidic communication with the plenum of the showerhead of each process station. The semiconductor fabrication apparatusAttorney Docket No. LAM1P105WO / 12165-1WOalso includes a radio frequency power supply electrically connected to the showerhead of each process station. The semiconductor fabrication apparatus also includes a vacuum pump in fluidic communication with the semiconductor processing chamber of each process station.

[0008] These and other aspects are described in further detail below with reference to the drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is a schematic diagram of a side view of an example of a semiconductor processing apparatus with a semiconductor processing showerhead for processing a substrate, according to various embodiments.

[0010] FIG. 2 is a schematic diagram of a cross-sectional side view of the showerhead, according to certain embodiments.

[0011] FIG. 3A is a radial cross-sectional illustration of a portion of the showerhead in FIG. 2 with an exemplary through-hole.

[0012] FIG. 3B is a cut away illustration of a portion of the showerhead in FIG. 2 with a clocked baffle plate.

[0013] FIG. 4A is a radial cross-sectional illustration of a through-hole in a showerhead, according to certain embodiments.

[0014] FIG. 4B radial cross-sectional illustration of a through-hole in a showerhead, according to certain embodiments.

[0015] FIG. 5 is a flowchart depicting a method of processing a semiconductor wafer, according to an embodiment.

[0016] FIG. 6 shows a schematic diagram of an example of a multi-station semiconductor processing apparatus, according to some embodiments.

[0017] The figures and components therein may not be drawn to scale.DETAILED DESCRIPTION

[0018] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known processAttorney Docket No. LAM1P105WO / 12165-1WOoperations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.I. Terminology

[0019] As used herein, a "processing chamber" or "semiconductor processing chamber" refers generally to a sealed enclosure in which a semiconductor substrate resides during semiconductor processing operations. The processing chamber may include components associated with delivery of and removal of process gases. It may include components associated with generating a plasma and controlling properties of the plasma within the processing chamber. It may include components for controlling the pressure such as, for example, a pump for pulling vacuum and / or for generating pressure within the processing chamber. In the context of this disclosure, the processing chamber may include a portion of a pedestal on which the substrate resides while it is being processed and a portion of a showerhead. FIG. 1 is a schematic drawing depicting an example of a semiconductor processing chamber 101, according to various embodiments.

[0020] A "pedestal" as used herein may refer to a structure that supports the wafer being processed within the processing chamber. A pedestal may be outfitted with a chuck such as an electrostatic chuck (ESC) to hold a substrate such as a semiconductor wafer in position during processing.

[0021] As used herein, an "undercoat" refers to a stack of material layers that are deliberately formed on one or more interior surfaces of a semiconductor processing chamber after a clean procedure has been performed. Undercoats are applied to the interior surface(s) of the semiconductor processing chamber when a wafer is not present in the semiconductor processing chamber. In various embodiments, an undercoat is formed on at least portions of interior surfaces of through-holes passing through a faceplate of a showerhead of each processing station in a single station or multi-station processing chamber. In various embodiments, the undercoat includes one or more silicon oxide layers (e.g., silane-based silicon dioxide layers or a Tetraethyl orthosilicate-based (TEOS-based) silicon dioxide layers), one or more silicon nitride layers (e.g., Si Nxlayers), and / or one or more silicon carbon layers (e.g., silicon carbide (SiC) layers). In some cases, the undercoat includes the same or similar stack ofAttorney Docket No. LAM1P105WO / 12165-1WOmaterial layers as in the film that will be deposited on the semiconductor wafer that is to be processed in that same semiconductor processing chamber. For example, the film deposited on the semiconductor wafer may include a stack of material layers (e.g., silicon oxide layers) and the undercoat may include a stack with the same arrangement of material layers or a portion of the stack.

[0022] As used herein, an "electrostatic chuck" (ESC) refers to a chuck that uses electrostatic force to clamp a substrate to the chuck during processing. The ESC may use one or more electrodes. Voltages may be applied to the one or more electrodes. The applied voltage may cause current to flow, thereby causing charge to migrate through a dielectric layer between the chuck and the substrate being processed. Opposite charges accumulating at an electrode relative to the substrate causes the substrate to be gripped or clamped to the chuck by electrostatic force. In some cases, the one or more electrodes may be integrated into the ESC, or may be separate from the ESC.

[0023] In certain embodiments, an ESC may refer to the one or more electrodes that generate the electrostatic force. In some embodiments, the ESC may employ a plasma in the circuit. In some embodiments, an ESC may be of a monopolar design that employs one or more electrodes to concurrently apply the same potential to the substrate. In other embodiments, the ESC may be of a multipolar design (e.g., bipolar, tripolar, etc.) to apply different potentials to the substrate. For example, an ESC may be a bipolar design that employs two electrodes to concurrently apply opposing potentials to the substrate.

[0024] As used herein, a "hollow cathode discharge" (HCD) refers to an electrical discharge resulting from arcing between a metal surface in the processing chamber and plasma generated within the chamber. In certain examples, the arcing may occur between the plasma and a bare metal portion of an interior surface of a through-hole in the faceplate of a showerhead. For example, a portion of an interior surface of a through-hole may be without a protective undercoat and during a plasma treatment arcing may occur in regions where the plasma contacts the uncoated bare metal surface.

[0025] The terms "wafer" and "substrate" may be used interchangeably. Those of ordinary skill in the art understand that these terms can refer to a substrate during any of many stages of electronic device fabrication thereon. A wafer or substrate used in the semiconductor device industry typically has a diameter of 200 mm, or 300 mm, or 450 mm. Besides semiconductorAttorney Docket No. LAM1P105WO / 12165-1WOdevices, other work pieces that may take advantage of the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices or components such as backplanes for pixelated display devices, flat-panel displays, micro-electromechanical devices (e.g., actuators and sensors), image sensors (e.g., complementary metal-oxide-semiconductor (CMOS) sensor), and the like. The work piece may be of various shapes, sizes, and materials.II. Introduction

[0026] Semiconductor device fabrication typically involves the deposition of a stack of material layers forming a film on a semiconductor wafer and various treatments to the layers being deposited. Some examples of deposition processes that can be employed include chemical vapor deposition (CVD), chemically enhanced plasma vapor deposition (CEPVD), plasma enhanced chemical vapor deposition (PECVD), sputtering physical vapor deposition (PVD), atomic layer deposition (ALD), thermal ALD (T-ALD), and plasma enhanced ALD (PEALD).

[0027] After a semiconductor processing apparatus is used to fabricate films on a batch of semiconductor wafers (e.g., ten (10) wafers, eleven (11) wafers, twelve (12) wafers, thirteen (13) wafers, fourteen (14) wafers, fifteen (15) wafers, etc.), a chamber clean procedure is typically performed on the interior surfaces of the semiconductor processing chamber. The chamber clean procedure may include flowing a fluorine or oxygen-based gas to etch away or remove byproducts or film layers that may have accumulated on exposed interior surfaces of the chamber. After the clean procedure and before the device fabrication process, the interior surfaces are bare without material accumulation. An undercoat process is performed after the chamber clean procedure to deposit an undercoat onto the interior chamber surfaces. The undercoat is a passivation layer of the same chemistry as the layers that will be deposited on the wafer. The undercoat can prevent reactions between the chamber components and the process gases during wafer processing since those reactive surfaces are coated by the material being deposited. The undercoat includes a stack of material layers similar (e.g., similar order and material of layers) to those of films being deposited on the semiconductor wafers during subsequent processing of the wafers in the batch. Typically, the undercoat is deposited without a wafer present in the semiconductor processing chamber. The undercoat forms on any interior surfaces exposed to (a) the reactants forming the undercoat, and (b) the energy driving the reaction between the reactants. In some cases, one or more interior chamber surfaces may be masked to prevent deposition of the undercoat thereon. Some examples of undercoats areAttorney Docket No. LAM1P105WO / 12165-1WOdescribed in U.S. Patent Application No. 14 / 089,653, filed November 25, 2013 (now U.S. Patent 9,745,658), and titled "CHAMBER UNDERCOAT PREPARATION METHOD FOR LOW TEMPERATURE ALD FILMS," which is hereby incorporated by reference in its entirety.

[0028] According to various embodiments, a fabrication process includes serially applying (multiple cycles) a two-step procedure with (i) a deposition operation for forming a layer of material on a substrate and (ii) a densification operation, which is a plasma treatment for densifying the material layer or layers previously formed on the substrate. The two-step procedure is typically repeated over multiple cycles (e.g., greater than 1000, greater than 2000, etc.) to form, layer-by-layer, a stack of material layers on the substrate until a desired thickness or a desired number of layers is reached. In some cases, the deposition operation is an ALD or T-ALD operation that forms a single-molecule thick layer of material during each cycle. The stack of material layers formed over multiple cycles may include any number of layers and have any thickness appropriate for the implementation. In one implementation, a multi-layer stack has a total thickness of about 1.0 pm. In one implementation, the multi-layer stack includes 20 or more layers and has a total thickness between about 2 pm and about 4 pm. In one implementation, a multi-layer stack has a total thickness of about 3.7 pm. In one implementation, a multi-layer stack includes one hundred (100) or more layers. In one case, a multi-layer stack includes five hundred (500) or more layers. In one implementation, a multilayer stack includes one thousand (1000) or more layers. A stack with more than one thousand (1000) layers may have a total thickness from between about 4 pm and about 12 pm, for example. The two-step procedure may be serially applied to form multi-layer stacks of material layers on various types of substrates. For example, the two-step procedure may be serially applied to form a multi-layered undercoat on interior surfaces of the semiconductor processing chambers or form multi-layer films on semiconductor wafers.

[0029] In certain implementations, the deposition operation of the two-step procedure is a T-ALD operation that involves flowing a single precursor and a co-reactant oxidizer across the substrate whereupon material from the precursor adsorbs onto the substrate forming a singlemolecule thick layer of material (e.g., a silicon oxide layer) on the substrate. During this T-ALD operation, the precursor and oxidizer are pulsed into the semiconductor processing chamber with a predefined duration sufficient to allow the precursor to fully react with the surface. Some examples of durations that may be used include pulse times greater than 0.1 seconds. The reaction is self-limiting in that the precursor reacts only with available reactive sites on theAttorney Docket No. LAM1P105WO / 12165-1WOsurface of the substrate to form a single-molecule thick adsorption layer. Any sites that have already reacted with the precursor will be unavailable until sites are subjected to a treatment (e.g., a plasma treatment, a treatment exposing adsorption layer to radicals, etc.) to form new reactive sites. The excess unreacted precursor is typically purged out of the semiconductor processing chamber using inert gas. In one example implementation, the T-ALD operation forms a silicon oxide layer by flowing a silicon oxide (SiOx) precursor and an oxidizer across the substrate. Some examples of silicon oxide (SiOx) precursors that can be used include an aminosilane silicon oxide precursor (e.g., monoaminosilane, bis(tertbutylamino)silane, and bis(diethylamino)silane, and tris(dimethylamino)silane). Some examples of oxidizers that can be used with silicon oxide (SiOx) precursors include ozone (O3), N2O and O2. In an alternative implementation, the deposition operation is a T-ALD operation that involves serially applying different types of precursors. For example, a first precursor may be flowed across a substrate whereupon material from the first precursor is adsorbed onto the substrate. The first precursor is then flushed from the processing chamber with a non-reactive purge gas after which a second precursor is flowed across the substrate whereupon the second precursor reacts with the first precursor in a self-limiting manner to form a layer. Any unreacted portion of the second precursor is then purged from the processing chamber with a non-reactive purge gas. In other implementations, other types of deposition operations may be used in the two-step procedure such as, for example, thermal CVD or RF densification.

[0030] The densification operation of the two-step procedure can reduce the thickness and increase the density of the layer or layers on the substrate. For example, the density may be reduced during the densification process by more than 1 %, 2%, 3%, 4 %, 5 %, etc. During the densification operation, a radio frequency (RF) field is applied in the processing chamber, which creates a plasma near the surface of the substrate. The plasma bombards the deposited material layer or layers with energetic ions (e.g., Argon ions, or other inert gas ions). This ion bombardment causes atoms in the deposited layer or layers to rearrange and pack closer together, leading to reduced thickness and / or increased density. In one example, the plasma densification operation applies a RF power of at least 1000 kW. Generally speaking, the densification operation is a plasma treatment providing a pulse of RF energy in a primarily inert gas (e.g., Argon) environment. In some cases, however, the processing chamber may also have a small amount of one or more electronegative gases such as oxygen. For example, the processing gas may have an environment that includes between about 1% and 5% of O2Attorney Docket No. LAM1P105WO / 12165-1WOcontent. Densification may advantageously harden the material layer or layers causing surface of the substrate to be more etch resistant. In addition, the densification operation includes a plasma treatment that can form new reactive sites on the surface of the substrate enabling the precursor to react with the newly formed sites during a subsequent deposition operation.

[0031] With pressure, temperature, and other operating parameters maintained at the semiconductor processing chamber, repeated application of the two-step procedure can be used to form a stack of material layers such as an undercoat on the interior surfaces of the semiconductor processing chamber or a film on a semiconductor wafer. In some cases, chamber pressures are between 1 torr and 9 torr. In other cases, processes may utilize much higher pressures such as, e.g., 15 torr, 18 torr, etc. In one example, the semiconductor processing chamber may be held at a pressure of at least 15 torr. In one example, the semiconductor processing chamber may be held at a pressure of at least 18 torr. In one example, the semiconductor processing chamber may be held at a temperature of at least 650 C. In one example, the semiconductor processing chamber may be held at a temperature of at least 550 C.

[0032] However, it has been observed that during the densification operation of certain fabrication processes, intermittent hollow cathode discharges (HCDs) can occur at the outlets of through-holes in the showerhead of the semiconductor processing chamber. For example, when the chamber pressure applied during deposition of undercoats on interior chamber surfaces (which may be referred to as an "undercoat pressure" herein) is much lower than the chamber pressure applied during a subsequent deposition of films on semiconductor wafers (which may be referred to as a "film pressure" herein), HCDs may occur at the through-hole outlets. For purposes of illustration, FIG. 1 includes a schematic representation of HCDs that may occur at outlets 132 of through-holes 130 in a showerhead 110 during a densification operation. In some cases, HCDs may have high enough energy to cause damage to the wafer being processed and / or to the showerhead. Damage caused by HCDs is sometimes referred to herein as "HCD damage." Without being bound by any theory, it is believed that plasma contacting bare metal (without undercoat) at the edges of the straight-bore holes was generating arcing that produces the HCDs. The heat from arcing can melt regions of the showerhead locally and the melted material may become dislodged (flaking off) causing damage to the semiconductor wafer and / or showerhead. The heat from arcing may also cause heat damage to the wafer.Attorney Docket No. LAM1P105WO / 12165-1WO

[0033] Certain embodiments herein pertain to techniques that advantageously control / reduce intensity and number of hollow cathode discharges (HCDs) that may occur at outlets of through-holes in showerheads. Controlling HCDs may reduce damage to semiconductor wafers and / or to showerheads resulting from HCD formation. One technique for controlling HCDs is to include through-holes with a flared portion (e.g., conical frustum shaped portion, ellipse conical shaped portion, etc.) facing the substrate being processed to spread the energy from any HCDs across a larger area. The flared portion may help control plasma / HCD formation inside the holes and away from the wafer. Another technique for controlling HCDs is to include through-holes with smaller diameters to reduce the volume of plasma reaching inside the through-holes which may reduce the likelihood of forming HCDs. Another technique for controlling HCDs, which may be used in conjunction with the above techniques, is a process that includes periodically forming undercoats on interior surfaces of the semiconductor chamber while the chamber is maintained at an undercoat pressure that is equal to, or greater than, (matching) the film pressure applied when forming films on semiconductor wafers in the same semiconductor chamber. The undercoat may protect the interior surfaces of the flared through-holes from HCD / plasma that may be predictably / controllably formed within.

[0034] Without being bound by theory, it is believed that by matching the undercoat pressure to the film pressure, the gases that form the undercoat will be forced into the holes to the same depth that they are during wafer processing operations, thereby causing the undercoat to be formed on the same regions of the interior surfaces of the through-holes that the plasma may contact during the subsequent film deposition process on the wafers. This can be advantageous in ensuring that the regions of the interior surfaces of the through-holes that are exposed to the plasma have a protective undercoat such that the plasma does not contact uncoated, bare regions of the holes, which may result in localized melting of the showerhead material in the holes and generate particulates and contaminants that may reduce wafer yield.

[0035] When undercoat processes were first developed, the semiconductor manufacturing processes for which they were developed were performed at a generally low pressure, e.g., ~2 Torr. Initial undercoat processes simply re-used the same process recipes as were used during such wafer processing operations, but performed them without a wafer present. Such undercoat recipes, after having been shown to work, were able to be re-used with other processes performed at different pressures. The present inventors, however, found that such earlier undercoat process recipes did not result in an undercoat that functioned as effectivelyAttorney Docket No. LAM1P105WO / 12165-1WOwith semiconductor manufacturing processes performed at much higher pressures, e.g., 18 Torr. It was found that the pressure that the undercoat process was performed at unexpectedly contributed to the effectiveness of the undercoat at protecting the showerhead during wafer processing operations. As discussed above, performing the undercoat at pressures less than the pressures used during wafer processing operations caused portions of the through-holes that were later exposed to plasma during wafer processing operations to be deprived of an adequate undercoat. It is believed that such a connection between undercoat process pressure and wafer process pressure was not previously known or recognized, particularly since higher-pressure wafer processes where an undercoat was desirable only recently started being explored.III. Semiconductor Processing Apparatus

[0036] FIG. 1 depicts a schematic diagram of a side view of an example of a semiconductor processing apparatus 100 with a semiconductor processing chamber 101 for processing a substrate 103 (e.g., semiconductor wafer), according to various embodiments. The semiconductor processing chamber 101 may be used in conjunction with systems or components used for various processing techniques such as ALD, T-ALD, PEALD, plasma-enhanced chemical vapor deposition (PECVD), densification, plasma etching, plasma stripping or ashing, sputtering, plasma spraying, and the like. Although a single processing station is described in connection with this illustrated example, additional stations may be included in the semiconductor processing chamber 101 in accordance with alternative embodiments of multistation apparatus (e.g., multi-station semiconductor processing apparatus 600 shown and described in connection with FIG. 6). In the illustrated example, the semiconductor processing apparatus 100 is shown being used in a plasma treatment such as a densification operation of a film process.

[0037] The semiconductor processing apparatus 100 includes a pedestal 170 configured to support and hold the substrate 103 in the semiconductor processing chamber 101 during processing. The pedestal 170 has a base portion 172 and a stem portion 174. At least a portion of the pedestal 170 is disposed within the semiconductor processing chamber 101. It should be understood that the semiconductor processing chamber 101 and pedestal 170 described with reference to FIG. 1 may be designed for a 300-mm semiconductor wafer according to one implementation. Suitable modifications may be made to scale various elements for larger orAttorney Docket No. LAM1P105WO / 12165-1WOsmaller wafers. Pedestal 170 includes an electrostatic chuck (ESC) 179 embedded in the body of the pedestal 170.

[0038] In some embodiments, an ESC may include a collection of electrodes with one or more clamping electrodes and / or one or more blocking electrodes. For example, in FIG. 1, ESC 179 has a collection of electrodes including clamping electrodes 175 and 176 and a blocking electrode 178. Blocking electrode 178 and clamping electrodes 175, 176 may be electrically connected to one or more electrical leads 184. The one or more electrical leads 184 are configured to electrically connect, either directly or indirectly, to at least radio frequency (RF) power supply 182, which may provide direct current (DC) and / or RF power to the electrodes. In one example, two clamping electrodes 175 and 176 may apply identical voltages to substrate 103 to pull (clamp) substrate 103 against pedestal 170 during operation. In an alternate example, clamping electrodes 175 and 176 have opposite voltages (e.g., -500 V and +500 V) to pull substrate 103 against pedestal 170.

[0039] Semiconductor processing apparatus 100 also includes a showerhead 110 positioned above the pedestal 170. The semiconductor processing apparatus 100 includes a gas distribution system 199 in fluidic communication with a process gas inlet 113 of the showerhead 110 for providing one or more processes gases during operation. The showerhead 110 has a base portion 114 and a faceplate 116 with a surface 118 facing the substrate 103. The showerhead 110 includes an interior volume 111 formed in the base portion 114 through which the one or more process gases from the gas distribution system 199 flow to a plurality of through-holes 130 in the faceplate 116 and from the through-holes 130 onto the substrate 103. The interior volume 111 typically includes a plenum formed in the base portion 114. The interior volume 111 of the showerhead 110 is in fluidic communication with an interior volume of the semiconductor processing chamber 101 via the showerhead 110. In this example, the through-holes 130 are cylindrical with a constant diameter.

[0040] In some embodiments, showerheads, including the components of showerhead 110 in FIG. 1 and showerhead 210 in FIG. 2, are made of aluminum, for example, aluminum 6061-T6 (which may include aluminum and small amounts of other materials such as chromium, copper, iron, magnesium, manganese, silicon, titanium, zinc, etc.). Alternatively, the showerheads may be fabricated from a ceramic material e.g., alumina or alumina nitride.Attorney Docket No. LAM1P105WO / 12165-1WO

[0041] A plasma 105 is shown formed between the substrate 103 and the showerhead 110. The plasma 105 may be generated during a plasma treatment such as a densification operation of a film process of a certain fabrication process, according to one implementation. Within the plasma 105 generated, three hollow cathode discharges (HCDs) 106 are shown as formed at the outlets 132 of through-holes 130 as an example. Without being bound by any theory, it is believed that during certain fabrication processes, plasma 105 generated by a plasma treatment may contact a bare metal portion at the edges / rims of through-holes 130 causing arcing that produces HCDs 106. Heat from the HCDs 106 may melt the showerhead 110 locally and create high enough heat to damage a wafer being processed. In some instances, melted material from the showerhead 110 may become dislodged causing damage to the substrate 103 and / or the showerhead 110. Certain techniques described herein (e.g., fabrication process 500 described in connection with FIG. 5 and / or showerhead 210 described in connection with FIG. 2) may be implemented to control and / or avoid creation of HCDs.

[0042] Semiconductor processing apparatus 100 includes a vacuum pump 191 in fluidic communication with the semiconductor processing chamber 101 via an outlet (not shown). Gases may be removed from the semiconductor processing chamber 101 via the outlet. Some examples of gases that may be removed include excess precursor gases, reactant gases, radical species, diluent gases, displacement gases, purge gases, and other gases. The vacuum pump 191 may have suitable throughput and may be sized and powered appropriately to maintain the semiconductor processing chamber 101 at certain process pressures. For example, the vacuum pump 191 may maintain the semiconductor processing chamber 101 at a predefined pressure (e.g., within + / - 10% of predefined pressure, within + / - 5% of predefined pressure, within + / - 1% of predefined pressure, within + / - 0.5 % of predefined pressure, etc.) during one or more operations of a film process during which a film is formed on the substrate 103. This predefined pressure is sometimes referred to herein as a "film pressure." In one aspect, the film pressure is at least 15 torr. In one aspect, the film pressure is at least 18 torr. In one aspect, the film pressure is between 15 and 20 torr. In addition or alternatively, the vacuum pump 191 may maintain semiconductor processing chamber 101 at a predefined pressure (e.g., within + / -10% of predefined pressure, within + / - 5% of predefined pressure, within + / - 1% of predefined pressure, within + / - 0.5 % of predefined pressure, etc.) during one or more operations of an undercoat process during which he substrate 103 is not present in the semiconductor processing chamber 101 and an undercoat is formed on at least one or more surfaces of theAttorney Docket No. LAM1P105WO / 12165-1WOshowerhead 110. This predefined pressure level is sometimes referred to herein as an "undercoat pressure." In one aspect, the undercoat pressure is at least 15 torr. In one aspect, the undercoat pressure is at least 18 torr. In one aspect, the undercoat pressure is between 15 and 20 torr. In various embodiments, the undercoat pressure is equal to, or greater than, the film pressure.

[0043] The semiconductor processing apparatus 100 also includes a radio frequency (RF) generator system with an RF power supply 182 and an impedance matching network 180. The matching network 180 is in electrical communication with the RF power supply 182 to facilitate the transfer of power to supply a radio frequency voltage to the showerhead 110 to form and sustain a plasma 105 within the semiconductor processing chamber 101. In the illustrated example, the plasma 105 is shown formed between the substrate 103 and the showerhead 110 during a plasma treatment such as a densification operation of an undercoat process or a film process. An example of a densification operation is described in connection with FIG. 5. During certain processes, the plasma 105 may reach at least partially into the through-holes 130 of the showerhead 110 when the semiconductor processing chamber 101 is pressurized as described in connection with FIGS.4A and 4B. RF power supply 182 and matching network 180 may be operated at any suitable power that can form the plasma 105 with a desired composition of species.

[0044] Semiconductor processing apparatus 100 also includes a controller 190 that is operatively coupled to matching network 180, RF power supply 182, vacuum pump 191, and gas distribution system 199. The controller 190 includes a processor system and a data system in electrical communication with the processor system to receive data for storage and to retrieve data. The controller 190 may be an analog controller, a discrete logic controller, a programmable array controller (PAL), a programmable logic controller (PLC), a microprocessor, a computer, or any other device capable of carrying out operations for effecting processing operations. In certain implementations, the controller is configured to send control instructions with operational parameters to one or more components of the semiconductor processing apparatus 100. For example, the controller 190 may be configured to determine magnitudes of power to be supplied to the showerhead and clamping and blocking electrodes of the chuck and provide commands based on these magnitudes to the RF power supply 182. As another example, controller 190 may be configured to provide commands to the gas distribution systemAttorney Docket No. LAM1P105WO / 12165-1WO199 to supply prescribed amounts of processing gas from one or more gas sources to the showerhead 210.

[0045] In some cases, the gas distribution system 199 may be coupled to one or more gas sources and may include one or more corresponding valves or other flow control components (e.g., mass flow controllers and / or liquid flow controllers). In some embodiments, controller 190 may be connected to the one or more valves or other flow control components to cause them to switch states and thereby allow different gases or combinations of gases to be flowed at different times and / or flow rates. In some embodiments, the one or more gas sources may be f luidica lly connected to a mixing vessel to allow for blending and / or conditioning of process gases prior to flow over the wafer.

[0046] The RF power supply 182 may be a radio frequency (RF) energy source or other source of energy capable of supplying power to and energizing electrodes to form an electric field. In some exemplary embodiments, RF power supply 182 may include an RF generator (not shown) that is configured to operate at a desired frequency. For example, the RF generator may be configured to operate within a frequency range of 0.2 MHz to 20.0 MHz. In some exemplary embodiments, the RF generator may operate at 13.56 MHz. In some embodiments, the RF generator may operate between 400-430 kHz.

[0047] The matching network 180 may be an impedance matching network that is configured to match an impedance of the RF power supply 182 to an impedance of electrodes connected to the RF generator. In this regard, matching network 180 may be made up of a combination of components, such as a phase angle detector and a control motor; however, in other embodiments, it will be appreciated that the matching network may include other or additional components as well.

[0048] As noted above, components of showerheads according to certain embodiments may advantageously control the energy discharged from HCDs and / or avoid generating HCDs. An example of a showerhead with such components is showerhead 200 described in connection with FIGS. 2, 3A and 3B. FIG. 2 is a schematic diagram of a cross-sectional side view of the showerhead 210, according to certain embodiments. FIG.3A is a radial cross-sectional illustration of a portion of the showerhead 210 in FIG.2 with an exemplary through-hole 230. FIG. 3B is a cut away illustration of a portion of the showerhead 210 in FIG. 2 with the clocked baffle plate 240.Attorney Docket No. LAM1P105WO / 12165-1WO

[0049] According to certain embodiments, showerhead 210 may be part of the semiconductor processing apparatus 100 in FIG. 1. In these embodiments, the showerhead 210 is in communication and arranged with components of the semiconductor processing apparatus 100 in a similar manner in which showerhead 110 is described in connection with FIG. 1 above. For example, showerhead 210 may be positioned above pedestal 170 and gas distribution system 199 may be in fluidic communication with a process gas inlet 213 of the showerhead 210.

[0050] As shown in FIG. 2, showerhead 210 has a stem 212, a base portion 214, and a faceplate 216 with a first surface 218 that can face a substrate (e.g., substrate 103) being processed during operation. The faceplate 216 includes a cylindrical edge portion that couples to the base portion 214. The base portion 214 forms a plenum 211 with a conical frustum portion 217 having a first diameter, Di, 222 and a second diameter, D2, 223. The plenum 211 generally represents a volume, space, or cavity defined between the base portion 214 and the faceplate 216. The plenum 211 may be in fluidic communication with a gas distribution system (e.g., gas distribution system 199) via a process gas inlet 213 for receiving one or more processes gases (e.g., a gaseous precursor and oxidizer, purge gases, etc.) during operation. The plenum 211 may also be in fluidic communication with an interior volume of a semiconductor processing chamber (e.g., semiconductor processing chamber 101) via the showerhead 210.

[0051] Without being bound by any theory, a plenum with a conical frustum portion having a relatively small volume may advantageously enable faster removal of gases such as purge gases from the plenum, which can reduce process cycle time and increase throughput. In one aspect, the first diameter, Di, 222 of plenum 211 is between 0.020 inches and 0.040 inches. In one aspect, the first diameter, D2, 223 of plenum 211 is between 0.100 inches and 0.250 inches.

[0052] The showerhead 210 also includes a clocked baffle plate 240 positioned above a second surface 219 (opposing first surface 218) of the faceplate 216. As shown in FIG. 3B, the clocked baffle plate 240 includes at least two posts 248 for coupling the clocked baffle plate 240 to the second surface 219. The at least two posts 248 maintain the clocked baffle plate 240 at a baffle distance, ds, 249 above a second surface 219. In some instances, distance, ds, 249 can be adjusted, for example, during the fabrication process to adjust flow. The clocked baffle plate 240 includes a plurality of baffle apertures 242 passing through the thickness thereof. The baffle apertures 242 are rotationally offset (clocked) 247 from the through-hole apertures 232 at the second surface 219 of the faceplate 216. Rotationally offsetting the baffle apertures 242 from the through-hole apertures 232 may advantageously reduce jetting of process gas throughAttorney Docket No. LAM1P105WO / 12165-1WOthe through-holes 230, particularly those through-holes 230 that lie directly under the stem 212 of the showerhead 210.

[0053] In some embodiments, showerheads have through-holes with a flared portion (e.g., conical frustum shaped portion, ellipse conical shaped portion, etc.) facing a wafer being processed during operation. An example of a showerhead 210 with a plurality of flared conical frustum shaped portions is shown in FIGS. 2, 3A, and 3B. Without being bound by any theory, the flared portion may spread energy from any HCDs to a larger area than with cylindrical through-holes. Also, a large number of through-holes in the showerhead faceplate and / or through-holes with relatively small diameters may also help spread the energy to a larger area. In addition, increased volume and / or inner surface area of the flared portion of the through-holes may improve spreading of the RF energy, thereby reducing its local intensity. Reducing intensity of RF energy may reduce the likelihood of arcing and prevent direct heat damage to the wafer and prevent melting of the showerhead where melted portions thereof might dislodge and damage the wafer.

[0054] In FIG. 2, the faceplate 216 of the showerhead 210 includes a plurality of through-holes 230 passing therethrough. According to various embodiments, the faceplate 216 may have any number of through-holes 230. In one aspect, the faceplate 216 has between one hundred (100) and two hundred (200) through-holes 230. In one aspect, the faceplate 216 has between fifty (50) and one hundred (100) through-holes 230. In one aspect, the faceplate 216 has more than fifty (50) through-holes. In one aspect, the faceplate 216 has more than three thousand (3000) through-holes.

[0055] As depicted in the example shown in FIG. 3A, each through-hole 230 has a cylindrical portion 234 with a diameter, di, and a conical frustum portion 236 with a first (inner) diameter, di, a second diameter, d2, and a cone angle, e, 238. Each through-hole 230 has a first end 231 and a second end 237. The first end 231 is in fluidic communication with the plenum 211. As depicted in FIG.3B, each through-hole 230 in the plurality of through-holes 230 has a circular aperture 232 at the first surface 218 of the faceplate 216.

[0056] The conical frustum portion may have various dimensions. In one aspect, the conical frustum portion may have a first diameter, di, of at about 0.020 inches. In one aspect, the conical frustum portion may have a first diameter, di, between 0.020 inches and 0.040 inches. In one aspect, the conical frustum portion may have a second diameter, d2, of at about 0.126Attorney Docket No. LAM1P105WO / 12165-1WOinches. In one aspect, the conical frustum portion may have a second diameter, d2, between 0.100 inches and 0.250 inches. In one aspect, the conical frustum portion may have a cone angle, e, of about 40 degrees. In one aspect, the conical frustum portion may have a cone angle, e, of between about 30 degrees and about 90 degrees.

[0057] According to certain embodiments, the through-holes in the faceplate of a showerhead have an undercoat on at least a portion of the interior surfaces of the through-holes. The undercoat may protect these surfaces from damage. The undercoat may cover at least the portion of the interior surfaces that may become in contact with plasma during subsequent deposition procedures to try to prevent arcing and creation of HCDs. The undercoat generally includes one or more material layers similar to the stack of layers being deposited on the semiconductor wafers in subsequent deposition operations in the same semiconductor processing chamber. For example, the same stack of material layers used to form films on semiconductor wafers may also be deposited in the undercoat on the interior surfaces of the semiconductor processing chamber including the portion of the interior surfaces of the through-holes discussed above. In one aspect, the undercoat may include one or more silicon oxide layers. In some cases, the undercoat is disposed over a substantial portion of the interior surface of the conical frustum portion of the through-hole.

[0058] FIG. 3A shows an example of an undercoat 239 disposed over a substantial portion of an interior surface 235 of the conical frustum portion 236 of through-hole 230 and disposed on the second surface 215 of base portion 214 of the faceplate 216. In one aspect, the undercoat 239 may be disposed over a substantial portion of the conical frustum portion 236 covering 100 % or nearly 100% of the interior surface area of the conical frustum portion 236 of through-hole 230. In one aspect, the undercoat 239 may be disposed over a substantial portion of the conical frustum portion 236 covering between 95-99 % of the interior surface area of the conical frustum portion 236 of through-hole 230. The surface area coverage is defined as starting at the second end 237. In one aspect, the undercoat 239 may be disposed over a substantial portion of the conical frustum portion 236 covering between 80-90 % of the interior surface area of the conical frustum portion 236 of through-hole 230. In one aspect, the undercoat 239 may be disposed over a substantial portion of the conical frustum portion 236 covering between 50-90% of the interior surface area of the conical frustum portion 236 of through-hole 230. In one aspect, the undercoat 239 may be disposed over a substantial portion of the conical frustumAttorney Docket No. LAM1P105WO / 12165-1WOportion 236 covering more than 50% of the interior surface area of the conical frustum portion 236 of through-hole 230.

[0059] In certain embodiments, undercoats such as the undercoat 239 in FIG. 3A may be formed during an undercoat process where the processing chamber is at an undercoat pressure that is equal to, or greater than, the film pressure applied during film processes where films are being deposited on semiconductor wafers. For example, the semiconductor processing chamber may be held at an undercoat pressure of at least about 15 torr while an undercoat is formed on interior surfaces of the semiconductor processing chamber and the semiconductor processing chamber may be held at a film pressure of about 15 torr during while films are being deposited on semiconductor wafers. For example, the semiconductor processing chamber may be held at an undercoat pressure of at least about 18 torr while an undercoat is formed on interior surfaces of the semiconductor processing chamber and the semiconductor processing chamber may be held at a film pressure of about 18 torr during while films are being deposited on semiconductor wafers. An example of a fabrication process that includes an undercoat process for forming an undercoat on interior surfaces of a semiconductor processing chamber where the undercoat pressure is equal to, or greater than, film pressure applied during film processes where films are being deposited on semiconductor wafers is described in connection with FIG.5.

[0060] Without being bound by any theory, it is believed that matching the undercoat pressure to the film pressure will help ensure that the undercoat is formed on at least the portion of the interior surfaces of the through-holes in which the plasma may contact during the subsequent film deposition process(es). Forming the undercoat on the portion of the interior metal surfaces exposed to plasma may prevent arcing and creation of HCDs. As used herein, matching the undercoat pressure to the film pressure generally refers to the undercoat pressure (i.e. pressure being maintained at the semiconductor processing chamber during undercoat deposition process) being equal to, or greater than, the film pressure (i.e. pressure being maintained at the semiconductor processing chamber during film deposition process).

[0061] FIGS.4A and 4B depict a portion of a showerhead 410 with a faceplate 416 having a plurality of through-holes includes the exemplary through-hole 430, according to an embodiment. Some of the elements shown in FIGS.4A and 4B are similar or analogous to elements shown in FIG.3A. For the sake of brevity, the prior discussion of such similar or analogous elements with regard to FIG.3A may be assumed to be equally applicable, unlessAttorney Docket No. LAM1P105WO / 12165-1WOindicated otherwise in the following discussion, to the similar or analogous counterparts of those elements in FIGS.4A and 4B that share the same last two digits in their respective callouts as in FIG. 3A.

[0062] In FIGS.4A and 4B, the through-hole 430 includes an undercoat 490 disposed on a portion of the interior surface 435 of the conical frustum portion 436 and disposed on the second surface 415 of base portion 414 of the faceplate 416. In this example, the undercoat 490 was formed in an undercoat process where the semiconductor processing chamber (e.g., semiconductor processing chamber 101 in FIG.l) was at an undercoat pressure (e.g. 2-4 torr) during which the undercoat 490 formed on a portion of the conical frustum portion 436 leaving a region 480 of bare metal surface (e.g., bare Al surface) on the conical frustum portion 436 that may be exposed to plasma under certain conditions.

[0063] FIG.4A depicts a plasma 407 formed during a first film process when the semiconductor processing chamber is at a first film pressure that is at or less than the undercoat pressure (i.e. undercoat pressure equal to, or greater than the first film pressure).FIG.4B depicts a plasma 408 formed during a densification operation of a second film process where the semiconductor processing chamber is at a second film pressure (e.g., greater than 15 torr, greater than 16 torr, greater than 17 torr, greater than 18 torr, etc.) that is much greater than the undercoat pressure. In FIG. 4B, the conditioning plasma 405 is shown reaching a bare Aluminum portion 438 of an inner surface of a through-hole 430 in a faceplate 416 of a showerhead 410.

[0064] For example, the second film pressure may be greater than 15 torr or greater than 18 torr and / or the undercoat pressure may be less than 5 torr, less than 4 torr, less than 3 torr, etc. It has been observed that when a plasma treatment is performed at a high film pressure (e.g., greater than 15 torr, greater than 16 torr, greater than 17 torr, greater than 18 torr, etc.) where the undercoat pressure used to form the undercoat was much lower (e.g., less than 5 torr, less than 4 torr, less than 3 torr, etc.), HCDs were observed to be formed.

[0065] As shown in FIG.4B, the region 480 of bare metal surface at the throat of the conical frustum portion 436 is exposed to plasma 408 generated during a densification operation when the second film pressure is much higher than the undercoat pressure. By comparison, the region 480 of bare metal surface at the throat of the conical frustum portion 436 is not exposed to plasma 407 in FIG.4A generated when the film pressure is lower than the undercoatAttorney Docket No. LAM1P105WO / 12165-1WOpressure. Without being bound by any theory, it is believed that by matching the undercoat pressure to the film pressure, an undercoat is on at least the portion of the interior surfaces of the through-holes in which the plasma may make contact. For example, it is believed that matching the undercoat pressure to a high film pressure (e.g., greater than 15 torr, greater than 16 torr, greater than 17 torr, greater than 18 torr, etc.) may control / reduce HCDs in a high pressure film process.IV. Methods

[0066] FIG. 5 is a flowchart depicting a method of processing a semiconductor wafer in each processing station of a semiconductor processing chamber, according to various embodiments. The semiconductor processing chamber may be a single station or multi-station reaction chamber (e.g., multi-station semiconductor processing apparatus 600 in FIG. 6). One or more operations of the method may be performed by executing instructions in system control software. In some embodiments, system control software may include input / output control (IOC) sequencing instructions for controlling various parameters of the operations of the method. Other computer software and / or programs stored on memory (e.g., memory associated with controller 190) may be employed. Examples of programs or sections of programs for this purpose include a material layer control program for an undercoat process, a material layer control program for a film process, a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0067] At operation 510, a chamber clean procedure is performed to remove built-up residues (e.g., silicon oxide and / or silicon nitride residues) that have been built up on interior surfaces of the semiconductor processing chamber. The chamber components can be cleaned using dry chemistry (with or without plasma) to remove the residues. In one example, the chamber clean procedure includes exposing the single or multi-station semiconductor processing chamber to a halogen-based species to remove material from the upper surface of the pedestal of each process station. In one aspect, exposing the single or multi-station semiconductor processing chamber to a halogen-based species also removes material from one or more additional interior surfaces of the single or multi-station semiconductor processing chamber.

[0068] In one example of a chamber clean procedure, the semiconductor processing chamber is exposed to plasma generated (directly or remotely) from at least one of F2, NF3, or a differentAttorney Docket No. LAM1P105WO / 12165-1WOfluorine-containing cleaning reactant. The chamber components may be exposed to dry chemistry (e.g., plasma) for a duration between about 0.5 seconds and 24 hours, depending on the technique that is used. In some cases, the duration may be between about 0.5 seconds and 2 minutes, or between about 1-30 seconds, or between about 1-15 minutes, or between about 1-60 minutes, or between about 1-24 hours. In some cases, the duration may be at least about 0.5 seconds, at least about 1 second, at least about 10 seconds, at least about 30 seconds, at least about 1 minute, at least about 10 minutes, at least about 30 minutes, or at least about 1 hour. In these or other cases, the duration may be about 24 hours or less, about 1 hour or less, about 30 minutes or less, about 10 minutes or less, about 1 minute or less, about 30 seconds or less, or about 10 seconds or less.

[0069] After a chamber clean process, an undercoat including one or more material layers is deposited on interior surfaces of the semiconductor processing chamber (operation 520). The layers of the undercoat are deposited in situ while there is no semiconductor wafer present in the semiconductor processing chamber. The undercoat may be formed on any interior chamber surface exposed to (a) the reactants that form the undercoat, and (b) the energy to drive the reaction between the reactants. For example, the undercoat may be deposited on at least a portion (e.g. portion of a conical frustum portion 236 or 426 of respective through-holes 230, 430) of the interior surfaces of one or more through-holes in a faceplate of a showerhead in the semiconductor processing chamber. In some cases, one or more interior chamber surfaces may be masked to prevent deposition of the undercoat thereon.

[0070] The layers of the undercoat may be deposited through various techniques including, for example, chemical vapor deposition (CVD) techniques such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), or atomic layer deposition techniques (ALD) such as thermal atomic layer deposition (T-ALD) and plasma enhanced atomic layer deposition (PEALD), or direct metal deposition (DMD), etc. These examples are not intended to be limiting.

[0071] The undercoat is deposited while the semiconductor processing chamber is at an undercoat pressure equal to, or greater than, (matching) the film pressure applied when forming a film on the semiconductor wafer during operation 540. In certain implementations, the layers of the undercoat are deposited using a T-ALD technique. In one of these implementations, the semiconductor processing chamber may be held at an undercoat pressure of at least 15 torr where the film pressure film pressure applied at operation 540 is 15Attorney Docket No. LAM1P105WO / 12165-1WOtorr. In one of these implementations, the semiconductor processing chamber may be held at an undercoat pressure of at least 18 torr where the film pressure applied at operation 540 is 18 torr. In one of these implementations, the semiconductor processing chamber may be held at a temperature of at least 650 C. In one of these implementations, the semiconductor processing chamber may be held at a temperature of at least 550 C.

[0072] In certain implementations, each material layer of the undercoat is deposited using a two-step procedure including (i) a deposition operation for forming a layer of material on the interior surfaces and (ii) a densification operation. The two-step procedure may be repeated for a plurality of cycles (e.g., greater than 10, greater than 15, greater than 20, etc.) to form a stack of material layers on the interior surfaces until a desired thickness or a desired number of layers is reached. The stack of material layers formed over multiple cycles may include various numbers of layers and thicknesses. In one implementation, the multi-layer stack of the undercoat has a thickness of about 1 pm. In one implementation, the multi-layer stack of an undercoat has a thickness between 1 pm and 2 pm. In one implementation, the multi-layer stack of an undercoat has a at least 10 material layers. In one implementation, the multi-layer stack of an undercoat has at least 15 material layers. In one implementation, the multi-layer stack of an undercoat has at least 20 material layers.

[0073] In certain implementations, the two-step procedure is a T-ALD procedure (sometimes referred to as "two-step T-ALD procedure) with a deposition operation that includes flowing a single precursor and a co-reactant oxidizer across the interior surfaces of the semiconductor processing chamber whereupon material from the precursor adsorbs onto the interior chamber surfaces forming a single-molecule thick layer of material (e.g., a silicon oxide layer). The precursor and oxidizer are pulsed into the semiconductor processing chamber with a predefined duration sufficient to allow the precursor to fully react with the surface. In one aspect, the duration is greater than 0.2 seconds. The precursor reacts only with available reactive sites on the surface of the interior surfaces to form a single-molecule thick adsorption layer. Any sites that have already reacted with the precursor will be unavailable until sites are subjected to a treatment (e.g., a plasma treatment, a treatment exposing adsorption layer to radicals, etc.) that forms new reactive sites such as the densification operation described below.

[0074] In one example, a silicon oxide layer is formed by flowing a silicon oxide (SiOx) precursor and an oxidizer across the interior chamber surfaces. Some examples of silicon oxideAttorney Docket No. LAM1P105WO / 12165-1WO(SiOx) precursors that can be used include an aminosilane silicon oxide precursor (e.g., monoaminosilane, bis(tertbutylamino)silane, bis(diethylamino)silane, and tris(dimethylamino)silane). Some examples of oxidizers that can be used with silicon oxide (SiOx) precursors include ozone (O3), N2O and O2.

[0075] In an alternative implementation, the two-step procedure is a T-ALD procedure that involves serially applying different types of precursors. For example, a first precursor may be flowed across a interior chamber surfaces whereupon material from the first precursor is adsorbed onto the interior chamber surfaces. The first precursor is then flushed from the processing chamber with a non-reactive purge gas after which a second precursor is flowed across the interior chamber surfaces whereupon the second precursor reacts with the first precursor in a self-limiting manner to form a layer. Any unreacted portion of the second precursor is then purged from the processing chamber with a non-reactive purge gas.

[0076] In one aspect, the two-step procedure includes (i) flowing a silicon-containing reactant and an oxygen-containing reactant into a semiconductor processing chamber to form a silicon oxide layer of an undercoat on one or more surfaces of a showerhead while the semiconductor processing chamber is at an undercoat pressure. The two-step procedure includes (ii) exposing the one or more surfaces of the showerhead to plasma to densify the silicon oxide layer of the undercoat. In this aspect, the operations of (i) and (ii) may be repeated until the undercoat reaches at least a minimum undercoat thickness (e.g., 1.0 pm) or a minimum number of silicon oxide layers. Some examples of minimum numbers of silicon oxide layers are 2, 3, and 4. In one aspect, the minimum number of silicon oxide layers is at least 2 silicon oxide layers. The minimum number of silicon oxide layers may be in the range of 2-5. Some examples of minimum thickness of the silicon oxide layers are 500 nm, lOOOnm and 1500 nm. The minimum thickness of the silicon oxide layers may be in the range of 100 nm and 2000 nm.

[0077] In one aspect, the two-step procedure includes (i) flowing a silicon-containing reactant and an oxygen-containing reactant into a semiconductor processing chamber to form a silicon oxide layer of a film on the substrate while the semiconductor processing chamber is at a film pressure. The two-step procedure includes (ii) exposing the one or more surfaces of the substrate to plasma to densify the silicon oxide layer. In this aspect, the operations of (i) and (ii) may be repeated until the film reaches at least a minimum film thickness or a minimum number of silicon oxide layers.Attorney Docket No. LAM1P105WO / 12165-1WO

[0078] During the densification operation, a pulse of radio frequency (RF) energy is provided in the semiconductor processing chamber to generate a plasma near the interior chamber surfaces. In one example, the RF power supply applies a high frequency RF power of at least 3000 kW and a low frequency RF power of at least 3000 kW. In one example, the operation applies a RF power of at least 1000 kW. The pulse of RF energy is generally provided in an inert gas (e.g., Argon) environment. In some cases, however, the semiconductor processing chamber may also include a small amount of one or more electronegative gases such as oxygen. For example, the processing gas may have an environment that includes between about 1% and 5% of O2 content.

[0079] The plasma bombards the deposited material layer or layers with the energetic inert gas ions causing atoms in the deposited layer or layers to rearrange and pack closer together, which may reduce the thickness and / or increase the density of the layer or layers that have been deposited. For example, the density may be reduced by more than 1%.

[0080] At operation 530, the semiconductor processing chamber is purged to remove process gases including any unreacted precursor. Such purging may be accomplished by evacuating the semiconductor processing chamber and / or sweeping the semiconductor processing chamber with another gas (e.g., an inert gas in many cases). Purging the semiconductor processing chamber minimizes the risk of an unwanted gas phase reaction between the reactant and another reactant. Such purging may not be necessary (and may therefore be omitted) in certain cases where the reactions are driven by plasma.

[0081] After the undercoat process, the semiconductor processing chamber is typically allowed to cool and / or is actively cooled. At operation 540, the semiconductor wafer is received onto the pedestal in a cool semiconductor processing chamber. A semiconductor processing chamber at a temperature in a range of 50C to 100C may be considered a cool chamber. In one example, a semiconductor wafer may be transferred to each pedestal using a wafer handing system such as, e.g., the wafer handling system 650 in FIG. 6.

[0082] At operation 550, a film process is performed to form one or more material layers of a film onto the semiconductor wafer disposed on the pedestal. The material layers may be deposited using various techniques including, for example, chemical vapor deposition (CVD) techniques such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), orAttorney Docket No. LAM1P105WO / 12165-1WOatomic layer deposition techniques (ALD) such as thermal atomic layer deposition (T-ALD) and plasma enhanced atomic layer deposition (PEALD), or direct metal deposition (DMD), etc. These examples are not intended to be limiting. The film is deposited while the semiconductor processing chamber is maintained at a film pressure. In certain implementations, the layers of the film are deposited onto the semiconductor wafer using a T-ALD technique. In one of these implementations, the semiconductor processing chamber may be held at a film pressure of about 15 torr. In one of these implementations, the semiconductor processing chamber may be held at a film pressure of about 18 torr. In one of these implementations, the semiconductor processing chamber may be held at a temperature of at least 650 C. In one of these implementations, the semiconductor processing chamber may be held at a temperature of at least 550 C.

[0083] In certain implementations, each material layer of the film is deposited using a two-step procedure including (i) a deposition operation for forming a layer of material on the semiconductor wafer (ii) the densification operation described above. The two-step procedure may be repeated for a plurality of cycles (e.g., greater than 10, greater than 15, greater than 20, etc.) to form a stack of material layers on the semiconductor wafer until a desired thickness or a desired number of layers is reached. The stack of material layers formed over multiple cycles may include various numbers of layers and thicknesses. In one implementation, the multi-layer stack of the film has a thickness of about 3.7 pm. In one implementation, the multi-layer stack of a film has a thickness between 3 pm and 5 pm. In one implementation, the multi-layer stack of a film with at least 40 material layers. In one implementation, the multi-layer stack of a film with at least 50 material layers. In one implementation, the multi-layer stack of a film with at least 100 material layers.

[0084] In certain implementations, the two-step procedure used to form the film on the semiconductor wafer is the same two-step T-ALD procedure that serially applies a single precursor as described above with respect to forming an undercoat. In other implementations, the two-step procedure used to form the film on the semiconductor wafer is the same two-step T-ALD procedure that serially applies different types of precursors as described above with respect to forming an undercoat.

[0085] In one embodiment, the method described in connection with FIG. 5 further includes a jitterbugging procedure performed before the cleaning procedure at operation 510. The jitterbugging procedure includes sanding the surface of the faceplate of the showerhead toAttorney Docket No. LAM1P105WO / 12165-1WOprepare the surface for adhesion of the undercoat. For example, the surface may be sanded with a vibratory sanding apparatus in conjunction with bonded abrasive grain media or fiber pads.- Batch basis

[0086] The semiconductor wafers that are processed in a particular semiconductor processing chamber in between cleaning operations is referred to herein as a batch. At least some of the semiconductor wafers in a batch are processed serially over time. In other words, this batch processing used herein is different from batch processing where all substrates in the batch are processed simultaneously. In the batch processing used herein, at least some of the substrates within the batch are processed at different times. However, it is understood that certain semiconductor processing chambers such as the multi-station semiconductor processing apparatus 600 shown in and described in connection with FIG. 6 are configured to process multiple substrates simultaneously, and that in such cases, certain substrates within a batch can be processed simultaneously. In one example, an undercoat is formed on one or more interior surfaces of a freshly cleaned semiconductor processing chamber and the semiconductor processing chamber is used to deposit film on one semiconductor wafer at a time, and the semiconductor processing chamber is cleaned after the batch of wafers (e.g., 10 wafers, 20 wafers, etc.) is processed. In one case, the batch includes ten (10) wafers. In this case, the batch includes the ten (10) wafers that were processed between subsequent chamber cleans. In another example, an undercoat is formed on one or more internal surfaces of a freshly cleaned semiconductor processing chamber and semiconductor processing chamber is used to deposit film on two wafers at a time. In one case, the batch of wafers includes 4 wafers and the semiconductor processing chamber is cleaned after twelve (12) wafers are processed. In this case, the batch includes the twelve (12) wafers that were processed between subsequent chamber cleans.

[0087] In certain implementation, an undercoat is formed on one or more interior surfaces of a semiconductor processing chamber in an in situ process on a batch basis between chamber clean procedures. For example, in one implementation of the method shown and described in connection with FIG. 5, operations 540 and 550 are performed multiple times to process a batch of wafers. Once the batch is complete, the method returns to operation 510 to perform a chamber clean procedure.Attorney Docket No. LAM1P105WO / 12165-1WOV. Multi-station semiconductor processing apparatus

[0088] FIG. 6 shows a schematic diagram of an example of a multi-station semiconductor processing apparatus 600 including a plurality of processing stations, according to some embodiments. At least one of the process stations may include the showerhead 210 in FIG. 2 and may be configured to perform the method described in connection with FIG.5, according to some implementations.

[0089] The multi-station semiconductor processing apparatus 600 includes an inbound load lock 602 and an outbound load lock 604, either or both of which may include a remote plasma source. A robot 606 at atmospheric pressure is configured to move wafers from a cassette loaded through a pod 608 into inbound load lock 602 via an atmospheric port 610. A wafer is placed by the robot 606 on a pedestal 612 in the inbound load lock 602, the atmospheric port 610 is closed, and the load lock is pumped down. Where the inbound load lock 602 includes a remote plasma source, the wafer may be exposed to a remote plasma to treat the substrate surface in the load lock prior to being introduced into a semiconductor processing chamber 601. Further, the wafer also may be heated in the inbound load lock 602 as well, for example, to remove moisture and adsorbed gases. Next, a chamber transport port 616 to semiconductor processing chamber 601 is opened, and another robot (not shown) places the wafer into the chamber on a pedestal of a first station shown in the chamber for processing. While the implementation depicted in FIG. 6 includes load locks, it will be appreciated that, in some implementations, direct entry of a wafer into a process station may be provided.

[0090] The depicted semiconductor processing chamber 601 includes four process stations, numbered from 1 to 4 in the implementation shown in FIG.6. Each station has a heated pedestal (shown at 618 for station 1), and gas line inlets. It will be appreciated that in some implementations, each process station may have different or multiple purposes. For example, in some implementations, a process station may be configured to perform deposition and etch process operations. In some implementations, a process station may be configured to perform deposition and treatment process operations. In some implementations, a process station may be configured for etch and treatment operations. In some implementations, a process station may be configured for deposition operations only. While the depicted semiconductor processing chamber 601 includes four stations, it will be understood that a semiconductor processing chamber 601 according to the present disclosure may have any suitable number of stations. For example, in some implementations, a semiconductor processing chamber 601 mayAttorney Docket No. LAM1P105WO / 12165-1WOhave five or more stations, while in other implementations a semiconductor processing chamber 601 may have three or fewer stations.

[0091] FIG. 6 depicts an implementation of a wafer handling system 691 for transferring wafers within semiconductor processing chamber 601. In some implementations, wafer handling system 691 may transfer wafers between various process stations and / or between a process station and a load lock. It will be appreciated that any suitable wafer handling system may be employed. Non-limiting examples include wafer carousels and wafer handling robots. FIG. 6 also depicts an implementation of a system controller 690 employed to control process conditions and hardware states of the multi-station semiconductor processing apparatus 600. System controller 690 may include one or more memory devices 656, one or more mass storage devices 654, and one or more processors 652. Processor 652 may include a CPU or computer, analog, and / or digital input / output connections, stepper motor controller boards, etc.

[0092] In some implementations, system controller 690 controls all of the activities of the multi-station processing semiconductor apparatus 600. System controller 690 executes system control software 658 stored in mass storage device 654, loaded into memory device 656, and executed on processor 652. Alternatively, the control logic may be hard coded in the system controller 690. Applications Specific Integrated Circuits, Programmable Logic Devices (e.g., field-programmable gate arrays, or FPGAs) and the like may be used for these purposes. In the following discussion, wherever "software" or "code" is used, functionally comparable hard coded logic may be used in its place. System control software 658 may include instructions for controlling the timing, mixture of gases, gas flow rates, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and / or susceptor position, and other parameters of a particular process performed by the multi-station semiconductor processing apparatus 600. System control software 658 may be configured in any suitable way. For example, various process component subroutines or control objects may be written to control operation of the process components used to carry out various processes. System control software 658 may be coded in any suitable computer readable programming language.

[0093] In some embodiments, the system controller 690 may be configured with instructions to perform the following operations of the method described with reference to FIG. 5. MultipleAttorney Docket No. LAM1P105WO / 12165-1WOstations in the semiconductor processing chamber 601 may be equipped to process a wafer in the station using the method described with reference to FIG.5.

[0094] In some implementations, system control software 658 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. Other computer software and / or programs stored on mass storage device 654 and / or memory device 656 associated with system controller 690 may be employed in some implementations. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0095] As noted above, depending on the process step or steps to be performed by the multistation semiconductor processing apparatus 600, the system controller 690 might communicate with one or more of other circuits or modules, other components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0096] In various embodiments, a semiconductor fabrication apparatus includes a controller (e.g., system controller 690) configured to execute instructions. In one aspect, the executed instructions are configured to cause a vacuum pump to generate an undercoat pressure during an undercoat deposition process that is equal to, or greater than, a film pressure (e.g., at least 18 torr) during a film deposition process. In one instance of this aspect, the executed instructions are further configured to cause the radio frequency power supply to supply a radio frequency voltage to the showerhead to generate a plasma between the pedestal and the showerhead. In another aspect, the executed instructions are configured to (i) cause the vacuum pump to generate an undercoat pressure at the semiconductor processing chamber, (ii) cause the gas distribution system to flow a silicon-containing reactant and an oxygencontaining reactant into the semiconductor processing chamber to form a silicon oxide layer of the undercoat on one or more surfaces of the showerhead while the semiconductor processing chamber is at the undercoat pressure, wherein the undercoat pressure is equal to, or greater than, a film pressure at the semiconductor processing chamber during a film deposition process in which a film is formed on the substrate; and (iii) cause the radio frequency power supply to supply a radio frequency voltage to the showerhead to generate a plasma between the pedestal and the showerhead to densify at least the silicon oxide layer formed on the one orAttorney Docket No. LAM1P105WO / 12165-1WOmore surfaces of the showerhead in (ii). In one instance of this aspect, the executed instructions are further configured to repeat (ii) and (iii) until the undercoat reaches at least a minimum undercoat thickness (e.g., 1.0 pm) or a minimum number of silicon oxide layers.

[0097] As discussed above, systems for applying undercoats (or for using showerheads having undercoats as described herein) may include electronics for controlling their operation during such processing or pre-processing operations. The electronics may be referred to generally as a "controller," and may control various components or subparts of the system or systems. The controller, depending on the processing requirements and / or the type of system, may be programmed to control any of the systems disclosed herein, including operation of the various valves and / or sensors that may be incorporated into semiconductor processing tool and operated in order to provide an undercoat or process a substrate as discussed herein.

[0098] Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular set of gas flows or other operations.

[0099] The controller, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or all or a part of a fab host computer system, which can allow for remote access of the wafer processing and / or maintenance operations. The computer may enable remote access to the system to monitor current progress of fabrication or maintenance operations, examine a history of past fabrication or maintenance operations, examine trends or performance metrics from a plurality of fabrication or maintenance operations, to change parameters of current processing or maintenance, to set processing or maintenance steps to follow a current process or maintenance operation, or to start a new process or maintenance operation. In some examples, a remote computer (e.g. a server) can provide process recipes or maintenance instructions to a system over a network, which may include a local network or the Internet. TheAttorney Docket No. LAM1P105WO / 12165-1WOremote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the maintenance or processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process or maintenance operation to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein.

[0100] Without limitation, example systems such as those discussed herein may be connected with one or more other pieces of equipment, including a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, or any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers in order to perform maintenance operations on such equipment.

[0101] The present disclosure includes at least, but is not limited to, the following embodiments.

[0102] Embodiment 1: An apparatus for facilitating semiconductor processing operations. The apparatus comprises a base portion defining a plenum; a faceplate comprising a plurality of through-holes in fluidic communication with the plenum, each of the through-holes comprising a conical frustum portion having a first end with a first diameter and a second end with a second diameter greater than the first diameter, wherein the second end is at a surface of the faceplate configured to face a substrate during operation; and an undercoat on at least a portion of an inner surface of the conical frustum portion of each of the through-holes.

[0103] Embodiment 2: The apparatus of embodiment 1, wherein the undercoat comprises one or more silicon oxide layers.Attorney Docket No. LAM1P105WO / 12165-1WO

[0104] Embodiment 3: The apparatus of embodiment 1 or embodiment 2, wherein the undercoat has a thickness of at least 1 pm.

[0105] Embodiment 4: The apparatus of embodiment 1, further comprising a baffle plate within the plenum, the baffle plate having one or more apertures offset from one or more of the through-holes.

[0106] Embodiment 5: The apparatus of embodiment 1, wherein the plenum comprises a conical frustum portion.

[0107] Embodiment 6: The apparatus of embodiment 1, wherein the plurality of through-holes comprises at least three thousand through-holes.

[0108] Embodiment 7: The apparatus of embodiment 1, wherein the conical frustum portion of each of through-holes has a cone angle between 30 degrees and 90 degrees.

[0109] Embodiment 8: The apparatus of embodiment 1, wherein the conical frustum portion of each of the through-holes has a cone angle of 40 degrees.

[0110] Embodiment 9: The apparatus of embodiment 1, wherein the second diameter of the second end of the conical frustum portion of each of the through-holes is at least 0.120 inches.

[0111] Embodiment 10: The apparatus of embodiment 1, wherein the first diameter of the first end of the conical frustum portion of each of the through-holes is at least 0.015 inches.

[0112] Embodiment 11: The apparatus of embodiment 1, wherein the first diameter of the first end of the conical frustum portion of each of the through-holes is about 0.020 inches.

[0113] Embodiment 12: The apparatus of embodiment 5, wherein each of the through-holes further comprises a cylindrical portion in fluidic communication with the conical frustum portion, wherein the cylindrical portion is in fluidic communication with the plenum.

[0114] Embodiment 13: The apparatus of embodiment 12, wherein the cylindrical portion has an inner diameter of 0.020 inches or less.

[0115] Embodiment 14: A method comprising (a) forming one or more layers of a first material of an undercoat on one or more surfaces of a showerhead in a semiconductor processing chamber, wherein the one or more layers are formed while the semiconductor processing chamber is at an undercoat pressure; (b) receiving a substrate at a pedestal in the semiconductor processing chamber; and (c) forming one or more layers of the first material of aAttorney Docket No. LAM1P105WO / 12165-1WOfilm on the substrate while the semiconductor processing chamber is at a film pressure, wherein the undercoat pressure is equal to, or greater than, the film pressure.

[0116] Embodiment 15: The method of embodiment 14, wherein the first material is silicon oxide.

[0117] Embodiment 16: The method of embodiment 14, wherein the film pressure is at least 15 torr.

[0118] Embodiment 17: The method of embodiment 14, wherein the film pressure is at least 18 torr.

[0119] Embodiment 18: The method of embodiment 14, further comprising, before (a), performing a chamber clean procedure on at least the one or more surfaces of the showerhead.

[0120] Embodiment 19: The method of embodiment 14, further comprising, after (a) and before (c), purging the semiconductor processing chamber.

[0121] Embodiment 20: The method of embodiment 14, wherein (a) comprises (i) flowing a silicon-containing reactant and an oxygen-containing reactant into the semiconductor processing chamber to form a silicon oxide layer of the undercoat on the one or more surfaces of the showerhead while the semiconductor processing chamber is at the undercoat pressure; (ii) exposing the one or more surfaces of the showerhead to plasma to densify at least the silicon oxide layer formed in (i); and (iii) repeating (i) and (ii) until the undercoat reaches at least a minimum undercoat thickness or a minimum number of silicon oxide layers.

[0122] Embodiment 21: The method of embodiment 14, wherein (c) comprises: (i) flowing a silicon-containing reactant and an oxygen-containing reactant into the semiconductor processing chamber to form a silicon oxide layer of the film on the substrate while the semiconductor processing chamber is at the film pressure; (ii) exposing the one or more surfaces of the substrate to plasma to densify at least the silicon oxide layer formed in (i); and (iii) repeating (i) and (ii) until the film reaches at least a minimum film thickness or a minimum number of silicon oxide layers.

[0123] Embodiment 22: The method of embodiment 21, wherein the minimum film thickness is at least 3.7 pm.Attorney Docket No. LAM1P105WO / 12165-1WO

[0124] Embodiment 23: The method of embodiment 14, wherein the showerhead includes a faceplate configured to face the substrate, the faceplate comprising a plurality of through-holes.

[0125] Embodiment 24: The method of embodiment 23, wherein (a) comprises forming the one or more layers of the first material on at least a portion of an inner surface of each of the through-holes.

[0126] Embodiment 25: The method of embodiment 23, wherein each of the through-holes comprises a conical frustum portion.

[0127] Embodiment 26: The method of embodiment 25, wherein the conical frustum portion of each of through-holes has a cone angle between 30 degrees and 90 degrees.

[0128] Embodiment 27: The method of embodiment 25, wherein the conical frustum portion of each of the through-holes has a cone angle of 40 degrees.

[0129] Embodiment 28: The method of embodiment 25, wherein the conical frustum portion comprises a first end with a first diameter and a second end with a second diameter greater than the first diameter, and the second end is at a surface of the faceplate configured to face the substrate.

[0130] Embodiment 29: The method of embodiment 28, wherein the second diameter of the second end of the conical frustum portion of each of the through-holes is at least 0.12 inches.

[0131] Embodiment 30: The method of embodiment 28, wherein the first diameter of the first end of the conical frustum portion of each of the through-holes is at least 0.015 inches.

[0132] Embodiment 31: The method of embodiment 28, wherein the first diameter of the first end of the conical frustum portion of each of the through-holes is about 0.020 inches.

[0133] Embodiment 32: A semiconductor fabrication apparatus, comprising: a semiconductor processing chamber having one or more process stations located therewithin; a pedestal in each of the one or more process stations, each pedestal configured to support a substrate during operation; and a showerhead above the pedestal in each of the one or more process stations. The showerhead comprising: a base portion defining a plenum; a faceplate with a plurality of through-holes in fluidic communication with the plenum, each of the through-holes comprising a conical frustum portion having a first end and a second end with a larger diameterAttorney Docket No. LAM1P105WO / 12165-1WOthan the first end, wherein the second end is at a surface of the faceplate facing the substrate during operation; and an undercoat disposed on at least on a portion of an inner surface of the conical frustum portion of each of the through-holes. The semiconductor fabrication apparatus further comprising a gas distribution system in fluidic communication with the plenum of the showerhead of each process station; a radio frequency power supply electrically connected to the showerhead of each process station; and a vacuum pump in fluidic communication with the semiconductor processing chamber of each process station.

[0134] Embodiment 33: The semiconductor fabrication apparatus of embodiment 32, further comprising a controller configured to execute instructions configured to: cause the vacuum pump to generate an undercoat pressure during an undercoat deposition process that is equal to, or greater than, a film pressure during a film deposition process.

[0135] Embodiment 34: The semiconductor fabrication apparatus of embodiment 33, wherein the film pressure is at least 18 torr.

[0136] Embodiment 35: The semiconductor fabrication apparatus of embodiment 33, wherein the controller is further configured to execute instructions configured to: cause the radio frequency power supply to supply a radio frequency voltage to the showerhead to generate a plasma between the pedestal and the showerhead.

[0137] Embodiment 36: The semiconductor fabrication apparatus of embodiment 32, further comprising a controller configured to execute instructions configured to: (i) cause the vacuum pump to generate an undercoat pressure at the semiconductor processing chamber; (ii) cause the gas distribution system to flow a silicon-containing reactant and an oxygen-containing reactant into the semiconductor processing chamber to form a silicon oxide layer of the undercoat on one or more surfaces of the showerhead while the semiconductor processing chamber is at the undercoat pressure, wherein the undercoat pressure is equal to, or greater than, a film pressure at the semiconductor processing chamber during a film deposition process in which a film is formed on the substrate; and (iii) cause the radio frequency power supply to supply a radio frequency voltage to the showerhead to generate a plasma between the pedestal and the showerhead to densify at least the silicon oxide layer formed on the one or more surfaces of the showerhead in (ii).

[0138] Embodiment 37: The semiconductor fabrication apparatus of embodiment 36, wherein the controller is further configured to execute instructions configured to repeat (ii) and (iii) untilAttorney Docket No. LAM1P105WO / 12165-1WOthe undercoat reaches at least a minimum undercoat thickness or a minimum number of silicon oxide layers.

[0139] Embodiment 38: The semiconductor fabrication apparatus of embodiment 37, wherein the minimum undercoat thickness is 1.0 pm.CONCLUSION

[0140] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

Attorney Docket No. LAM1P105WO / 12165-1WOCLAIMSWhat is claimed is:

1. An apparatus for facilitating semiconductor processing operations, the apparatus comprising:a base portion defining a plenum;a faceplate comprising a plurality of through-holes in fluidic communication with the plenum, each of the through-holes comprising a conical frustum portion having a first end with a first diameter and a second end with a second diameter greater than the first diameter, wherein the second end is at a surface of the faceplate configured to face a substrate during operation; andan undercoat on at least a portion of an inner surface of the conical frustum portion of each of the through-holes.

2. The apparatus of claim 1, wherein the undercoat comprises one or more silicon oxide layers.

3. The apparatus of claim 1, wherein the undercoat has a thickness of at least 1 pm.

4. The apparatus of claim 1, further comprising a baffle plate within the plenum, the baffle plate having one or more apertures offset from one or more of the through-holes.

5. The apparatus of claim 1, wherein the plenum comprises a conical frustum portion.

6. The apparatus of claim 1, wherein the plurality of through-holes comprises at least three thousand through-holes.

7. The apparatus of claim 1, wherein the conical frustum portion of each of through-holes has a cone angle between 30 degrees and 90 degrees.

8. The apparatus of claim 1, wherein the conical frustum portion of each of the through-holes has a cone angle of 40 degrees.

9. The apparatus of claim 1, wherein the second diameter of the second end of the conical frustum portion of each of the through-holes is at least 0.120 inches.

10. The apparatus of claim 1, wherein the first diameter of the first end of the conical frustum portion of each of the through-holes is at least 0.015 inches.Attorney Docket No. LAM1P105WO / 12165-1WO11. The apparatus of claim 1, wherein the first diameter of the first end of the conical frustum portion of each of the through-holes is about 0.020 inches.

12. The apparatus of claim 5, wherein each of the through-holes further comprises a cylindrical portion in fluidic communication with the conical frustum portion, wherein the cylindrical portion is in fluidic communication with the plenum.

13. The apparatus of claim 12, wherein the cylindrical portion has an inner diameter of 0.020 inches or less.

14. The apparatus for facilitating semiconductor processing operations of any of claims 1 through 13, further comprising:a semiconductor processing chamber having one or more process stations located therewithin;a pedestal in each of the one or more process stations, each pedestal configured to support a substrate during operation;a showerhead above the pedestal in each of the one or more process stations, the showerhead comprising the base portion, the faceplate, and the undercoat;a gas distribution system in fluidic communication with the plenum of the showerhead of each process station;a radio frequency power supply electrically connected to the showerhead of each process station; anda vacuum pump in fluidic communication with the semiconductor processing chamber of each process station.

15. The apparatus for facilitating semiconductor processing operations of claim 14, further comprising a controller configured to execute instructions configured to:cause the vacuum pump to generate an undercoat pressure during an undercoat deposition process that is equal to, or greater than, a film pressure during a film deposition process.

16. The apparatus for facilitating semiconductor processing operations of claim 15, wherein the film pressure is at least 18 torr.

17. The apparatus for facilitating semiconductor processing operations of claim 15, wherein the controller is further configured to execute instructions configured to:cause the radio frequency power supply to supply a radio frequency voltage to the showerhead to generate a plasma between the pedestal and the showerhead.Attorney Docket No. LAM1P105WO / 12165-1WO18. The apparatus for facilitating semiconductor processing operations of claim 14, further comprising a controller configured to execute instructions configured to:(i) cause the vacuum pump to generate an undercoat pressure at the semiconductor processing chamber;(ii) cause the gas distribution system to flow a silicon-containing reactant and an oxygen-containing reactant into the semiconductor processing chamber to form a silicon oxide layer of the undercoat on one or more surfaces of the showerhead while the semiconductor processing chamber is at the undercoat pressure, wherein the undercoat pressure is equal to, or greater than, a film pressure at the semiconductor processing chamber during a film deposition process in which a film is formed on the substrate; and(iii) cause the radio frequency power supply to supply a radio frequency voltage to the showerhead to generate a plasma between the pedestal and the showerhead to densify at least the silicon oxide layer formed on the one or more surfaces of the showerhead in (ii).

19. The apparatus for facilitating semiconductor processing operations of claim 18, wherein the controller is further configured to execute instructions configured to repeat (ii) and (iii) until the undercoat reaches at least a minimum undercoat thickness or a minimum number of silicon oxide layers.

20. The apparatus for facilitating semiconductor processing operations of claim 19, wherein the minimum undercoat thickness is 1.0 pm.

Images