Display panel and display device
Patent Information
- Application Number
- PCT/CN2025/084696
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2026-10-01
Smart Images
Figure CN2025084696_01102026_PF_FP_ABST
Abstract
Description
Display panel, display device Technical Field
[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology
[0002] In related technologies, the light-emitting units in the display panel can be connected in series. Correspondingly, a column of pixel units needs to be equipped with multiple power lines. However, the size of the pixel unit in the row direction is limited, and the line width of each power line is small, which leads to problems such as large voltage drop of the power line and insufficient current resistance.
[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0004] According to one aspect of this disclosure, a display panel is provided, the display panel comprising:
[0005] Substrate;
[0006] Multiple pixel units are located on one side of the substrate. The multiple pixel units are arrayed in a first direction and a second direction, and the first direction and the second direction intersect. Each pixel unit includes multiple pixel driving circuits and multiple light-emitting units. The pixel driving circuits and the light-emitting units are correspondingly arranged. The pixel driving circuits are used to provide driving current to their corresponding light-emitting units.
[0007] The plurality of pixel units distributed in the second direction form a pixel unit column, the pixel unit column includes a plurality of pixel unit groups distributed in the second direction, the pixel unit group includes a plurality of pixel units distributed in the second direction, and in the same pixel unit group, at least some of the light-emitting units distributed in the second direction are arranged in series.
[0008] A power line group, comprising a plurality of adjacent power lines, wherein the orthographic projection of the power lines on the substrate extends along the second direction, and the power lines in the power line group are at least used to provide power signals to the same pixel unit group;
[0009] The orthographic projection of the power line group on the substrate and the orthographic projection of the multiple adjacent pixel unit groups distributed in the first direction on the substrate overlap.
[0010] In an exemplary embodiment of this disclosure, the maximum dimension of the orthographic projection of the power line on the substrate in the first direction is S1, the minimum distance between the orthographic projections of two adjacent power lines on the substrate is S2, and S1 / S2 is 5-20.
[0011] In one exemplary embodiment of this disclosure, the display panel further includes:
[0012] Multiple power connection lines are provided, and the orthographic projection of the multiple power connection lines on the substrate extends along the first direction. The power connection lines and the power lines are correspondingly arranged, and the power lines are connected to multiple pixel unit groups distributed in the first direction through their corresponding power connection lines.
[0013] In an exemplary embodiment of this disclosure, the pixel unit group includes n light-emitting units connected in series, the n light-emitting units in series include a first-level light-emitting unit to an nth-level light-emitting unit, the cathode of the i-th-level light-emitting unit is connected to the anode of the (i+1)-th-level light-emitting unit, n is a positive integer greater than or equal to 2, and i is a positive integer greater than or equal to 1 and less than or equal to n.
[0014] The plurality of pixel driving circuits include a first-level pixel driving circuit to an nth-level pixel driving circuit, wherein the i-th-level pixel driving circuit is used to provide driving current to the anode of the i-th-level light-emitting unit;
[0015] The same power line group includes multiple high-level power lines and multiple low-level power lines. The multiple high-level power lines include a first high-level power line to an nth high-level power line, and the multiple low-level power lines include a first low-level power line to an nth low-level power line. The i-th high-level power line is used to provide a high-level power signal to the i-th level pixel driving circuit, the first low-level power line is used to provide a low-level power signal to the nth level light-emitting unit, and the (i+1)-th low-level power line is used to provide a low-level power signal to the (i+1)-th level pixel driving circuit.
[0016] In one exemplary embodiment of this disclosure, the power line group includes multiple low-level power lines and multiple high-level power lines, wherein the high-level power lines and the low-level power lines are located in different conductive layers.
[0017] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a plurality of transistors, and the display panel further includes:
[0018] A first source / drain layer is located on one side of the substrate, and a portion of the structure of the first source / drain layer is used to bridge different transistors in the pixel driving circuit.
[0019] The second source / drain layer is located on the side of the first source / drain layer away from the substrate, and the high-level power line is located in the second source / drain layer.
[0020] The third source / drain layer is located on the side of the second source / drain layer away from the substrate, and the low-level power line is located in the third source / drain layer.
[0021] In one exemplary embodiment of this disclosure, the power line group includes multiple low-level power lines and multiple high-level power lines, wherein the high-level power lines and the low-level power lines are located in the same conductive layer.
[0022] In one exemplary embodiment of this disclosure, the pixel driving circuit includes an oxide transistor, wherein at least a portion of the power lines of the plurality of power lines have their orthographic projections on the substrate and the orthographic projections of the channel region of the oxide transistor on the substrate at least partially overlap.
[0023] In one exemplary embodiment of this disclosure, the display panel further includes:
[0024] A planarization layer is located on one side of the substrate.
[0025] A passivation layer is located on the side of the planarization layer opposite to the substrate, and vent holes are formed on the passivation layer;
[0026] In this embodiment, at least a portion of the power lines have a missing portion formed therein, and the orthographic projection of the vent hole on the substrate is at least partially located within the orthographic projection of the missing portion on the substrate.
[0027] In one exemplary embodiment of this disclosure, the display panel further includes:
[0028] A conductive block, the conductive block being used to connect to the cathode of the light-emitting unit;
[0029] Among them, at least a portion of the power lines located on the same conductive layer as the conductive block have missing portions, and at least a portion of the orthogonal projection of the conductive block on the substrate is located within the orthogonal projection of the missing portions on the substrate.
[0030] In one exemplary embodiment of this disclosure, the missing portion is a notch or opening formed on the power line.
[0031] In one exemplary embodiment of this disclosure, the display panel further includes:
[0032] A power connection cable assembly, comprising multiple power connection cables, wherein the orthographic projection of the power connection cables on the substrate extends along the first direction;
[0033] In the same power connection line group, the multiple power connection lines include multiple high-level power connection lines and multiple low-level power connection lines. The multiple high-level power connection lines include a first high-level power connection line to an nth high-level power connection line, and the multiple low-level power connection lines include a first low-level power connection line to an nth low-level power connection line.
[0034] The i-th high-level power line connects to multiple pixel unit groups distributed in the first direction via the i-th high-level power connection line, and the i-th low-level power line connects to multiple pixel unit groups distributed in the first direction via the i-th low-level power connection line.
[0035] In one exemplary embodiment of this disclosure, the high-level power supply connection line and the low-level power supply connection line are located in the same conductive layer or in different conductive layers.
[0036] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a polysilicon transistor and a capacitor, and the display panel further includes:
[0037] A first gate layer is located on one side of the substrate, and a portion of the structure of the first gate layer is used to form the gate of the polysilicon transistor. The high-level power supply connection line is located in the first gate layer.
[0038] The second gate layer is located on the side of the first gate layer away from the substrate. A portion of the structure of the second gate layer is used to form the electrode of the capacitor. The low-level power supply connection line is located in the second gate layer.
[0039] In an exemplary embodiment of this disclosure, the orthographic projections of multiple power lines in the same power line group on the substrate are distributed at intervals along a first direction.
[0040] Alternatively, the power line group may include multiple low-level power lines and multiple high-level power lines, with at least a portion of the orthographic projections of the low-level power lines and the high-level power lines overlapping on the substrate.
[0041] In one exemplary embodiment of this disclosure, the power line group includes multiple low-level power lines and multiple high-level power lines;
[0042] The maximum dimension of the orthogonal projection of the high-level power line onto the substrate in the first direction is greater than the maximum dimension of the orthogonal projection of the low-level power line onto the substrate in the first direction.
[0043] In one exemplary embodiment of this disclosure, the maximum size of the orthographic projection of the i-th high-level power line onto the substrate in the first direction is greater than the maximum size of the orthographic projection of the (i+1)-th high-level power line onto the substrate in the first direction.
[0044] The maximum size of the orthogonal projection of the i-th low-level power line onto the substrate in the first direction is greater than the maximum size of the orthogonal projection of the (i+1)-th low-level power line onto the substrate in the first direction.
[0045] In one exemplary embodiment of this disclosure, the display panel includes a display area and a border area surrounding the display area. The pixel unit and power line group are located in the display area. The display panel further includes: a plurality of border power lines located in the border area. The orthographic projections of the plurality of border power lines on the substrate extend along a first direction and are spaced apart along a second direction. The plurality of border power lines include:
[0046] Multiple high-level border power lines, including a first high-level border power line to an nth high-level border power line, and an i-th high-level power line connected to the i-th high-level border power line.
[0047] Multiple low-level border power lines, including a first low-level border power line to an nth low-level border power line, and an i-th low-level power line connected to the i-th low-level border power line.
[0048] Wherein, the maximum size of the orthographic projection of the i-th high-level border power line on the substrate in the second direction is greater than the maximum size of the orthographic projection of the (i+1)-th high-level border power line on the substrate in the second direction.
[0049] The maximum size of the orthographic projection of the i-th low-level border power line on the substrate in the second direction is greater than the maximum size of the orthographic projection of the (i+1)-th low-level border power line on the substrate in the second direction.
[0050] In one exemplary embodiment of this disclosure, the first-stage pixel driving circuit includes:
[0051] The first driving circuit connects the first node, the second node, and the third node, and is used to input driving current from the second node to the third node based on the voltage of the first node.
[0052] The first data writing circuit is connected to the second node and the data line, and is used to respond to a control signal to transmit the signal on the data line to the second node;
[0053] A first reset circuit is connected to a first node, a first initial signal line, and a fourth node. It is used to respond to a control signal to transmit the signal of the first initial signal line to the first node, and to respond to a control signal to transmit the signal of the first initial signal line to the fourth node. The fourth node is used to connect to the anode of the first-stage light-emitting unit.
[0054] A first compensation circuit, connecting a first node and a third node, is used to respond to a control signal to connect the first node and the third node;
[0055] A first storage circuit, connected to a first node, is used to store the voltage of the first node;
[0056] A first control circuit is connected to a first high-level power supply line, a second node, a third node, a fourth node, and a fifth node. It is used to respond to a control signal to connect the first high-level power supply line and the second node, and to respond to a signal from the fifth node to connect the third node and the fourth node.
[0057] A first control circuit is connected to a fifth node, a sixth node, a second enable signal line, a third enable signal line, and a control signal line. The first control circuit is used to respond to a control signal to transmit a signal on the control signal line to the sixth node, and to respond to a signal from the sixth node to selectively transmit one of the signals on the second enable signal line and the third enable signal line to the fifth node.
[0058] In one exemplary embodiment of this disclosure, the first driving circuit includes:
[0059] The first driving transistor has its first terminal connected to the second node, its second terminal connected to the third node, and its gate connected to the first node.
[0060] The first data writing circuit includes:
[0061] The fourth transistor has its first terminal connected to the data line, its second terminal connected to the second node, and its gate connected to the first gate line.
[0062] The first reset circuit includes:
[0063] The first transistor has a first terminal connected to a first initial signal line, a second terminal connected to a first node, and a gate connected to a first reset line.
[0064] The seventh transistor has its first terminal connected to the first initial signal line, its second terminal connected to the fourth node, and its gate connected to the third reset line.
[0065] The first compensation circuit includes:
[0066] The second transistor has its first terminal connected to the first node, its second terminal connected to the third node, and its gate connected to the first gate line.
[0067] The first storage circuit includes:
[0068] The first capacitor has its first electrode connected to the first node and its second electrode connected to the first high-level power supply line.
[0069] The first control circuit includes:
[0070] The fifth transistor has its first terminal connected to the first high-level power supply line, its second terminal connected to the second node, and its gate connected to the first enable signal line.
[0071] The sixth transistor has its first terminal connected to the third node, its second terminal connected to the fourth node, and its gate connected to the fifth node.
[0072] The first control circuit includes:
[0073] The tenth transistor has its first terminal connected to the control signal line, its second terminal connected to the sixth node, and its gate connected to the second reset line.
[0074] The eighth transistor has its first terminal connected to the second enable signal line, its second terminal connected to the fifth node, and its gate connected to the sixth node.
[0075] The ninth transistor has its first terminal connected to the third enable signal line, its second terminal connected to the fifth node, and its gate connected to the sixth node. The conduction voltage polarities of the eighth and ninth transistors are opposite.
[0076] The second capacitor has its first electrode connected to the sixth node and its second electrode connected to a stable power supply terminal.
[0077] In one exemplary embodiment of this disclosure, the (i+1)th level pixel driving circuit includes:
[0078] The i-th sub-pixel driving circuit is connected to the (i+1)-th high-level power line, the data line, and the (i+6)-th node, and is used to input driving current to the (i+6)-th node using the (i+1)-th high-level power line according to the signal on the data line.
[0079] The (i+n-1)th sub-pixel driving circuit is connected to the (i+1)th low-level power line, the data line, and the (i+6)th node, and is used to input driving current to the (i+6)th node using the (i+1)th low-level power line according to the signal on the data line.
[0080] The (i+6)th node is connected to the anode of the (i+1)th light-emitting unit.
[0081] In one exemplary embodiment of this disclosure, the (i+1)th level pixel driving circuit further includes:
[0082] The (i+1)th light-emitting control circuit is connected to the (i+6)th node and the anode of the (i+1)th stage light-emitting unit. The (i+n+5)th node is used to respond to the signal of the (i+n+5)th node to connect the (i+6)th node and the anode of the (i+1)th light-emitting unit.
[0083] The (i+1)th control circuit is connected to the (i+n+5)th node, the (i+2n+4)th node, the (i+3)th enable signal line, the (i+n+2)th enable signal line, and the control signal line. The (i+1)th control circuit is used to respond to a control signal to transmit the signal on the control signal line to the (i+2n+4)th node, and to respond to the signal on the (i+2n+4)th node to selectively transmit one of the signals on the (i+3)th enable signal line and the (i+n+2)th enable signal line to the (i+n+5)th node.
[0084] In one exemplary embodiment of this disclosure, the i-th sub-pixel driving circuit includes:
[0085] The (i+1)th driving circuit is connected to the (i+3n+3), (i+4n+2), and (i+6)th nodes, and is used to input driving current to the (i+6)th node through the (i+4n+2)th node based on the voltage of the (i+3n+3)th node.
[0086] The (i+1)th data writing circuit is connected to the (i+4n+2)th node and the data line, and is used to respond to a control signal to transmit the signal on the data line to the (i+4n+2)th node.
[0087] The (i+1)th reset circuit is connected to the (i+3)th (n+3)th node and the first initial signal line, and is used to respond to a control signal to transmit the signal of the first initial signal line to the (i+3)th (n+3)th node.
[0088] The (i+1)th compensation circuit is connected to the (i+3)th (n+3)th node and the (i+6)th node, and is used to respond to a control signal to connect the (i+3)th (n+3)th node and the (i+6)th node.
[0089] The (i+1)th storage circuit is connected to the (i+3)n+3rd node and is used to store the voltage of the (i+3)n+3rd node.
[0090] The (i+1)th control circuit is connected to the (i+1)th high-level power supply line and the (i+4n+2)th node, and is used to respond to a control signal to connect the (i+1)th high-level power supply line and the (i+4n+2)th node.
[0091] The i+n-1th sub-pixel driving circuit includes:
[0092] The i+n driving circuit is connected to the i+5n+1 node, the i+6n node, and the i+6 node. It is used to input driving current from the i+5n+1 node to the i+6 node based on the voltage of the i+6n node.
[0093] The i+n data writing circuit is connected to the i+5n+1 node and the data line, and is used to respond to a control signal to transmit the signal on the data line to the i+5n+1 node.
[0094] The (i+n)th reset circuit is connected to the (i+6n)th node and the second initial signal line, and is used to respond to a control signal to transmit the signal of the second initial signal line to the (i+6n)th node;
[0095] The (i+n)th compensation circuit connects the (i+6n)th node and the (i+6)th node, and is used to respond to a control signal to connect the (i+6n)th node and the (i+6)th node.
[0096] The (i+n)th storage circuit is connected to the (i+6n)th node and is used to store the voltage of the (i+6n)th node.
[0097] The (i+n)th control circuit is connected to the (i+1)th low-level power supply line and the (i+5n+1)th node, and is used to respond to a control signal to connect the (i+1)th low-level power supply line and the (i+5n+1)th node.
[0098] In one exemplary embodiment of this disclosure, the (i+1)th light-emitting control circuit includes:
[0099] The (i+10)th transistor has its first terminal connected to the (i+6)th node, its second terminal connected to the anode of the (i+1)th stage light-emitting unit, and its gate connected to the (i+n+5)th node.
[0100] The (i+1)th control circuit includes:
[0101] The (i+n+9)th transistor has its first terminal connected to the (i+3)th enable signal line, its second terminal connected to the (i+n+5)th node, and its gate connected to the (i+2n+4)th node.
[0102] The first terminal of the (i+2n+8)th transistor is connected to the (i+n+2)th enable signal line, the second terminal is connected to the (i+n+5)th node, and the gate is connected to the (i+2n+4)th node. The conduction polarities of the (i+n+9)th transistor and the (i+2n+8)th transistor are opposite.
[0103] The (i+3)n+7th transistor has its first terminal connected to the control signal line, its second terminal connected to the (i+2)n+4th node, and its gate connected to the (i+3)th reset line.
[0104] The (i+2)th capacitor has its first electrode connected to the (i+2n+4)th node and its second electrode connected to the stable power supply terminal.
[0105] In one exemplary embodiment of this disclosure, the (i+1)th driving circuit includes:
[0106] The (i+1)th driving transistor has its first terminal connected to the (i+4)th (n+2)th node, its second terminal connected to the (i+6)th node, and its gate connected to the (i+3)th (n+3)th node.
[0107] The (i+1)th data writing circuit includes:
[0108] The (i+4n+6)th transistor has its first terminal connected to the data line, its second terminal connected to the (i+4n+2)th node, and its gate connected to the (i+1)th gate line.
[0109] The (i+1)th reset circuit includes:
[0110] The (i+5)n+5th transistor has its first terminal connected to the first initial signal line, its second terminal connected to the (i+3)n+3rd node, and its gate connected to the (i+n+2)th reset line.
[0111] The (i+1)th compensation circuit includes:
[0112] The (i+6)n+4th transistor has its first terminal connected to the (i+3)n+3rd node, its second terminal connected to the (i+6)th node, and its gate connected to the (i+1)th gate line.
[0113] The (i+1)th storage circuit includes:
[0114] The (i+n+1)th capacitor has its first electrode connected to the (i+3)th (n+3)th node and its second electrode connected to the (i+1)th high-level power supply line.
[0115] The (i+1)th control circuit includes:
[0116] The (i+7)n+3rd transistor has its first terminal connected to the (i+1)th high-level power supply line, its second terminal connected to the (i+4)n+2nd node, and its gate connected to the (i+2)n+1st enable signal line.
[0117] The i+nth driving circuit includes:
[0118] The (i+n)th driving transistor has its first terminal connected to the (i+5n+1)th node, its second terminal connected to the (i+6)th node, and its gate connected to the (i+6n)th node.
[0119] The i+nth data writing circuit includes:
[0120] The (i+8)n+2nd transistor has its first terminal connected to the data line, its second terminal connected to the (i+5)n+1st node, and its gate connected to the (i+n)th gate line.
[0121] The i+nth reset circuit includes:
[0122] The (i+9)n+1th transistor has its first terminal connected to the second initial signal line, its second terminal connected to the (i+6)nth node, and its gate connected to the (i+n+2)th reset line.
[0123] The i+nth compensation circuit includes:
[0124] The (i+10n)th transistor has its first terminal connected to the (i+6n)th node, its second terminal connected to the (i+6)th node, and its gate connected to the (i+n)th gate line.
[0125] The i+nth storage circuit includes:
[0126] The (i+2n)th capacitor has its first electrode connected to the (i+6n)th node and its second electrode connected to the (i+1)th low-level power supply line.
[0127] The i+nth control circuit includes:
[0128] The (i+1)th transistor has its first terminal connected to the (i+1)th low-level power supply line, its second terminal connected to the (i+5)th node (n+1), and its gate connected to the (i+3)th enable signal line.
[0129] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.
[0130] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0131] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0132] Figure 1 is a schematic diagram of the structure of the display panel of this disclosure;
[0133] Figure 2 is an equivalent circuit diagram of the pixel driving circuit and the light-emitting unit in the display panel shown in Figure 1;
[0134] Figure 3 is the equivalent circuit diagram of the first-stage pixel driving circuit Pi1 in Figure 2;
[0135] Figure 4 is the equivalent circuit diagram of the (i+1)th level pixel driving circuit in Figure 2;
[0136] Figure 5 is a partial structural schematic diagram of an exemplary embodiment of the display panel of this disclosure;
[0137] Figure 6 is a partial structural schematic diagram of an exemplary embodiment of the display panel of this disclosure;
[0138] Figure 7 is a partial structural schematic diagram of an exemplary embodiment of the display panel of this disclosure;
[0139] Figure 8 is a partial cross-sectional view of an exemplary embodiment of the display panel of this disclosure;
[0140] Figure 9 is a partial structural layout of an exemplary embodiment of the display panel of this disclosure;
[0141] Figure 10 is a partial structural layout of an exemplary embodiment of the display panel of this disclosure;
[0142] Figure 11 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;
[0143] Figure 12 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;
[0144] Figure 13 is a partial view of the area within the elliptical dashed frame in the display panel shown in Figure 9;
[0145] Figure 14 is a partial structural schematic diagram of another exemplary embodiment of the display panel of this disclosure;
[0146] Figure 15 is a partial structural diagram of another exemplary embodiment of the display panel of this disclosure. Detailed Implementation
[0147] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.
[0148] The terms “a,” “one,” and “” are used to indicate the existence of one or more elements / components / etc.; the terms “include” and “have” are used to indicate an open-ended meaning of inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.
[0149] Figure 1 shows a schematic diagram of the structure of the display panel of this disclosure. The display panel includes multiple pixel units Pix, which are arrayed along a first direction X and a second direction Y. The first direction X and the second direction Y intersect. The first direction X can be a row direction, and the second direction Y can be a column direction. Each pixel unit Pix includes multiple pixel driving circuits Pi and multiple light-emitting units LED. The pixel driving circuit Pi is used to provide driving current to its corresponding light-emitting unit LED. The multiple light-emitting units include n LEDs connected in series (from the first-level light-emitting unit LED1 to the nth-level light-emitting unit LEDn). The multiple pixel driving circuits include n pixel driving circuits (from the first-level pixel driving circuit Pi1 to the nth-level pixel driving circuit Pin). The i-th level pixel driving circuit provides driving current to the i-th level light-emitting unit. n is a positive integer greater than or equal to 2, and i is a positive integer greater than or equal to 1 and less than or equal to n.
[0150] As shown in Figures 2, 3, and 4, Figure 2 is the equivalent circuit diagram of the pixel driving circuit and the light-emitting unit in the display panel shown in Figure 1; Figure 3 is the equivalent circuit diagram of the first-level pixel driving circuit Pi1 in Figure 2; and Figure 4 is the equivalent circuit diagram of the (i+1)th-level pixel driving circuit Pi(i+1) in Figure 2. The structures of the (i+1)th-level pixel driving circuit Pi(i+1) to the nth-level pixel driving circuit Pin are the same.
[0151] In this exemplary embodiment, as shown in FIG3, the first-level pixel driving circuit includes: a first driving circuit 11, a first data writing circuit 12, a first reset circuit 13, a first compensation circuit 14, a first storage circuit 15, a first control circuit 16, and a first adjustment circuit 17.
[0152] A first driving circuit 11 is connected to a first node N1, a second node N2, and a third node N3. The first driving circuit 11 is used to input a driving current to the third node N3 via the second node N2 based on the voltage of the first node N1. A first data writing circuit 12 is connected to the second node N2 and the data line Data. The first data writing circuit 12 is used to respond to a control signal to transmit the signal on the data line to the second node N2. A first reset circuit 13 is connected to the first node N1, a first initial signal line Vinit1, and a fourth node N4. The first reset circuit 13 is used to respond to a control signal to transmit the signal of the first initial signal line Vinit1 to the first node N1, and to respond to a control signal to transmit the signal of the first initial signal line Vinit1 to the fourth node N4. The fourth node N4 is used to connect to the anode of the first-stage light-emitting unit LED1. A first compensation circuit 14 is connected to the first node N1 and the third node N3, and is used to respond to a control signal... A signal connects the first node N1 and the third node N3; a first storage circuit 15 is connected to the first node N1 to store the voltage of the first node N1; a first control circuit 16 is connected to the first high-level power line VDD1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5, and is used to respond to a control signal to connect the first high-level power line VDD1 and the second node N2, and to respond to a signal from the fifth node N5 to connect the third node N3 and the fourth node N4; a first regulation circuit 17 is connected to the fifth node N5, the sixth node N6, the second enable signal line EM2, the third enable signal line EM3, and the regulation signal line Dat, and is used to respond to a control signal to transmit the signal on the regulation signal line Dat to the sixth node N6, and to respond to a signal from the sixth node N6 to selectively transmit one of the signals on the second enable signal line EM2 and the third enable signal line EM3 to the fifth node N5.
[0153] In this exemplary embodiment, as shown in FIG3, the first driving circuit 11 may include: a first driving transistor DT1, the first terminal of the first driving transistor DT1 being connected to the second node N2, the second terminal being connected to the third node N3, and the gate being connected to the first node N1; the first data writing circuit 12 includes: a fourth transistor T4, the first terminal of the fourth transistor T4 being connected to the data line Data, the second terminal being connected to the second node N2, and the gate being connected to the first gate line G1; the first reset circuit 13 includes: a first transistor T1 and a seventh transistor T7, the first terminal of the first transistor T1 being connected to the first initial signal line Vinit1, and the second terminal being connected to the first node N1. The gate of the seventh transistor T7 is connected to the first reset line Re1; the first electrode of the seventh transistor T7 is connected to the first initial signal line Vinit1, the second electrode is connected to the fourth node N4, and the gate is connected to the third reset line Re3; the first compensation circuit 14 includes: a second transistor T2, the first electrode of the second transistor T2 is connected to the first node N1, the second electrode is connected to the third node N3, and the gate is connected to the first gate line G1; the first storage circuit 15 includes: a first capacitor C1, the first electrode of the first capacitor C1 is connected to the first node N1, and the second electrode is connected to the first high-level power supply line VDD1; the first control circuit 16 includes: a fifth transistor T5 and a sixth transistor T6, the fifth transistor T5... The first terminal of transistor T6 is connected to the first high-level power supply line VDD1, the second terminal is connected to the second node N2, and the gate is connected to the first enable signal line EM1; the first terminal of the sixth transistor T6 is connected to the third node N3, the second terminal is connected to the fourth node N4, and the gate is connected to the fifth node N5; the first control circuit 17 includes: a tenth transistor T10, an eighth transistor T8, a ninth transistor T9, and a second capacitor C2; the first terminal of the tenth transistor T10 is connected to the control signal line Dat, the second terminal is connected to the sixth node N6, and the gate is connected to the second reset line Re2; the first terminal of the eighth transistor T8 is connected to the second enable signal line EM2, the second terminal is connected to the fifth node N5, and the gate is connected to the sixth node N2. N6; The first electrode of the ninth transistor T9 is connected to the third enable signal line EM3, the second electrode is connected to the fifth node N5, and the gate is connected to the sixth node N6. The conduction voltages of the eighth transistor T8 and the ninth transistor T9 have opposite polarities; that is, one of the conduction voltages of the eighth transistor T8 and the ninth transistor T9 is at a high level, and the other is at a low level. For example, the eighth transistor T8 can be a P-type transistor, and the ninth transistor T9 can be an N-type transistor. The first electrode of the second capacitor C2 is connected to the sixth node N6, and the second electrode is connected to a stable power supply terminal. For example, the second electrode of the second capacitor C2 can be connected to the first low-level power supply line VSS. In this exemplary embodiment, the first transistor T1 and the tenth transistor T10 can be N-type oxide transistors. N-type oxide transistors have smaller leakage current, and this arrangement can reduce the leakage current of the first node N1 and the sixth node N6.The second transistor T2, the first driving transistor DT1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type polysilicon transistors, and the ninth transistor T9 can also be an N-type oxide transistor.
[0154] The driving method of the first-level pixel driving circuit can include a reset stage, a data writing stage, and a light-emitting stage. In the reset stage, the first transistor T1, the seventh transistor T7, and the tenth transistor T10 are turned on. The first initial signal line Vinit1 inputs an initial signal to the first node N1 and the fourth node N4, and the control signal line Dat inputs a mode control signal to the sixth node. In the data writing stage, the second transistor T2 and the fourth transistor T4 are turned on. The data signal line writes a compensation voltage Vdata+Vth to the first node N1 through the fourth transistor T4 and the second transistor T2, where Vdata is the voltage of the data signal on the data line, and Vth is the threshold voltage of the first driving transistor DT1. In the light-emitting stage, the fifth transistor T5 is turned on, and one of the eighth transistor T8 and the ninth transistor T9 is selectively turned on to transmit the signal on the second enable signal line EM2 or the third enable signal line EM3 to the fifth node. The second enable signal line EM2 and the third enable signal line EM3 have different duty cycles, thereby enabling the sixth transistor to have different on-times. For example, when the gray level corresponding to the data signal is greater than the threshold, the sixth transistor T6 can be turned on by selecting the enable signal line with a larger duty cycle between the second enable signal line EM2 and the third enable signal line EM3. When the gray level corresponding to the data signal is less than the threshold, the sixth transistor T6 can be turned on by selecting the enable signal line with a smaller duty cycle between the second enable signal line EM2 and the third enable signal line EM3. This setting can reduce the power consumption of the display panel.
[0155] In this exemplary embodiment, as shown in FIG4, the (i+1)th level pixel driving circuit includes: an i-th sub-pixel driving circuit Piz(i) and an (i+n-1)-th sub-pixel driving circuit Piz(i+n-1). The i-th sub-pixel driving circuit Piz(i) is connected to the (i+1)-th high-level power line VDD(i+1), the data line Data, and the (i+6)-th node N(i+6). The i-th sub-pixel driving circuit Piz(i) is used to utilize the (i+1)-th high-level power line VDD(i+1) according to the signal on the data line Data. The driving current is input to the (i+6)th node N(i+6); the (i+n-1)th sub-pixel driving circuit Piz(i+n-1) is connected to the (i+1)th low-level power line VSS(i+1), the data line Data, and the (i+6)th node N(i+6), and is used to input the driving current to the (i+6)th node N(i+6) using the (i+1)th low-level power line VSS(i+1) according to the signal on the data line Data; the (i+6)th node N(i+6) is connected to the anode of the (i+1)th light-emitting unit LED(i+1).
[0156] In this exemplary embodiment, as shown in FIG4, the (i+1)th level pixel driving circuit further includes: an (i+1)th light emission control circuit CN(i+1) and an (i+1)th modulation circuit CK(i+1). The (i+1)th light emission control circuit CN(i+1) is connected to the (i+6)th node N(i+6) and the anode of the (i+1)th level light emission unit LED(i+1), and to the (i+n+5)th node N(i+n+5). The (i+1)th light emission control circuit CN(i+1) is used to respond to the signal of the (i+n+5)th node N(i+n+5) to connect the (i+6)th node N(i+6) and the anode of the (i+1)th level light emission unit; the (i+1)th modulation circuit CK(i+1) is connected to the (i+n+5)th node N(i+6) and the anode of the (i+1)th level light emission unit LED(i+1). Point N(i+n+5), node N(i+2n+4) of the i+2n+4th order, enable signal line EM(i+3) of the i+3rd order, enable signal line EM(i+n+2) of the i+n+2nd order, and control signal line Dat. The control circuit CK(i+1) is used to respond to a control signal to transmit the signal on the control signal line Dat to node N(i+2n+4) of the i+2n+4th order, and to respond to the signal of node N(i+2n+4) of the i+2n+4th order to selectively transmit the signal on the enable signal line EM(i+3) of the i+3rd order and the enable signal line EM(i+n+2) of the i+n+2nd order to node N(i+n+5).
[0157] In this exemplary embodiment, as shown in FIG4, the i-th sub-pixel driving circuit includes: an i+1 driving circuit Q(i+1), an i+1 data writing circuit S(i+1), an i+1 reset circuit F(i+1), an i+1 compensation circuit B(i+1), an i+1 storage circuit V(i+1), and an i+1 control circuit K(i+1). The i+1 driving circuit Q(i+1) is connected to the i+3n+3 node N(i+3n+3), the i+4n+2 node N(i+4n+2), and the i+6 node N(i+6). The i+1 driving circuit Q(i+1) is used to input a driving current to the i+6 node N(i+6) using the i+4n+2 node N(i+4n+2) based on the voltage of the i+3n+3 node N(i+3n+3). The i+1 data writing circuit S(i+1) is connected to the i+3n+3 node N(i+3n+3), the i+4n+2 node N(i+4n+2), and the i+6 node N(i+6). The i+4n+2 node N(i+4n+2) and data line Data are connected. The (i+1)th data writing circuit S(i+1) is used to respond to a control signal to transmit the signal on the data line Data to the i+4n+2 node N(i+4n+2). The (i+1)th reset circuit F(i+1) is connected to the i+3n+3 node N(i+3n+3) and the first initial signal line Vinit1. The (i+1)th reset circuit F(i+1) is used to respond to a control signal to reset the first initial signal line Vinit1. The signal of line Vinit1 is transmitted to the (i+3n+3)th node N(i+3n+3); the (i+1)th compensation circuit B(i+1) is connected to the (i+3n+3)th node N(i+3n+3) and the (i+6)th node N(i+6), and the (i+1)th compensation circuit B(i+1) is used to respond to a control signal to connect the (i+3n+3)th node N(i+3n+3) and the (i+6)th node N(i+6); the (i+1)th storage circuit V(i+1) is connected to the (i+3n+3)th node N(i+3n+3)... The (i+3n+3)th storage circuit V(i+1) is used to store the voltage of the (i+3n+3)th node N(i+3n+3); the (i+1)th control circuit K(i+1) is connected to the (i+1)th high-level power supply line VDD(i+1) and the (i+4n+2)th node N(i+4n+2), and the (i+1)th control circuit K(i+1) is used to respond to a control signal to connect the (i+1)th high-level power supply line VDD(i+1) and the (i+4n+2)th node N(i+4n+2).
[0158] In this exemplary embodiment, as shown in FIG4, the i+n-1th sub-pixel driving circuit includes: the i+nth driving circuit Q(i+n), the i+nth data writing circuit S(i+n), the i+nth reset circuit F(i+n), the i+nth compensation circuit B(i+n), the i+nth storage circuit V(i+n), and the i+nth control circuit K(i+n). The (i+n)th driving circuit Q(i+n) is connected to the (i+5n+1)th node N(i+5n+1), the (i+6n)th node N(i+6n), and the (i+6)th node N(i+6), and is used to input driving current from the (i+5n+1)th node N(i+6) to the (i+6)th node N(i+6n) based on the voltage of the (i+6n)th node N(i+6n). The (i+n)th data writing circuit S(i+n) is connected to the (i+5n+1)th node N(i+5n+1) and the data line Data, and is used to respond to a control signal to transmit the signal on the data line Data to the (i+5n+1)th node N(i+5n+1). The (i+n)th reset circuit F(i+n) is connected to the (i+6n)th node N(i+6n) and the second initial signal line Vinit2, and is used to respond to a control signal to reset the (i+6)th node N(i+6n) to the second initial signal line Vinit2. The signals of the two initial signal lines Vinit2 are transmitted to the (i+6n)th node N(i+6n); the (i+6n)th compensation circuit B(i+n) is connected to the (i+6n)th node N(i+6n) and the (i+6)th node N(i+6), and is used to respond to a control signal to connect the (i+6n)th node N(i+6n) and the (i+6)th node N(i+6); the (i+6n)th storage circuit V(i+n) is connected to the (i+6n)th node N(i+6n), and the (i+6)th storage circuit B(i+n) is connected to the (i+6n)th node N(i+6n). The +n storage circuit V(i+n) is used to store the voltage of the i+6nth node N(i+6n); the i+n control circuit K(i+n) is connected to the i+1th low-level power line VSS(i+1) and the i+5n+1th node N(i+5n+1), and the i+n control circuit K(i+n) is used to respond to a control signal to connect the i+1th low-level power line VSS(i+1) and the i+5n+1th node N(i+5n+1).
[0159] In this exemplary embodiment, as shown in FIG4, the (i+1)th light-emitting control circuit CN(i+1) includes: the (i+10)th transistor T(i+10), the first terminal of the (i+10)th transistor T(i+10) is connected to the (i+6)th node N(i+6), the second terminal is connected to the anode of the (i+1)th stage light-emitting unit LED(i+1), and the gate is connected to the (i+n+5)th node N(i+n+5); the (i+1)th regulation circuit CK(i+1) includes: the (i+n+9)th transistor T(i+n+9), the (i+2n+8)th transistor T(i+2n+8), the (i+3n+7)th transistor T(i+3n+7), and the (i+2)th capacitor C(i+2). The first terminal of transistor T(i+n+9) of the (i+n+9)th generation is connected to the enable signal line EM(i+3) of the (i+3)th generation, the second terminal is connected to the node N(i+n+5) of the (i+n+5)th generation, and the gate is connected to the node N(i+2n+4) of the (i+2n+4)th generation. Similarly, the first terminal of transistor T(i+2n+8) of the (i+2n+8)th generation is connected to the enable signal line EM(i+n+2) of the (i+n+2)th generation, the second terminal is connected to the node N(i+n+5) of the (i+n+5)th generation, and the gate is connected to the node N(i+2n+4) of the (i+2n+4)th generation. The (i+n+9)th transistor and the (i+2n+8)th transistor... The conduction polarities of transistors T(i+2n+8) are opposite; the first electrode of transistor T(i+3n+7) is connected to the control signal line Dat, the second electrode is connected to node N(i+2n+4) of the i+2n+4, and the gate is connected to the reset line Re(i+3) of the i+3n+7; the first electrode of capacitor C(i+2) of the i+2n+4 is connected to node N(i+2n+4), and the second electrode is connected to the stable power supply terminal. For example, the second electrode of capacitor C(i+2) of the i+2n+7 can be connected to the low-level power supply line VSS(i+1) of the i+1n+7n+8 ...
[0160] In this exemplary embodiment, as shown in FIG4, the (i+1)th driving circuit Q(i+1) may include: the (i+1)th driving transistor DT(i+1), wherein the first terminal of the (i+4n+2)th driving transistor is connected to the (i+4n+2)th node N(i+4n+2), the second terminal is connected to the (i+6)th node N(i+6), and the gate is connected to the (i+3n+3)th node N(i+3n+3); the (i+1)th data writing circuit S(i+1) includes: the (i+4n+6)th transistor T(i+4n+6), the (i+4n+6)th transistor T(… The first terminal of the (i+4n+6) transistor is connected to the data line Data, the second terminal is connected to the (i+4n+2)th node N(i+4n+2), and the gate is connected to the (i+1)th gate line G(i+1); the (i+1)th reset circuit F(i+1) includes: the (i+5n+5)th transistor T(i+5n+5), the first terminal of the (i+5n+5)th transistor T(i+5n+5) is connected to the first initial signal line Vinit1, the second terminal is connected to the (i+3n+3)th node N(i+3n+3), and the gate is connected to the (i+n+2)th reset line; the (i+4n+6 ... transistor T(i+4n+6)th transistor F(i+4n+6)th transistor F(i+4n+6)th transistor F(i+4n+6)th transistor F(i+4n+6)th transistor F(i+4n+6)th transistor F(i+4n+6 The i+1 compensation circuit B(i+1) includes: the i+6n+4th transistor T(i+6n+4), the first electrode of the i+6n+4th transistor T(i+6n+4) is connected to the i+3n+3th node N(i+3n+3), the second electrode is connected to the i+6th node N(i+6), and the gate is connected to the i+1th gate line G(i+1); the i+1th storage circuit V(i+1) includes: the i+n+1th capacitor C(i+n+1), the first electrode is connected to the i+3n+3th node N(i+3n+3), and the second electrode is connected to... Connect to a stable power supply terminal. For example, the second electrode of the (i+n+1)th capacitor C(i+n+1) can be connected to the (i+1)th high-level power supply line VDD(i+1); the (i+1)th control circuit K(i+1) includes: the (i+7n+3)th transistor T(i+7n+3), the first electrode of the (i+7n+3)th transistor T(i+7n+3) is connected to the (i+1)th high-level power supply line, the second electrode is connected to the (i+4n+2)th node N(i+4n+2), and the gate is connected to the (i+2n+1)th enable signal line EM(i+2n+1).The (i+n)th driving circuit Q(i+n) includes: an (i+n)th driving transistor DT(i+n), the first terminal of the (i+5n+1)th driving transistor DT(i+n) is connected to the (i+5n+1)th node N(i+5n+1), the second terminal is connected to the (i+7n-1)th node, and the gate is connected to the (i+6n)th node N(i+6n); the (i+n)th data writing circuit includes: an (i+8n+2)th transistor T(i+8n+2), the first terminal of the (i+8n+2)th transistor T(i+8n+2) is connected to the (i+5n+1)th node, and the gate is connected to the (i+7n-1)th node. According to the data line, the second terminal is connected to the (i+5n+1)th node N(i+5n+1), and the gate is connected to the (i+n)th gate line G(i+n); the (i+n)th reset circuit F(i+n) includes: the (i+9n+1)th transistor T(i+9n+1), the first terminal of the (i+9n+1)th transistor T(i+9n+1) is connected to the second initial signal line Vinit2, the second terminal is connected to the (i+6n)th node N(i+6n), and the gate is connected to the (i+n+2)th reset line Re(i+n+2). The (i+n)th compensation circuit B(i+n) includes: an (i+10n)th transistor T(i+10n), the first electrode of which is connected to the (i+6n)th node N(i+6n), the second electrode of which is connected to the (i+6)th node N(i+6), and the gate of which is connected to the (i+n)th gate line G(i+n); the (i+n)th storage circuit V(i+n) includes: an (i+2n)th capacitor C(i+2n), the first electrode of which is connected to the (i+6)th node N(i+6). The nth node N(i+6n) has its second electrode connected to the (i+1)th low-level power supply line VSS(i+1); the (i+n)th control circuit K(i+n) includes: the (i+11n-1)th transistor T(i+11n-1), the first electrode of the (i+11n-1)th transistor T(i+11n-1) is connected to the (i+1)th low-level power supply line VSS(i+1), the second electrode is connected to the (i+5n+1)th node N(i+5n+1), and the gate is connected to the (i+3n)th enable signal line EM(i+3n).
[0161] In this exemplary embodiment, as shown in FIG4, the (i+1)th driving transistor DT(i+1), the (i+4n+6)th transistor T(i+4n+6), the (i+6n+4)th transistor T(i+6n+4), the (i+7n+3)th transistor T(i+7n+3), the (i+10)th transistor T(i+10), and the (i+n+9)th transistor T(i+n+9) can be P-type polysilicon transistors; the (i+2n+8)th transistor T(i+2n+8), the (i+3n+7)th transistor T(i+3n+7), the (i+n)th driving transistor DT(i+n), the (i+5n+5)th transistor T(i+5n+5), the (i+8n+2)th transistor T(i+8n+2), the (i+9n+1)th transistor T(i+9n+1), the (i+10n)th transistor T(i+10n), and the (i+11n-1)th transistor T(i+11n-1) can be N-type transistors.
[0162] It should be understood that in other exemplary embodiments, the transistors described above may also be of other types. For example, the i+11n-1 transistor T(i+11n-1) may also be a P-type transistor, and the i+6n+4 transistor T(i+6n+4) may be an N-type transistor.
[0163] In this exemplary embodiment, the first low-level power line VSS1 is connected to the cathode of the nth-level light-emitting unit LEDn. Multiple LEDs connected in series are connected between the fourth node N4 and the first low-level power line VSS1. In this exemplary embodiment, the first-level pixel driving circuit to the nth-level pixel driving circuit can jointly adjust the brightness of the first-level light-emitting units to the nth-level light-emitting units. For example, the brightness of the second-level light-emitting unit LED2 can be adjusted by inputting a forward or reverse driving current to the anode of the second-level light-emitting unit LED2 through the second-level pixel driving circuit. This setting can reduce the power consumption of the display panel.
[0164] In related technologies, each column of pixel units needs to be equipped with 2n power lines (from the first high-level power line VDD1 to the nth high-level power line VDDn, and from the first low-level power line VSS1 to the nth low-level power line VSSn). However, the size of a column of pixel units is limited in the first direction, which results in a small width of the power lines, a large voltage drop of the power lines, and insufficient current resistance.
[0165] Based on this, this exemplary embodiment provides a display panel, as shown in Figures 5, 6, and 7. Figure 5 is a partial structural schematic diagram of an exemplary embodiment of the display panel of this disclosure, Figure 6 is a partial structural schematic diagram of an exemplary embodiment of the display panel of this disclosure, and Figure 7 is a partial structural schematic diagram of an exemplary embodiment of the display panel of this disclosure. The display panel includes: a substrate, a plurality of pixel units Pix, and a power line group Vz. The plurality of pixel units Pix are arrayed in a first direction X and a second direction Y, and the first direction X and the second direction Y intersect. For example, the first direction X can be a row direction, and the second direction can be a column direction. The pixel unit Pix includes multiple pixel driving circuits Pi and multiple light-emitting units LED, with the pixel driving circuits Pi and the light-emitting units LED correspondingly arranged. The pixel driving circuit Pi is used to provide driving current to its corresponding light-emitting unit LED. The multiple pixel units Pix distributed in the second direction Y form a pixel unit column Piv. The pixel unit column Piv includes multiple pixel unit groups Pz distributed in the second direction. The pixel unit group Pz includes multiple pixel units Pix distributed in the second direction Y. In the same pixel unit group Pz, at least some of the light-emitting units LED distributed in the second direction are connected in series. The power line group Vz includes multiple adjacent power lines Vzi. The orthographic projection of the power lines Vzi on the substrate extends along the second direction Y. The power lines in the power line group Vz are used to provide power signals to at least the same pixel unit group Pz. The orthographic projection of the power line group Vz on the substrate overlaps with the orthographic projection of the multiple adjacent pixel unit groups Pz distributed in the first direction X on the substrate.
[0166] In this exemplary embodiment, the power line group Vz and the multi-column pixel unit group Pz are configured to correspond to each other, that is, the multi-column pixel unit group Pz corresponds to a power line group Vz. The multi-column power line group Vz has a larger first direction dimension, so that the power lines in the power line group Vz can have a larger width.
[0167] In this exemplary embodiment, the maximum dimension of the orthographic projection of the power line Vzi on the substrate in the first direction X is S1, the minimum distance between the orthographic projections of adjacent power lines Vzi on the substrate is S2, and S1 / S2 is 5-20. For example, S1 / S2 can be equal to 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, etc.
[0168] In this exemplary embodiment, the display panel further includes a power connection line group VLz, which includes multiple power connection lines VL. The orthographic projection of the multiple power connection lines VL on the substrate extends along a first direction X. The power connection lines VL and power lines Vzi are correspondingly arranged, and the power lines Vzi are connected to multiple columns of pixel unit groups Pz through their corresponding power connection lines VL. As shown in Figures 5-7, a pixel unit Pix may include three pixel driving circuits Pi distributed along the first direction X. The orthographic projection of the pixel driving circuits Pi on the substrate may be distributed along the first direction X and the second direction Y in an array. In the same pixel unit group Pz, the light-emitting units corresponding to the same column of pixel driving circuits are connected in series. It should be understood that in other exemplary embodiments, the pixel driving circuits corresponding to the series-connected light-emitting units may also be located in different columns.
[0169] In this exemplary embodiment, as shown in FIG6, the power connection line VL can be connected to the same row of pixel driving circuits through vias (black circles), and as shown in FIG7, the power line Vzi can be connected to its corresponding power connection line VL through vias (black squares).
[0170] In this exemplary embodiment, as shown in Figures 5-7, the pixel unit group includes n LEDs connected in series. The n LEDs include a first-level LED1 to an nth-level LEDn. The cathode of the i-th-level LED is connected to the anode of the (i+1)-th-level LED. n is a positive integer greater than or equal to 2, and i is a positive integer greater than or equal to 1 and less than or equal to n. The plurality of pixel driving circuits Pi includes a first-level pixel driving circuit Pi1 to an nth-level pixel driving circuit Pin. The i-th-level pixel driving circuit provides driving current to the anode of the i-th-level LED. The power line group V... z includes n high-level power lines VDD and n low-level power lines VSS. The n high-level power lines VDD include a first high-level power line VDD1 to an nth high-level power line VDDn, and the n low-level power lines VSS include a first low-level power line VSS1 to an nth low-level power line VSSn. The i-th high-level power line is used to provide a high-level power signal to the i-th level pixel driving circuit, the first low-level power line VSS1 is used to provide a low-level power signal to the nth level light-emitting unit, and the (i+1)-th low-level power line is used to provide a low-level power signal to the (i+1)-th level pixel driving circuit.
[0171] In this exemplary embodiment, as shown in Figures 5-7, in the same power connection line group VLz, multiple power connection lines VL include multiple high-level power connection lines VLd and multiple low-level power connection lines VLs. The multiple high-level power connection lines VLd include first high-level power connection lines VLd1 to nth high-level power connection lines VLdn, and the multiple low-level power connection lines VLs include first low-level power connection lines VLs1 to nth low-level power connection lines VLsn. The i-th high-level power line is connected to multiple columns of pixel unit groups through the i-th high-level power connection line, and the i-th low-level power line is connected to multiple columns of pixel unit groups through the i-th low-level power connection line.
[0172] In this exemplary embodiment, as shown in FIG8, it is a partial cross-sectional view of an exemplary embodiment of the display panel of the present disclosure. The display panel may include a substrate 100, a shielding layer 101, a first buffer layer 102, a first active layer 103, a first insulating layer 104, a first gate layer 105, a second insulating layer 106, a second gate layer 107, a first dielectric layer 108, a second buffer layer 109, a second active layer 110, a third insulating layer 111, a third gate layer 112, a second dielectric layer 113, a first source / drain layer 114, a first planarization layer 115, a first passivation layer 116, a second source / drain layer 117, a second planarization layer 118, a second passivation layer 119, a third source / drain layer 120, a third planarization layer 121, a third passivation layer 122, a fourth source / drain layer 123, a fourth passivation layer 124, a fourth planarization layer 125, and an electrode portion 126, which are stacked sequentially.
[0173] In this exemplary embodiment, the buffer layer (including the first buffer layer 102 and the second buffer layer 109) and the insulating layer (including the first insulating layer 104, the second insulating layer 106, and the third insulating layer 111) can be a single-layer structure or a multi-layer structure, and the materials of the buffer layer and the insulating layer can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the dielectric layer (including the first dielectric layer 108 and the second dielectric layer 113) can be a silicon nitride layer; the planarization layer (including the first planarization layer 115, the second planarization layer 118, the third planarization layer 121, and the fourth planarization layer 125) can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer (including the first passivation layer 116, the second passivation layer 119, the third passivation layer 122, and the fourth passivation layer 124) can be a silicon oxide layer. The substrate may include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, wherein the barrier layer may be an inorganic material. The materials of the first gate layer, second gate layer, and third gate layer may be molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first source / drain layer, second source / drain layer, third source / drain layer, and fourth source / drain layer may include metallic materials, for example, molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked layer, or a titanium / aluminum / titanium stacked conductive layer. The sheet resistance of any one of the first, second, third, and fourth source / drain layers may be less than the sheet resistance of any one of the first, second, and third gate layers.
[0174] In this exemplary embodiment, the pixel driving circuit may include an N-type transistor, a P-type transistor, and a capacitor. The shielding layer can be used to shield a portion of the channel region in the first active layer. At least a portion of the structure of the first active layer is used to form the channel region of the P-type transistor. At least a portion of the structure of the first gate layer is used to form the gate of the P-type transistor. At least a portion of the structure of the second gate layer is used to form the bottom gate of the N-type transistor and the electrode of the capacitor. At least a portion of the structure of the second active layer is used to form the channel region of the N-type transistor. At least a portion of the structure of the third gate layer is used to form the top gate of the N-type transistor. At least a portion of the structure of the first source / drain layer is used to bridge different transistors. The electrode portion 126 is applied to form the anode or cathode of the light-emitting unit. The light-emitting unit LED can be a Mini LED or micro LED, etc.
[0175] It should be understood that in other exemplary embodiments, the pixel driving circuit may also include only one type of transistor; for example, the pixel driving circuit may include only P-type transistors or only N-type transistors. Accordingly, the display panel may not include the second active layer and the third gate layer. Furthermore, in other exemplary embodiments, the display panel may not have a fourth source / drain layer.
[0176] In this exemplary embodiment, as shown in FIG9, a partial structural layout diagram of an exemplary embodiment of the display panel of this disclosure is presented. The power line group Vz includes multiple low-level power lines and multiple high-level power lines VDD, wherein the high-level power lines and the low-level power lines VSS are located on different conductive layers. This arrangement can reduce the risk of short circuits between adjacent power lines. In this exemplary embodiment, the high-level power line VDD may be located on a second source-drain layer, and the low-level power line VSS may be located on a third source-drain layer. It should be understood that in other exemplary embodiments, the high-level power line VDD may also be located on a third source-drain layer, and the low-level power line VSS may also be located on a second source-drain layer.
[0177] It should be noted that this exemplary embodiment is illustrated by taking a pixel unit group Pz that includes 4 light-emitting units connected in series as an example. Correspondingly, the power line group Vz includes 4 low-level power lines VSS and 4 high-level power lines VDD.
[0178] In this exemplary embodiment, as shown in FIG10, a partial structural layout diagram of an exemplary embodiment of the display panel of this disclosure is provided. The high-level power line VDD and the low-level power line VSS may also be located on the same conductive layer. This arrangement can reduce the number of conductive layers in the display panel, thereby simplifying the manufacturing process. For example, the high-level power line VDD and the low-level power line VSS may be located on the second source / drain layer. Correspondingly, the display panel may not have a third source / drain layer, or may have other structures on the third source / drain layer.
[0179] In this exemplary embodiment, as shown in Figures 9 and 10, the orthographic projections of multiple power lines in the same power line group Vz on the substrate are distributed at intervals along a first direction. It should be understood that in other exemplary embodiments, the orthographic projections of the high-level power line VDD and the low-level power line VSS on the substrate may overlap. For example, as shown in Figures 11 and 12, Figure 11 is a schematic structural diagram of another exemplary embodiment of the display panel of this disclosure, and Figure 12 is a schematic structural diagram of another exemplary embodiment of the display panel of this disclosure. In Figures 11 and 12, the orthographic projections of the high-level power line VDD and the low-level power line VSS on the substrate overlap. This arrangement can increase the linewidth of the power line Vzi within a limited space.
[0180] In this exemplary embodiment, the pixel driving circuit includes an oxide transistor, and at least a portion of the power lines' orthographic projections on the substrate and the channel region of the oxide transistor's orthographic projection on the substrate at least partially overlap. For example, as shown in FIG13, a partial enlargement within the elliptical dashed frame in the display panel shown in FIG9, the orthographic projection of the high-level power line VDD on the substrate and the orthographic projection of the channel region IG of the oxide transistor's orthographic projection on the substrate at least partially overlap. The high-level power line VDD can shield the channel region IG of the oxide transistor from light, thereby reducing the impact of light on the characteristics of the oxide transistor. It should be understood that in the embodiments shown in FIG10-12, the orthographic projections of at least a portion of the power lines' orthographic projections on the substrate may also at least partially overlap with the orthographic projection of the channel region of the oxide transistor's orthographic projection on the substrate.
[0181] In this exemplary embodiment, as shown in Figures 9-13, vent holes Hq can be formed on the passivation layer above the planarization layer. For example, as shown in Figure 8, vent holes are formed on one or more of the first passivation layer 116, the second passivation layer 119, and the third passivation layer 122. The vent holes on different passivation layers can be located in the same region or in different regions. The vent holes are used to remove undesirable gases such as water vapor from the planarization layer.
[0182] In this exemplary embodiment, as shown in Figures 9-13, at least a portion of the power lines has a missing portion Qs1 formed on them, and the orthographic projection of the vent hole Hq on the substrate is at least partially located within the orthographic projection of the missing portion Qs1 on the substrate. That is, this exemplary embodiment avoids the power line Vxi from blocking the vent hole Hq by forming a missing portion Qs1 on the power line Vxi. It should be noted that the missing portion Qs1 can be located on either the high-level power line VDD or the low-level power line VSS. When the orthographic projections of the high-level power line VDD and the low-level power line VSS on the substrate overlap, the missing portion Qs1 can be provided at the same location on both the high-level power line VDD and the low-level power line VSS.
[0183] In this exemplary embodiment, as shown in Figures 9-13, the display panel further includes a conductive block Dk, which is used to connect the cathode or anode of the light-emitting unit LED; wherein at least a portion of the power lines located on the same conductive layer as the conductive block Dk has a missing portion Qs2 formed therein, and at least a portion of the orthographic projection of the conductive block Dk on the substrate is located within the orthographic projection of the missing portion Qs2 on the substrate. That is, this exemplary embodiment can reserve space for setting the conductive block Dk by setting the missing portion Qs2.
[0184] In this exemplary embodiment, as shown in FIG9-13, the missing portions Qs1 and Qs2 can be notches formed on the power line or openings formed on the power line.
[0185] In this exemplary embodiment, the high-level power connection line VLd and the low-level power connection line VLs are located in the same conductive layer or in different conductive layers. For example, the high-level power connection line VLd may be located in the first gate layer, and the low-level power connection line VLs may be located in the second gate layer. In other exemplary embodiments, the high-level power connection line VLd may be located in one or more of the first gate layer, the second gate layer, and the third gate layer, and the low-level power connection line VLs may be located in one or more of the first gate layer, the second gate layer, and the third gate layer.
[0186] In this exemplary embodiment, the formula for the output current of the driving transistor is as follows:
[0187] I = (μWCox / 2L)(Vgs-Vth) 2
[0188] Where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit described above, the output current of the driving transistor I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 .
[0189] In this exemplary embodiment, as shown in Figures 9 and 10, the maximum dimension d1 of the orthogonal projection of the high-level power line VDD onto the substrate in the first direction is greater than the maximum dimension d2 of the orthogonal projection of the low-level power line VSS onto the substrate in the first direction. Since the output current of the driving transistor is related to the voltage of the high-level power line VDD, this exemplary embodiment sets the high-level power line VDD to be wider to reduce its resistance, thereby improving the display uniformity of the display panel.
[0190] In this exemplary embodiment, as shown in Figures 9-13, within the same power line group Vz, the orthographic projections of each high-level power line VDD onto the substrate in the first direction X can be equal in size, and the orthographic projections of each low-level power line VSS onto the substrate in the first direction X can also be equal in size. It should be understood that in other exemplary embodiments, the orthographic projections of each high-level power line VDD onto the substrate in the first direction X can also be unequal, and the orthographic projections of each low-level power line VSS onto the substrate in the first direction X can also be unequal.
[0191] Figure 14 shows a partial structural schematic diagram of another exemplary embodiment of the display panel of this disclosure. The maximum size of the orthogonal projection of the i-th high-level power line onto the substrate in the first direction is greater than the maximum size of the orthogonal projection of the (i+1)-th high-level power line onto the substrate in the first direction. For example, the maximum size of the orthogonal projection of the first high-level power line onto the substrate in the first direction is greater than the maximum size of the orthogonal projection of the second high-level power line onto the substrate in the first direction, and the maximum size of the orthogonal projection of the second high-level power line onto the substrate in the first direction is greater than the maximum size of the orthogonal projection of the third high-level power line onto the substrate in the first direction. Similarly, the maximum size of the orthogonal projection of the i-th low-level power line onto the substrate in the first direction is greater than the maximum size of the orthogonal projection of the (i+1)-th low-level power line onto the substrate in the first direction. For example, the maximum size of the orthogonal projection of the first low-level power line onto the substrate in the first direction is greater than the maximum size of the orthogonal projection of the second low-level power line onto the substrate in the first direction, and the maximum size of the orthogonal projection of the second low-level power line onto the substrate in the first direction is greater than the maximum size of the orthogonal projection of the third low-level power line onto the substrate in the first direction. Based on the working principle of series-connected LEDs, generally, the voltage of the i-th high-level power line is greater than that of the (i+1)-th high-level power line. Compared to the (i+1)-th high-level power line, the i-th high-level power line suffers from more severe voltage drop and current draw issues. Conversely, the voltage of the i-th low-level power line is less than that of the (i+1)-th low-level power line. Again, compared to the (i+1)-th low-level power line, the i-th low-level power line suffers from more severe voltage drop and current draw issues. This exemplary embodiment employs a stepped design for the linewidths of the high-level and low-level power lines, thereby significantly improving the voltage drop and current draw issues for both low-level and high-level power lines within a limited space.
[0192] In this exemplary embodiment, as shown in Figures 8-12 and 14, in the same power line group Vz, the i-th high-level power line to the n-th high-level power line are arranged adjacent to each other, and the i-th low-level power line to the n-th low-level power line are arranged adjacent to each other. It should be understood that in other exemplary embodiments, the power lines in the same power line group Vz may be distributed in other ways. For example, Figure 15 shows a partial structural schematic diagram of another exemplary embodiment of the display panel of this disclosure. High-level power lines VDD and low-level power lines VSS are arranged alternately.
[0193] In this exemplary embodiment, as shown in FIG15, the display panel includes a display area AA and a border area BB located around the display area. The aforementioned pixel unit Pix and power line group Vz are located in the display area. The display panel further includes: a plurality of border power lines BL located in the border area. The orthographic projection of the plurality of border power lines BL on the substrate extends along a first direction X and is distributed at intervals along a second direction Y. The plurality of border power lines BL includes: a plurality of high-level border power lines BLd and a plurality of low-level border power lines BLs. The plurality of high-level border power lines BLd include a first high-level border power line BLd1 to an nth high-level border power line BLdn, and the i-th high-level power line is connected to the i-th high-level border power line; the plurality of low-level border power lines BLs include a first low-level border power line BLs1 to an nth low-level border power line BLsn, and the i-th low-level power line is connected to the i-th low-level border power line; wherein, the maximum size of the orth projection of the i-th high-level border power line on the substrate in the second direction is greater than the maximum size of the orth projection of the (i+1)-th high-level border power line on the substrate in the second direction; the maximum size of the orth projection of the i-th low-level border power line on the substrate in the second direction Y is greater than the maximum size of the orth projection of the (i+1)-th low-level border power line on the substrate in the second direction.
[0194] In this exemplary embodiment, as shown in Figures 14 and 15, the low-level power line VSS and the high-level power line VDD can be located in the same conductive layer or in different conductive layers.
[0195] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.
[0196] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.
Claims
1. A display panel, wherein, The display panel includes: Substrate; Multiple pixel units are located on one side of the substrate. The multiple pixel units are arrayed in a first direction and a second direction, the first direction and the second direction intersect. Each pixel unit includes multiple pixel driving circuits and multiple light-emitting units. The pixel driving circuits and the light-emitting units are correspondingly arranged. The pixel driving circuits are used to provide driving current to their corresponding light-emitting units. The plurality of pixel units distributed in the second direction form a pixel unit column, the pixel unit column includes a plurality of pixel unit groups distributed in the second direction, the pixel unit group includes a plurality of pixel units distributed in the second direction, and in the same pixel unit group, at least some of the light-emitting units distributed in the second direction are arranged in series. A power line group, comprising a plurality of adjacent power lines, wherein the orthographic projection of the power lines on the substrate extends along the second direction, and the power lines in the power line group are at least used to provide power signals to the same pixel unit group; The orthographic projection of the power line group on the substrate and the orthographic projection of the multiple adjacent pixel unit groups distributed in the first direction on the substrate overlap.
2. The display panel of claim 1, wherein, The maximum dimension of the orthographic projection of the power line on the substrate in the first direction is S1, and the minimum distance between the orthographic projections of two adjacent power lines on the substrate is S2, with S1 / S2 being 5-20.
3. The display panel of claim 1, wherein, The display panel also includes: Multiple power connection lines are provided, and the orthographic projection of the multiple power connection lines on the substrate extends along the first direction. The power connection lines and the power lines are correspondingly arranged, and the power lines are connected to multiple pixel unit groups distributed in the first direction through their corresponding power connection lines.
4. The display panel of claim 1, wherein, The pixel unit group includes n light-emitting units connected in series. The n light-emitting units connected in series include a first-level light-emitting unit to an nth-level light-emitting unit. The cathode of the i-th-level light-emitting unit is connected to the anode of the (i+1)-th-level light-emitting unit. n is a positive integer greater than or equal to 2, and i is a positive integer greater than or equal to 1 and less than or equal to n. The plurality of pixel driving circuits include a first-level pixel driving circuit to an nth-level pixel driving circuit, wherein the i-th-level pixel driving circuit is used to provide driving current to the anode of the i-th-level light-emitting unit; The same power line group includes multiple high-level power lines and multiple low-level power lines. The multiple high-level power lines include a first high-level power line to an nth high-level power line, and the multiple low-level power lines include a first low-level power line to an nth low-level power line. The i-th high-level power line is used to provide a high-level power signal to the i-th level pixel driving circuit, the first low-level power line is used to provide a low-level power signal to the nth level light-emitting unit, and the (i+1)-th low-level power line is used to provide a low-level power signal to the (i+1)-th level pixel driving circuit.
5. The display panel of claim 1, wherein, The power line group includes multiple low-level power lines and multiple high-level power lines, with the high-level power lines and the low-level power lines located in different conductive layers.
6. The display panel of claim 5, wherein, The pixel driving circuit includes multiple transistors, and the display panel further includes: A first source / drain layer is located on one side of the substrate, and a portion of the structure of the first source / drain layer is used to bridge different transistors in the pixel driving circuit. The second source / drain layer is located on the side of the first source / drain layer away from the substrate, and the high-level power line is located in the second source / drain layer. The third source / drain layer is located on the side of the second source / drain layer away from the substrate, and the low-level power line is located in the third source / drain layer.
7. The display panel of claim 1, wherein, The power line group includes multiple low-level power lines and multiple high-level power lines, with the high-level power lines and the low-level power lines located on the same conductive layer.
8. The display panel of claim 1, wherein, The pixel driving circuit includes an oxide transistor, and at least a portion of the power lines of the plurality of power lines have their orthographic projections on the substrate and the orthographic projections of the channel region of the oxide transistor on the substrate at least partially overlap.
9. The display panel of claim 1, wherein, The display panel also includes: A planarization layer is located on one side of the substrate. A passivation layer is located on the side of the planarization layer opposite to the substrate, and vent holes are formed on the passivation layer; In this embodiment, at least a portion of the power lines have a missing portion formed therein, and the orthographic projection of the vent hole on the substrate is at least partially located within the orthographic projection of the missing portion on the substrate.
10. The display panel of claim 1, wherein, The display panel also includes: A conductive block, the conductive block being used to connect to the cathode of the light-emitting unit; Among them, at least a portion of the power lines located on the same conductive layer as the conductive block have missing portions, and at least a portion of the orthogonal projection of the conductive block on the substrate is located within the orthogonal projection of the missing portions on the substrate.
11. The display panel of claim 9 or 10, wherein, The missing portion is a notch or opening formed on the power line.
12. The display panel of claim 4, wherein, The display panel also includes: A power connection cable assembly, comprising multiple power connection cables, wherein the orthographic projection of the power connection cables on the substrate extends along the first direction; In the same power connection line group, the multiple power connection lines include multiple high-level power connection lines and multiple low-level power connection lines. The multiple high-level power connection lines include a first high-level power connection line to an nth high-level power connection line, and the multiple low-level power connection lines include a first low-level power connection line to an nth low-level power connection line. The i-th high-level power line connects to multiple pixel unit groups distributed in the first direction via the i-th high-level power connection line, and the i-th low-level power line connects to multiple pixel unit groups distributed in the first direction via the i-th low-level power connection line.
13. The display panel of claim 12, wherein, The high-level power supply connection line and the low-level power supply connection line are located on the same conductive layer or on different conductive layers.
14. The display panel of claim 12, wherein, The pixel driving circuit includes polysilicon transistors and capacitors, and the display panel further includes: A first gate layer is located on one side of the substrate, and a portion of the structure of the first gate layer is used to form the gate of the polysilicon transistor. The high-level power supply connection line is located in the first gate layer. The second gate layer is located on the side of the first gate layer away from the substrate. A portion of the structure of the second gate layer is used to form the electrode of the capacitor. The low-level power supply connection line is located in the second gate layer.
15. The display panel of claim 1, wherein, The orthographic projections of multiple power lines in the same power line group on the substrate are distributed at intervals along a first direction. Alternatively, the power line group may include multiple low-level power lines and multiple high-level power lines, with at least a portion of the orthographic projections of the low-level power lines and the high-level power lines overlapping on the substrate.
16. The display panel of claim 1, wherein, The power line group includes multiple low-level power lines and multiple high-level power lines; The maximum dimension of the orthogonal projection of the high-level power line onto the substrate in the first direction is greater than the maximum dimension of the orthogonal projection of the low-level power line onto the substrate in the first direction.
17. The display panel of claim 4, wherein, The maximum size of the orthographic projection of the i-th high-level power line onto the substrate in the first direction is greater than the maximum size of the orthographic projection of the (i+1)-th high-level power line onto the substrate in the first direction. The maximum size of the orthographic projection of the i-th low-level power line onto the substrate in the first direction is greater than the maximum size of the orthographic projection of the (i+1)-th low-level power line onto the substrate in the first direction.
18. The display panel of claim 17, wherein, The display panel includes a display area and a border area surrounding the display area. The pixel unit and power line group are located in the display area. The display panel further includes: a plurality of border power lines located in the border area. The orthographic projection of the plurality of border power lines on the substrate extends along the first direction and is spaced apart along the second direction. The plurality of border power lines include: Multiple high-level border power lines, including a first high-level border power line to an nth high-level border power line, and an i-th high-level power line connected to the i-th high-level border power line. Multiple low-level border power lines, including a first low-level border power line to an nth low-level border power line, and an i-th low-level power line connected to the i-th low-level border power line. Wherein, the maximum size of the orthographic projection of the i-th high-level border power line on the substrate in the second direction is greater than the maximum size of the orthographic projection of the (i+1)-th high-level border power line on the substrate in the second direction. The maximum size of the orthographic projection of the i-th low-level border power line on the substrate in the second direction is greater than the maximum size of the orthographic projection of the (i+1)-th low-level border power line on the substrate in the second direction.
19. The display panel of claim 4, wherein, The first-stage pixel driving circuit includes: The first driving circuit connects the first node, the second node, and the third node, and is used to input driving current from the second node to the third node based on the voltage of the first node. The first data writing circuit is connected to the second node and the data line, and is used to respond to a control signal to transmit the signal on the data line to the second node; A first reset circuit is connected to a first node, a first initial signal line, and a fourth node. It is used to respond to a control signal to transmit the signal of the first initial signal line to the first node, and to respond to a control signal to transmit the signal of the first initial signal line to the fourth node. The fourth node is used to connect to the anode of the first-stage light-emitting unit. A first compensation circuit, connecting a first node and a third node, is used to respond to a control signal to connect the first node and the third node; A first storage circuit, connected to a first node, is used to store the voltage of the first node; A first control circuit is connected to a first high-level power supply line, a second node, a third node, a fourth node, and a fifth node. It is used to respond to a control signal to connect the first high-level power supply line and the second node, and to respond to a signal from the fifth node to connect the third node and the fourth node. A first control circuit is connected to a fifth node, a sixth node, a second enable signal line, a third enable signal line, and a control signal line. The first control circuit is used to respond to a control signal to transmit a signal on the control signal line to the sixth node, and to respond to a signal from the sixth node to selectively transmit one of the signals on the second enable signal line and the third enable signal line to the fifth node.
20. The display panel of claim 19, wherein, The first driving circuit includes: The first driving transistor has its first terminal connected to the second node, its second terminal connected to the third node, and its gate connected to the first node. The first data writing circuit includes: The fourth transistor has its first terminal connected to the data line, its second terminal connected to the second node, and its gate connected to the first gate line. The first reset circuit includes: The first transistor has a first terminal connected to a first initial signal line, a second terminal connected to a first node, and a gate connected to a first reset line. The seventh transistor has its first terminal connected to the first initial signal line, its second terminal connected to the fourth node, and its gate connected to the third reset line. The first compensation circuit includes: The second transistor has its first terminal connected to the first node, its second terminal connected to the third node, and its gate connected to the first gate line. The first storage circuit includes: The first capacitor has its first electrode connected to the first node and its second electrode connected to the first high-level power supply line. The first control circuit includes: The fifth transistor has its first terminal connected to the first high-level power supply line, its second terminal connected to the second node, and its gate connected to the first enable signal line. The sixth transistor has its first terminal connected to the third node, its second terminal connected to the fourth node, and its gate connected to the fifth node. The first control circuit includes: The tenth transistor has its first terminal connected to the control signal line, its second terminal connected to the sixth node, and its gate connected to the second reset line. The eighth transistor has its first terminal connected to the second enable signal line, its second terminal connected to the fifth node, and its gate connected to the sixth node. The ninth transistor has its first terminal connected to the third enable signal line, its second terminal connected to the fifth node, and its gate connected to the sixth node. The conduction voltage polarities of the eighth and ninth transistors are opposite. The second capacitor has its first electrode connected to the sixth node and its second electrode connected to a stable power supply terminal.
21. The display panel of claim 4, wherein, The (i+1)th level pixel driving circuit includes: The i-th sub-pixel driving circuit is connected to the (i+1)-th high-level power line, the data line, and the (i+6)-th node, and is used to input driving current to the (i+6)-th node using the (i+1)-th high-level power line according to the signal on the data line. The (i+n-1)th sub-pixel driving circuit is connected to the (i+1)th low-level power line, the data line, and the (i+6)th node, and is used to input driving current to the (i+6)th node using the (i+1)th low-level power line according to the signal on the data line. The (i+6)th node is connected to the anode of the (i+1)th light-emitting unit.
22. The display panel of claim 21, wherein, The (i+1)th level pixel driving circuit also includes: The (i+1)th light-emitting control circuit is connected to the (i+6)th node and the anode of the (i+1)th stage light-emitting unit. The (i+n+5)th node is used to respond to the signal of the (i+n+5)th node to connect the (i+6)th node and the anode of the (i+1)th light-emitting unit. The (i+1)th control circuit is connected to the (i+n+5)th node, the (i+2n+4)th node, the (i+3)th enable signal line, the (i+n+2)th enable signal line, and the control signal line. The (i+1)th control circuit is used to respond to a control signal to transmit the signal on the control signal line to the (i+2n+4)th node, and to respond to the signal on the (i+2n+4)th node to selectively transmit one of the signals on the (i+3)th enable signal line and the (i+n+2)th enable signal line to the (i+n+5)th node.
23. The display panel of claim 21, wherein, The i-th sub-pixel driving circuit includes: The (i+1)th driving circuit is connected to the (i+3n+3), (i+4n+2), and (i+6)th nodes, and is used to input driving current to the (i+6)th node through the (i+4n+2)th node based on the voltage of the (i+3n+3)th node. The (i+1)th data writing circuit is connected to the (i+4n+2)th node and the data line, and is used to respond to a control signal to transmit the signal on the data line to the (i+4n+2)th node. The (i+1)th reset circuit is connected to the (i+3)th (n+3)th node and the first initial signal line, and is used to respond to a control signal to transmit the signal of the first initial signal line to the (i+3)th (n+3)th node. The (i+1)th compensation circuit is connected to the (i+3)th (n+3)th node and the (i+6)th node, and is used to respond to a control signal to connect the (i+3)th (n+3)th node and the (i+6)th node. The (i+1)th storage circuit is connected to the (i+3)n+3rd node and is used to store the voltage of the (i+3)n+3rd node. The (i+1)th control circuit is connected to the (i+1)th high-level power supply line and the (i+4n+2)th node, and is used to respond to a control signal to connect the (i+1)th high-level power supply line and the (i+4n+2)th node. The i+n-1th sub-pixel driving circuit includes: The i+n driving circuit is connected to the i+5n+1 node, the i+6n node, and the i+6 node. It is used to input driving current from the i+5n+1 node to the i+6 node based on the voltage of the i+6n node. The i+n data writing circuit is connected to the i+5n+1 node and the data line, and is used to respond to a control signal to transmit the signal on the data line to the i+5n+1 node. The (i+n)th reset circuit is connected to the (i+6n)th node and the second initial signal line, and is used to respond to a control signal to transmit the signal of the second initial signal line to the (i+6n)th node; The (i+n)th compensation circuit connects the (i+6n)th node and the (i+6)th node, and is used to respond to a control signal to connect the (i+6n)th node and the (i+6)th node. The (i+n)th storage circuit is connected to the (i+6n)th node and is used to store the voltage of the (i+6n)th node. The (i+n)th control circuit is connected to the (i+1)th low-level power supply line and the (i+5n+1)th node, and is used to respond to a control signal to connect the (i+1)th low-level power supply line and the (i+5n+1)th node.
24. The display panel of claim 22, wherein, The (i+1)th light-emitting control circuit includes: The (i+10)th transistor has its first terminal connected to the (i+6)th node, its second terminal connected to the anode of the (i+1)th stage light-emitting unit, and its gate connected to the (i+n+5)th node. The (i+1)th control circuit includes: The (i+n+9)th transistor has its first terminal connected to the (i+3)th enable signal line, its second terminal connected to the (i+n+5)th node, and its gate connected to the (i+2n+4)th node. The first terminal of the (i+2n+8)th transistor is connected to the (i+n+2)th enable signal line, the second terminal is connected to the (i+n+5)th node, and the gate is connected to the (i+2n+4)th node. The conduction polarities of the (i+n+9)th transistor and the (i+2n+8)th transistor are opposite. The (i+3)n+7th transistor has its first terminal connected to the control signal line, its second terminal connected to the (i+2)n+4th node, and its gate connected to the (i+3)th reset line. The (i+2)th capacitor has its first electrode connected to the (i+2n+4)th node and its second electrode connected to the stable power supply terminal.
25. The display panel of claim 23, wherein, The (i+1)th driving circuit includes: The (i+1)th driving transistor has its first terminal connected to the (i+4)th (n+2)th node, its second terminal connected to the (i+6)th node, and its gate connected to the (i+3)th (n+3)th node. The (i+1)th data writing circuit includes: The (i+4n+6)th transistor has its first terminal connected to the data line, its second terminal connected to the (i+4n+2)th node, and its gate connected to the (i+1)th gate line. The (i+1)th reset circuit includes: The (i+5)n+5th transistor has its first terminal connected to the first initial signal line, its second terminal connected to the (i+3)n+3rd node, and its gate connected to the (i+n+2)th reset line. The (i+1)th compensation circuit includes: The (i+6)n+4th transistor has its first terminal connected to the (i+3)n+3rd node, its second terminal connected to the (i+6)th node, and its gate connected to the (i+1)th gate line. The (i+1)th storage circuit includes: The (i+n+1)th capacitor has its first electrode connected to the (i+3)th (n+3)th node and its second electrode connected to the (i+1)th high-level power supply line. The (i+1)th control circuit includes: The (i+7)n+3rd transistor has its first terminal connected to the (i+1)th high-level power supply line, its second terminal connected to the (i+4)n+2nd node, and its gate connected to the (i+2)n+1st enable signal line. The i+nth driving circuit includes: The (i+n)th driving transistor has its first terminal connected to the (i+5n+1)th node, its second terminal connected to the (i+6)th node, and its gate connected to the (i+6n)th node. The i+nth data writing circuit includes: The (i+8)n+2nd transistor has its first terminal connected to the data line, its second terminal connected to the (i+5)n+1st node, and its gate connected to the (i+n)th gate line. The i+nth reset circuit includes: The (i+9)n+1th transistor has its first terminal connected to the second initial signal line, its second terminal connected to the (i+6)nth node, and its gate connected to the (i+n+2)th reset line. The i+nth compensation circuit includes: The (i+10n)th transistor has its first terminal connected to the (i+6n)th node, its second terminal connected to the (i+6)th node, and its gate connected to the (i+n)th gate line. The i+nth storage circuit includes: The (i+2n)th capacitor has its first electrode connected to the (i+6n)th node and its second electrode connected to the (i+1)th low-level power supply line. The i+nth control circuit includes: The (i+1)th transistor has its first terminal connected to the (i+1)th low-level power supply line, its second terminal connected to the (i+5)th node (n+1), and its gate connected to the (i+3)th enable signal line.
26. A display device comprising: The display device includes the display panel according to any one of claims 1-25.