Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. At least one circuit unit comprises a pixel driving circuit, at least one first initial signal line (71) extending in a unit row direction, and at least one second initial trace extending in the unit row direction; the first initial signal line (71) is configured to provide a first initial signal to the pixel driving circuit, and the second initial trace is configured to provide a second initial signal to the pixel driving circuit; and the second initial trace may comprise a second initial signal line (72) and a third initial signal line (73). The pixel driving circuits and the first initial signal lines (71) of adjacent unit rows are symmetrically arranged with respect to a row centerline, the pixel driving circuits and the first initial signal lines (71) of adjacent unit columns are symmetrically arranged with respect to a column centerline, and the pixel driving circuits of adjacent unit rows share a second initial trace.

Description

Display substrate and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate including a plurality of repeating units; in a direction perpendicular to the display substrate, the repeating unit includes a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate; in a plane parallel to the display substrate, the driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit, at least one first initial signal line extending along the unit row direction, and at least one second initial trace extending along the unit row direction, the first initial signal line being configured to provide a first initial signal to the pixel driving circuit, and the second initial trace being configured to provide a first initial signal to the pixel driving circuit. The second initial signal; the light-emitting structure layer includes multiple light-emitting units, at least one light-emitting unit includes a light-emitting device, and the light-emitting device of the at least one light-emitting unit is connected to a pixel driving circuit in at least one circuit unit; the pixel driving circuit and the first initial signal line of adjacent unit rows are symmetrically arranged with respect to the row center line, and the pixel driving circuit and the first initial signal line of adjacent unit columns are symmetrically arranged with respect to the column center line, the row center line is a straight line located between two adjacent unit rows and extending along the unit row direction, and the column center line is a straight line located between two adjacent unit columns and extending along the unit column direction; in at least one repeating unit, the pixel driving circuits of adjacent unit rows share the second initial trace.

[0005] In an exemplary embodiment, at least one repeating unit further includes at least one first initial connection line extending along the unit column direction, the first initial connection line being connected to the first initial signal line to form a network connection structure on the display substrate for transmitting the first initial signal.

[0006] In an exemplary embodiment, at least one repeating unit further includes at least one first power connection line extending along the unit row direction and at least one first power line extending along the unit column direction. The first power line is configured to provide a first power signal to the pixel driving circuits in the first circuit unit to the fourth circuit unit through the first power connection line. The first power line is connected to the first power connection line to form a network interconnection structure on the display substrate for transmitting the first power signal.

[0007] In an exemplary embodiment, in at least one repeating unit, the pixel driving circuits in adjacent unit rows share the same first power connection line.

[0008] In an exemplary embodiment, at least one repeating unit further includes at least one second power connection line and at least one second power line extending along the unit column direction. The second power line is configured to provide a second power signal to the light-emitting device. At least a portion of the second power connection line extends along the unit row direction. The second power line is connected to the second power connection line to form a network interconnection structure on the display substrate for transmitting the second power signal.

[0009] In an exemplary embodiment, at least one circuit unit further includes a data signal line extending along the cell column direction, the data signal line being configured to provide a data signal to the pixel driving circuit, wherein the orthographic projection of the second power line on the substrate at least partially overlaps with the orthographic projection of the two data signal lines of the adjacent cell column on the substrate.

[0010] In an exemplary embodiment, the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor. The first terminal of the first transistor is connected to the first initial signal line; the second terminal of the first transistor is connected to the top gate electrode of the third transistor, the second terminal of the fourth transistor, and the first terminal of the first capacitor; the first terminal of the second transistor is connected to the second initial trace; the second terminal of the second transistor is connected to the second terminal of the sixth transistor and the first terminal of the seventh transistor; the first terminal of the third transistor is connected to the second terminal of the fifth transistor; the second terminal of the third transistor is connected to the first terminal of the sixth transistor, the second terminal of the first capacitor, and the second terminal of the second capacitor; the first terminal of the fourth transistor is connected to the data signal line; the first terminal of the fifth transistor is connected to the first power line; and the second terminal of the seventh transistor is connected to the first terminal of the second capacitor. The first to seventh transistors are oxide transistors, and the third transistor has a dual-gate structure.

[0011] In an exemplary embodiment, in at least one repeating unit, the plurality of circuit units include a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit periodically arranged in the unit row direction. The plurality of light-emitting units include a first light-emitting unit emitting red light, a second light-emitting unit emitting green light, a fourth light-emitting unit emitting green light, and a third light-emitting unit emitting blue light. The pixel driving circuit in the first circuit unit is connected to the light-emitting device in the first light-emitting unit, the pixel driving circuit in the second circuit unit is connected to the light-emitting device in the second light-emitting unit, the pixel driving circuit in the third circuit unit is connected to the light-emitting device in the third light-emitting unit, and the pixel driving circuit in the fourth circuit unit is connected to the light-emitting device in the fourth light-emitting unit. The first initial signal line is configured to... The pixel driving circuits in the first to fourth circuit units provide a first initial signal. The second initial trace includes a second initial signal line and a third initial signal line. The second initial signal line is configured to provide a first type of second initial signal to the pixel driving circuit in the first circuit unit. The third initial signal line is configured to provide a second type of second initial signal to the pixel driving circuits in the second, third, and fourth circuit units. The voltage of the first type of second initial signal is different from the voltage of the second type of second initial signal. The pixel driving circuits of the first circuit unit in adjacent unit rows share the same second initial signal line, and the pixel driving circuits of the second, third, and fourth circuit units in adjacent unit rows share the same third initial signal line.

[0012] In an exemplary embodiment, at least one repeating unit further includes at least one second initial connection line extending along the unit column direction, the second initial connection line being connected to the second initial signal line, forming a network connection structure on the display substrate for transmitting the first type of second initial signal.

[0013] In an exemplary embodiment, the pixel driving circuit includes at least a third transistor, and a first blocking block is disposed on the second initial connection line. The orthographic projection of the first blocking block on the substrate at least partially overlaps with the orthographic projection of the top gate electrode of the third transistor of the first circuit unit and the second circuit unit in a cell row on the substrate. Alternatively, the orthographic projection of the first blocking block on the substrate at least partially overlaps with the orthographic projection of the top gate electrode of the third transistor of the third circuit unit and the fourth circuit unit in a cell row on the substrate.

[0014] In an exemplary embodiment, the pixel driving circuit includes at least a second transistor, the second transistor includes at least a second active layer, a second blocking block is disposed on the second initial connection line, and the orthographic projection of the second blocking block on the substrate at least partially overlaps with the orthographic projections of the second active layers of the first circuit unit and the second circuit unit in one cell row, and the second active layers of the third circuit unit and the fourth circuit unit in another cell row on the substrate.

[0015] In an exemplary embodiment, at least one repeating unit further includes at least one third initial connection line extending along the unit column direction, the third initial connection line being connected to the third initial signal line to form a network connection structure on the display substrate for transmitting the second type of second initial signal.

[0016] In an exemplary embodiment, the pixel driving circuit includes at least a third transistor, and a third blocking block is disposed on the third initial connection line. The orthographic projection of the third blocking block on the substrate at least partially overlaps with the orthographic projection of the top gate electrode of the third transistor of the first circuit unit and the second circuit unit in a cell row on the substrate. Alternatively, the orthographic projection of the third blocking block on the substrate at least partially overlaps with the orthographic projection of the top gate electrode of the third transistor of the third circuit unit and the fourth circuit unit in a cell row on the substrate.

[0017] In an exemplary embodiment, the pixel driving circuit includes at least a second transistor, the second transistor includes at least a second active layer, and a fourth blocking block is disposed on the third initial connection line. The orthographic projection of the fourth blocking block on the substrate at least partially overlaps with the orthographic projections of the second active layers of the third circuit unit and the fourth circuit unit in one cell row, and the second active layers of the first circuit unit and the second circuit unit in another cell row on the substrate.

[0018] In an exemplary embodiment, the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, a seventh transistor, a first capacitor, and a second capacitor. The first terminal of the first transistor is connected to the first initial signal line, the second terminal of the first transistor is connected to the top gate electrode of the third transistor and the first terminal of the first capacitor, the first terminal of the second transistor is connected to the second initial trace, the second terminal of the second transistor is connected to the first terminal of the seventh transistor, the second terminal of the seventh transistor is connected to the first terminal of the second capacitor, and the second terminal of the third transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor. In at least one repeating unit, the aspect ratio of the third transistor in the third circuit unit is greater than the aspect ratio of the third transistor in the first circuit unit.

[0019] In an exemplary embodiment, the aspect ratio of the third transistor in the first circuit unit is greater than that of the third transistor in the second circuit unit, and the aspect ratio of the third transistor in the first circuit unit is greater than that of the third transistor in the fourth circuit unit.

[0020] In an exemplary embodiment, the seventh transistor includes at least a seventh active layer, and the second capacitor includes a stacked third plate and a fourth plate; in at least one circuit unit, the orthographic projection of the seventh active layer on the substrate at least partially overlaps with the orthographic projection of the fourth plate on the substrate.

[0021] In an exemplary embodiment, at least one circuit unit further includes a shielding line and a shielding block, the shielding block being connected to the shielding line, and the orthographic projection of the seventh active layer on the substrate at least partially overlapping the orthographic projection of the shielding block on the substrate; in a direction perpendicular to the display substrate, the shielding block is disposed between the fourth electrode plate and the seventh active layer.

[0022] In an exemplary embodiment, in at least one repeating unit, the plurality of circuit units include a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit periodically arranged in the unit row direction. The plurality of light-emitting units include a first light-emitting unit emitting red light, a second light-emitting unit emitting green light, a fourth light-emitting unit emitting green light, and a third light-emitting unit emitting blue light. The pixel driving circuit in the first circuit unit is connected to the light-emitting device in the first light-emitting unit. The pixel driving circuit in the second circuit unit is connected to the light-emitting device in the second light-emitting unit. The pixel driving circuit in the third circuit unit is connected to the light-emitting device in the third light-emitting unit. The pixel driving circuit in the fourth circuit unit is connected to the light-emitting device in the fourth light-emitting unit. The first initial signal line is configured to provide a first initial signal to the pixel driving circuits in the first to fourth circuit units. The second initial trace includes a fourth initial signal line, which is configured to provide a second initial signal to the pixel driving circuits in the first to fourth circuit units.

[0023] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0024] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0025] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0026] Figure 1 is a schematic diagram of a display device;

[0027] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0028] Figure 3 is a schematic cross-sectional view of a display substrate;

[0029] Figure 4 is an equivalent circuit diagram of a pixel driving circuit;

[0030] Figure 5 is a driving timing diagram of the pixel driving circuit shown in Figure 4;

[0031] Figure 6A is a schematic diagram of the arrangement of a circuit unit according to an exemplary embodiment of the present disclosure;

[0032] Figure 6B is a schematic diagram of the arrangement of light-emitting units according to an exemplary embodiment of the present disclosure;

[0033] Figure 6C is a schematic diagram of the connection between a circuit unit and a light-emitting unit according to an exemplary embodiment of the present disclosure;

[0034] Figure 7 is a schematic diagram of the signal line arrangement in a repeating unit according to an exemplary embodiment of the present disclosure;

[0035] Figure 8 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0036] Figure 9 is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0037] Figures 10A and 10B are schematic diagrams of a display substrate after the formation of a second conductive layer pattern according to the present disclosure;

[0038] Figures 11A and 11B are schematic diagrams of a display substrate after the formation of a third conductive layer pattern according to the present disclosure.

[0039] Figures 12A and 12B are schematic diagrams of a display substrate after a semiconductor layer pattern has been formed in this disclosure;

[0040] Figures 13A and 13B are schematic diagrams of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure.

[0041] Figure 14 is a schematic diagram of a display substrate after the formation of the fifth insulating layer pattern according to the present disclosure;

[0042] Figures 15A and 15B are schematic diagrams of a display substrate after the formation of the fifth conductive layer pattern according to the present disclosure.

[0043] Figure 16 is a schematic diagram of a display substrate after the formation of a first planarization layer pattern according to the present disclosure;

[0044] Figures 17A and 17B are schematic diagrams of a display substrate after the formation of the sixth conductive layer pattern according to the present disclosure.

[0045] Figure 18 is a schematic diagram of a display substrate after the formation of a second planarization layer pattern according to the present disclosure;

[0046] Figures 19A and 19B are schematic diagrams of a display substrate after the formation of the seventh conductive layer pattern according to the present disclosure.

[0047] Figure 20 is a schematic diagram of a display substrate after the formation of a third planarization layer pattern according to the present disclosure;

[0048] Figures 21A and 21B are schematic diagrams of a display substrate after an anode conductive layer pattern has been formed in this disclosure.

[0049] Figure 22 is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to the present disclosure;

[0050] Figure 23 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0051] Figure 24 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure.

[0052] Explanation of reference numerals in the attached figures: 10—First capacitor; 11—First electrode; 12—Second electrode; 13—Third electrode; 14—Fourth electrode; 20—Second capacitor; 21—First active layer; 22—Second active layer; 23—Third active layer; 24—Fourth active layer; 25—Fifth active layer; 26—Sixth active layer; 27—Seventh active layer; 31—First gate electrode; 33—Third top gate electrode; 34—Fourth gate electrode; 35—Third bottom gate electrode; 36—Shielding line; 37—Seventh gate electrode; 41—First light-emitting signal line; 42—Second light-emitting signal line; 51—First connecting electrode; 52—Second connecting electrode; 53—Third connecting electrode; 54—Fourth connecting electrode; 55—Fifth connecting electrode; 61—First scan signal line; 62—Second scan signal line; 63—Third scan signal line; 64—Fourth scan signal line; 65—First power supply connection line; 71—First initial signal line; 72—Second initial signal line; 73—Third initial signal line; 74—Fourth initial signal line; 81—First power supply line; 82—Second power supply line; 83—Data signal line; 84—First anode connection electrode; 85—Second anode connection electrode; 86—Second power supply connection line; 91—First initial connection line; 92—Second initial connection line; 93—Third initial connection line; 95—First blocking block; 96—Second blocking block; 97—Third blocking block; 98—Fourth blocking block; 90A—First anode; 90B—Second anode; 90C—Third anode; 90D—Fourth anode; 100A—First pixel opening; 100B—Second pixel opening; 100C—Third pixel opening; 100D—Fourth pixel aperture; 101—Substrate; 102—Driving structure layer;103—Light-emitting structural layer; 104—Encapsulation structural layer. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0054] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0055] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0056] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0057] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0058] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the area through which current primarily flows.

[0059] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0060] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0061] In this specification, "parallel" refers to two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" refers to two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0062] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0063] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances, and may include chamfers, curved edges, and other variations. The term "approximately" in this disclosure means that the limits are not strictly defined, and the values ​​are within the allowable range of process and measurement errors.

[0064] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). n, m, and o can be natural numbers. The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and clock signals, transmit stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, a scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. An emissive driver can generate transmit signals to be provided to the emissive signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the emissive driver can sequentially provide transmit signals with off-level pulses to the emissive signal lines E1 to Eo. For example, the emissive driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of off-level pulses, to the next stage circuit under the control of a clock signal. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0065] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0066] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a first green sub-pixel (G1) emitting green light, the third sub-pixel P3 can be a blue sub-pixel (B) emitting blue light, and the fourth sub-pixel P4 can be a second green sub-pixel (G2) emitting green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square or similar manner.

[0067] In other exemplary embodiments, a pixel unit may include three sub-pixels, which may be arranged in a horizontal, vertical, or triangular manner, etc., and this disclosure does not limit the arrangement.

[0068] Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of four sub-pixels in the display substrate. As shown in Figure 3, on a plane perpendicular to the display substrate, the display area may include a driving structure layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display area may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0069] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving structure layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include a light-emitting device. The light-emitting device can include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0070] Figure 4 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, 8T1C, or 8T2C structure. As shown in Figure 4, the pixel driving circuit can adopt a 7T2C structure. Each pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7) and 2 capacitors (first capacitor C1 and second capacitor C2). The pixel driving circuit is connected to 10 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, first light emission signal line EM1, second light emission signal line EM2, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA, and first power supply line VDD).

[0071] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second terminal of the first transistor T1, the gate electrode of the third transistor T3, the second terminal of the fourth transistor T4, and the first terminal of the first capacitor C1. The second node N2 is connected to the second terminal of the third transistor T3, the first terminal of the sixth transistor T6, the second terminal of the first capacitor C1, and the second terminal of the second capacitor C2. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the sixth transistor T6, and the first terminal of the seventh transistor T7. The fourth node N4 is connected to the second terminal of the seventh transistor T7 and the first terminal of the second capacitor C2.

[0072] In an exemplary embodiment, the first terminal of the first capacitor C1 is connected to the first node N1, and the second terminal of the first capacitor C1 is connected to the second node N2. The first terminal of the second capacitor C2 is connected to the fourth node N4, and the second terminal of the second capacitor C2 is connected to the second node N2.

[0073] In an exemplary embodiment, the first transistor T1 may be referred to as the first reset transistor. The gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the first node N1.

[0074] In an exemplary embodiment, the second transistor T2 may be referred to as the second reset transistor. The gate electrode of the second transistor T2 is connected to the second scan signal line S2, the first electrode of the second transistor T2 is connected to the second initial signal line INIT2, and the second electrode of the second transistor T2 is connected to the third node N3.

[0075] In an exemplary embodiment, the third transistor T3 can be referred to as the driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second electrode of the fifth transistor T5, and the second electrode of the third transistor T3 is connected to the second node N2.

[0076] In an exemplary embodiment, the fourth transistor T4 can be referred to as a data write transistor. The gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the first node N1.

[0077] In an exemplary embodiment, the fifth transistor T5 can be referred to as the first light-emitting control transistor. The gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3.

[0078] In an exemplary embodiment, the sixth transistor T6 can be referred to as the second light-emitting control transistor. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is connected to the second node N2, and the second electrode of the sixth transistor T6 is connected to the third node N3.

[0079] In an exemplary embodiment, the seventh transistor T7 can be referred to as an isolation transistor. The gate electrode of the seventh transistor T7 is connected to the fourth scan signal line S4, the first electrode of the seventh transistor T7 is connected to the third node N3, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0080] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the third node N3, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0081] In an exemplary embodiment, the seven transistors in the pixel driving circuit can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve the product yield.

[0082] In an exemplary embodiment, all seven transistors in the pixel driving circuit can be oxide transistors, and the active layer of the oxide transistors can be oxide semiconductor. Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage current. By using a display substrate with oxide transistors, low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.

[0083] In some possible implementations, the seven transistors in the pixel driving circuit can be partly N-type transistors and partly P-type transistors. The active layer of the N-type transistors can be made of oxide semiconductor, and the active layer of the P-type transistors can be made of low-temperature polycrystalline silicon (LTPS). LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS and oxide transistors onto a single display substrate forms a low-temperature polycrystalline oxide (LTPO) display substrate. This leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality. For example, the fifth transistor T5 can be replaced with a LTPS transistor to reduce the power consumption of the display substrate; however, this disclosure does not limit the scope of the invention.

[0084] In an exemplary embodiment, the first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS can be configured to provide a constant second voltage signal to the light-emitting device. The voltage of the first voltage signal is greater than the voltage of the second voltage signal, i.e., the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The first initial signal line INIT1 and the second initial signal line INIT2 can be configured to provide a constant voltage first initial signal and a constant voltage second initial signal to the pixel driving circuit; this disclosure does not limit the specific configuration.

[0085] In some possible implementations, the second voltage signal, the first initial signal, and the second initial signal can be signals with adjustable voltages. For example, the voltages of the second voltage signal, the first initial signal, and the second initial signal can be adaptively adjusted according to factors such as the temperature of the display substrate and the transistor mobility, which is not limited herein.

[0086] Figure 5 is a timing diagram of one possible pixel driving circuit shown in Figure 4. As shown in Figure 5, in an exemplary embodiment, the operation of the pixel driving circuit may include:

[0087] The first stage, A1, can be called the reset stage. The signals of the first scan signal line S1, the second scan signal line S2, the fourth scan signal line S4, and the second light-emitting signal line EM2 are high-level signals, while the signals of the third scan signal line S3 and the first light-emitting signal line EM1 are low-level signals. This turns on the first transistor T1, the second transistor T2, the sixth transistor T6, and the seventh transistor T7, while turning off the fourth transistor T4 and the fifth transistor T5. The turn-on of the first transistor T1 provides the first initial signal, INIT1, to the first node N1, initializing it. The turn-on of the second transistors T2, T6, and T7 provides the second initial signal, INIT2, to the second node N2, the third node N3, and the fourth node N4, respectively, initializing them. During this stage, the voltage difference between the first node N1 and the second node N2 turns on the third transistor T3.

[0088] The second stage, A2, can be called the compensation stage. The signals of the first scan signal line S1, the second scan signal line S2, and the fourth scan signal line S4 remain high-level signals, while the signal of the third scan signal line S3 remains low-level. The signal of the first light-emitting signal line EM1 changes from low-level to high-level, and the signal of the second light-emitting signal line EM2 changes from high-level to low-level, causing the first transistor T1, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 to conduct, while the fourth transistor T4 and the sixth transistor T6 are de-energized. The conduction of the first transistor T1 ensures that the potential of the first node N1 remains at the potential of the first initial signal. The conduction of the second transistor T2 and the seventh transistor T7 ensures that the potentials of the third node N3 and the fourth node N4 remain at the potentials of the second initial signal. The conduction of the fifth transistor T5 causes the first power signal of the first power line VDD to be output to the first terminal of the third transistor T3, turning on the third transistor T3. When the potential of the second node N2 becomes Vinit1-Vth, the third transistor T3 is de-energized. Here, Vinit1 is the voltage of the first initial signal, and Vth is the threshold voltage of the third transistor T3.

[0089] The third stage, A3, can be called the data writing stage. The first scan signal line S1 and the fourth scan signal line S4 change from high to low level. The second scan signal line S2 remains continuously high, and the third scan signal line S3 is briefly high. The first light-emitting signal line EM1 changes from high to low, and the second light-emitting signal line EM2 changes from low to high, causing the second transistor T2 to remain continuously on, the fourth transistor T4 to briefly turn on, and the fifth transistor T5 and the sixth transistor T6 to turn off. The on of the second transistor T2 ensures that the potential of the third node N3 remains at the potential of the second initial signal. The on of the fourth transistor T4 causes the data signal output from the data signal line DATA to be written to the first node N1, and the potential of the first node N1 becomes the potential of the data signal.

[0090] The fourth stage, A4, can be called the light-emitting stage. The signals on the first scan signal line S1, the third scan signal line S3, and the fourth scan signal line S4 are continuously low-level signals. The signal on the second scan signal line S2 changes from a high-level signal to a low-level signal. The signal on the first light-emitting signal line EM1 changes from a low-level signal to a high-level signal. The signal on the second light-emitting signal line EM2 is continuously high-level. The fifth transistor T5 and the sixth transistor T6 are turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned off. The turn on of the fifth transistor T5 allows the first power signal output from the first power line VDD to provide a driving voltage to the first terminal of the light-emitting element EL through the turned-on third transistor T3, fifth transistor T5, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0091] The output current of the pixel driving circuit is independent of the threshold voltage Vth of the third transistor T3, thus eliminating the influence of the threshold voltage of the third transistor T3 on the output current. The output current can be controlled by controlling the voltage of the data signal, thereby controlling the brightness of the light-emitting device EL. This ensures uniform display brightness of the display product and improves the overall display effect.

[0092] The pixel driving circuit provided in this exemplary embodiment performs threshold voltage compensation in the second stage A2 and data writing in the third stage A3. The threshold voltage compensation and data writing are separated, and the threshold voltage compensation is no longer limited by the line cycle time, enabling high-frequency driving display and enhancing the threshold voltage compensation effect. Since the first transistor T1 is disconnected before the light-emitting stage, the first power signal output from the first power line VDD can be quickly written to the second node N2, avoiding brightness differences caused by charging the first capacitor C1 and the second capacitor C2 for different low-grayscale pixels. Because the signal of the second scan signal line S2 is a continuous high-level signal during the non-light-emitting stage, the second transistor T2 remains continuously conducting, thus the potential of the third node N3 is essentially unaffected. This effectively eliminates differences in transistors at different positions due to process variations, effectively eliminates the coupling of the third node N3 to different potentials, and effectively eliminates the problem of inconsistent potentials of the third node N3 when it is lit.

[0093] This disclosure provides an exemplary embodiment of a display substrate. In an exemplary embodiment, the display substrate may include a plurality of repeating units; in a direction perpendicular to the display substrate, the repeating unit includes a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate; in a plane parallel to the display substrate, the driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit, at least one first initial signal line extending along the unit row direction, and at least one second initial trace extending along the unit row direction, the first initial signal line being configured to provide a first initial signal to the pixel driving circuit, and the second initial trace being configured to provide a first initial signal to the pixel driving circuit. The second initial signal; the light-emitting structure layer includes multiple light-emitting units, at least one light-emitting unit includes a light-emitting device, and the light-emitting device of the at least one light-emitting unit is connected to a pixel driving circuit in at least one circuit unit; the pixel driving circuit and the first initial signal line of adjacent unit rows are symmetrically arranged with respect to the row center line, and the pixel driving circuit and the first initial signal line of adjacent unit columns are symmetrically arranged with respect to the column center line, the row center line is a straight line located between two adjacent unit rows and extending along the unit row direction, and the column center line is a straight line located between two adjacent unit columns and extending along the unit column direction; in at least one repeating unit, the pixel driving circuits of adjacent unit rows share the second initial trace.

[0094] In an exemplary embodiment, the pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor. The first terminal of the first transistor is connected to the first initial signal line; the second terminal of the first transistor is connected to the top gate electrode of the third transistor, the second terminal of the fourth transistor, and the first terminal of the first capacitor; the first terminal of the second transistor is connected to the second initial trace; the second terminal of the second transistor is connected to the second terminal of the sixth transistor and the first terminal of the seventh transistor; the first terminal of the third transistor is connected to the second terminal of the fifth transistor; the second terminal of the third transistor is connected to the first terminal of the sixth transistor, the second terminal of the first capacitor, and the second terminal of the second capacitor; the first terminal of the fourth transistor is connected to the data signal line; the first terminal of the fifth transistor is connected to the first power line; and the second terminal of the seventh transistor is connected to the first terminal of the second capacitor. The first to seventh transistors are oxide transistors, and the third transistor has a dual-gate structure.

[0095] In an exemplary embodiment, in at least one repeating unit, the plurality of circuit units include a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit arranged periodically in the unit row direction. The plurality of light-emitting units include a first light-emitting unit emitting red light, a second light-emitting unit emitting green light, a fourth light-emitting unit emitting green light, and a third light-emitting unit emitting blue light. The pixel driving circuit in the first circuit unit is connected to the light-emitting device in the first light-emitting unit. The pixel driving circuit in the second circuit unit is connected to the light-emitting device in the second light-emitting unit. The pixel driving circuit in the third circuit unit is connected to the light-emitting device in the third light-emitting unit. The pixel driving circuit in the fourth circuit unit is connected to the light-emitting device in the fourth light-emitting unit. The first initial signal line is configured to provide a first initial signal to the pixel driving circuits in the first to fourth circuit units.

[0096] In one exemplary embodiment, the second initial trace includes a second initial signal line and a third initial signal line. The second initial signal line is configured to provide a first type of second initial signal to the pixel driving circuit in the first circuit unit, and the third initial signal line is configured to provide a second type of second initial signal to the pixel driving circuits in the second, third, and fourth circuit units. The voltage of the first type of second initial signal is different from the voltage of the second type of second initial signal. The pixel driving circuits of the first circuit unit in adjacent unit rows share the same second initial signal line, and the pixel driving circuits of the second, third, and fourth circuit units in adjacent unit rows share the same third initial signal line.

[0097] In another exemplary embodiment, the second initial trace includes a fourth initial signal line configured to provide a second initial signal to the pixel driving circuitry in the first to the fourth circuit units.

[0098] The following examples illustrate the display substrate of this embodiment.

[0099] An exemplary embodiment of this disclosure provides a display substrate, which may include a plurality of repeating units. In a direction perpendicular to the display substrate, the repeating unit may include at least a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. In a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. Each circuit unit may include at least a pixel driving circuit. The light-emitting structure layer may include a plurality of light-emitting units, each light-emitting unit may include at least a light-emitting device. At least one pixel driving circuit is connected to at least one light-emitting unit, and the pixel driving circuit is configured to provide a driving signal to the connected light-emitting device to drive the corresponding light-emitting device to emit light.

[0100] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to a pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to a light-emitting device. In exemplary embodiments, the orthographic projection of the light-emitting unit on the substrate and the orthographic projection of the circuit unit on the substrate may at least partially overlap, or the orthographic projection of the light-emitting unit on the substrate and the orthographic projection of the circuit unit on the substrate may not overlap.

[0101] Figure 6A is a schematic diagram of the arrangement of circuit units according to an exemplary embodiment of the present disclosure, Figure 6B is a schematic diagram of the arrangement of light-emitting units according to an exemplary embodiment of the present disclosure, and Figure 6C is a schematic diagram of the connection between circuit units and light-emitting units according to an exemplary embodiment of the present disclosure. As shown in Figures 6A, 6B, and 6C, the display substrate may include a plurality of repeating units CF, at least one repeating unit CF may include 8 circuit units and 8 light-emitting units, the 8 circuit units may form 2 unit rows and 4 unit columns, and the positions of the 8 light-emitting units may substantially correspond to the positions of the 8 circuit units.

[0102] In an exemplary embodiment, the eight circuit units of the repeating unit CF may include two first circuit units Q1, two second circuit units Q2, two third circuit units Q3, and two fourth circuit units Q4. In one unit row, the first circuit units Q1, Q2, Q3, and Q4 may be periodically arranged in the first direction X. In another unit row, the third circuit units Q3, Q4, Q1, and Q2 may be periodically arranged in the first direction X. The eight light-emitting units of the repeating unit CF may include two first light-emitting units F1, two second light-emitting units F2, two third light-emitting units F3, and two fourth light-emitting units F4. The first light-emitting units F1 and F3 may be arranged in the first direction X, and the second light-emitting units F2 and F4 may be arranged in the first direction X. The first light-emitting units F1 and F3 are staggered from the second light-emitting units F2 and F4.

[0103] In an exemplary embodiment, the first light-emitting unit F1 may include at least a first light-emitting device, the second light-emitting unit F2 may include at least a second light-emitting device, the third light-emitting unit F3 may include at least a third light-emitting device, and the fourth light-emitting unit F4 may include at least a fourth light-emitting device. The pixel driving circuit in the first circuit unit Q1 is connected to the first light-emitting device in the first light-emitting unit F1 to form a first sub-pixel. The pixel driving circuit in the second circuit unit Q2 is connected to the second light-emitting device in the second light-emitting unit F2 to form a second sub-pixel. The pixel driving circuit in the third circuit unit Q3 is connected to the third light-emitting device in the third light-emitting unit F3 to form a third sub-pixel. The pixel driving circuit in the fourth circuit unit Q4 is connected to the fourth light-emitting device in the fourth light-emitting unit F4 to form a fourth sub-pixel. In an exemplary embodiment, a sub-pixel is formed by a connected circuit unit and a light-emitting unit.

[0104] In an exemplary embodiment, the first light-emitting device may be a light-emitting device that emits red light, the second and fourth light-emitting devices may be light-emitting devices that emit green light, and the third light-emitting device may be a light-emitting device that emits blue light. Thus, the first circuit unit Q1 is the circuit unit whose pixel driving circuit drives the red light-emitting device, the second circuit unit Q2 and the fourth circuit unit Q4 are the circuit units whose pixel driving circuit drives the green light-emitting device, and the third circuit unit Q3 is the circuit unit whose pixel driving circuit drives the blue light-emitting device.

[0105] In an exemplary embodiment, the shape of the circuit unit may include any one or more of the following: triangle, rectangle, rhombus, pentagon, and hexagon, and the shape of the light-emitting unit may include any one or more of the following: triangle, rectangle, rhombus, pentagon, and hexagon.

[0106] Figure 7 is a schematic diagram of the signal line arrangement in a repeating unit according to an exemplary embodiment of the present disclosure. As shown in Figure 7, at least one repeating unit may include two first circuit units Q1, two second circuit units Q2, two third circuit units Q3, and two fourth circuit units Q4. The first circuit unit Q1 is a circuit unit whose pixel driving circuit drives a red light-emitting device, the second circuit units Q2 and the fourth circuit units Q4 are circuit units whose pixel driving circuit drives a green light-emitting device, and the third circuit unit Q3 is a circuit unit whose pixel driving circuit drives a blue light-emitting device.

[0107] In an exemplary embodiment, the pixel driving circuit in at least one repeating unit can employ a mirror-symmetric design. The pixel driving circuits of adjacent unit rows can be symmetrically arranged with respect to the row center line, and the pixel driving circuits of adjacent unit columns can be symmetrically arranged with respect to the column center line. The row center line can be a straight line located between two adjacent unit rows and extending along a first direction X (unit row direction), and the column center line can be a straight line located between two adjacent unit columns and extending along a second direction Y (unit column direction). For example, in a unit row, the pixel driving circuits of the first circuit unit Q1 and the second circuit unit Q2 can be mirror-symmetric with respect to the column center line; the pixel driving circuits of the second circuit unit Q2 and the third circuit unit Q3 can be mirror-symmetric with respect to the column center line; the pixel driving circuits of the third circuit unit Q3 and the fourth circuit unit Q1 can be mirror-symmetric with respect to the column center line; and the pixel driving circuits of the fourth circuit unit Q1 and the first circuit unit Q1 can be mirror-symmetric with respect to the column center line. For example, in a cell column, the pixel driving circuits of the first circuit unit Q1 and the third circuit unit Q3 can be mirror-symmetrical with respect to the row center line, and the pixel driving circuits of the second circuit unit Q2 and the fourth circuit unit Q1 can be mirror-symmetrical with respect to the row center line.

[0108] In an exemplary embodiment, at least one repeating unit may further include at least one first initial signal line 71 transmitting a first initial signal and at least one second initial trace transmitting a second initial signal. The shape of the first initial signal line 71 may be a straight line or a broken line extending along the first direction X of the main body. The first initial signal line 71 may be disposed in each unit row and connected to the pixel driving circuits in the plurality of circuit units in the unit row. The first initial signal line 71 is configured to provide the same first initial signal to the pixel driving circuits in the first circuit unit Q1 to the fourth circuit unit Q4 in the unit row.

[0109] In an exemplary embodiment, in at least one repeating unit, the two first initial signal lines 71 in adjacent unit rows can be mirror-symmetrical with respect to the row center line.

[0110] In an exemplary embodiment, in at least one repeating unit, the second initial trace may include a second initial signal line 72 and a third initial signal line 73. The shapes of the second initial signal line 72 and the third initial signal line 73 may be straight lines or broken lines extending along the first direction X. The second initial signal line 72 may be connected to the pixel driving circuits of the two first circuit units Q1 in the repeating unit and is configured to provide a first type of second initial signal to the pixel driving circuits of the two first circuit units Q1. The third initial signal line 73 may be connected to the pixel driving circuits of the two second circuit units Q2, the two third circuit units Q3, and the two fourth circuit units Q4 in the repeating unit and is configured to provide a second type of second initial signal to the pixel driving circuits of the two second circuit units Q2, the two third circuit units Q3, and the two fourth circuit units Q4. The voltage of the first type of second initial signal is different from the voltage of the second type of second initial signal.

[0111] This embodiment of the disclosure splits the second initial trace for transmitting the second initial signal into a second initial signal line 72 and a third initial signal line 73. The second initial signal line 72 is configured to provide a first type of second initial signal to the pixel driving circuit of a plurality of first circuit units Q1, and the third initial signal line 73 is configured to provide a second type of second initial signal to the pixel driving circuit of a plurality of second circuit units Q2, a plurality of third circuit units Q3, and a plurality of fourth circuit units Q4. This enables the provision of different reset voltages to light-emitting devices of different colors, which can effectively improve the low grayscale display quality, display quality, and display effect.

[0112] In some possible implementations, the second initial trace transmitting the second initial signal can be split into three initial signal lines. One initial signal line is configured to provide a first type of second initial signal to the pixel driving circuit of the first circuit unit, another initial signal line is configured to provide a second type of second initial signal to the pixel driving circuits of the second and fourth circuit units, and yet another initial signal line is configured to provide a third type of second initial signal to the pixel driving circuit of the third circuit unit. This disclosure does not limit the scope of the implementation.

[0113] In an exemplary embodiment, at least one repeating unit may further include at least one first initial connecting line 91, at least one second initial connecting line 92, and at least one third initial connecting line 93. The shapes of the first initial connecting line 91, the second initial connecting line 92, and the third initial connecting line 93 may be straight lines or broken lines extending along the second direction Y of the main body portion.

[0114] In an exemplary embodiment, the first initial connection line 91 can be connected to the first initial signal line 71 to form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal. The second initial connection line 92 can be connected to the second initial signal line 72 to form a mesh-like interconnected structure on the display substrate for transmitting a first type of second initial signal. The third initial connection line 93 can be connected to the third initial signal line 73 to form a mesh-like interconnected structure on the display substrate for transmitting a second type of second initial signal.

[0115] In an exemplary embodiment, at least one repeating unit may further include at least one first power connection line 65 and at least one first power line 81. The shape of the first power connection line 65 may be a straight line or a broken line extending along the first direction X of the main body. The shape of the first power line 81 may be a straight line or a broken line extending along the second direction Y of the main body.

[0116] In an exemplary embodiment, a first power connection line 65 may be disposed in each cell row, and a first power line 81 may be disposed in some cell columns. The first power connection line 65 is connected to the first power line 81 to form a mesh-like interconnected structure on the display substrate for transmitting a first power signal. The first power line 81 is configured to provide a first power signal to the pixel driving circuits in the first circuit unit Q1 to the fourth circuit unit Q4 through the first power connection line 65.

[0117] Figure 8 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit. The circuit units defined by the Mth unit row and Nth unit column, and the circuit units defined by the (M+1)th unit row and N+2th unit column are first circuit units; the circuit units defined by the Mth unit row and N+1th unit column, and the circuit units defined by the (M+1)th unit row and N+3th unit column are second circuit units; the circuit units defined by the Mth unit row and N+2th unit column, and the circuit units defined by the (M+1)th unit row and Nth unit column are third circuit units; and the circuit units defined by the Mth unit row and N+3th unit column, and the circuit units defined by the (M+1)th unit row and N+1th unit column are fourth circuit units. As shown in Figure 8, the display substrate may include multiple repeating units, and at least one repeating unit may include eight circuit units forming two unit rows and four unit columns. At least one unit row may include first, second, third, and fourth circuit units periodically arranged in a first direction X.

[0118] In an exemplary embodiment, at least one circuit unit may include a pixel driving circuit, and a first light-emitting signal line 41, a second light-emitting signal line 42, a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a first initial signal line 71, a second initial trace (either the second initial signal line 72 or the third initial signal line 73), a first power supply line 81, and a data signal line 83 connected to the pixel driving circuit. At least one pixel driving circuit may include at least a first capacitor 10, a second capacitor 20, a first transistor T1 as a first reset transistor, a second transistor T2 as a second reset transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, and a seventh transistor T7 as an isolation transistor. In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be oxide transistors, the third transistor T3 may be a dual-gate structure, and the other transistors may be single-gate structures.

[0119] In some possible implementations, all seven transistors of the pixel driving circuit may be dual-gate structures, or at least two transistors may be dual-gate structures and the remaining transistors may be single-gate structures, which is not limited herein.

[0120] In an exemplary embodiment, the first capacitor 10 may include at least a first electrode and a second electrode stacked together, wherein the orthographic projection of the second electrode onto the base plane at least partially overlaps with the orthographic projection of the first electrode onto the base plane. The first electrode may serve as the first terminal of the first capacitor 10, having the potential of the first node N1 in the pixel driving circuit, and the second electrode may serve as the second terminal of the first capacitor 10, having the potential of the second node N2 in the pixel driving circuit.

[0121] In an exemplary embodiment, the second capacitor 20 may include at least a stacked third plate and a fourth plate, wherein the orthographic projection of the fourth plate 14 onto the base plane at least partially overlaps with the orthographic projection of the third plate onto the base plane. The third plate may serve as the first terminal of the second capacitor 20, having the potential of the fourth node N4 in the pixel driving circuit, and the fourth plate may serve as the second terminal of the second capacitor 20, having the potential of the second node N2 in the pixel driving circuit.

[0122] In an exemplary embodiment, the first light-emitting signal line 41 to the second light-emitting signal line 42 are configured to provide a first light-emitting control signal and a second light-emitting control signal to the pixel driving circuit, respectively; the first scan signal line 61 to the fourth scan signal line 64 are configured to provide a first scan signal to a fourth scan signal to the pixel driving circuit, respectively; the first initial signal line 71 and the second initial trace are configured to provide a first initial signal and a second initial signal to the pixel driving circuit, respectively; the first power line 81 is configured to provide a first power signal to the pixel driving circuit; and the data signal line 83 is configured to provide a data signal to the pixel driving circuit.

[0123] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first scan signal line 61, the first terminal of the first transistor T1 is connected to the first initial signal line 71, and the second terminal of the first transistor T1 is connected to the top gate electrode 33 of the third transistor T3, the second terminal of the fourth transistor T4, and the first plate of the first capacitor 10, respectively. The gate electrode of the second transistor T2 is connected to the second scan signal line 62, the first terminal of the second transistor T2 is connected to the second initial trace, and the second terminal of the second transistor T2 is connected to the second terminal of the sixth transistor T6 and the first terminal of the seventh transistor T7, respectively. The first terminal of the third transistor T3 is connected to the second terminal of the fifth transistor T5, and the second terminal of the third transistor T3 is connected to the first terminal of the sixth transistor T6, the second plate of the first capacitor 10, and the fourth plate of the second capacitor 20, respectively. The gate electrode of the fourth transistor T4 is connected to the third scan signal line 63, and the first terminal of the fourth transistor T4 is connected to the data signal line 83. The gate electrode of the fifth transistor T5 is connected to the first light emission signal line 41, and the first terminal of the fifth transistor T5 is connected to the first power supply line 81. The gate electrode of the sixth transistor T6 is connected to the second light-emitting signal line 42. The gate electrode of the seventh transistor T7 is connected to the fourth scan signal line 64, and the second electrode of the seventh transistor T7 is connected to the third plate of the second capacitor 20.

[0124] In an exemplary embodiment, in at least one repeating unit, the pixel driving circuits of adjacent unit rows can be arranged substantially symmetrically with respect to the row center line, and the pixel driving circuits of adjacent unit columns can be arranged substantially symmetrically with respect to the column center line. For example, the pixel driving circuits in the Mth unit row and the (M+1)th unit row can be arranged substantially symmetrically with respect to the row center line. Similarly, the pixel driving circuits in the Nth unit column and the (N+1)th unit column can be arranged substantially symmetrically with respect to the column center line, the pixel driving circuits in the (N+1)th unit column and the (N+2)th unit column can be arranged substantially symmetrically with respect to the column center line, and the pixel driving circuits in the (N+2)th unit column and the (N+3)th unit column can be arranged substantially symmetrically with respect to the column center line.

[0125] In an exemplary embodiment, the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the first light emission signal line 41, the second light emission signal line 42, the first initial signal line 71, the second initial signal line 72, and the third initial signal line 73 can be straight lines or broken lines extending along the first direction X of the main body, and the shapes of the first power line 81 and the data signal line 83 can be straight lines or broken lines extending along the second direction Y of the main body.

[0126] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0127] In an exemplary embodiment, in the Mth cell row, the first scan signal line 61 may be located on the side opposite to the second direction Y of the top gate electrode 33 (i.e., the third top gate electrode) of the third transistor T3, and the third scan signal line 63 may be located on the side of the second direction Y of the top gate electrode 33 of the third transistor T3. In the M+1th cell row, the first scan signal line 61 may be located on the side of the second direction Y of the top gate electrode 33 of the third transistor T3, and the third scan signal line 63 may be located on the side opposite to the second direction Y of the top gate electrode 33 of the third transistor T3.

[0128] In an exemplary embodiment, the first initial signal line 71 may be located on the side of the first scan signal line 61 away from the top gate electrode 33 of the third transistor T3, and the first light-emitting signal line 41 may be located on the side of the first initial signal line 71 away from the top gate electrode 33 of the third transistor T3. The second light-emitting signal line 42 may be located on the side of the third scan signal line 63 away from the top gate electrode 33 of the third transistor T3, and the fourth scan signal line 64 may be located on the side of the second light-emitting signal line 42 away from the top gate electrode 33 of the third transistor T3, and the second scan signal line 62 may be located on the side of the fourth scan signal line 64 away from the top gate electrode 33 of the third transistor T3.

[0129] In an exemplary embodiment, in at least one repeating unit, a first initial signal line 71 may be provided in each unit row and connected to the pixel driving circuits in the first to fourth circuit units in the unit row. The first initial signal line 71 is configured to provide the same first initial signal to the pixel driving circuits in the first to fourth circuit units Q1 to Q4 in the unit row.

[0130] In an exemplary embodiment, the position and shape of the first initial signal line 71 of adjacent cell rows can be set substantially symmetrically with respect to the row center line.

[0131] In an exemplary embodiment, in at least one repeating unit, the second initial trace may be located between the fourth scan signal lines 64 of two unit rows, and the pixel driving circuits of adjacent unit rows may share the second initial trace. The second initial signal line 72 may be located on the side of the fourth scan signal line 64 in the (M+1)th unit row away from the top gate electrode 33 of the third transistor T3. The second initial signal line 72 is configured to provide a first type of second initial signal to the pixel driving circuits of the first circuit units in the two adjacent unit rows, and the pixel driving circuits of the first circuit units in the two adjacent unit rows share the same second initial signal line 72. The third initial signal line 73 may be located on the side of the fourth scan signal line 64 in the Mth unit row away from the top gate electrode 33 of the third transistor T3. The third initial signal line 73 is configured to provide a second type of second initial signal to the pixel driving circuits of the second, third, and fourth circuit units in the two adjacent unit rows, and the pixel driving circuits of the second, third, and fourth circuit units in the two adjacent unit rows share the same third initial signal line 73. The voltage of the first type of second initial signal is different from the voltage of the second type of second initial signal. The voltage values ​​of the first type of second initial signal and the second type of second initial signal can be determined based on the OLED capacitor connected to the circuit unit.

[0132] In some possible implementations, the second initial trace can be split into a second initial signal line, a third initial signal line, and a fourth initial signal line, depending on the spatial layout. The second initial signal line is configured to provide a first type of second initial signal to the pixel driving circuit of the first circuit unit, the third initial signal line is configured to provide a second type of second initial signal to the pixel driving circuits in the second and fourth circuit units, and the fourth initial signal line is configured to provide a third type of second initial signal to the pixel driving circuit in the third circuit unit. This disclosure does not limit the scope of the implementation.

[0133] In an exemplary embodiment, at least one repeating unit may further include at least one first power connection line 65. The shape of the first power connection line 65 may be a straight line or a broken line with its main body extending along the first direction X, and it may be located on the side of the first light-emitting signal line 41 away from the top gate electrode 33 of the third transistor T3. The first power connection line 65 extending along the first direction X is connected to a first power line 81 extending along the second direction Y, and the first power connection line 65 and the first power line 81 form a mesh-like interconnected structure on the display substrate for transmitting the first power signal.

[0134] In an exemplary embodiment, the first power line 81 can be connected to the first power connection line 65 via a via, and the first power line 81 is configured to provide a first power signal to the pixel driving circuits in the first circuit unit Q1 to the fourth circuit unit Q4 via the first power connection line 65.

[0135] In an exemplary embodiment, the first power connection line 65 can be provided in each cell row, and the pixel driving circuits in adjacent cell rows can share the same first power connection line 65. The first power line 81 can be provided in some cell columns.

[0136] In an exemplary embodiment, at least one repeating unit may further include at least one first initial connecting line 91, at least one second initial connecting line 92, and at least one third initial connecting line 93. The shapes of the first initial connecting line 91, the second initial connecting line 92, and the third initial connecting line 93 may be straight lines or broken lines extending along the second direction Y of the main body portion.

[0137] In an exemplary embodiment, a first initial signal line 71 extending along a first direction X is connected to a first initial connection line 91 extending along a second direction Y, and the first initial signal line 71 and the first initial connection line 91 form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal.

[0138] In an exemplary embodiment, the first initial signal line 71 may be disposed in each cell row, and the first initial connection line 91 may be disposed between some cell columns (such as between the N+1th cell column and the N+2th cell column). The first initial connection line 91 may be connected to the first initial signal line 71 through a via.

[0139] In an exemplary embodiment, the first initial connection line 91 may be disposed between two data signal lines 83 of adjacent cell columns.

[0140] In an exemplary embodiment, a second initial signal line 72 extending along a first direction X is connected to a second initial connection line 92 extending along a second direction Y. The second initial signal line 72 and the second initial connection line 92 form a mesh-like interconnected structure on the display substrate for transmitting a first type of second initial signal. A third initial signal line 73 extending along the first direction X is connected to a third initial connection line 93 extending along the second direction Y. The third initial signal line 73 and the third initial connection line 93 form a mesh-like interconnected structure on the display substrate for transmitting a second type of second initial signal.

[0141] In an exemplary embodiment, in at least one repeating unit, a first blocking block 95 and a second blocking block 96 may be connected to the second initial connection line 92. The orthographic projection of the first blocking block 95 on the substrate at least partially overlaps with the orthographic projection of the top gate electrode 33 of the third transistor T3 of the first and second circuit units in one unit row on the substrate, or the orthographic projection of the first blocking block 95 on the substrate at least partially overlaps with the orthographic projection of the top gate electrode 33 of the third transistor T3 of the third and fourth circuit units in one unit row on the substrate. The orthographic projection of the second blocking block 96 on the substrate at least partially overlaps with the orthographic projections of the active layers of the second transistor T2 of the first and second circuit units in one unit row, and the active layers of the second transistor T2 of the third and fourth circuit units in another unit row on the substrate.

[0142] In an exemplary embodiment, in at least one repeating unit, a third blocking block 97 and a fourth blocking block 98 may be connected to the third initial connection line 93. The orthographic projection of the third blocking block 97 on the substrate at least partially overlaps with the orthographic projection of the top gate electrode 33 of the third transistor T3 of the first and second circuit units in one unit row on the substrate, or the orthographic projection of the third blocking block 97 on the substrate at least partially overlaps with the orthographic projection of the top gate electrode 33 of the third transistor T3 of the third and fourth circuit units in one unit row on the substrate. The orthographic projection of the fourth blocking block 98 on the substrate at least partially overlaps with the orthographic projections of the active layers of the second transistor T2 of the third and fourth circuit units in one unit row, and the active layers of the second transistor T2 of the first and second circuit units in another unit row on the substrate.

[0143] In some possible implementations, the first blocking block, the second blocking block, the third blocking block and / or the fourth blocking block can be disposed on other constant voltage signal lines extending along the second direction Y, or can be disposed on the anode in the anode conductive layer, all of which can serve to block the second transistor T2 and the third transistor T3. This disclosure does not limit the scope of the invention.

[0144] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a first conductive layer (first gate metal layer) disposed on a substrate, a first insulating layer disposed on the side of the first conductive layer away from the substrate, a second conductive layer (second gate metal layer) disposed on the side of the first insulating layer away from the substrate, a second insulating layer disposed on the side of the second conductive layer away from the substrate, a third conductive layer (third gate metal layer) disposed on the side of the second insulating layer away from the substrate, a third insulating layer disposed on the side of the third conductive layer away from the substrate, a semiconductor layer disposed on the side of the third insulating layer away from the substrate, a fourth insulating layer disposed on the side of the semiconductor layer away from the substrate, a fourth conductive layer (fourth gate metal layer) disposed on the side of the fourth insulating layer away from the substrate, a fifth insulating layer disposed on the side of the fourth conductive layer away from the substrate, a fifth conductive layer (first source / drain metal layer) disposed on the side of the fifth insulating layer away from the substrate, a first planarization layer disposed on the side of the fifth conductive layer away from the substrate, a sixth conductive layer (second source / drain metal layer) disposed on the side of the first planarization layer away from the substrate, a seventh conductive layer (third source / drain metal layer) disposed on the side of the sixth conductive layer away from the substrate, and a third planarization layer disposed on the side of the seventh conductive layer away from the substrate.

[0145] In an exemplary embodiment, the first and third electrode plates can be disposed in the first conductive layer, the second and fourth electrode plates can be disposed in the second conductive layer, the bottom gate electrode of the third transistor T3 can be disposed in the third conductive layer, the active layer of the plurality of transistors can be disposed in the semiconductor layer, the first light-emitting signal line 41, the second light-emitting signal line 42, the second scan signal line 62 and the gate electrodes of the plurality of transistors can be disposed in the fourth conductive layer, the first scan signal line 61, the third scan signal line 63, the fourth scan signal line 64, the first power connection line 65, the first initial signal line 71, the second initial signal line 72, the third initial signal line 73 and the plurality of connection electrodes can be disposed in the fifth conductive layer, the first power line 81, the data signal line 83, the first initial connection line 91, the second initial connection line 92 and the third initial connection line 93 can be disposed in the sixth conductive layer, and the second power line and the second power connection line can be disposed in the seventh conductive layer.

[0146] The following exemplary description illustrates the fabrication process of the display substrate using this exemplary embodiment. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film layer, coating the film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include coating the organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching, and this disclosure does not limit the methods. A "thin film" refers to a thin film made by depositing, coating, or other processes onto a substrate using a certain material. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0147] In an exemplary embodiment, taking eight circuit units of a repeating unit as an example, the fabrication process of the display substrate in this embodiment may include the following operations. The circuit units defined by the Mth unit row and Nth unit column, and the circuit units defined by the (M+1)th unit row and N+2th unit column are first circuit units; the circuit units defined by the Mth unit row and N+1th unit column, and the circuit units defined by the (M+1)th unit row and N+3th unit column are second circuit units; the circuit units defined by the Mth unit row and N+2th unit column, and the circuit units defined by the (M+1)th unit row and Nth unit column are third circuit units; and the circuit units defined by the Mth unit row and N+3th unit column, and the circuit units defined by the (M+1)th unit row and N+1th unit column are fourth circuit units.

[0148] (11) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a first conductive thin film on a substrate, patterning the first conductive thin film using a patterning process, and forming a first conductive layer pattern on the substrate, as shown in FIG9. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0149] In an exemplary embodiment, the first conductive layer pattern of each circuit unit (including the first to fourth circuit units, hereinafter the same) in the display substrate may include at least the first electrode 11 of the first capacitor and the third electrode 13 of the second capacitor.

[0150] In an exemplary embodiment, the shape of the first plate 11 of the first capacitor can be block-shaped (such as rectangular), the corners of the block shape can be rounded, and the edge of the block shape can be a straight line or a broken line. The first plate 11 is configured as a capacitor plate of the first capacitor (the first end of the first capacitor C1).

[0151] In an exemplary embodiment, the third plate 13 of the second capacitor can be block-shaped (such as rectangular), the corners of the block shape can be rounded, the edges of the block shape can be straight lines or broken lines, and it can be located on one side of the first plate 11 in the second direction Y. The third plate 13 is configured as a capacitor plate of the second capacitor (the first end of the second capacitor C2).

[0152] In an exemplary embodiment, the shapes of the first electrode plates 11 in the first to fourth circuit units can be substantially the same, and the areas of the first electrode plates 11 projected onto the substrate in the first to fourth circuit units can be substantially the same. The shapes of the third electrode plates 13 in the first to fourth circuit units can be substantially the same, and the areas of the third electrode plates 13 projected onto the substrate in the first to fourth circuit units can be substantially the same.

[0153] In an exemplary embodiment, the first conductive layers in adjacent cell columns can be arranged substantially symmetrically with respect to the column center line. For example, the first electrode 11 and the third electrode 13 in the Nth and N+1th cell columns can be arranged substantially symmetrically with respect to the column center line. Similarly, the first electrode 11 and the third electrode 13 in the N+1th and N+2th cell columns can be arranged substantially symmetrically with respect to the column center line. And again, the first electrode 11 and the third electrode 13 in the N+2th and N+3th cell columns can be arranged substantially symmetrically with respect to the column center line.

[0154] In an exemplary embodiment, the first conductive layer in adjacent cell rows can be arranged substantially symmetrically with respect to the row center line. For example, the first electrode 11 and the third electrode 13 in the Mth cell row and the M+1th cell row can be arranged substantially symmetrically with respect to the row center line.

[0155] (12) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a first insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a first insulating layer covering the first conductive layer pattern; and a second conductive layer pattern disposed on the first insulating layer, as shown in Figures 10A and 10B, where Figure 10B is a planar schematic diagram of the second conductive layer in Figure 10A. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0156] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: the second electrode 12 of the first capacitor and the fourth electrode 14 of the second capacitor.

[0157] In an exemplary embodiment, the shape of the second electrode plate 12 of the first capacitor can be block-shaped (such as rectangular), the corners of the block shape can be rounded, and the edge of the block shape can be a straight line or a broken line. The orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 12 is configured as another capacitor electrode plate of the first capacitor (the second end of the first capacitor C1). The stacked first electrode plate 11 and the second electrode plate 12 constitute the first capacitor C1 of the pixel driving circuit.

[0158] In an exemplary embodiment, the area of ​​the second electrode 12 projected onto the substrate can be larger than the area of ​​the first electrode 11 projected onto the substrate. The block-shaped first electrode 11 can have multiple edges, and the orthogonal projection of at least one edge onto the substrate can be within the range of the orthogonal projection of the second electrode 12 onto the substrate, that is, the second electrode 12 covers at least one edge of the first electrode 11. By setting the area of ​​the second electrode 12 to be larger than the area of ​​the first electrode 11, the present disclosure effectively shields the first electrode 11 by substantially covering it, thereby improving the stability of the first node potential.

[0159] In an exemplary embodiment, the fourth electrode plate 14 of the second capacitor can be block-shaped (such as rectangular), with rounded corners at the corners and straight or broken edges. It can be located on one side of the second electrode plate 12 in the second direction Y. The orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate. The fourth electrode plate 14 is configured as another capacitor electrode of the second capacitor (the second end of the second capacitor C2). The stacked third electrode plate 13 and the fourth electrode plate 14 constitute the second capacitor C2 of the pixel driving circuit.

[0160] In an exemplary embodiment, the area of ​​the fourth electrode 14 projected onto the substrate can be larger than the area of ​​the third electrode 13 projected onto the substrate. The block-shaped third electrode 13 can have multiple edges, and the orthogonal projection of at least one edge onto the substrate can be within the range of the orthogonal projection of the fourth electrode 14 onto the substrate, that is, the fourth electrode 14 covers at least one edge of the third electrode 13. By setting the area of ​​the fourth electrode 14 to be larger than the area of ​​the third electrode 13, the present disclosure effectively shields the third electrode 13 and improves the stability of the third node potential by substantially covering the third electrode 13.

[0161] In an exemplary embodiment, a first groove 12-1 may be provided on the second electrode plate 12, the first groove 12-1 being configured to expose the first electrode plate 11.

[0162] In an exemplary embodiment, a second groove 14-1 may be provided on the fourth electrode plate 14, the second groove 14-1 being configured to expose the third electrode plate 13.

[0163] In an exemplary embodiment, the shapes of the second electrode plates 12 in the first to fourth circuit units can be substantially the same, and the overlapping areas of the orthographic projections of the second electrode plates 12 and 11 onto the substrate in the first to fourth circuit units can be substantially the same, meaning the capacitance values ​​of the first capacitors in the first to fourth circuit units can be substantially the same. Similarly, the shapes of the fourth electrode plates 14 in the first to fourth circuit units can be substantially the same, and the overlapping areas of the orthographic projections of the fourth electrode plates 14 and 3 onto the substrate in the first to fourth circuit units can be substantially the same, meaning the capacitance values ​​of the second capacitors in the first to fourth circuit units can be substantially the same.

[0164] In an exemplary embodiment, in at least one circuit unit, the second electrode plate 12 and the fourth electrode plate 14 can be an integral structure that is interconnected.

[0165] In an exemplary embodiment, the second conductive layers in adjacent cell columns can be arranged substantially symmetrically with respect to the column center line. For example, the second electrode 12 and the fourth electrode 14 in the Nth and N+1th cell columns can be arranged substantially symmetrically with respect to the column center line. Similarly, the second electrode 12 and the fourth electrode 14 in the N+1th and N+2th cell columns can be arranged substantially symmetrically with respect to the column center line. Furthermore, the second electrode 12 and the fourth electrode 14 in the N+2th and N+3th cell columns can be arranged substantially symmetrically with respect to the column center line.

[0166] In an exemplary embodiment, the second conductive layers in adjacent cell rows can be arranged substantially symmetrically with respect to the row center line. For example, the second electrode 12 and the fourth electrode 14 in the Mth cell row and the M+1th cell row can be arranged substantially symmetrically with respect to the row center line.

[0167] (13) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a second insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a second insulating layer covering the second conductive layer pattern; and a third conductive layer pattern disposed on the second insulating layer, as shown in Figures 11A and 11B, where Figure 11B is a planar schematic diagram of the third conductive layer in Figure 11A. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0168] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate includes at least a third bottom gate electrode 35.

[0169] In an exemplary embodiment, the third bottom gate electrode 35 may be rectangular in shape, and the orthographic projection of the third bottom gate electrode 35 on the substrate may at least partially overlap with the orthographic projection of the second electrode plate 12 on the substrate. The third bottom gate electrode 35 may serve as the bottom gate electrode of the third transistor T3.

[0170] In an exemplary embodiment, the orthogonal projection of the third bottom gate electrode 35 onto the substrate is within the range of the orthogonal projection of the second electrode plate 12 onto the substrate.

[0171] In an exemplary embodiment, a third gate connection block 35-1 may be provided on the third gate electrode 35. The third gate connection block 35-1 may be strip-shaped, with a first end connected to the third gate electrode 35 and a second end extending away from the third gate electrode 35. The second end of the third gate connection block 35-1 is configured to connect to a subsequently formed second connection electrode.

[0172] In an exemplary embodiment, the orthographic projection of the third bottom grid connecting block 35-1 on the substrate is within the range of the orthographic projection of the second pole plate 12 on the substrate.

[0173] In an exemplary embodiment, in at least one circuit unit, the third bottom gate electrode 35 and the third bottom gate connection block 35-1 can be an integral structure that is interconnected.

[0174] In some possible implementations, the display substrate may not have a third conductive layer, and the second electrode plate 12 may be used as the bottom gate electrode of the third transistor T3. This disclosure does not limit the scope of the invention.

[0175] In an exemplary embodiment, the positions of the third bottom gate electrode 35 and the third bottom gate connecting block 35-1 in adjacent cell columns can be arranged substantially symmetrically with respect to the column center line, and the positions of the third bottom gate electrode 35 and the third bottom gate connecting block 35-1 in adjacent cell rows can be arranged substantially symmetrically with respect to the row center line.

[0176] (14) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a third insulating film and a semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the semiconductor film by a patterning process to form a third insulating layer covering a third conductive layer, and a semiconductor layer pattern disposed on the third insulating layer, as shown in Figures 12A and 12B, where Figure 12B is a planar schematic diagram of the semiconductor layer in Figure 12A.

[0177] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display substrate may include the first active layer 21 of the first transistor T1 to the seventh active layer 27 of the seventh transistor T7, and the first active layer 21 and the fourth active layer 24 may be an integral structure interconnected with each other, and the second active layer 22, the third active layer 23, the fifth active layer 25, the sixth active layer 26 and the seventh active layer 27 may be an integral structure interconnected with each other.

[0178] In an exemplary embodiment, the first active layer 21 to the sixth active layer 26 may be strip-shaped extending along the second direction Y, and the seventh active layer 27 may be strip-shaped extending along the first direction X. The first active layer 21 and the fourth active layer 24 may be located on the same side of the third active layer 23 in the first direction X, the fifth active layer 25 may be located on one side of the third active layer 23 in the second direction Y, and the second active layer 22, the sixth active layer 26, and the seventh active layer 27 may be located on the other side of the third active layer 23 in the second direction Y.

[0179] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region.

[0180] In an exemplary embodiment, in at least one circuit unit, the second region 21-2 of the first active layer and the second region 24-2 of the fourth active layer can be interconnected, and the second region 21-2 of the first active layer can serve as the second region 24-2 of the fourth active layer. The second region 22-2 of the second active layer, the second region 26-2 of the sixth active layer, and the first region 27-1 of the seventh active layer can be interconnected, and the second region 22-2 of the second active layer can simultaneously serve as the second region 26-2 of the sixth active layer and the first region 27-1 of the seventh active layer. The first region 23-1 of the third active layer and the second region 25-2 of the fifth active layer can be interconnected, and the first region 23-1 of the third active layer can serve as the second region 25-2 of the fifth active layer. The second region 23-2 of the third active layer and the first region 26-1 of the sixth active layer can be interconnected, and the second region 23-2 of the third active layer can serve as the first region 26-1 of the sixth active layer. The first active layer's first zone 21-1, the second active layer's first zone 22-1, the fourth active layer's first zone 24-1, the fifth active layer's first zone 25-1, and the seventh active layer's second zone 27-2 can be set individually.

[0181] In an exemplary embodiment, in at least one repeating unit, the first region 22-1 of the second active layer of two partially adjacent circuit units in a unit column can be interconnected. The second active layers 22 of the two adjacent circuit units can be an integral structure interconnected, and the two adjacent circuit units share the same first region 22-1 of the second active layer. For example, in the N+1th unit column, the second active layers 22 of the second circuit unit and the fourth circuit unit can be an integral structure interconnected. Similarly, in the N+3th unit column, the second active layers 22 of the second circuit unit and the fourth circuit unit can be an integral structure interconnected.

[0182] In an exemplary embodiment, in at least one repeating unit, the first region 22-1 of the second active layer of two partially adjacent circuit units in a unit row can be interconnected. The second active layers 22 of the two adjacent circuit units can be an integral structure interconnected, and the two adjacent circuit units share the same first region 22-1 of the second active layer. For example, in the Mth unit row, the second active layers 22 of the third and fourth circuit units can be an integral structure interconnected. Similarly, in the M+1th unit row, the second active layers 22 of the third and fourth circuit units can be an integral structure interconnected.

[0183] In an exemplary embodiment, in at least one repeating unit, the first region 22-1 of the second active layer of three partially adjacent circuit units can be interconnected, and the second active layers 22 of the three adjacent circuit units can be an integral structure interconnected, with the three adjacent circuit units sharing the same first region 22-1 of the second active layer. For example, the second active layers 22 of the fourth circuit unit, the third circuit unit adjacent to the fourth circuit unit in the first direction X, and the second circuit unit adjacent to the fourth circuit unit in the second direction Y can be an integral structure interconnected, that is, the second active layers 22 of the adjacent second circuit unit, third circuit unit, and fourth circuit unit can be an integral structure interconnected. By setting some adjacent circuit units to share the first region of the second active layer (i.e., the first electrode of the second transistor T2), this disclosure can effectively reduce the vertical wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0184] In an exemplary embodiment, in some circuit units, the orthographic projection of the seventh active layer 27 onto the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 14 onto the substrate.

[0185] In an exemplary embodiment, the first region 21-1 of the first active layer can serve as the first electrode of the first transistor T1, the second region 21-2 of the first active layer can serve as the second electrode of the first transistor T1, the first region 22-1 of the second active layer can serve as the first electrode of the second transistor T2, the second region 22-2 of the second active layer can serve as the second electrode of the second transistor T2, the first region 23-1 of the third active layer can serve as the first electrode of the third transistor T3, the second region 23-2 of the third active layer can serve as the second electrode of the third transistor T3, and the first region 24-1 of the fourth active layer can serve as the fourth transistor T4. The first electrode of the fourth active layer, the second region 24-2, can be used as the second electrode of the fourth transistor T4; the first region 25-1 of the fifth active layer can be used as the first electrode of the fifth transistor T5; the second region 25-2 of the fifth active layer can be used as the second electrode of the fifth transistor T5; the first region 26-1 of the sixth active layer can be used as the first electrode of the sixth transistor T6; the second region 26-2 of the sixth active layer can be used as the second electrode of the sixth transistor T6; the first region 27-1 of the seventh active layer can be used as the first electrode of the seventh transistor T7; the second region 27-2 of the seventh active layer can be used as the second electrode of the seventh transistor T7.

[0186] In an exemplary embodiment, the orthographic projection of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the third bottom gate electrode 35 on the substrate.

[0187] In an exemplary embodiment, the third active layer 23 may have an active width W, and the active width W of the third active layer 23 may be different in different circuit units.

[0188] In an exemplary embodiment, the third active layer 23 in the first circuit unit (circuit units in the Mth unit row, the Nth unit column, and the M+1th unit row and the N+2th unit column) may have a first active width W1, the third active layer 23 in the second circuit unit (circuit units in the Mth unit row, the N+1th unit column, and the M+1th unit row and the N+3th unit column) may have a second active width W2, the third active layer 23 in the third circuit unit (circuit units in the Mth unit row, the N+2th unit column, and the M+1th unit row and the Nth unit column) may have a third active width W3, and the third active layer 23 in the fourth circuit unit (circuit units in the Mth unit row, the N+3th unit column, and the M+1th unit row and the N+1th unit column) may have a fourth active width W4. The third active width W3 can be greater than the first active width W1, the first active width W1 can be greater than the second active width W2, the first active width W1 can be greater than the fourth active width W4, and the second active width W2 can be equal to the fourth active width W4.

[0189] In an exemplary embodiment, the ratio of the third active width W3 to the first active width W1 can be approximately 1.3 to 1.7, the ratio of the first active width W1 to the second active width W2 can be approximately 1.4 to 1.8, and the ratio of the first active width W1 to the fourth active width W4 can be approximately 1.4 to 1.8. This disclosure, through differentiated design of the active width of the third active layer in different circuit units, enables the third transistor in different circuit units to have different width-to-length ratios (W / L).

[0190] In some possible implementations, the active width W of the third active layer 23 in different circuit units may be substantially the same, and this disclosure does not limit it.

[0191] In an exemplary embodiment, the semiconductor layer can be an oxide layer, i.e., the first transistor T1 to the seventh transistor T7 are oxide transistors. Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage current. In an exemplary embodiment, the semiconductor layer can be indium gallium zinc oxide (IGZO).

[0192] (15) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: sequentially depositing a fourth insulating film and a fourth conductive film on a substrate on which the aforementioned pattern is formed; patterning the fourth conductive film using a patterning process to form a fourth insulating layer covering the semiconductor layer pattern; and a fourth conductive layer pattern disposed on the fourth insulating layer, as shown in Figures 13A and 13B, where Figure 13B is a schematic diagram of the fourth conductive layer in Figure 13A. In an exemplary embodiment, the fourth conductive layer may be referred to as a fourth gate metal (GATE4) layer.

[0193] In an exemplary embodiment, the fourth conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 31, a third top gate electrode 33, a fourth gate electrode 34, a seventh gate electrode 37, a first light-emitting signal line 41, a second light-emitting signal line 42, and a second scan signal line 62.

[0194] In an exemplary embodiment, the first gate electrode 31 may be block-shaped (such as rectangular), and the orthographic projection of the first gate electrode 31 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate. The first gate electrode 31 may serve as the gate electrode of the first transistor T1.

[0195] In an exemplary embodiment, in at least one cell row, the first gate electrodes 31 in some adjacent circuit cells can be interconnected, and the first gate electrodes 31 of two circuit cells can be an integral structure interconnected. By setting the first gate electrodes 31 in some adjacent circuit cells to an integral structure interconnected, this disclosure can effectively reduce wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0196] In an exemplary embodiment, the third top gate electrode 33 may be block-shaped (e.g., rectangular), and the orthographic projection of the third top gate electrode 33 on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate. The third top gate electrode 33 may serve as the top gate electrode of the third transistor T3.

[0197] In an exemplary embodiment, the orthographic projection of the third top gate electrode 33 on the substrate and the orthographic projection of the third bottom gate electrode 35 on the substrate at least partially overlap to form the third transistor T3 with a top gate and bottom gate structure.

[0198] In an exemplary embodiment, the third top gate electrode 33 may have a gate length L, and the gate length L of the third top gate electrode 33 may be different in different circuit units.

[0199] In an exemplary embodiment, the third top gate electrode 23 in the first circuit unit (circuit units in the Mth row and Nth column, and circuit units in the M+1th row and N+2th column) may have a first gate length L1; the third top gate electrode 23 in the second circuit unit (circuit units in the Mth row and N+1th column, and circuit units in the M+1th row and N+3th column) may have a second gate length L2; the third top gate electrode 23 in the third circuit unit (circuit units in the Mth row and N+2th column, and circuit units in the M+1th row and Nth column) may have a third gate length L3; and the third top gate electrode 23 in the fourth circuit unit (circuit units in the Mth row and N+3th column, and circuit units in the M+1th row and N+1th column) may have a fourth gate length L4. The first gate length L1, the second gate length L2, and the fourth gate length L4 may be substantially the same, and the third gate length L3 may be less than the first gate length L1.

[0200] In an exemplary embodiment, the ratio of the third gate length L3 to the first gate length L1 can be approximately 0.6 to 0.9. This disclosure achieves different width-to-length ratios (W / L) of the third transistor in different circuit units through differentiated design of the gate length of the third top gate electrode in different circuit units.

[0201] In an exemplary embodiment, the third active width W3 is greater than the first active width W1, and the third gate length L3 is less than the first gate length L1. Therefore, the width-to-length ratio of the third transistor T3 in the third circuit unit can be greater than the width-to-length ratio of the third transistor T3 in the first circuit unit.

[0202] In an exemplary embodiment, the ratio of the width-to-length ratio of the third transistor T3 in the third circuit unit to the width-to-length ratio of the third transistor T3 in the first circuit unit can be approximately 1.9 to 2.3.

[0203] In an exemplary embodiment, the first active width W1 is greater than the second active width W2 and the fourth active width W4, while the first gate length L1, the second gate length L2 and the fourth gate length L4 are substantially the same. Therefore, the width-to-length ratio of the third transistor T3 in the first circuit unit can be greater than the width-to-length ratio of the third transistor T3 in the second circuit unit and the fourth circuit unit.

[0204] In an exemplary embodiment, the ratio of the aspect ratio of the third transistor T3 in the first circuit unit to that in the second circuit unit can be approximately 1.4 to 1.8, and the ratio of the aspect ratio of the third transistor T3 in the first circuit unit to that in the fourth circuit unit can also be approximately 1.4 to 1.8. This disclosure, through the differentiated design of the aspect ratios of the third transistors in the first to fourth circuit units, ensures that the data range corresponding to different pixel driving circuits can match the data driver.

[0205] In an exemplary embodiment, a third top gate connecting block 33-1 may be provided on the third top gate electrode 33. The third top gate connecting block 33-1 may be strip-shaped, with a first end connected to the third top gate electrode 33 and a second end extending toward the first gate electrode 31. The second end of the third top gate connecting block 33-1 is configured to connect to a subsequently formed first connecting electrode.

[0206] In an exemplary embodiment, in at least one circuit unit, the third top gate electrode 33 and the third top gate connection block 33-1 can be an integral structure that is interconnected.

[0207] In an exemplary embodiment, the fourth gate electrode 34 may be block-shaped (e.g., rectangular), and the orthographic projection of the fourth gate electrode 34 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate. The fourth gate electrode 34 may serve as the gate electrode of the fourth transistor T4.

[0208] In an exemplary embodiment, in at least one cell row, the fourth gate electrodes 34 in some adjacent circuit cells can be interconnected, and the fourth gate electrodes 34 of two circuit cells can be an integral structure interconnected. By setting the fourth gate electrodes 34 in some adjacent circuit cells to an integral structure interconnected, this disclosure can effectively reduce wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0209] In an exemplary embodiment, the seventh gate electrode 37 may be block-shaped (e.g., rectangular), and the orthographic projection of the seventh gate electrode 37 on the substrate at least partially overlaps with the orthographic projection of the seventh active layer on the substrate. The seventh gate electrode 37 may serve as the gate electrode of the seventh transistor T7.

[0210] In an exemplary embodiment, the shape of the first light-emitting signal line 41 can be a broken line extending along the first direction X, and it can be disposed on the side of the first gate electrode 31 away from the fourth gate electrode 34. The orthographic projection of the first light-emitting signal line 41 on the substrate and the orthographic projection of the fifth active layer on the substrate at least partially overlap. The first light-emitting signal line 41 in the overlapping area can serve as the gate electrode of the fifth transistor T5, thus realizing that the first light-emitting signal line 41 can control the conduction or disconnection of the fifth transistor T5.

[0211] In an exemplary embodiment, the first light-emitting signal line 41 can be a variable-width polygonal line structure, and the width of the first light-emitting signal line is the dimension of the second direction Y. The first light-emitting signal line 41 may include a first region that overlaps with the fifth active layer and a second region that does not overlap with the fifth active layer, and the width of the first region may be greater than the width of the second region.

[0212] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first light-emitting signal line 41 on the substrate does not overlap with the orthographic projections of the first electrode plate 11, the second electrode plate 12, the third electrode plate 13, and the fourth electrode plate 14 on the substrate.

[0213] In an exemplary embodiment, the shape of the second light-emitting signal line 42 can be a broken line extending along the first direction X, and it can be disposed on the side of the fourth gate electrode 34 away from the first gate electrode 31. The orthographic projection of the second light-emitting signal line 42 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer on the substrate. The second light-emitting signal line 42 in the overlapping area can serve as the gate electrode of the sixth transistor T6, thus realizing that the second light-emitting signal line 42 can control the conduction or disconnection of the sixth transistor T6.

[0214] In an exemplary embodiment, the second light-emitting signal line 42 can be a variable-width polygonal line structure, and the width of the second light-emitting signal line is the dimension of the second direction Y. The second light-emitting signal line 42 may include a first region that overlaps with the sixth active layer and a second region that does not overlap with the sixth active layer, and the width of the first region may be greater than the width of the second region.

[0215] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second light-emitting signal line 42 on the substrate at least partially overlaps with the orthographic projections of the integrally structured second electrode plate 12 and fourth electrode plate 14 on the substrate.

[0216] In an exemplary embodiment, the shape of the second scan signal line 62 can be a straight line or a broken line extending along the first direction X. It can be disposed on the side of the second light-emitting signal line 42 away from the third top gate electrode 33. The orthographic projection of the second scan signal line 62 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The second scan signal line 62 in the overlapping area can serve as the gate electrode of the second transistor T2, thus realizing the connection between the second scan signal line 62 and the gate electrode of the second transistor T2 in each circuit unit. The second scan signal line 62 can control the conduction or disconnection of the second transistor T2.

[0217] In an exemplary embodiment, the second scan signal line 62 can be a straight line structure with a variable width, the width of which is the dimension in the second direction Y. The second scan signal line 62 may include a first region that overlaps with the second active layer and a second region that does not overlap with the second active layer, the width of the first region may be greater than the width of the second region.

[0218] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second scan signal line 62 on the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate 14 on the substrate.

[0219] In an exemplary embodiment, the positions of the first gate electrode 31, the third top gate electrode 33, the fourth gate electrode 34, the seventh gate electrode 37, the first light-emitting signal line 41, the second light-emitting signal line 42, and the second scan signal line 62 in adjacent cell columns can be arranged substantially symmetrically with respect to the column center line, and the positions of the first gate electrode 31, the third top gate electrode 33, the fourth gate electrode 34, the seventh gate electrode 37, the first light-emitting signal line 41, the second light-emitting signal line 42, and the second scan signal line 62 in adjacent cell rows can be arranged substantially symmetrically with respect to the row center line.

[0220] (16) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming a fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the fourth conductive layer, wherein a plurality of vias are provided on the fifth insulating layer, as shown in FIG14.

[0221] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate includes at least: a first via V1 to a sixteenth via V16.

[0222] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate. The fourth and fifth insulating layers within the first via V1 are etched away, exposing the surface of the first region of the first active layer. The first via V1 is configured to allow a subsequently formed first initial signal line to be connected to the first region of the first active layer through the via.

[0223] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the first region of the second active layer onto the substrate. The fourth and fifth insulating layers within the second via V2 are etched away, exposing the surface of the first region of the second active layer. The second via V2 is configured to allow subsequently formed second or third initial signal lines to connect to the first region of the second active layer through this via. Since two partially adjacent circuit units share the same first region of the second active layer, they can share the same second via V2, effectively reducing the number of vias and decreasing the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0224] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the range of the orthographic projection of the second region of the second active layer (which is also the second region of the sixth active layer and the first region of the seventh active layer) onto the substrate. The fourth and fifth insulating layers within the third via V3 are etched away, exposing the surface of the second region of the second active layer (which is also the second region of the sixth active layer and the first region of the seventh active layer). The third via V3 is configured to allow a subsequently formed third connection electrode to be connected to the second region of the second active layer (which is also the second region of the sixth active layer and the first region of the seventh active layer) through the via.

[0225] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate is within the range of the orthographic projection of the second region of the third active layer (which is also the first region of the sixth active layer) onto the substrate. The fourth and fifth insulating layers within the fourth via V4 are etched away, exposing the surface of the second region of the third active layer (which is also the first region of the sixth active layer). The fourth via V4 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the third active layer (which is also the first region of the sixth active layer) through the via.

[0226] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is located within the orthographic projection range of the second region of the first active layer (which is also the second region of the fourth active layer) onto the substrate. The fourth and fifth insulating layers within the fifth via V5 are etched away, exposing the surface of the second region of the first active layer (which is also the second region of the fourth active layer). The fifth via V5 is configured to allow a subsequently formed first connection electrode to be connected to the second region of the first active layer (which is also the second region of the fourth active layer) through the via.

[0227] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The fourth and fifth insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the fourth active layer. The sixth via V6 is configured to allow a subsequently formed fifth connection electrode to be connected to the first region of the fourth active layer through the via.

[0228] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the first region of the fifth active layer onto the substrate. The fourth and fifth insulating layers within the seventh via V7 are etched away, exposing the surface of the first region of the fifth active layer. The seventh via V7 is configured to allow a subsequently formed first power connection line to be connected to the first region of the fifth active layer through the via.

[0229] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate is within the range of the orthographic projection of the second region of the seventh active layer onto the substrate. The fourth and fifth insulating layers within the eighth via V8 are etched away, exposing the surface of the second region of the seventh active layer. The eighth via V8 is configured to allow a subsequently formed fourth connection electrode to be connected to the second region of the seventh active layer through the via.

[0230] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the substrate lies within the range of the orthogonal projection of the first gate electrode 31 onto the substrate. The fifth insulating layer within the ninth via V9 is etched away, exposing the surface of the first gate electrode 31. The ninth via V9 is configured to allow the subsequently formed first scan signal line to connect to the first gate electrode 31 through this via. Since the first gate electrodes 31 in two partially adjacent circuit units are interconnected as a single structure, the two partially adjacent circuit units can share the ninth via V9, effectively reducing the number of vias and decreasing the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0231] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is within the range of the orthographic projection of the third bottom gate connection block 35-1 of the third bottom gate electrode 35 on the substrate. The third, fourth, and fifth insulating layers within the tenth via V10 are etched away, exposing the surface of the third bottom gate connection block 35-1. The tenth via V10 is configured to allow the subsequently formed second connection electrode to be connected to the third bottom gate connection block 35-1 through the via.

[0232] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate is within the range of the orthographic projection of the third top gate connection block 33-1 of the third top gate electrode 33 onto the substrate. The fifth insulating layer within the eleventh via V11 is etched away, exposing the surface of the third top gate connection block 33-1. The eleventh via V11 is configured to allow the subsequently formed first connection electrode to be connected to the third top gate connection block 33-1 through the via.

[0233] In an exemplary embodiment, the orthogonal projection of the twelfth via V12 onto the substrate is within the range of the orthogonal projection of the fourth gate electrode 34 onto the substrate. The fifth insulating layer within the twelfth via V12 is etched away, exposing the surface of the fourth gate electrode 34. The twelfth via V12 is configured to allow the subsequently formed third scan signal line to be connected to the fourth gate electrode 34 through the via.

[0234] In an exemplary embodiment, the orthogonal projection of the thirteenth via V13 onto the substrate is within the range of the orthogonal projection of the seventh gate electrode 37 onto the substrate. The fifth insulating layer within the thirteenth via V13 is etched away, exposing the surface of the seventh gate electrode 37. The thirteenth via V13 is configured to allow the subsequently formed fourth scan signal line to be connected to the seventh gate electrode 37 through the via.

[0235] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the orthographic projection range of the first groove 12-1 provided on the second electrode plate 12 on the substrate. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer in the fourteenth via V14 are etched away, exposing the surface of the first electrode plate 11. The fourteenth via V14 is configured to allow the subsequently formed first connection electrode to be connected to the first electrode plate 11 through the via.

[0236] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is within the range of the orthographic projection of the second groove 14-1 provided on the fourth electrode plate 14 on the substrate. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer in the fifteenth via V15 are etched away, exposing the surface of the third electrode plate 13. The fifteenth via V15 is configured to allow the subsequently formed fourth connection electrode to be connected to the third electrode plate 13 through the via.

[0237] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 onto the substrate lies within the range of the orthographic projections of the second electrode plate 12 and the fourth electrode plate 14 of the integral structure onto the substrate. The second, third, fourth, and fifth insulating layers within the sixteenth via V16 are etched away, exposing the surfaces of the second electrode plate 12 and the fourth electrode plate 14 of the integral structure. The sixteenth via V16 is configured to allow a subsequently formed second connection electrode to be connected to the second electrode plate 12 and the fourth electrode plate 14 of the integral structure through the via.

[0238] (17) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer disposed on a fifth insulating layer, as shown in Figures 15A and 15B, where Figure 15B is a planar schematic diagram of the fifth conductive layer in Figure 15A. In an exemplary embodiment, the fifth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0239] In an exemplary embodiment, the fifth conductive layer of each circuit unit in the display substrate includes at least: a first connection electrode 51 to a fifth connection electrode 55, a first scan signal line 61, a third scan signal line 63, a fourth scan signal line 64, a first power connection line 65, and a first initial signal line 71.

[0240] In an exemplary embodiment, the first connecting electrode 51 can be a strip extending along the first direction X. The first end of the first connecting electrode 51 is connected to the second region of the first active layer (which is also the second region of the fourth active layer) through the fifth via V5. The second end of the first connecting electrode 51 is connected to the third top gate connecting block 33-1 through the eleventh via V11. The portion between the first end and the second end is connected to the first electrode plate 11 through the fourteenth via V14. The third top gate connecting block 33-1 is connected to the third top gate electrode 33. Thus, the first connecting electrode 51 realizes the connection between the second electrode of the first transistor T1, the top gate electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the first end (first electrode plate 11) of the first capacitor C1, forming the first node N1 of the pixel driving circuit. The first electrode plate 11, the top gate electrode of the third transistor T3, and the first connecting electrode 51 have the potential of the first node.

[0241] In an exemplary embodiment, the second connecting electrode 52 can be a strip shape extending along the first direction X. The first end of the second connecting electrode 52 is connected to the second region of the third active layer (which is also the first region of the sixth active layer) through the fourth via V4. The second end of the second connecting electrode 52 is connected to the third bottom gate connecting block 35-1 through the tenth via V10. The portion between the first end and the second end is connected to the second electrode plate 12 and the fourth electrode plate 14 of the integral structure through the sixteenth via V16. Since the third bottom gate connecting block 35-1 is connected to the third bottom gate electrode 35, the second connecting electrode 52 realizes the connection between the bottom gate electrode of the third transistor T3, the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, the second end of the first capacitor C1 (second electrode plate 12), and the second end of the second capacitor C2 (fourth electrode plate 14), forming a partial second node N2 of the pixel driving circuit. The second electrode plate 12, the fourth electrode plate 14, and the second connecting electrode 52 have the potential of the second node.

[0242] In an exemplary embodiment, the third connection electrode 53 may be block-shaped (e.g., rectangular). The third connection electrode 53 is connected to the second region of the second active layer (which is also the second region of the sixth active layer and the first region of the seventh active layer) through the third via V3, forming the third node N3 of the pixel driving circuit. In an exemplary embodiment, the third connection electrode 53 is configured to be connected to the subsequently formed first anode connection electrode.

[0243] In an exemplary embodiment, the fourth connecting electrode 54 can be a strip extending along the first direction X. The first end of the fourth connecting electrode 54 is connected to the second region of the seventh active layer through the eighth via V8, and the second end of the fourth connecting electrode 54 is connected to the third electrode plate 13 through the fifteenth via V15. The fourth connecting electrode 54 realizes the interconnection between the second electrode of the seventh transistor T7 and the first end (third electrode plate 13) of the second capacitor C2, forming the fourth node N4 of the pixel driving circuit. The third electrode plate 13 and the fourth connecting electrode 54 have the potential of the fourth node.

[0244] In an exemplary embodiment, since the first electrode plate 11 has a potential of a first node and the second electrode plate 12 has a potential of a second node, the first electrode plate 11 having a potential of a first node and the second electrode plate 12 having a potential of a second node form the first capacitor C1 of the pixel driving circuit.

[0245] In an exemplary embodiment, since the third electrode 13 has the potential of the fourth node and the fourth electrode 14 has the potential of the second node, the third electrode 13 with the potential of the fourth node and the fourth electrode 14 with the potential of the second node form the second capacitor C2 of the pixel driving circuit.

[0246] In an exemplary embodiment, the fifth connection electrode 55 may be block-shaped (e.g., rectangular), and the fifth connection electrode 55 is connected to the first region of the fourth active layer through the sixth via V6. The fifth connection electrode 55 is configured to be connected to a subsequently formed data signal line.

[0247] In an exemplary embodiment, the shape of the first scan signal line 61 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a unit row. The orthographic projection of the first scan signal line 61 on the substrate at least partially overlaps with the orthographic projection of the first gate electrode 31 on the substrate. The first scan signal line 61 is connected to the first gate electrode 31 in each circuit unit through the ninth via V9, thereby realizing the connection between the first scan signal line 61 and the gate electrode of the first transistor T1 in each circuit unit. The first scan signal line 61 can control the conduction or disconnection of the first transistor T1.

[0248] In an exemplary embodiment, the shape of the third scan signal line 63 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a unit row. The orthographic projection of the third scan signal line 63 on the substrate at least partially overlaps with the orthographic projection of the fourth gate electrode 34 on the substrate. The third scan signal line 63 is connected to the fourth gate electrode 34 in each circuit unit through the twelfth via V12, thereby realizing the connection between the third scan signal line 63 and the gate electrode of the fourth transistor T4 in each circuit unit. The third scan signal line 63 can control the conduction or disconnection of the fourth transistor T4.

[0249] In an exemplary embodiment, the shape of the fourth scan signal line 64 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a unit row. The orthographic projection of the fourth scan signal line 64 on the substrate at least partially overlaps with the orthographic projection of the seventh gate electrode 37 on the substrate. The fourth scan signal line 64 is connected to the seventh gate electrode 37 in each circuit unit through the thirteenth via V13, thus realizing the connection between the fourth scan signal line 64 and the gate electrode of the seventh transistor T7 in each circuit unit. The fourth scan signal line 64 can control the conduction or disconnection of the seventh transistor T7.

[0250] This embodiment of the present disclosure, by placing the first scan signal line 61, the third scan signal line 63, and the fourth scan signal line 64 in a thicker fifth conductive layer, can effectively reduce the resistance of the scan signal lines, lower the voltage drop of the scan signal, and improve the driving quality, display quality, and overall display quality.

[0251] In an exemplary embodiment, the shape of the first power connection line 65 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a cell row. The first power connection line 65 is connected to the first region of the fifth active layer through the seventh via V7. The first power connection line 65 is configured to be connected to the subsequently formed first power line, so that the first power line can write the first power signal into the first pole of the fifth transistor T5 in each circuit cell.

[0252] In an exemplary embodiment, in at least one circuit unit, a first power connection line 65 may be disposed on the side of the first scan signal line 61 away from the third top gate electrode 33, and located between two adjacent unit rows. The two adjacent unit rows share the same first power connection line 65, meaning the pixel driving circuits in the two adjacent unit rows are connected to the same first power connection line 65, reducing the number of signal lines and effectively saving layout space. For example, the first power connection line 65 may be disposed between the (M-1)th unit row and the Mth unit row, with the pixel driving circuits in the (M-1)th unit row and the Mth unit row sharing the first power connection line 65. Alternatively, the first power connection line 65 may be disposed between the M+1th unit row and the M+2th unit row, with the pixel driving circuits in the M+1th unit row and the M+2th unit row sharing the first power connection line 65.

[0253] In an exemplary embodiment, a first power connection block 65-1 may be provided on the first power connection line 65. The first power connection block 65-1 may be block-shaped (such as rectangular) and connected to the first power connection line 65. The first power connection block 65-1 is configured to connect to the first power line formed subsequently.

[0254] In an exemplary embodiment, the first power connection block 65-1 may be disposed between the Nth unit column and the N+1th unit column, and between the N+2th unit column and the N+3th unit column. The first power connection line 65 and the first power connection block 65-1 may be an integral structure that is interconnected.

[0255] In an exemplary embodiment, the shape of the first initial signal line 71 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a cell row. The first initial signal line 71 is connected to the first region of the first active layer in each circuit cell through the first via V1, and the first initial signal line 71 realizes the writing of the first initial signal to the first terminal of the first transistor T1 in each circuit cell.

[0256] In an exemplary embodiment, a first initial signal line 71 may be provided in each cell row, and two first initial signal lines 71 in adjacent cell rows may be symmetrically arranged with respect to the row center line.

[0257] In an exemplary embodiment, a first initial connection block 71-1 may be provided on the first initial signal line 71. The first initial connection block 71-1 may be block-shaped (such as rectangular) and connected to the first initial signal line 71. The first initial connection block 71-1 is configured to connect to the subsequently formed first initial connection line.

[0258] In an exemplary embodiment, the first initial connection block 71-1 may be disposed between the (N-1)th and Nth unit columns, between the N+1th and N+2th unit columns, and between the N+3th and N+4th unit columns. In at least one unit row, the first initial signal line 71 and the plurality of first initial connection blocks 71-1 may be an integral structure interconnected with each other.

[0259] In an exemplary embodiment, the fifth conductive layer of at least one repeating unit may further include: a second initial signal line 72 and a third initial signal line 73.

[0260] In an exemplary embodiment, the shape of the second initial signal line 72 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a cell row. The second initial signal line 72 is connected to the first region of the second active layer in the first circuit cell through the second via V2 in the first circuit cell (the circuit cell in the Mth cell row, the Nth cell column, and the circuit cell in the M+1th cell row and the N+2th cell column), thereby enabling the second initial signal line 72 to write the first type of second initial signal into the first terminal of the second transistor T2 in the first circuit cell.

[0261] In an exemplary embodiment, in at least one repeating unit, the second initial signal line 72 can be disposed between adjacent unit rows. Two adjacent unit rows share the same second initial signal line 72, meaning the pixel driving circuits in two adjacent unit rows are connected to the same second initial signal line 72. This reduces the number of signal lines and effectively saves layout space. For example, the pixel driving circuits of the first circuit units in the Mth unit row and the M+1th unit row are connected to the same second initial signal line 72, and the pixel driving circuits in the two unit rows reuse the signal of the same second initial signal line 72.

[0262] In an exemplary embodiment, a second initial connection block 72-1 may be provided on the second initial signal line 72. The second initial connection block 72-1 may be block-shaped (such as rectangular) and connected to the second initial signal line 72. The second initial connection block 72-1 is configured to connect to the second initial connection line formed subsequently.

[0263] In an exemplary embodiment, the second initial connection block 72-1 may be disposed in the Nth unit column, and the second initial signal line 72 and the second initial connection block 72-1 may be an integral structure that is interconnected.

[0264] In an exemplary embodiment, the shape of the third initial signal line 73 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a unit row. The third initial signal line 73 is connected to the first region of the second active layer in the second circuit unit, the third circuit unit, and the fourth circuit unit (circuit units in the Mth unit row, the N+1th unit column, the Mth unit row, the N+2th unit column, the Mth unit row, the N+3th unit column, the M+1th unit row, the Nth unit column, the M+1th unit row, the N+1th unit column, and the M+1th unit row, the N+3th unit column) through the second via V2, thereby enabling the third initial signal line 73 to write the second type of second initial signal into the first terminal of the second transistor T2 in the second circuit unit, the third circuit unit, and the fourth circuit unit.

[0265] In an exemplary embodiment, in at least one repeating unit, the third initial signal line 73 can be disposed between adjacent unit rows. Two adjacent unit rows share the same third initial signal line 73, meaning the pixel driving circuits in two adjacent unit rows are connected to the same third initial signal line 73. This reduces the number of signal lines and effectively saves layout space. For example, the pixel driving circuits of the second, third, and fourth circuit units in the Mth and M+1th unit rows are connected to the same third initial signal line 73, and the pixel driving circuits in the two unit rows reuse the signal of the same third initial signal line 73.

[0266] In an exemplary embodiment, a third initial connection block 73-1 may be provided on the third initial signal line 73. The third initial connection block 73-1 may be block-shaped (e.g., rectangular) and connected to the third initial signal line 73. The third initial connection block 73-1 is configured to connect to the subsequently formed third initial connection line.

[0267] In an exemplary embodiment, the third initial connection block 73-1 may be disposed in the N+2th cell column. In at least one cell row, the third initial signal line 73 and the third initial connection block 73-1 may be an integral structure interconnected with each other.

[0268] In an exemplary embodiment, in at least one circuit unit, the first scan signal line 61, the first power connection line 65, and the first initial signal line 71 may be located on one side of the third top gate electrode 33 in the second direction Y. The first initial signal line 71 may be located on the side of the first scan signal line 61 away from the third top gate electrode 33, and the first power connection line 65 may be located on the side of the first initial signal line 71 away from the third top gate electrode 33. The third scan signal line 63 and the fourth scan signal line 64 may be located on the other side of the third top gate electrode 33 in the second direction Y. The fourth scan signal line 64 may be located on the side of the third scan signal line 63 away from the third top gate electrode 33. For example, in the Mth unit row, the first scan signal line 61 may be located on the side opposite to the second direction Y of the third top gate electrode 33, and the third scan signal line 63 may be located on one side of the third top gate electrode 33 in the second direction Y. For example, in the M+1th cell row, the first scan signal line 61 can be located on one side of the second direction Y of the third top gate electrode 33, and the third scan signal line 63 can be located on the opposite side of the second direction Y of the third top gate electrode 33.

[0269] In an exemplary embodiment, the second initial signal line 72 and the third initial signal line 73 may be located between two fourth scan signal lines 64 in adjacent cell rows. For example, the second initial signal line 72 may be located on the side of the fourth scan signal line 64 in the (M+1)th cell row that is away from the third top gate electrode 33, and the third initial signal line 73 may be located on the side of the fourth scan signal line 64 in the Mth cell row that is away from the third top gate electrode 33.

[0270] In an exemplary embodiment, the positions of the first connecting electrode 51 to the fifth connecting electrode 55, the first scan signal line 61, the third scan signal line 63, the fourth scan signal line 64, the first power connection line 65, and the first initial signal line 71 to the third initial signal line 73 in adjacent cell columns can be arranged substantially symmetrically with respect to the column center line. The positions of the first connecting electrode 51 to the fifth connecting electrode 55, the first scan signal line 61, the third scan signal line 63, the fourth scan signal line 64, the first power connection line 65, and the first initial signal line 71 in adjacent cell rows can be arranged substantially symmetrically with respect to the row center line. The positions of the second initial signal line 72 and the third initial signal line 73 in adjacent cell rows can be arranged substantially symmetrically with respect to the row center line.

[0271] (18) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, and patterning the first planarization film using a patterning process to form a first planarization layer covering the fifth conductive layer pattern, wherein a plurality of vias are provided on the first planarization layer, as shown in FIG16.

[0272] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate include at least: a twenty-first via V21 and a twenty-second via V22.

[0273] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the substrate is within the range of the orthographic projection of the fifth connecting electrode 55 onto the substrate. The first planarization layer within the 21st via V21 is removed, exposing the surface of the fifth connecting electrode 55. The 21st via V21 is configured to allow subsequently formed data signal lines to be connected to the fifth connecting electrode 55 through the via.

[0274] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate is within the range of the orthographic projection of the third connecting electrode 53 onto the substrate. The first planarization layer within the 22nd via V22 is removed, exposing the surface of the third connecting electrode 53. The 22nd via V22 is configured to allow the subsequently formed first anode connecting electrode to be connected to the third connecting electrode 53 through the via.

[0275] In an exemplary embodiment, the plurality of vias of at least one repeating unit may further include: a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, and a twenty-sixth via V26.

[0276] In an exemplary embodiment, the twenty-third via V23 may be disposed between the Nth and N+1th unit columns, and between the N+2th and N+3th unit columns. The orthographic projection of the twenty-third via V23 onto the substrate lies within the orthographic projection of the first power connection block 65-1 on the first power connection line 65 onto the substrate. The first planarization layer within the twenty-third via V23 is removed, exposing the surface of the first power connection block 65-1. The twenty-third via V23 is configured to allow a subsequently formed first power line to connect to the first power connection block 65-1 through this via.

[0277] In an exemplary embodiment, the twenty-fourth via V24 may be disposed between the (N-1)th and Nth unit columns, between the N+1th and N+2th unit columns, and between the N+3th and N+4th unit columns. The orthographic projection of the twenty-fourth via V24 onto the substrate lies within the orthographic projection of the first initial connecting block 71-1 disposed on the first initial signal line 71 onto the substrate. The first planarization layer within the twenty-fourth via V24 is removed, exposing the surface of the first initial connecting block 71-1. The twenty-fourth via V24 is configured to allow subsequently formed first initial connecting lines to connect to the first initial connecting block 71-1 through this via.

[0278] In an exemplary embodiment, the 25th via V25 may be disposed in the Nth cell column. The orthographic projection of the 25th via V25 onto the substrate lies within the orthographic projection of the second initial connection block 72-1 disposed on the second initial signal line 72 onto the substrate. The first planarization layer within the 25th via V25 is removed, exposing the surface of the second initial connection block 72-1. The 25th via V25 is configured to allow subsequently formed second initial connection lines to connect to the second initial connection block 72-1 through this via.

[0279] In an exemplary embodiment, the 26th via V26 may be disposed in the N+2th cell column. The orthographic projection of the 26th via V26 onto the substrate lies within the orthographic projection of the third initial connection block 73-1 disposed on the third initial signal line 73 onto the substrate. The first planarization layer within the 26th via V26 is removed, exposing the surface of the third initial connection block 73-1. The 26th via V26 is configured to allow the subsequently formed third initial connection line to be connected to the third initial connection block 73-1 through this via.

[0280] (19) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer may include: depositing a sixth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the sixth conductive thin film using a patterning process to form a sixth conductive layer disposed on the first planarization layer, as shown in Figures 17A and 17B, where Figure 17B is a planar schematic diagram of the sixth conductive layer in Figure 17A. In an exemplary embodiment, the sixth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0281] In an exemplary embodiment, the sixth conductive layer of each circuit unit in the display substrate includes at least: a data signal line 83 and a first anode connection electrode 84.

[0282] In an exemplary embodiment, the data signal line 83 can be a straight line or a broken line extending along the second direction Y in its main body. The data signal line 83 is connected to the fifth connection electrode 55 through the twenty-first via V21. Since the fifth connection electrode 55 is connected to the first region of the fourth active layer through the via, the data signal line 83 can write data signals to the first electrode of the fourth transistor T4.

[0283] In an exemplary embodiment, the first anode connection electrode 84 may be a strip shape extending along the second direction Y. The first anode connection electrode 84 is connected to the third connection electrode 53 through the second twelve via V22. The first anode connection electrode 84 is configured to be connected to the second anode connection electrode formed subsequently.

[0284] In an exemplary embodiment, the sixth conductive layer of at least one repeating unit may further include a first power line 81, a first initial connection line 91, a second initial connection line 92, and a third initial connection line 93.

[0285] In an exemplary embodiment, the first power line 81 can be a straight line or a broken line extending along the second direction Y, and can be disposed in the N+1th and N+3th unit columns. A first power connection strip 81-1 can be disposed on the first power line 81. The first power connection strip 81-1 can be a strip extending along the first direction X. The first end of the first power connection strip 81-1 is connected to the first power line 81, and the second end of the first power connection strip 81-1 is connected to the first power connection block 65-1 through the twenty-third through-hole V23. Since the first power connection block 65-1 is connected to the first power connection line 65 and the first power connection strip 81-1 is connected to the first power line 81, the first power connection line 65 extending along the first direction X of the main body and the first power line 81 extending along the second direction Y of the main body are interconnected. The first power connection line 65 and the first power line 81 form a mesh-like interconnected structure on the display substrate to transmit the first power signal. This can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0286] In an exemplary embodiment, the shape of the first initial connection line 91 can be a straight line or a broken line extending along the second direction Y of the main body. The first initial connection line 91 is connected to the first initial connection block 71-1 through the twenty-fourth via V24. Since the first initial connection block 71-1 is connected to the first initial signal line 71, the interconnection between the first initial signal line 71 extending along the first direction X of the main body and the first initial connection line 91 extending along the second direction Y of the main body is realized. The first initial signal line 71 and the first initial connection line 91 form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal. This not only effectively reduces the resistance of the first initial signal line and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, effectively improving display uniformity, display quality, and display performance.

[0287] In an exemplary embodiment, the first initial connection line 91 may be disposed between the (N-1)th cell column and the Nth cell column, between the N+1th cell column and the N+2th cell column, and between the N+3th cell column and the N+4th cell column.

[0288] In an exemplary embodiment, the first initial connection line 91 can be disposed between two data signal lines 83 in adjacent cell columns. The first initial connection line 91 with a constant potential can effectively shield crosstalk between adjacent data signal lines 83, effectively improve the stability of the output current of the pixel driving circuit, and effectively improve the display quality and display effect.

[0289] In an exemplary embodiment, the shape of the second initial connection line 92 can be a straight line or a broken line extending along the second direction Y of the main body portion, and it can be disposed in the Nth unit column. The second initial connection line 92 is connected to the second initial connection block 72-1 through the twenty-fifth via V25. Since the second initial connection block 72-1 is connected to the second initial signal line 72, the interconnection between the second initial signal line 72 extending along the first direction X of the main body portion and the second initial connection line 92 extending along the second direction Y of the main body portion is realized. The second initial signal line 72 and the second initial connection line 92 form a mesh-like interconnected structure on the display substrate for transmitting the first type of second initial signal. This not only effectively reduces the resistance of the second initial signal line and reduces the voltage drop of the first type of second initial signal, but also effectively improves the uniformity of the first type of second initial signal in the display substrate, effectively improving display uniformity, display quality, and display performance.

[0290] In an exemplary embodiment, at least one repeating unit may be provided with a second initial signal line 72 and a second initial connection line 92. The second initial signal line 72 may be provided in the M+1th unit row, and the second initial connection line 92 may be provided in the Nth unit column.

[0291] In an exemplary embodiment, in at least one repeating unit, two first blocking blocks 95 and one second blocking block 96 may be provided on the second initial connection line 92. The first blocking blocks 95 and the second blocking blocks 96 may be block-shaped (such as rectangular), and may be located on the side of the second initial connection line 92 away from the data signal line 83 in this circuit unit, and connected to the second initial connection line 92.

[0292] In an exemplary embodiment, the orthographic projection of the first blocking block 95 on the substrate at least partially overlaps with the orthographic projections of the third top gate electrode 33 in the current circuit unit and the third top gate electrode 33 in adjacent circuit units in the first direction X. For example, in the Mth unit row, the orthographic projection of the first blocking block 95 on the substrate at least partially overlaps with the orthographic projections of the third top gate electrode 33 in the first and second circuit units. Similarly, in the M+1th unit row, the orthographic projection of the first blocking block 95 on the substrate at least partially overlaps with the orthographic projections of the third top gate electrode 33 in the third and fourth circuit units. The orthographic projection of the second blocking block 96 on the substrate at least partially overlaps with the orthographic projections of the second active layers in the four adjacent circuit units. For example, the orthographic projection of the second blocking block 96 on the substrate at least partially overlaps with the orthographic projections of the second active layers of the first and second circuit units in the Mth unit row, and the second active layers of the third and fourth circuit units in the M+1th unit row. This disclosure utilizes a first blocking block 95 to block the third transistor T3 and a second blocking block 96 to block the second transistor T2. The first and second blocking blocks 95 and 96 effectively block the light emitted by the light-emitting device and the reflected light from the film layer from illuminating the channel regions of the oxide transistors T2 and T3, preventing characteristic drift of the oxide transistors due to light exposure and improving their electrical characteristics. Furthermore, since the third top gate electrode 33 has the potential of the first node, the first blocking block 95, with its constant potential, can effectively shield the first node N1, improving the potential stability of the first node N1.

[0293] In an exemplary embodiment, in at least one repeating unit, the second initial connecting line 92, the first blocking block 95, and the second blocking block 96 can be an integral structure that is interconnected.

[0294] In an exemplary embodiment, the shape of the third initial connection line 93 can be a straight line or a broken line extending along the second direction Y of the main body portion. It can be disposed in the N+2 unit column. The third initial connection line 93 is connected to the third initial connection block 73-1 through the twenty-sixth via V26. Since the third initial connection block 73-1 is connected to the third initial signal line 73, the interconnection between the third initial signal line 73 extending along the first direction X of the main body portion and the third initial connection line 93 extending along the second direction Y of the main body portion is realized. The third initial signal line 73 and the third initial connection line 93 form a mesh-like interconnection structure on the display substrate for transmitting the second type of second initial signal. This not only effectively reduces the resistance of the third initial signal line and reduces the voltage drop of the second type of second initial signal, but also effectively improves the uniformity of the second type of second initial signal in the display substrate, effectively improving display uniformity and display quality.

[0295] In an exemplary embodiment, at least one repeating unit may be provided with a third initial signal line 73 and a third initial connection line 93. The third initial signal line 73 may be provided between the Mth unit row and the M+1th unit row, and the third initial connection line 93 may be provided in the N+2th unit column.

[0296] In an exemplary embodiment, in at least one repeating unit, two third blocking blocks 97 and one fourth blocking block 98 may be provided on the third initial connection line 93. The third blocking blocks 97 and the fourth blocking blocks 98 may be block-shaped (such as rectangular), and may be located on the side of the third initial connection line 93 away from the data signal line 83 in this circuit unit, and connected to the third initial connection line 93.

[0297] In an exemplary embodiment, the orthographic projection of the third blocking block 97 on the substrate at least partially overlaps with the orthographic projections of the third top gate electrode 33 in this circuit unit and the third top gate electrode 33 in adjacent circuit units in the first direction X on the substrate. For example, in the Mth unit row, the orthographic projection of the third blocking block 97 on the substrate at least partially overlaps with the orthographic projections of the third top gate electrode 33 in the third and fourth circuit units on the substrate. Similarly, in the M+1th unit row, the orthographic projection of the third blocking block 97 on the substrate at least partially overlaps with the orthographic projections of the third top gate electrode 33 in the first and second circuit units on the substrate. The orthographic projection of the fourth blocking block 98 on the substrate at least partially overlaps with the orthographic projections of the second active layers in the four adjacent circuit units on the substrate. For example, the orthographic projection of the fourth blocking block 98 on the substrate at least partially overlaps with the orthographic projections of the second active layers of the third and fourth circuit units in the Mth unit row, and the second active layers of the first and second circuit units in the M+1th unit row. This disclosure utilizes a third blocking block 97 to block the third transistor T3 and a fourth blocking block 98 to block the second transistor T2. The third and fourth blocking blocks 97 and 98 effectively block the light emitted by the light-emitting device and the reflected light from the film layer from illuminating the channel regions of the oxide transistors T2 and T3, preventing characteristic drift of the oxide transistors due to light exposure and improving their electrical characteristics. Furthermore, since the third top gate electrode 33 has the potential of the first node, the third blocking block 97, with its constant potential, can effectively shield the first node N1, improving the potential stability of the first node N1.

[0298] In an exemplary embodiment, in at least one repeating unit, the third initial connecting line 93, the third blocking block 97, and the fourth blocking block 98 can be an integral structure that is interconnected.

[0299] In an exemplary embodiment, the positions and shapes of the data signal lines 83 and the first anode connection electrodes 84 in adjacent cell columns can be arranged substantially symmetrically with respect to the column center line, and the positions and shapes of the data signal lines 83 and the first anode connection electrodes 84 in adjacent cell rows can be arranged substantially symmetrically with respect to the row center line. Similarly, the positions and shapes of the first initial connection lines 91 in adjacent cell rows and adjacent cell columns can be arranged substantially symmetrically with respect to the column center line.

[0300] (20) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film using a patterning process to form a second planarization layer covering the pattern of the sixth conductive layer, wherein a plurality of vias are provided on the second planarization layer, as shown in FIG18.

[0301] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate includes at least a first anode via V31.

[0302] In an exemplary embodiment, the orthographic projection of the first anode via V31 on the substrate is within the range of the orthographic projection of the first anode connection electrode 84 on the substrate. The second planarization layer within the first anode via V31 is removed, exposing the surface of the first anode connection electrode 84. The first anode via V31 is configured to allow a subsequently formed second anode connection electrode to be connected to the first anode connection electrode 84 through the via.

[0303] (21) Forming a seventh conductive layer pattern. In an exemplary embodiment, forming the seventh conductive layer may include: depositing a seventh conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the seventh conductive thin film using a patterning process to form a seventh conductive layer disposed on the second planarization layer, as shown in Figures 19A and 19B, where Figure 19B is a planar schematic diagram of the seventh conductive layer in Figure 19A. In an exemplary embodiment, the seventh conductive layer may be referred to as the third source / drain metal (SD3) layer.

[0304] In an exemplary embodiment, the seventh conductive layer of each circuit unit in the display substrate includes at least a second anode connection electrode 85.

[0305] In an exemplary embodiment, the second anode connection electrode 85 can be a strip extending along the second direction Y. The second anode connection electrode 85 is connected to the first anode connection electrode 84 through the first anode via V31, and the second anode connection electrode 85 is configured to connect with the subsequently formed anode. Since the first anode connection electrode 84 is connected to the third connection electrode 53, and the third connection electrode 53 is the third node N3 of the pixel driving circuit, the pixel driving circuit can output driving current to the light-emitting device.

[0306] In an exemplary embodiment, the seventh conductive layer of at least one repeating unit may further include a second power line 82 and a second power connection line 86.

[0307] In an exemplary embodiment, the second power line 82 may be a straight line extending along the second direction Y, and may be disposed in a portion of the cell column. The second power line 82 is configured to provide a second power signal to the light-emitting device. For example, the second power line 82 may span across the (N-1)th cell column and the Nth cell column. Alternatively, the second power line 82 may span across the N+1th cell column and the N+2th cell column.

[0308] In an exemplary embodiment, the orthographic projection of the second power line 82 on the substrate at least partially overlaps with the orthographic projections of a first initial connection line 91 and two data signal lines 83 of the adjacent unit column on the substrate. The second power line 82 with a constant potential can effectively shield the influence of the data signal lines 83 on the anode, effectively improve the stability of the output current of the pixel driving circuit, and effectively improve the display quality and display effect.

[0309] In an exemplary embodiment, the orthographic projection of the second power line 82 onto the substrate may include the orthographic projections of a first initial connection line 91 and two data signal lines 83 of the adjacent cell column onto the substrate.

[0310] In an exemplary embodiment, the second power connection line 86 can be shaped like a broken line extending along the first direction X of the main body. It can be disposed between two adjacent second power lines 82 in the first direction X, and both ends of the second power connection line 86 are connected to the two second power lines 82 respectively. Thus, the second power connection line 86 extending along the first direction X of the main body and the second power line 82 extending along the second direction Y of the main body are interconnected. The second power lines 82 and the second power connection line 86 form a mesh-like interconnected structure on the display substrate for transmitting the second power signal. This not only effectively reduces the resistance of the second power lines and the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, thereby improving display uniformity and display quality. In addition, by setting the second power line in the display area, the second power line is located in the panel (VSS in Panel, or SIP) structure, which can significantly reduce the width of the bezel power leads, greatly reduce the width of the left and right bezels, increase the screen ratio, and facilitate the realization of full-screen display.

[0311] (22) Forming a third planarization layer pattern. In an exemplary embodiment, forming a third planarization layer pattern may include: coating a third planarization film on a substrate on which the aforementioned pattern is formed, and patterning the third planarization film using a patterning process to form a third planarization layer covering the pattern of the seventh conductive layer, wherein a plurality of vias are provided on the third planarization layer, as shown in FIG20.

[0312] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate includes at least a second anode via V32.

[0313] In an exemplary embodiment, the orthographic projection of the second anode via V32 on the substrate is within the range of the orthographic projection of the second anode connection electrode 85 on the substrate. The third planarization layer within the second anode via V32 is removed, exposing the surface of the second anode connection electrode 85. The second anode via V32 is configured to allow a subsequently formed anode to be connected to the second anode connection electrode 85 through the via.

[0314] Thus, the driving structure layer of the display substrate according to the exemplary embodiments of this disclosure is completed. In a plane parallel to the display substrate, the driving structure layer may include multiple circuit units. Each circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a first light-emitting signal line, a second light-emitting signal line, a first initial signal line, a second initial trace (or a third initial signal line), a first power line, and a data signal line connected to the pixel driving circuit. In a direction perpendicular to the display substrate, the driving structure layer may include a first conductive layer (GATE1), a first insulating layer, a second conductive layer (GATE2), a second insulating layer, a third conductive layer (GATE3), a third insulating layer, a semiconductor layer, a fourth insulating layer, a fourth conductive layer (GATE4), a fifth insulating layer, a fifth conductive layer (SD1), a first planarization layer, a sixth conductive layer (SD2), a second planarization layer, a seventh conductive layer (SD3), and a third planarization layer, sequentially disposed on the substrate.

[0315] In an exemplary embodiment, the first conductive layer may include at least the first electrode of the first capacitor and the third electrode of the second capacitor; the second conductive layer may include at least the second electrode of the first capacitor and the fourth electrode of the second capacitor; the third conductive layer may include at least the bottom gate electrode of the third transistor T3; the semiconductor layer may include at least the active layers of the first transistor T1 to the seventh transistor T7; the fourth conductive layer may include at least a first light-emitting signal line, a second light-emitting signal line, a second scan signal line, and the gate electrodes of a plurality of transistors; the fifth conductive layer may include at least a first scan signal line, a third scan signal line, a fourth scan signal line, a first initial signal line to a third initial signal line; the sixth conductive layer may include at least a first power line and a data signal line; and the seventh conductive layer may include at least a second power line.

[0316] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz. The flexible substrate can be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass substrate. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0317] In an exemplary embodiment, the first to fifth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first to seventh conductive layers can be metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or can be alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti. The first to third planarization layers can be organic materials, such as resin or polyimide.

[0318] In an exemplary embodiment, after the driving structure layer is fabricated, a light-emitting structure layer and an encapsulation structure layer can be fabricated on the driving structure layer. The fabrication process may include the following operations.

[0319] (23) Forming an anode conductive layer pattern. In an exemplary embodiment, forming an anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on a third planarization layer, as shown in Figures 21A and 21B, where Figure 21B is a planar schematic diagram of the anode conductive layer in Figure 21A.

[0320] In an exemplary embodiment, the anode conductive layer of at least one repeating unit may include at least a first anode 90A, a second anode 90B, a third anode 90C, and a fourth anode 90D, and each anode may be connected to the second anode connection electrode 85 of the corresponding circuit unit through a second anode via V32.

[0321] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may include an anode body portion and an anode connecting portion that are interconnected. The anode connecting portion is connected to the anode body portion on one hand, and to the second anode connecting electrode 85 of the corresponding circuit unit through the second anode via V32 on the other hand.

[0322] In an exemplary embodiment, the orthographic projections of the first anode 90A and the second anode 90B on the substrate at least partially overlap with the orthographic projection of the second power line 82 on the substrate, and the orthographic projections of the third anode 90C and the fourth anode 90D on the substrate at least partially overlap with the orthographic projection of the second power connection line 86 on the substrate.

[0323] In an exemplary embodiment, the anode conductive layer can be a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can be a multi-layer composite structure, such as ITO / Ag / ITO.

[0324] (24) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form a pixel definition layer pattern covering the anode conductive layer pattern, as shown in FIG22.

[0325] In an exemplary embodiment, at least a first pixel opening 100A, a second pixel opening 100B, a third pixel opening 100C, and a fourth pixel opening 100D may be provided on the pixel definition layer of at least one repeating unit.

[0326] In an exemplary embodiment, the orthographic projection of the first pixel opening 100A onto the substrate lies within the range of the orthographic projection of the first anode 90A onto the substrate. The pixel definition film within the first pixel opening 100A is removed, exposing the surface of the first anode 90A. The orthographic projection of the second pixel opening 100B onto the substrate lies within the range of the orthographic projection of the second anode 90B onto the substrate. The pixel definition film within the second pixel opening 100B is removed, exposing the surface of the second anode 90B. The orthographic projection of the third pixel opening 100C onto the substrate lies within the range of the orthographic projection of the third anode 90C onto the substrate. The pixel definition film within the third pixel opening 100C is removed, exposing the surface of the third anode 90C. The orthographic projection of the fourth pixel opening 100D onto the substrate lies within the range of the orthographic projection of the fourth anode 90D onto the substrate. The pixel definition film within the fourth pixel opening 100D is removed, exposing the surface of the fourth anode 90D.

[0327] In an exemplary embodiment, the orthographic projection of at least one of the first pixel opening 100A, the second pixel opening 100B, the third pixel opening 100C, and the fourth pixel opening 100D onto the substrate does not overlap with the orthographic projection of the second anode via onto the substrate. This disclosure achieves good flatness of the anode by ensuring that there are no anode vias within the range of the pixel openings.

[0328] In an exemplary embodiment, the orthographic projections of the first pixel opening 100A and the third pixel opening 100C on the substrate at least partially overlap with the orthographic projection of the second power line 82 on the substrate, and the orthographic projections of the second pixel opening 100B and the fourth pixel opening 100D on the substrate at least partially overlap with the orthographic projection of the second power connection line 86 on the substrate.

[0329] In an exemplary embodiment, the shapes of the first pixel opening 100A and the third pixel opening 100C can be rhomboid. The first pixel opening 100A may have a first opening center line, which can be a straight line extending along the second direction Y and passing through the geometric center of the first pixel opening 100A; the first opening center line is a dummy line. The third pixel opening 100C may have a third opening center line, which can be a straight line extending along the second direction Y and passing through the geometric center of the third pixel opening 100C; the third opening center line is a dummy line.

[0330] In an exemplary embodiment, the second power line 82 may have a power line centerline, which may be a straight line that bisects the second power line 82 in the first direction X and extends along the second direction Y. The power line centerline is a dummy line. The orthographic projection of the first opening centerline on the substrate at least partially overlaps with the orthographic projection of the power line centerline on the substrate, and the orthographic projection of the third opening centerline on the substrate at least partially overlaps with the orthographic projection of the power line centerline on the substrate.

[0331] In an exemplary embodiment, the orthographic projection of the center line of the first opening onto the substrate and the orthographic projection of the center line of the power line onto the substrate can substantially overlap, as can the orthographic projection of the center line of the third opening onto the substrate and the orthographic projection of the center line of the power line onto the substrate. By setting the center lines of the first and third openings to substantially overlap with the center line of the power line, this disclosure enables the first and third anodes to have good flatness and symmetry, effectively avoiding defects such as screen-off watermarks (mura) caused by poor anode flatness, effectively improving color shift, and enhancing display quality.

[0332] In an exemplary embodiment, the shapes of the second pixel opening 100B and the fourth pixel opening 100D can be elliptical. The second pixel opening 100B may have a second opening center line, which can be a straight line extending along the major axis of the second pixel opening 100B and passing through the geometric center of the second pixel opening 100B; the second opening center line is a dummy line. The fourth pixel opening 100D may have a fourth opening center line, which can be a straight line extending along the major axis of the fourth pixel opening 100D and passing through the geometric center of the fourth pixel opening 100D; the fourth opening center line is a dummy line.

[0333] In an exemplary embodiment, the second power connection line 86 may include at least a straight segment and an oblique segment. The straight segment may be a straight line extending along the first direction X, and the oblique segment may be a straight line extending at an angle of approximately 45° to the first direction X. The oblique segment may have a connection centerline, which may be a straight line that bisects the oblique segment in a direction perpendicular to its extension and extends at an angle of approximately 45° to the first direction X. The connection centerline is a hypothetical line. The orthographic projection of the second opening centerline onto the substrate at least partially overlaps with the orthographic projection of the connection centerline onto the substrate, and the orthographic projection of the fourth opening centerline onto the substrate at least partially overlaps with the orthographic projection of the connection centerline onto the substrate.

[0334] In an exemplary embodiment, the orthographic projection of the second opening centerline onto the substrate and the orthographic projection of the connecting line centerline onto the substrate can substantially overlap, as can the orthographic projection of the fourth opening centerline onto the substrate and the orthographic projection of the connecting line centerline onto the substrate. By setting the second and fourth opening centerlines to substantially overlap with the connecting line centerlines, this disclosure enables the second and fourth anodes to have good flatness and symmetry, effectively avoiding defects such as screen-off watermarks caused by poor anode flatness, effectively improving color shift, and enhancing display quality.

[0335] In an exemplary embodiment, the subsequent preparation process may include: first forming an organic light-emitting layer using vapor deposition or inkjet printing, then forming a cathode on the organic light-emitting layer, and subsequently forming an encapsulation structure layer. The encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0336] An exemplary embodiment of this disclosure provides a display substrate that employs pixel driving circuits in adjacent unit rows that are substantially symmetrically arranged with respect to the row center line, and pixel driving circuits in adjacent unit columns that are substantially symmetrically arranged with respect to the column center line. This not only improves the uniformity and symmetry of the pixel driving circuits, enabling uniformity in process and coupling capacitance, and uniform current distribution, but also effectively improves display stability and uniformity, and enhances display effect and quality. Furthermore, it simplifies the structure of the pixel driving circuits, effectively improves the utilization of layout space, has a more reasonable structural arrangement, and reduces the area occupied by the pixel driving circuits, which is beneficial for achieving a high resolution (PPI) display of 400 to 500.

[0337] This disclosed display substrate splits the second initial trace that transmits the second initial signal into a second initial signal line and a third initial signal line. The second initial signal line is configured to provide a first type of second initial signal to the pixel driving circuit of the first circuit unit, and the third initial signal line is configured to provide a second type of second initial signal to the pixel driving circuits of the second, third, and fourth circuit units. This enables the provision of different reset voltages to light-emitting devices of different colors, which can effectively improve the low grayscale display quality, display quality, and display effect.

[0338] The display substrate disclosed herein, by providing a first power connection line and a first power line, and the first power connection line and the first power line forming a mesh-like interconnected structure on the display substrate for transmitting the first power signal, can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve display uniformity, and improve display quality and display performance.

[0339] The present disclosure displays a substrate that reduces the number of signal lines by setting two adjacent cell rows to share the same first power supply connection line, effectively saving layout space and facilitating high-resolution display.

[0340] This disclosed display substrate, by setting a second power connection line and a second power line, and forming a mesh-like interconnected structure on the display substrate to transmit the second power signal, can not only effectively reduce the resistance of the second power line and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate, thereby improving display uniformity, display quality, and display performance. By setting the second power line in the display area, the second power line is located in the panel (VSS in Panel, or SIP) structure, which can significantly reduce the width of the bezel power leads, greatly reduce the width of the left and right bezels, increase the screen-to-body ratio, and facilitate the realization of full-screen display.

[0341] This embodiment of the present disclosure, by setting a first initial connection line, a second initial connection line, and a third initial connection line, forms a mesh-like interconnected structure on the display substrate to transmit a first initial signal with the first initial signal line and the first initial connection line, and forms a mesh-like interconnected structure on the display substrate to transmit a first type of second initial signal with the second initial signal line and the third initial signal line and the third initial connection line, and forms a mesh-like interconnected structure on the display substrate to transmit a second type of second initial signal, can not only effectively reduce the resistance of the initial signal line and reduce the voltage drop of the initial signal, but also effectively improve the uniformity of the initial signal in the display substrate, effectively improve display uniformity, and improve display quality.

[0342] The display substrate of this disclosure reduces the number of signal lines and effectively saves layout space by setting the pixel driving circuits of two adjacent unit rows to share the same second initial signal line and the pixel driving circuits of two adjacent unit rows to share the same third initial signal line, which is conducive to achieving high-resolution display.

[0343] The display substrate disclosed herein provides a first initial connection line between two data signal lines of adjacent circuit units. The first initial connection line, having a constant potential, can effectively shield crosstalk between adjacent data signal lines, effectively improve the stability of the output current of the pixel driving circuit, and effectively improve display quality and display effect.

[0344] The display substrate of this disclosure has a first gate electrode and a fourth gate electrode of some adjacent unit columns that are interconnected as an integral structure, and a second active layer of some adjacent circuits that are interconnected as an integral structure. On the one hand, it can effectively reduce wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is conducive to achieving high resolution. On the other hand, it can effectively increase the size of the capacitor plate and effectively increase the capacitance value of the capacitor, so as to maintain the stability of the pixel driving circuit to the maximum extent.

[0345] The display substrate disclosed herein effectively reduces the resistance of the scan signal lines and lowers the voltage drop of the scan signal by placing multiple scan signal lines in the first source-drain metal layer, thereby improving the compensation speed and display quality.

[0346] This disclosure shows that by setting the aspect ratio of the third transistor T3 in different circuit units, the data range corresponding to different pixel driving circuits can be matched with the data driver.

[0347] The present disclosure shows that by setting a first blocking block and a third blocking block to block the third transistor T3, and setting a second blocking block and a fourth blocking block to block the second active layer, the light emitted by the light-emitting device and the reflected light from the film layer can be effectively blocked from illuminating the channel region of the second transistor T2 and the third transistor T3. This can prevent the oxide transistor from experiencing characteristic drift due to light exposure, improve the electrical characteristics of the oxide transistor, and improve the driving performance of the pixel driving circuit.

[0348] The display substrate disclosed herein features a first and third opening center line that substantially overlaps with the power line center line, and a second and fourth opening center line that substantially overlaps with the connecting line center line. This design allows the first to fourth anodes to have good flatness and symmetry, effectively avoiding defects such as screen-off watermarks caused by poor anode flatness, effectively improving color shift, and enhancing display quality.

[0349] The preparation process of this disclosure is well compatible with existing preparation processes. The process is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0350] Figure 23 is a schematic diagram of another display substrate structure according to an exemplary embodiment of the present disclosure. The main structure of the display substrate in this embodiment is basically the same as that of the display substrate shown in Figure 8. The difference is that the display substrate in this embodiment is also provided with shielding lines. Figure 23 only shows the structure of the first conductive layer, the second conductive layer, the third conductive layer and the semiconductor layer.

[0351] As shown in Figure 23, the shielding line 36 can be a straight line or a broken line extending along the first direction X. A shielding block 36-1 can be connected to the shielding line 36. The shielding block 36-1 can be block-shaped (such as rectangular). The orthographic projection of the shielding block 36-1 on the substrate at least partially overlaps with the orthographic projection of the seventh active layer on the substrate.

[0352] In an exemplary embodiment, the orthographic projection of the channel region of the seventh active layer onto the substrate may be within the range of the orthographic projection of the shielding block 36-1 onto the substrate.

[0353] In an exemplary embodiment, the orthographic projection of the shielding line 36 on the substrate at least partially overlaps with the orthographic projection of the subsequently formed seventh gate electrode on the substrate.

[0354] In an exemplary embodiment, in at least one unit row, the shielding line 36 and the plurality of shielding blocks 36-1 can be an integral structure that is interconnected.

[0355] In an exemplary embodiment, the shielding line 36 and a plurality of shielding blocks 36-1 may be disposed in the third conductive layer. In a direction perpendicular to the display substrate, the shielding blocks 36-1 are disposed between the fourth electrode plate 14 and the seventh active layer.

[0356] In an exemplary embodiment, the orthographic projection of the seventh active layer onto the substrate at least partially overlaps with the orthographic projection of the fourth electrode onto the substrate, and the fourth electrode with the second node potential affects the seventh transistor T7. This disclosure, by providing a shielding line and a shielding block, where the orthographic projection of the shielding block onto the substrate includes the orthographic projection of the channel region of the seventh transistor T7 onto the substrate, and the shielding block is located between the fourth electrode and the seventh active layer, effectively eliminates the influence of the fourth electrode potential on the seventh transistor T7, thereby improving the electrical characteristics of the seventh transistor T7.

[0357] In some implementations, the shield line can transmit the fourth scan signal, that is, the shield line and the fourth scan signal line can be connected to the same signal source. The overlapping area of ​​the shield line and the seventh active layer can serve as the bottom gate electrode of the seventh transistor T7, and the seventh gate electrode can serve as the top gate electrode of the seventh transistor T7, forming a top-gate and bottom-gate structure of the seventh transistor T7.

[0358] In other embodiments, the shielding line can transmit a first type of second initial signal, that is, the shielding line and the second initial signal line can be connected to the same signal source to form a double-layer structure of initial signal line, which can further reduce the resistance of the second initial signal line, reduce the voltage drop of the first type of second initial signal, and further improve the display uniformity.

[0359] In some other embodiments, the shielding line can transmit a second type of second initial signal, that is, the shielding line and the third initial signal line can be connected to the same signal source to form a double-layer structure of initial signal lines, which can further reduce the resistance of the third initial signal line, reduce the voltage drop of the second type of second initial signal, and further improve the display uniformity.

[0360] In some possible implementations, the shielding wires in one part of the units can transmit a first type of second initial signal, while the shielding wires in another part of the units can transmit a second type of second initial signal; this disclosure does not limit this.

[0361] In an exemplary embodiment, the fabrication process of the display substrate in this embodiment is basically the same as that in the previous embodiment. The difference is that, in forming the third conductive layer pattern, the third conductive layer of each circuit unit in the display substrate further includes a shielding line 36 and a shielding block 36-1.

[0362] Figure 24 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. The main structure of the display substrate in this embodiment is basically the same as that of the display substrate shown in Figure 8. The difference is that the second initial trace in the display substrate of this embodiment includes a fourth initial signal line. Figure 24 only illustrates the structure of the first conductive layer, the second conductive layer, the third conductive layer, the semiconductor layer, the fourth conductive layer, and the fifth conductive layer.

[0363] As shown in Figure 24, the shape of the fourth initial signal line 74 can be a straight line or a broken line extending along the first direction X. It can be continuously arranged in a cell row and located between two adjacent cell rows. The fourth initial signal line 74 can be connected to the first region of the second active layer in each circuit cell through the second via V2. The fourth initial signal line 74 realizes the writing of the second initial signal from the first circuit cell to the first terminal of the second transistor T2 in the fourth circuit cell.

[0364] In an exemplary embodiment, two adjacent cell rows share the same fourth initial signal line 74, meaning that the pixel driving circuits in two adjacent cell rows are connected to the same fourth initial signal line 74, which reduces the number of signal lines and can effectively save layout space.

[0365] In this exemplary embodiment, the substrate fabrication process is substantially the same as that in the aforementioned embodiments. The difference is that, in forming the semiconductor layer pattern, the second active layers of the first, second, third, and fourth circuit units adjacent in the first direction X and the second direction Y are interconnected as an integral structure, and the four circuit units share the first region of the same second active layer. In forming the fifth conductive layer pattern, the fourth initial signal line 74 is located between two adjacent cell rows and is connected to the first region of the second active layer in the first to fourth circuit units through the second via V2.

[0366] The structure and its preparation process described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs, and this disclosure does not limit them.

[0367] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0368] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0369] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate comprising a plurality of repeating units; in a direction perpendicular to the display substrate, each repeating unit includes a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate; in a plane parallel to the display substrate, the driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit, at least one first initial signal line extending along a unit row direction, and at least one second initial trace extending along a unit row direction, the first initial signal line being configured to provide a first initial signal to the pixel driving circuit, and the second initial trace being configured to provide a second initial signal to the pixel driving circuit. The light-emitting structure layer includes multiple light-emitting units, at least one light-emitting unit includes a light-emitting device, and the light-emitting device of at least one light-emitting unit is connected to a pixel driving circuit in at least one circuit unit; the pixel driving circuit and the first initial signal line of adjacent unit rows are symmetrically arranged with respect to the row center line, and the pixel driving circuit and the first initial signal line of adjacent unit columns are symmetrically arranged with respect to the column center line, the row center line is a straight line located between two adjacent unit rows and extending along the unit row direction, and the column center line is a straight line located between two adjacent unit columns and extending along the unit column direction; in at least one repeating unit, the pixel driving circuits of adjacent unit rows share the second initial trace.

2. The display substrate according to claim 1, wherein, At least one repeating unit further includes at least one first initial connection line extending along the unit column direction, the first initial connection line being connected to the first initial signal line to form a network connection structure on the display substrate for transmitting the first initial signal.

3. The display substrate according to claim 1, wherein, At least one repeating unit further includes at least one first power connection line extending along the unit row direction and at least one first power line extending along the unit column direction. The first power line is configured to provide a first power signal to the pixel driving circuits in the first circuit unit to the fourth circuit unit through the first power connection line. The first power line is connected to the first power connection line to form a network interconnection structure on the display substrate for transmitting the first power signal.

4. The display substrate according to claim 3, wherein, In at least one repeating unit, the pixel driving circuits in adjacent unit rows share the same first power supply connection line.

5. The display substrate according to claim 1, wherein, At least one repeating unit further includes at least one second power connection line and at least one second power line extending along the unit column direction, the second power line being configured to provide a second power signal to the light-emitting device, at least a portion of the second power connection line extending along the unit row direction, the second power line being connected to the second power connection line, forming a network interconnection structure on the display substrate for transmitting the second power signal.

6. The display substrate according to claim 5, wherein, At least one circuit unit further includes a data signal line extending along the cell column direction, the data signal line being configured to provide a data signal to the pixel driving circuit, wherein the orthographic projection of the second power line on the substrate at least partially overlaps with the orthographic projection of the two data signal lines of the adjacent cell column on the substrate.

7. The display substrate according to claim 1, wherein, The pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor. The first terminal of the first transistor is connected to the first initial signal line. The second terminal of the first transistor is connected to the top gate electrode of the third transistor, the second terminal of the fourth transistor, and the first terminal of the first capacitor. The first terminal of the second transistor is connected to the second initial trace. The second terminal of the second transistor is connected to the second terminal of the sixth transistor and the first terminal of the seventh transistor. The first terminal of the third transistor is connected to the second terminal of the fifth transistor. The second terminal of the third transistor is connected to the first terminal of the sixth transistor, the second terminal of the first capacitor, and the second terminal of the second capacitor. The first terminal of the fourth transistor is connected to the data signal line. The first terminal of the fifth transistor is connected to the first power line. The second terminal of the seventh transistor is connected to the first terminal of the second capacitor. The first to seventh transistors are oxide transistors, and the third transistor has a dual-gate structure.

8. The display substrate according to any one of claims 1 to 7, wherein, In at least one repeating unit, the plurality of circuit units include a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit periodically arranged in the unit row direction. The plurality of light-emitting units include a first light-emitting unit emitting red light, a second and fourth light-emitting units emitting green light, and a third light-emitting unit emitting blue light. The pixel driving circuit in the first circuit unit is connected to the light-emitting device in the first light-emitting unit, the pixel driving circuit in the second circuit unit is connected to the light-emitting device in the second light-emitting unit, the pixel driving circuit in the third circuit unit is connected to the light-emitting device in the third light-emitting unit, and the pixel driving circuit in the fourth circuit unit is connected to the light-emitting device in the fourth light-emitting unit. The first initial signal line is configured to send to the first circuit... The pixel driving circuit in the unit to the fourth circuit unit provides a first initial signal. The second initial trace includes a second initial signal line and a third initial signal line. The second initial signal line is configured to provide a first type of second initial signal to the pixel driving circuit in the first circuit unit. The third initial signal line is configured to provide a second type of second initial signal to the pixel driving circuits in the second, third, and fourth circuit units. The voltage of the first type of second initial signal is different from the voltage of the second type of second initial signal. The pixel driving circuits of the first circuit unit in adjacent unit rows share the same second initial signal line, and the pixel driving circuits of the second, third, and fourth circuit units in adjacent unit rows share the same third initial signal line.

9. The display substrate according to claim 8, wherein, At least one repeating unit further includes at least one second initial connection line extending along the unit column direction, the second initial connection line being connected to the second initial signal line, forming a network connection structure on the display substrate for transmitting the first type of second initial signal.

10. The display substrate according to claim 9, wherein, The pixel driving circuit includes at least a third transistor. A first blocking block is disposed on the second initial connection line. The orthographic projection of the first blocking block on the substrate at least partially overlaps with the orthographic projection of the top gate electrode of the third transistor of the first circuit unit and the second circuit unit in a cell row on the substrate. Alternatively, the orthographic projection of the first blocking block on the substrate at least partially overlaps with the orthographic projection of the top gate electrode of the third transistor of the third circuit unit and the fourth circuit unit in a cell row on the substrate.

11. The display substrate according to claim 9, wherein, The pixel driving circuit includes at least a second transistor, the second transistor includes at least a second active layer, a second blocking block is disposed on the second initial connection line, and the orthographic projection of the second blocking block on the substrate at least partially overlaps with the orthographic projections of the second active layers of the first circuit unit and the second circuit unit in one cell row, and the second active layers of the third circuit unit and the fourth circuit unit in another cell row on the substrate.

12. The display substrate according to claim 8, wherein, At least one repeating unit further includes at least one third initial connection line extending along the unit column direction, the third initial connection line being connected to the third initial signal line, forming a network connection structure on the display substrate for transmitting the second type of second initial signal.

13. The display substrate according to claim 12, wherein, The pixel driving circuit includes at least a third transistor, and a third blocking block is disposed on the third initial connection line. The orthographic projection of the third blocking block on the substrate at least partially overlaps with the orthographic projection of the top gate electrode of the third transistor of the first circuit unit and the second circuit unit in a cell row on the substrate. Alternatively, the orthographic projection of the third blocking block on the substrate at least partially overlaps with the orthographic projection of the top gate electrode of the third transistor of the third circuit unit and the fourth circuit unit in a cell row on the substrate.

14. The display substrate according to claim 12, wherein, The pixel driving circuit includes at least a second transistor, the second transistor includes at least a second active layer, and a fourth blocking block is disposed on the third initial connection line. The orthographic projection of the fourth blocking block on the substrate at least partially overlaps with the orthographic projections of the second active layers of the third circuit unit and the fourth circuit unit in one cell row, and the second active layers of the first circuit unit and the second circuit unit in another cell row on the substrate.

15. The display substrate according to claim 8, wherein, The pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, a seventh transistor, a first capacitor, and a second capacitor. The first terminal of the first transistor is connected to the first initial signal line, and the second terminal of the first transistor is connected to the top gate electrode of the third transistor and the first terminal of the first capacitor. The first terminal of the second transistor is connected to the second initial trace, and the second terminal of the second transistor is connected to the first terminal of the seventh transistor. The second terminal of the seventh transistor is connected to the first terminal of the second capacitor, and the second terminal of the third transistor is connected to the second terminal of the first capacitor and the second terminal of the second capacitor. In at least one repeating unit, the aspect ratio of the third transistor in the third circuit unit is greater than the aspect ratio of the third transistor in the first circuit unit.

16. The display substrate according to claim 15, wherein, The aspect ratio of the third transistor in the first circuit unit is greater than that of the third transistor in the second circuit unit, and the aspect ratio of the third transistor in the first circuit unit is greater than that of the third transistor in the fourth circuit unit.

17. The display substrate according to claim 15, wherein, The seventh transistor includes at least a seventh active layer, and the second capacitor includes a stacked third plate and a fourth plate; in at least one circuit unit, the orthographic projection of the seventh active layer on the substrate and the orthographic projection of the fourth plate on the substrate at least partially overlap.

18. The display substrate according to claim 17, wherein, At least one circuit unit further includes a shielding wire and a shielding block, the shielding block being connected to the shielding wire, and the orthographic projection of the seventh active layer on the substrate at least partially overlapping the orthographic projection of the shielding block on the substrate; In a direction perpendicular to the display substrate, the shielding block is disposed between the fourth electrode plate and the seventh active layer.

19. The display substrate according to any one of claims 1 to 7, wherein, In at least one repeating unit, the plurality of circuit units include a first circuit unit, a second circuit unit, a third circuit unit, and a fourth circuit unit arranged periodically in the unit row direction. The plurality of light-emitting units include a first light-emitting unit emitting red light, a second light-emitting unit emitting green light, a fourth light-emitting unit emitting green light, and a third light-emitting unit emitting blue light. The pixel driving circuit in the first circuit unit is connected to the light-emitting device in the first light-emitting unit. The pixel driving circuit in the second circuit unit is connected to the light-emitting device in the second light-emitting unit. The pixel driving circuit in the third circuit unit is connected to the light-emitting device in the third light-emitting unit. The pixel driving circuit in the fourth circuit unit is connected to the light-emitting device in the fourth light-emitting unit. The first initial signal line is configured to provide a first initial signal to the pixel driving circuits in the first to fourth circuit units. The second initial trace includes a fourth initial signal line, which is configured to provide a second initial signal to the pixel driving circuits in the first to fourth circuit units.

20. A display device comprising a display substrate as described in any one of claims 1 to 19.

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