Active snubber and controlling method thereof
Patent Information
- Application Number
- PCT/CN2025/084874
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2026-10-01
Smart Images
Figure CN2025084874_01102026_PF_FP_ABST
Abstract
Description
ACTIVE SNUBBER AND CONTROLLING METHOD THEREOFTechnical Field
[0001] The embodiments herein relate generally to the field of circuit, and more particularly, the embodiments herein relate to an active snubber and controlling method thereof.Background
[0002] In a power source circuit including a hard switching full bridge converter, the stress at some position such as the secondary Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) (e.g., MOSFETs within the bridge converter) is high when output power is high. Using a snubber is a useful way to clamp the voltage spike. Compared with a passive snubber, an active snubber may be coupled into the circuit when necessary, therefore may reduce the power consumption.
[0003] Figure 1 shows a full bridge converter with an active snubber 100. As shown in Figure 1, the snubber 100 comprises a capacitor CCL, a N-MOSFET QCL and a control circuit 130. The control signal (e.g., Pulse-Width Modulation (PWM) signal) for the N-MOSFET QCL is directly from Texas Instruments (TI) digital controller C2000 Digital Signal Processor (DSP) . The source of N-MOSFET QCL is connected to the capacitor CCL, instead of connected to the secondary ground.
[0004] Figure 2 shows another full bridge converter with an active snubber 200. As shown in Figure 2, the snubber 200 comprises a capacitor C1, a P-MOSFET Q1 and a control circuit 230. The PWM for the P-MOSFET Q1 is from Analog Devices, Inc. (ADI) digital controller ADP1055. The source of the P-MOSFET Q1 is directly connected to the secondary ground. The PWM for the P-MOSFET Q1 is got from a logic operation of main PWM1 and PWM2. The main PWM1 and PWM2 may be PWM for primary MOSFET or PWM for secondary MOSFET.
[0005] Figure 3 shows another full bridge converter with an active snubber 300. As shown in Figure 3, the snubber 300 comprises a capacitor C3, a P-MOSFET Q3 and a logic circuit. The input of the logic circuit is obtained from the DPWM1A and DPWM1B of the primary side.Summary
[0006] However, there are some deficiencies with the active snubber in the Figure 1 to Figure 3.
[0007] For the active snubber shown in Figure 1, the logic operation is integrated in digital Integrated Circuit (IC) (e.g., TI C2000 DSP) , and cannot be used in analog controlled converter. In addition, the PWM for the N-MOSFET QCL should synchronize with other PWM (s) , and thus there are high requirements for digital controllers, for controlling the delay. In addition, since the QCL is a N-MOSFET, source of QCL are not connected to the secondary ground, and the driver should be isolated; in addition, there needs one more auxiliary output which provides reference to the source of QCL.
[0008] For the active snubber shown in Figure 2, the logic operation is integrated in digital IC (e.g., ADP1055) , and cannot be used in analog controlled converter. In addition, multiple firmware version is required for driver or primary MOSFET for multiple sources.
[0009] For the active snubber shown in Figure 3, the turn on time period of the P-MOSFET Q3 should be well-designed. For example, for a vendor providing the primary MOSFET, driver and isolator, the Q3 turn on time (for example the time point t3 and the time period t3 to t5 shown in Figure 4) should be controlled. For example, the Q3turn on time t3 should be aligned with the time point at which the OUTL voltage raises up to a high voltage.
[0010] The time point t3 is determined by the inputs DPWM1A and DPWM1B, and the time period t3 to t5 is determined by R1 and C1 of the logic circuit. Therefore, when the logic circuit is fixed based on vendor1, t3 and t5 is fixed. In addition, the time period t1 to t2 is determined by delay of MOSFET turning on, driver and isolator.
[0011] Considering the multi-sources, sometimes the primary MOSFET, driver and isolator of a vendor2 is used to replace that of vendor1. However, as shown in Figure 4, which shows waveform differences between vendors, the time point at which the OUTL voltage begins to raise is different due to parameter difference; for vendor 1 (see the solid line) , the time point is t2 and for vendor 2 (see the dashed line) , the time point is t4. That is, for the time point t3, vendor1’s OUTL have raised to a high level, but vendor2’s OUTL is still zero.
[0012] Therefore, due to the waveform difference between vendors, if the vendor 2 is used to replace vendor 1, the capacitor C3 will discharge through Q3 at the time t3 (since the turning on time t3 for Q3 is fixed according to the parameters of vendor1) , which causes more power consumption on Q3. As a result, it’s difficult to find a second source of primary MOSFET, driver and isolator to replace the original source, which brings big risk of supply chain.
[0013] In view of the above deficiencies, the embodiments herein propose an active snubber and controlling method thereof.
[0014] In some embodiments, there proposes an active snubber, which may comprise a clamping circuit, a switch, and a control circuit. The switch is to selectively couple the clamping circuit to an output of a rectifier module of a circuit module when the switch is turned on so as to clamp the output of the rectifier module, and is to selectively decouple the clamping circuit from the output of the rectifier module when the switch is turned off. The control circuit is to generate, based on the output of the rectifier module, a control signal for turning on and offthe switch.
[0015] In some embodiments, there proposes a method for controlling an active snubber. The method may comprise the step of generating a control signal based on an output of a rectifier module of a circuit module; and the step of turning on and off a switch based on the control signal, to selectively couple a clamping circuit to the output of the rectifier module when the switch is turned on so as to clamp the output of the rectifier module or decouple the clamping circuit from the output of the rectifier module when the switch is turned off.
[0016] In some embodiments, there proposes an apparatus comprising the above active snubber.
[0017] With the embodiments, the control signal is generated based on the output ofthe rectifier module (i.e., OUTL) . As a result, the active snubber may be easily used in both analog and digital controlled power converters.
[0018] In addition, with the embodiments, since the control signal is generated based on the output of the rectifier module (i.e., OUTL) , the turning on time for the switch (e.g., MOSFET Q3)is set directly according to the OUTL voltage. As a result, the active snubber can be used by ignoring parameters difference of MOSFET driver, isolator and primary MOSFET; which makes supply chain more secure and resilient.Brief Description of the Drawings
[0019] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the embodiments disclosed herein. In the drawings, like reference numbers indicate identical or functionally similar elements, and in which:
[0020] Figure 1 shows a full bridge converter with an active snubber;
[0021] Figure 2 shows another full bridge converter with an active snubber;
[0022] Figure 3 shows another full bridge converter with an active snubber;
[0023] Figure 4 shows waveform differences among multi-sources;
[0024] Figure 5 shows a full bridge converter with active snubber, according to the embodiments herein;
[0025] Figure 6 is a timing sequence diagram for the active snubber of Figure5;
[0026] Figure 7 is another timing sequence diagram for the active snubber of Figure5;
[0027] Figure 8 shows a full bridge converter with another active snubber, according to the embodiments herein;
[0028] Figure 9 is a timing sequence diagram for the active snubber of Figure 8; and
[0029] Figure 10 is a schematic flow chart showing an example method for controlling an active snubber, according to the embodiments herein.Detailed Description of Embodiments
[0030] Embodiments herein will be described in detail hereinafter with reference to the accompanying drawings, in which embodiments are shown. These embodiments herein may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. The elements of the drawings are not necessarily to scale relative to each other.
[0031] References in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” and the like indicate that the embodiment described may include a particular feature, structure, or characteristic, but it is not necessary that every embodiment includes the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
[0032] It shall be understood that although the terms “first” and “second” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and / or” includes any and all combinations of one or more ofthe associated listed terms.
[0033] As used herein unless expressly stated to the contrary, the phrase “at least one of A and B” or “at least one of A or B” should be understood to mean any of the following “only A, only B, or both A and B. ” The phrase “A and / or B” should be understood to mean any of the following “only A, only B, or both A and B” .
[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a” , “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” , “comprising” , “has” , “having” , “includes” and / or “including” , when used herein, specify the presence of stated features, elements, and / or components etc., but do not preclude the presence or addition of one or more other features, elements, components and / or combinations thereof.
[0035] The term "coupled" herein denotes both direct and indirect junctions, which may be mediated by an intervening part or material.
[0036] It is noted that these terms as used in this document are used only for ease of description and differentiation among nodes, devices or networks etc. With the development of the technology, other terms with the similar / same meanings may also be used.
[0037] In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skills in the art to which this disclosure belongs.
[0038] Figure 5 shows a full bridge converter with active snubber 500. As shown in Figure 5, the active snubber 500 may comprise a clamping circuit, a switch, and a control circuit 530. The full bridge converter (also be referred as "circuit module" ) may comprise a rectifier module 540. In an example, the rectifier module 540 may be a rectifier bridge comprising a set of transistors, such as MOSFET Q21, Q22, Q23, and Q24 shown in Figure 5.
[0039] In an example, the clamping circuit may comprise a capacitor such as the capacitor C3 shown in Figure 5. In an example, the switch may comprise a transistor such as the P-MOSFET Q3 shown in Figure 5.
[0040] In an example, the switch Q3 is to selectively couple the clamping circuit C3 to an output of a rectifier module 540 when the switch Q3 is turned on, so as to clamp the output ( "OUTL" as shown in Figure 5) of the rectifier module 540, and the switch Q3 is to selectively decouple the clamping circuit C3 from the output "OUTL" of the rectifier module 540 when the switch Q3 is turned off.
[0041] In an example, the control circuit 530 is to generate, based on the output of the rectifier module 540, a control signal for turning on and off the switch Q3. That is, in Figure 5, the control signal is generated based on the OUTL, instead of the DPWM1A and DPWM1B of the primary side.
[0042] The OUTL voltage is usually much higher than a working voltage of a logic circuit 532 within the control circuit 530. Therefore, in an example, the control circuit 530 may comprise a voltage dividing circuit 531 (sometimes referred as "voltage sample block" ) , in addition to the logic circuit 532. By using the voltage dividing circuit 531, the voltage OUTL may be divided as a divided voltage (sometimes referred as "OUTL_S" ) . The divided voltage OUTL_S is lower and is proportional to OUTL. The divided voltage OUTL_S may be supplied directly to the logic circuit532, to generate the control signal.
[0043] In an example, the voltage dividing circuit 531 may comprise two resistors shown as Rup and Rdown in Figure 5. In an example, the first end of the resistor Rup is coupled to the voltage OUTL at the output of the rectifier module 540, and the second end of the resistor Rup is coupled to the voltage OUTL_S at the output of the voltage dividing circuit 531 and to the first end of the resistor Rdown. The second end of the resistor Rdown may be coupled to the ground of the secondary side. Note that, each of the resistors may be a single resistor or several resistors.
[0044] The resistors Rup and Rdown may be adjusted to ensure the requirements on the OUTL_S. For example, the time point T3 of Figure 6 is PMOS Q3 turn on (PWM for Q3 from high to low) time. At t3, OUTL raises up to a high voltage. Therefore, the requirements on the OUTL_S may be that OUTL_S (at time point t1) should be raised up to an input threshold voltage VIH at a high voltage of the following logic module (such as ST1) ; and that the OUTL_S should be lower than a breakdown voltage of ST1 input port.
[0045] In an example, the logic circuit 532 may comprise a first logic module to generate a first square wave signal from the OUTL_S. For example, the first logic module may be but not limited to a Schmitt trigger shown as ST1 in Figure 5, which may help to stabilize signal transitions and filter out noise. OUTL_S is not a square wave and even include some ringing. The Schmitt trigger ST1 may convert OUTL_S to a clean square wave (sometimes referred as "ST1 OUT" ) .
[0046] In an example, the first logic module may be other logic components (such as OR gate, AND gate) and / or a combination of several logic components. By adopting the logic components or their combination, a first square wave signal may be obtained.
[0047] In an example, the logic circuit 532 may comprise a delay circuit coupled to an output of the first logic module ST1, to delay a rising edge of the first square wave ST1 OUT to a period of time. For example, the delay circuit may comprise a capacitor C1 and a resistor R1. The R1, C1 may define the PMOS Q3 turn on time ton (t3 to t4 as shown in Figure 6) .
[0048] In an example, the first end of the resistor R1 may be coupled to the output of the first logic module ST1. The first end of the capacitor C1 may be coupled to a second end of the resistor R1 and an output of the delay circuit; the second end of the capacitor C1 may be coupled to the ground of the secondary side.
[0049] The delay circuit may be adjusted to control the turn on time period t3 to t4. For example, the turn on time period t3 to t4 may be adjusted according to the time constant of R-C circuit including R1 and C1.
[0050] In an example, the logic circuit 532 may further comprise a diode D1. An anode of the diode D1 may be coupled to the first end of the capacitor C1, a cathode of the diode D1 may be coupled to the output of the first logic module ST1. Due to the diode D1, at the falling edge of square wave ST1 OUT, the diode D1 may discharge capacitor C1 rapidly, which does not change the falling edge of ST1 OUT. The diode D1 can fast discharge capacitor C1 to make PMOS Q3 can turn on every switching time even the full bridge works in maximum duty condition (i.e., lowest Vin and highest Vout) .
[0051] In an example, the logic circuit 532 may further comprise a second logic module to provide a second square wave having an opposite phase with the first square wave ST1 OUT. In an example, as shown in Figure 5, an input of the second logic module may be coupled to the output of the voltage divider circuit 531, to generate the second square wave based on the divided voltage. In an example, the second logic module may be a NOT gate, thus the generated second square wave may be referred as "NOT1 OUT" accordingly.
[0052] In an example, the second logic module may be other logic components (such as NOR gate, NAND gate) and / or a combination of several logic components. By adopting the logic components or their combination, a second square wave signal with inverted phase may be obtained.
[0053] In an example, the logic circuit 532 may further comprise a third logic module to combine the delayed first square wave (sometimes referred as "OR1IN1" ) and the second square wave signal NOT1 OUT to form the control signal.
[0054] In an example, the third logic module may be an OR gate, which does an OR operation of the OR1 IN1 and the NOT1 OUT. If both the OR1 IN1 and the NOT1 OUT are high, the output of the OR gate is also high. If either the OR1 IN1 or the NOT1 OUT is low, the output of the OR gate is low. So, When OR1 IN1 raise up to VIH of OR1, PWM for Q3 becomes high (see time point t4 of Figure 6 and t2 of Figure 9) .
[0055] In an example, the second logic module may be other logic components (such as NOR gate) and / or a combination of several logic components. By adopting the logic components or their combination, a control signal may be obtained from the delayed first square wave and the inverted second square wave.
[0056] In an example, the active snubber 500 may further comprise a driving circuit. An input of the driving circuit may be coupled to the output of the logic circuit 532, and an output of the driving circuit may be coupled to the switch Q3, for generating a driving signal for turning on and off the switch Q3.
[0057] In an example, the first end of the capacitor C1 may be coupled to the output of the rectifier module 540; a second end of the capacitor C2 may be coupled to a drain of the transistor Q3; a source of the transistor Q3 may be coupled to the ground; and a gate of the transistor Q3 may be coupled to the output of the driving circuit.
[0058] Figure 6 is a timing sequence diagram for the active snubber of Figure 5. As shown in Figure 6, for the active snubber of Figure 5, the PMOS turn on time t3 is only determined by OUTL voltage, and the MOSFET delay can be decoupled with snubber control. That is, the PMOS turn on time t3 is not fixed according to a specific vendor, and may be moved according to the OUTL voltage. As a result, when the vendor 2 is used to replace vendor 1, the PMOS turn on time t3 will be delayed if the OUTL is delayed, the deficiency of Figure 4 may be solved. That is, the turn on time t3 does not be fixed depending on vendors for MOSFET driver, isolator and primary MOSFET, which means that multi-sources are possible.
[0059] Figure 7 is another timing sequence diagram for the active snubber of Figure 5. As shown in Figure 7, under some conditions such as light load condition, there may be some problem if the first, second, third logic modules are provided by different vendors.
[0060] Due to the ST1 and NOT1 shown in Figure 5 are provided by different vendors, the thresholds of input voltage for ST1 and NOT1 are different. As a result, as shown in Figure 7, when OUTL drop down slowly under the light load condition, the falling edge of the first square wave ST1 OUT may be in advance than the rising edge of the second square wave NOT1 OUT, which results that the PMOS Q3 turn on incorrectly during time period t4 to t5 as shown in Figure 7.
[0061] Figure 8 shows a full bridge converter with another active snubber 800. The active snubber 800 is different than the active snubber 500 in that the input of the second logic module (NOT1 shown in Figure 5 and Figure 8) is coupled to the output of the first logic module ST1, instead of the output of the voltage divider circuit 531.
[0062] Figure 9is a timing sequence diagram for the active snubber of Figure 8. Different than the OUTL and the divided OUTL_S (they may drop down slowly under the light load condition) , the output of the first logic module ST1 (STI OUT as shown in Figure 9) is a square wave which drops down very quickly. That is, OUTL_S raises up to VIH (input high threshold voltage) at time t1, ST1 output becomes high. Once OUTL_S falls down to VIL (input low threshold voltage) at time t3, ST1 output becomes low. As a result, the difference of threshold voltages of the first and second logic modules almost have no influence on the output of the third logic module.
[0063] Therefore, the active snubber can be used by further ignoring parameters difference of logic ICs from different vendors; which makes supply chain further more secure and resilient.
[0064] Figure 10 is a schematic flow chart showing an example method 1000 for controlling a active snubber, according to the embodiments herein. In an embodiment, the flow chart in Figure 10 may be implemented in the circuit shown in Figure 5 or Figure 8.
[0065] The method 1000 may begin with step S1001 of generating a control signal based on an output of a rectifier module 540 of a circuit module.
[0066] In an example, the step S1001 of generating a control signal may further comprise the step of dividing an output voltage at the output of the rectifier module to a divided voltage.
[0067] In an example, the step S1001 of generating a control signal may further comprise the step of generating a first square wave based on the divided voltage.
[0068] In an example, the step S1001 of generating a control signal may further comprise the step of delaying a rising edge ofthe first square wave to a period of time,
[0069] In an example, the step S1001 of generating a control signal may further comprise the step of generating a second square wave based on the divided voltage or the first square wave, wherein the second square wave has an opposite phase with the first square wave.
[0070] In an example, the step S1001 of generating a control signal may further comprise the step of generating the control signal based on the delayed first square wave and the second square wave.
[0071] The method 1000 may further a step S1002 of turning on and off a switch Q3 based on the control signal, to selectively couple a clamping circuit C3 to the output of the rectifier module 540 when the switch Q3 is turned on so as to clamp the output of the rectifier module 540 or decouple the clamping circuit C3 from the output of the rectifier module 540 when the switch Q3 is turned off.
[0072] In an example, the step S1002 of turning on and off the switch based on the control signal may further comprise the step of generating a driving signal for turning on and off the switch, based on the control signal.
[0073] It will be recognized that principles of the disclosure are not limited to the embodiments so described, but instead can be practiced with modification and alteration without departing from the scope of the appended claims. The above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and / or undertaking additional features than those features explicitly listed. The scope of the embodiments should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims
1.An active snubber (500, 700) , comprising:- a clamping circuit (C3) ;- a switch (Q3) , to selectively couple the clamping circuit (C3) to an output of a rectifier module (540) of a circuit module when the switch (Q3) is turned on so as to clamp the output of the rectifier module (540) or decouple the clamping circuit (C3) from the output of the rectifier module (540) when the switch (Q3) is turned off; and- a control circuit (530) , to generate, based on the output of the rectifier module (540) , a control signal for turning on and off the switch (Q3) .2.The active snubber (500, 700) according to claim 1, wherein the control circuit (530) further comprises:- a voltage dividing circuit (531) coupled to the output of the rectifier module (540) , to divide an output voltage at the output of the rectifier module (540) to a divided voltage.3.The active snubber (500, 700) according to claim 2, wherein the control circuit (530) further comprises:- a logic circuit (532) coupled to an output of the voltage divider circuit (531) , to generate the control signal.4.The active snubber (500, 700) according to claim 3, wherein the logic circuit (532) further comprising:- a first logic module coupled to the output of the voltage divider circuit (531) , to generate a first square wave based on the divided voltage.5.The active snubber (500, 700) according to claim 4, wherein the logic circuit (532) further comprising:- a delay circuit coupled to an output of the first logic module (ST1) , to delay a rising edge of the first square wave to a period of time.6.The active snubber (500, 700) according to claim 5, wherein the delay circuit further comprising:- a first resistor (R1) , a first end of the first resistor (R1) is coupled to the output of the first logic module (ST1) ; and- a first capacitor (C1) , a first end of the first capacitor (C1) is coupled to a second end of the first resistor (R1) and an output of the delay circuit, a second end of the first capacitor (C1) is coupled to the ground.7.The active snubber (500, 700) according to claim 6, wherein the logic circuit (532) further comprising:- a diode (D1) , an anode of the diode (D1) is coupled to the first end of the first capacitor (C1) , a cathode of the diode (D1) is coupled to the output of the first logic module (ST1) .8.The active snubber (500, 700) according to any one of claims 5 to 7, wherein the logic circuit further comprising:- a second logic module (NOT1) , an input of the second logic module (NOT1) is coupled to the output of the voltage divider circuit (531) or the output of the first logic module (ST1) , to generate a second square wave based on the divided voltage or the first square wave, wherein the second square wave has an opposite phase with the first square wave; and- a third logic module (OR1) , a first input of the third logic module (OR1) is coupled to an output of the delay circuit, a second input of the third logic module (OR1) is coupled to an output of the second logic module (NOT1) , to generate the control signal based on the delayed first square wave and the second square wave.9.The active snubber (500, 700) according to any one of claims 3 to 8, further comprising:- a driving circuit, an input of the driving circuit is coupled to the output of the logic circuit (530) , an output of the driving circuit is coupled to the switch (Q3) , for generating, based on the control signal, a driving signal for turning on and off the switch (Q3) .10.The active snubber (500, 700) according to any one of claims 2 to 9, wherein the voltage dividing circuit further comprises:- a second resistor (Rup) , a first end of the second resistor (Rup) is coupled to the output of the rectifier module (540) ; and- a third resistor (Rdown) , a first end of the third resistor (Rdown) is coupled to a second end of the second resistor (Rup) and an output of the voltage dividing circuit (531) , a second end of the third resistor (Rdown) is coupled to the ground.11.The active snubber (500, 700) according to any one of claims 1 to 10, wherein the clamping circuit (C3) comprises a second capacitor.12.The active snubber (500, 700) according to any one of claims 1 to 11, wherein the switch (Q3) comprises a transistor.13.The active snubber (500, 700) according to claim 12 when depending on claim 11, wherein:a first end of the second capacitor (C3) is coupled to the output of the rectifier module (540) ;a second end of the second capacitor (C3) is coupled to a drain of the transistor (Q3) ;a source of the transistor (Q3) is coupled to the ground; anda gate of the transistor (Q3) is coupled to the output of the driving circuit.14.The active snubber (500, 700) according to any one of claims 1 to 13, wherein the first logic module (ST1) is a Schmitt trigger;the second logic module (NOT1) is a NOT gate; and / orthe third logic module (OR1) is an OR gate.15.The active snubber (500, 700) according to any one of claims 1 to 14, wherein the circuit module is a bridge converter module; and / orwherein the rectifier module (540) is a rectifier bridge comprising a set of transistors (Q21, Q22, Q23, Q24) .16.A method (1000) for controlling an active snubber (500, 700) , comprising:- generating (S1001) a control signal based on an output of a rectifier module (540) of a circuit module; and- turning on and off (S1002) a switch (Q3) based on the control signal, to selectively couple a clamping circuit (C3) to the output of the rectifier module (540) when the switch is turned on so as to clamp the output of the rectifier module (540) or decouple the clamping circuit (C3) from the output of the rectifier module (540) when the switch (Q3) is turned off.17.The method (1000) according to claim 16, wherein generating (S1001) the control signal further comprising:- dividing an output voltage at the output of the rectifier module to a divided voltage.18.The method (1000) according to claim 17, wherein generating (S1001) the control signal further comprising:- generating a first square wave based on the divided voltage.19.[Corrected under Rule 26, 17.04.2025]The method (1000) according to claim 18, wherein generating (S1001) the control signal further comprising:- delaying a rising edge of the first square wave to a period of time.20.The method (1000) according to claim 19, wherein generating (S1001) the control signal further comprising- generating a second square wave based on the divided voltage or the first square wave, wherein the second square wave has an opposite phase with the first square wave; and- generating the control signal based on the delayed first square wave and the second square wave.21.The method (1000) according to any one of claims 16 to 20, wherein turning on and off (S1002) the switch based on the control signal further comprising:- generating a driving signal for turning on and off the switch, based on the control signal.22.The method (1000) according to any one of claims 16 to 21, wherein the circuit module is a bridge converter module; and / orwherein the rectifier module (540) is a rectifier bridge comprising a set of transistors (Q21, Q22, Q23, Q24) .23.An apparatus comprising the active snubber (500, 700) according to any one of claims 1 to 15.24.The apparatus according to claim 23,wherein the apparatus is a power source.