Array substrate, display panel, and display apparatus
Patent Information
- Application Number
- PCT/CN2025/084989
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2026-10-01
Smart Images
Figure CN2025084989_01102026_PF_FP_ABST
Abstract
Description
Array substrate, display panel and display device Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology
[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention
[0003] The array substrate, display panel, and display device disclosed herein are specifically designed as follows:
[0004] On one hand, this disclosure provides an array substrate, comprising:
[0005] A substrate, the substrate including a display area;
[0006] Pixel electrodes are arranged in an array in the display area;
[0007] A gate line extends at the row gap of the pixel electrode, the gate line including a groove structure and a bottom surrounding the groove structure;
[0008] The data line extends at the column gaps of the pixel electrodes;
[0009] A transistor, wherein the gate of the transistor is electrically connected to the gate line, the first electrode of the transistor is electrically connected to the data line, and the second electrode of the transistor is electrically connected to the pixel electrode. The second electrode of the transistor includes a notch structure, wherein the orthographic projection of the notch structure on the substrate overlaps with the orthographic projection of the groove structure on the substrate, and the orthographic projection opening of the notch structure on the substrate faces the orthographic projection of the bottom on the substrate.
[0010] In some embodiments, in the array substrate provided in the present disclosure, the gate line further includes a first sidewall portion and a second sidewall portion forming the groove structure, and the orthogonal projection of the second electrode of the transistor on the substrate crosses the orthogonal projection of the groove structure on the substrate and overlaps with the orthogonal projection portions of the first sidewall portion and the second sidewall portion on the substrate.
[0011] In some embodiments, in the array substrate provided in the present disclosure, the second electrode of the transistor includes an electrode portion that overlaps with the first sidewall portion on one side of the notch structure, and a compensation portion that overlaps with the second sidewall portion on the other side of the notch structure.
[0012] In some embodiments, in the array substrate provided in the present disclosure, the first electrode of the transistor includes two U-shaped structures arranged along the column direction, and the adjacent sides of the two U-shaped structures are shared.
[0013] The electrode portion includes two sub-electrode portions, which extend outward from the two U-shaped structures and are connected to each other at the groove structure.
[0014] In some embodiments, in the array substrate provided in the present disclosure, the sub-electrode portion includes a widened portion located outside the U-shaped structure and partially overlapping with the first sidewall portion, and the compensation portion includes two sub-compensation portions extending from the side of the notch structure away from the widened portion to partially overlapping with the second sidewall portion, and the sub-compensation portions and the widened portion are substantially collinear along the row direction.
[0015] In some embodiments, in the array substrate provided in the present disclosure, the sub-electrode portion includes a widened portion located outside the U-shaped structure and partially overlapping with the first sidewall portion, and the compensation portion includes a main body portion extending from the side of the notch structure away from the widened portion to partially overlapping with the second sidewall portion;
[0016] The overlap dimension of the main body portion and the second sidewall portion in the column direction is approximately equal to the sum of the overlap dimensions of the two widened portions and the first sidewall portion in the column direction.
[0017] In some embodiments, in the array substrate provided in the present disclosure, the compensation portion further includes a protrusion located on the side of the main body portion facing the bottom and not overlapping with the second sidewall portion, wherein the size of the protrusion in the column direction is approximately the same as the distance between the two widened portions.
[0018] In some embodiments, the array substrate provided in this disclosure further includes a transition electrode, and the second electrode of the transistor is electrically connected to the pixel electrode through the transition electrode;
[0019] The gate line also includes a first sidewall portion and a second sidewall portion forming the groove structure. The orthographic projection of the second electrode of the transistor on the substrate overlaps with the orthographic projection of the first sidewall portion and the notch structure on the substrate. The orthographic projection of the transition electrode on the substrate overlaps with the orthographic projection of the second sidewall portion on the substrate.
[0020] In some embodiments, the array substrate provided in the present disclosure further includes a first insulating layer located between the data line layer and the gate line layer, and a second insulating layer located between the data line layer and the transition electrode layer.
[0021] The ratio of the overlap width of the transition electrode and the second sidewall portion in the column direction to the overlap width of the second electrode and the first sidewall portion of the transistor in the column direction is approximately equal to the ratio of the thickness of the first insulating layer to the sum of the thicknesses of the first insulating layer and the second insulating layer.
[0022] In some embodiments, the array substrate provided in this disclosure further includes connection lines and compensation lines, the transistor includes a first transistor and a second transistor, and the pixel electrode includes a first pixel electrode and a second pixel electrode; wherein...
[0023] The first pixel electrode is located in the spacing column of the data lines connected to the first transistor, and the connecting line is connected between the first pixel electrode and the second electrode of the first transistor;
[0024] The second pixel electrode is located in the adjacent column of the data line connected to the second transistor, and the compensation line is electrically connected to the second electrode of the second transistor and the second pixel electrode.
[0025] In some embodiments, the array substrate provided in this disclosure further includes a common electrode line, wherein the orthographic projection of the connecting line on the substrate overlaps with the orthographic projection of the common electrode line on the substrate, and the orthographic projection of the compensation line on the substrate overlaps with the orthographic projection of the common electrode line on the substrate.
[0026] In some embodiments, in the array substrate provided in the present disclosure, the first pixel electrode includes a first conductive portion and a first connecting portion protruding from the first conductive portion toward the row gap, and the second pixel electrode includes a second conductive portion and a second connecting portion protruding from the second conductive portion toward the row gap.
[0027] The orthographic projection of the connecting line on the substrate overlaps with the orthographic projections of the first connecting portion and the first conductive portion on the substrate.
[0028] The orthographic projection of the compensation line on the substrate overlaps with the orthographic projections of the second connecting portion and the second conductive portion on the substrate.
[0029] In some embodiments, in the array substrate provided in the present disclosure, the connecting lines, the compensation lines, and the gate lines are on the same layer.
[0030] In some embodiments, in the array substrate provided in the present disclosure, the connecting lines, the compensation lines, and the pixel electrodes are on the same layer.
[0031] In some embodiments, the array substrate provided in the present disclosure further includes a transfer electrode, a first insulating layer located between the data line layer and the gate line layer, and a second insulating layer located between the data line layer and the transfer electrode layer.
[0032] The second electrode of the transistor is electrically connected to the transition electrode through a first sub-via penetrating the second insulating layer, and the pixel electrode is electrically connected to the transition electrode through a second sub-via penetrating the first insulating layer and the second insulating layer. The first sub-via and the second sub-via are integrally formed.
[0033] In some embodiments, in the array substrate provided in the present disclosure, in the row direction, the orthogonal projection of the transition electrode on the substrate extends by more than 3 μm relative to the orthogonal projection of the first sub-via and / or the second sub-via on the substrate.
[0034] In some embodiments, in the array substrate provided in the present disclosure, the orthogonal projection of the gate of the transistor on the substrate is extended by more than 7.5 μm relative to the orthogonal projection of the first electrode of the transistor on the substrate.
[0035] In some embodiments, in the array substrate provided in the present disclosure, the substrate further includes a first non-display area extending along the column direction on at least one of the two sides of the display area;
[0036] The array substrate further includes a first dummy pixel electrode, a first dummy common electrode, and a common electrode bus located in the first non-display area, wherein the first dummy pixel electrode and the first dummy common electrode are electrically connected to the common electrode bus.
[0037] In some embodiments, in the array substrate provided in the present disclosure, the substrate further includes a second non-display area extending along the row direction on at least one side of the display area;
[0038] The array substrate further includes a second dummy pixel electrode, a second dummy common electrode, and a common electrode bus located in the second non-display area. The second dummy pixel electrode is floating, and the second dummy common electrode is electrically connected to the common electrode bus.
[0039] In some embodiments, in the array substrate provided in the present disclosure, two gate lines are provided in the same row spacing.
[0040] On the other hand, this disclosure provides a display panel, including the array substrate provided in the embodiments of this disclosure, and a counter substrate disposed opposite to the array substrate.
[0041] On the other hand, this disclosure provides a display device, including the display panel described above in the embodiments of this disclosure, and a backlight module located on the light-incident side of the display panel. Attached Figure Description
[0042] Figure 1 is a schematic diagram of the connection of 4*14 sub-pixels in the array substrate;
[0043] Figure 2 is an enlarged structural diagram of region Z1 in Figure 1;
[0044] Figure 3 is an enlarged structural diagram of region Z2 in Figure 2;
[0045] Figure 4 is a schematic diagram of the structure in Figure 3 after omitting the common electrode;
[0046] Figure 5 is an enlarged structural diagram of region Z3 in Figure 4;
[0047] Figure 6 is a cross-sectional view along line I-I' in Figure 3;
[0048] Figure 7 is a schematic diagram of the structure of the transparent electrode layer where the pixel electrodes are located in Figure 2;
[0049] Figure 8 is a schematic diagram of the structure of the metal layer where the gate lines are located in Figure 2;
[0050] Figure 9 is a schematic diagram of the active layer in Figure 2;
[0051] Figure 10 is a schematic diagram of the structure of the metal layer where the data line is located in Figure 2;
[0052] Figure 11 is a schematic diagram of the insulating layer where the vias are located in Figure 2;
[0053] Figure 12 is a schematic diagram of the structure of the transparent electrode layer where the common electrode is located in Figure 2;
[0054] Figure 13 shows a parallel technical solution of the embodiment shown in Figure 4;
[0055] Figure 14 is an enlarged structural diagram of region Z4 in Figure 13;
[0056] Figure 15 shows another parallel technical solution of the embodiment shown in Figure 4;
[0057] Figure 16 is an enlarged structural diagram of region Z5 in Figure 15;
[0058] Figure 17 shows another parallel technical solution of the embodiment shown in Figure 4;
[0059] Figure 18 is a schematic diagram of a dummy sub-pixel structure in the first non-display area of the array substrate provided in an embodiment of the present disclosure;
[0060] Figure 19 is a schematic diagram of a dummy sub-pixel structure in the second non-display area of the array substrate provided in an embodiment of the present disclosure;
[0061] Figure 20 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure;
[0062] Figure 21 is a schematic diagram of the structure of the display device provided in an embodiment of this disclosure. Detailed Implementation
[0063] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.
[0064] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.
[0065] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.
[0066] To reduce the number of source ICs and lower chip costs, traditional single-gate pixel driving schemes are gradually being upgraded to dual-gate pixel driving schemes. At the same frequency, the data signal writing time is reduced to about half that of the single-gate driving scheme, and the charging problem of the product is becoming increasingly prominent.
[0067] To address the aforementioned technical problems, this disclosure provides an array substrate. Figure 1 is a schematic diagram of the connection of 4*14 sub-pixels in the array substrate; Figure 2 is an enlarged schematic diagram of the Z1 region in Figure 1; Figure 3 is an enlarged schematic diagram of the Z2 region in Figure 2; Figure 4 is a schematic diagram of the structure in Figure 3 after omitting the common electrode; Figure 5 is an enlarged schematic diagram of the Z3 region in Figure 4; Figure 6 is a cross-sectional view along line I-I' in Figure 3; and Figures 7 to 12 are schematic diagrams of the structures of different film layers in Figure 2. As shown in Figures 1 to 12, the array substrate of this disclosure may include:
[0068] The substrate 101 includes a display area AA. The substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, or plastic.
[0069] The pixel electrodes 102 are arranged in an array in the display area AA; the material of the pixel electrodes 102 can be transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and gallium zinc oxide (GZO).
[0070] Gate lines 103 extend at the row gaps of pixel electrodes 102. Optionally, two gate lines 103 are provided at the same row gap. Gate lines 103 include a groove structure GV and a bottom 1031 surrounding the groove structure GV. In some embodiments, the material of gate lines 103 may include metals such as copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). Gate lines 103 may be a single-layer structure or a multilayer structure. For example, gate lines 103 may be a single-layer structure made of copper.
[0071] Data lines 104 extend at the column gaps of pixel electrodes 102. Optionally, one data line 104 is provided between every two adjacent columns of pixel electrodes 102. In some embodiments, the material of the data line 104 may include metals such as copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The data line 102 may be a single-layer structure or a multilayer structure. For example, the data line 102 may be a single-layer structure made of aluminum.
[0072] Transistor 105 has its gate g electrically connected to gate line 103, its first electrode s electrically connected to data line 104, and its second electrode d electrically connected to pixel electrode 102. The second electrode d of transistor 105 includes a notch structure SF. The orthographic projection of the notch structure SF onto the substrate 101 overlaps with the orthographic projection of the groove structure GV onto the substrate 101. For example, the orthographic projection of the notch structure SF onto the substrate 101 is located within the orthographic projection of the groove structure GV onto the substrate 101. Optionally, the orthographic projection opening of the notch structure SF onto the substrate 101 faces the orthographic projection of the bottom 1031 onto the substrate 101. In some embodiments, transistor 105 can be a P-type transistor or an N-type transistor. The gate g of transistor 104 can be located above and / or below the active layer a. The active layer a material of transistor 104 includes, but is not limited to, amorphous silicon, polycrystalline silicon, indium gallium zinc oxide, etc.
[0073] In the array substrate provided in this embodiment, by providing a notch structure SF on the second electrode d, the distance between the gate line 103 on the opening side of the notch structure SF and the second electrode d on the bottom side of the notch structure SF is relatively large. Combined with C = εS / 4πkD, it can be seen that the lateral capacitance between the second electrode d and the gate line 103 is reduced. Furthermore, when the notch structure SF and the groove structure GV overlap, the second electrode d around the notch structure SF can overlap with the groove structure GV, thus reducing the overlap capacitance between the second electrode d and the gate line 103. Therefore, this disclosure can effectively reduce the load on the second electrode d, thereby improving the charging rate.
[0074] In some embodiments, as shown in FIG5, in the array substrate provided in the present disclosure, the gate line 103 may further include a first sidewall portion 1032 and a second sidewall portion 1033 forming a groove structure GV. Optionally, the first sidewall portion 1032 is shared with the gate g of the transistor 105. The orthogonal projection of the second electrode d of the transistor 105 on the substrate 101 can cross the orthogonal projection of the groove structure GV on the substrate 101 and overlap with the orthogonal projection portions of the first sidewall portion 1032 and the second sidewall portion 1033 on the substrate 101. If an interlayer shift occurs between the layer where the gate line 103 is located and the layer where the data line 104 is located, it will cause a difference in the load of the transistors 105 on the left and right sides of the data line 104. In this disclosure, the second electrode d is extended from the first sidewall portion 1032 to cross the groove structure GV and overlap with the second sidewall portion 1033, which helps to ensure that the load of different transistors 105 is as consistent as possible after the interlayer shift occurs between the layer where the gate line 103 is located and the layer where the data line 104 is located.
[0075] Referring again to Figure 5, in the array substrate provided in this embodiment, the second electrode d of transistor 105 may include an electrode portion d1 that partially overlaps with the first sidewall portion 1032 on one side of the notch structure SF, and a compensation portion d2 that partially overlaps with the second sidewall portion 1033 on the other side of the notch structure SF. Optionally, the overlap size of the compensation portion d2 and the second sidewall portion 1033 along the column direction Y is approximately equal to (for example, within the error range caused by factors such as process and measurement) the overlap size of the electrode portion d1 and the first sidewall portion 1032 along the column direction Y. The overlap size of the compensation portion d2 and the second sidewall portion 1033 along the column direction Y is greater than or equal to the upper limit of interlayer offset. This ensures that the load of transistor 105 remains unchanged before and after the interlayer offset between the layer where gate line 103 is located and the layer where data line 104 is located.
[0076] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 3 to 5, the first electrode s of transistor 105 may include two U-shaped structures arranged along the column direction Y, with adjacent sides of the two U-shaped structures shared; the electrode portion d1 of the second electrode d of transistor 105 may include two sub-electrode portions d11, which extend outward from the two U-shaped structures and are interconnected at the groove structure GV. Using this dual U-shaped transistor is beneficial for improving the charging rate. Optionally, the sub-electrode portion d11 includes a widened portion d11' located outside the U-shaped structure and overlapping with the first sidewall portion 1032. The compensation portion d2 includes two sub-compensation portions d21 extending from the side of the notch structure SF away from the widened portion d11' to overlapping with the second sidewall portion 1033. The sub-compensation portions d21 and the widened portion d11' are approximately collinear along the row direction X (e.g., within the deviation range caused by factors such as process and measurement). In other words, the width a1 of the sub-compensation portion d21 along the column direction Y is approximately the same as the width a2 of the widened portion d11' along the column direction Y (e.g., within the error range caused by factors such as process and measurement). The spacing b1 between the two sub-compensation portions d21 is approximately the same as the spacing b2 between the two widened portions d11', so as to ensure that after the interlayer offset occurs between the layer where the gate line 103 is located and the layer where the data line 104 is located, the loads of different transistors 105 are similar or even the same.
[0077] In some embodiments, FIG13 is a parallel technical solution of the embodiment shown in FIG4, and FIG14 is an enlarged structural schematic diagram of the Z4 region in FIG13. As shown in FIG13 and FIG14, in the array substrate provided in the embodiments of this disclosure, the compensation portion d2 may include a main body portion d22 extending from the side of the notch structure SF away from the widened portion d11' to partially overlap with the second sidewall portion 1033; the overlap size a3 of the main body portion d22 and the second sidewall portion 1033 in the column direction Y is approximately equal to (for example, within the error range caused by factors such as process and measurement) the sum of the overlap sizes 2*a2 of the two widened portions d11' and the first sidewall portion 1032 in the column direction Y, so that when there is an interlayer offset between the layer where the gate line 103 is located and the layer where the data line 104 is located, the load difference of the gate line 103 caused by the movement of the second pole d can be effectively compensated.
[0078] As can be seen, in the embodiments shown in Figures 13 and 14, the two sub-compensation portions d21 of the embodiment shown in Figure 4 are essentially merged into a single main portion d22 to achieve interlayer offset compensation. Referring further to Figures 13 and 14, in the array substrate provided in this embodiment, the compensation portion d2 may further include a protrusion d23 located on the side of the main portion d22 facing the bottom 1031 and not overlapping with the second sidewall portion 1033. The dimension a4 of the protrusion d23 in the column direction Y is approximately the same as the distance b2 between the two widened portions d11' (e.g., within the error range caused by factors such as process and measurement). Since the lateral coupling length between the protrusion d23 and the gate line 103 is small, the load on the gate line 103 can be effectively reduced, which is beneficial for improving the charging rate.
[0079] In some embodiments, FIG15 is another parallel technical solution of the embodiment shown in FIG4, and FIG16 is an enlarged structural schematic diagram of the Z5 region in FIG15. As shown in FIG15 and FIG16, the array substrate provided in the embodiments of this disclosure may further include a transition electrode 106. The second electrode d of transistor 105 is electrically connected to pixel electrode 102 through transition electrode 106. The orthographic projection of the second electrode d of transistor 105 on substrate 101 overlaps with the orthographic projection of the first sidewall portion 1032 and the notch structure SF on substrate 101, but does not overlap with the orthographic projection of the second sidewall portion 1033 on substrate 101. The orthographic projection of transition electrode 106 on substrate 101 overlaps with the orthographic projection of the second sidewall portion 1033 on substrate 101. Thus, the transition electrode 106 replaces the compensation portion d2 to compensate for the load difference caused by interlayer offset.
[0080] In some embodiments, the array substrate provided in this disclosure, as shown in FIG6 and FIG16, may further include a first insulating layer 107 located between the source / drain metal layer SDL where the data line 104 is located and the gate metal layer GTL where the gate line 103 is located, and a second insulating layer 108 located between the source / drain metal layer SDL where the data line 104 is located and the transparent electrode layer 2ITO where the transition electrode 106 is located. Since the transition electrode 106 and the second electrode d of the transistor 105 are offset by the same offset distance relative to the gate line 103 when the source / drain metal layer SDL is offset relative to the gate metal layer GTL, the ratio of the overlap area of the transition electrode 106 and the second sidewall portion 1033 and the overlap area of the second electrode d of the transistor 105 and the first sidewall portion 1032 is the ratio of the overlap width a5 of the transition electrode 106 and the second sidewall portion 1033 in the column direction Y to the overlap width 2*a2 of the second electrode d of the transistor 105 and the first sidewall portion 1032 in the column direction Y. Combining C=εS / 4πkD, a first insulating layer 107 and a second insulating layer 108 are provided between the transition electrode 106 and the second sidewall portion 1033, and a first insulating layer 107 is provided between the second electrode d of the transistor 105 and the first sidewall portion 1032. It can be seen that the ratio of the overlap width a5 of the transition electrode 106 and the second sidewall portion 1033 in the column direction Y to the overlap width 2*a2 of the second electrode d of the transistor 105 and the first sidewall portion 1032 in the column direction Y is approximately equal to the ratio of the thickness h1 of the first insulating layer 107 to the sum of the thickness h1 of the first insulating layer 107 and the thickness of the second insulating layer 108, that is, a5 / (2*a2)≈h1 / (h1+h2). Since the distance b3 between the transition electrode 106 and the bottom 1031 is greater than the distance b4 between the widened portion d11' and the bottom 1031, the lateral capacitance between the transition electrode 106 and the bottom 1031 is smaller compared to the embodiment shown in FIG4, which can effectively reduce the load on the gate line 103 and improve the charging rate.
[0081] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 4 and 5, may further include a connecting line 109 and a compensation line 110. Transistor 105 may include a first transistor TFT1 and a second transistor TFT2. Pixel electrode 102 may include a first pixel electrode P1 and a second pixel electrode P2. The first pixel electrode P1 is located in the spaced column of the data lines 104 connected to the first transistor TFT1, and the connecting line 109 connects the first pixel electrode P1 to the second electrode d of the first transistor TFT1. The second pixel electrode P2 is located in the adjacent column of the data lines 104 connected to the second transistor TFT2, and the compensation line 110 is electrically connected to the second electrode d of the second transistor TFT2 and the second pixel electrode P2. In the pixel architecture of this disclosure, there is a long-connected first pixel electrode P1 and a short-connected second pixel electrode P2. The lateral capacitance of the gate line 103 corresponding to the long-connected first pixel electrode P1 is relatively large, causing the long-connected first pixel electrode P1 and the short-connected second pixel electrode P2 to be pulled differently by the lateral capacitance after charging, resulting in different gray levels at the same voltage, thus causing a head-shaking pattern defect. By increasing the lateral capacitance of the gate line 103 corresponding to the short-connected second pixel electrode P2 through the compensation line 110 extending along the row direction X, the lateral capacitance pull of the long-connected first pixel electrode P1 and the short-connected second pixel electrode P2 after charging is as similar as possible, thereby improving the head-shaking pattern defect.
[0082] In some embodiments, as shown in FIG4 and FIG5, the array substrate provided in the present disclosure may further include a common electrode line 111 disposed at the adjacent column gap of the column gap where the data line 104 is located. The common electrode line 111 may be disposed in the same layer and of the same material as the data line 104. The orthographic projection of the connecting line 109 on the substrate 101 may overlap with the orthographic projection of the common electrode line 111 on the substrate 101, and the orthographic projection of the compensation line 110 on the substrate 101 may also overlap with the orthographic projection of the common electrode line 111 on the substrate 101. The overlap between the connecting line 109 and the common electrode line 111 increases the storage capacitance Cst of the long connected pixels, resulting in a further increase in the head-shaking pattern difference. The present disclosure sets the compensation line 110 and the common electrode line 111 to overlap, which can increase the storage capacitance of the short connected pixels, thereby reducing or even eliminating the storage capacitance difference between the long connected pixels and the short connected pixels, effectively preventing head-shaking pattern defects. Optionally, the compensation line 110 extends 5 μm beyond the common electrode line 111 along the X direction to ensure that the compensation line 110 and the common electrode line 111 still overlap when the source / drain metal layer shifts relative to the gate metal layer.
[0083] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIGS. 3 to 5, the first pixel electrode P1 may include a first conductive portion P11 and a first connecting portion P12 protruding from the first conductive portion P11 toward the row gap; the second pixel electrode P2 includes a second conductive portion P21 and a second connecting portion P22 protruding from the second conductive portion P21 toward the row gap; the orthographic projection of the connecting line 109 on the substrate 101 overlaps with the orthographic projections of the first connecting portion P12 and the first conductive portion P11 on the substrate 101; the compensation line 110 is on the substrate... The orthographic projection on the substrate 101 overlaps with the orthographic projections of the second connecting portion P22 and the second conductive portion P21 on the substrate 101. In other words, the connecting line 109 may include a structure protruding along the column direction Y towards the first pixel electrode P1, which overlaps with the first connecting portion P12 and the portion of the first conductive portion P11 directly connected to the first connecting portion P12. The compensation line 110 may include a structure protruding along the column direction Y towards the second pixel electrode P2, which overlaps with the second connecting portion P22 and the portion of the second conductive portion P21 directly connected to the second connecting portion P22. This allows for a partial wrapping design between the first pixel electrode P1 and the connecting line 109, and also a partial wrapping design between the second pixel electrode P2 and the compensation line 110, effectively preventing the pixel electrode 102 from disconnecting from the connecting line 109 and the compensation line 110 due to interlayer misalignment. Optionally, to ensure a better wrapping effect, the overlap dimensions of the first conductive portion P11 and the connecting line 109 in the row direction X and column direction Y, the overlap dimensions of the first connecting portion P12 and the connecting line 109 in the row direction X and column direction Y, the overlap dimensions of the second conductive portion P21 and the compensation line 110 in the row direction X and column direction Y, and the overlap dimensions of the second connecting portion P22 and the compensation line 110 in the row direction X and column direction Y can all be greater than or equal to 3μm. In some embodiments, the connecting line 109 can be directly contacted and electrically connected to the first pixel electrode P1, and the compensation line 110 can be directly contacted and electrically connected to the second pixel electrode P2. Optionally, the layer where the pixel electrode 102 is located is disposed on the side of the layer where the gate line 103 is located away from the substrate 101.
[0084] In some embodiments, in the array substrate provided in this disclosure, as shown in FIG4, the connecting line 109 and the compensation line 110 can be disposed in the same layer and with the same material as the gate line 103. Alternatively, as shown in FIG17, the connecting line 109 and the compensation line 110 can also be disposed in the same layer and with the same material as the pixel electrode 102. There may be no insulating layer between the pixel electrode 102 and the gate line 103. Since the thickness of the pixel electrode 102 is relatively low, only about one-tenth that of the gate line 103, the facing area of the connecting line 109 and the compensation line 110 in the same layer and with the gate line 103 in the same material and with the pixel electrode 102 in the same thickness direction is much smaller than the facing area of the connecting line 109 and the compensation line 110 in the same layer and with the gate line 103 in the same thickness direction. The lateral capacitance between the connecting line 109 and the compensation line 110 in the same layer and with the gate line 103 in the same material and with the pixel electrode 102 will be greatly reduced, which greatly improves the charging rate.
[0085] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG3 and FIG6, the second electrode d of transistor 105 can be electrically connected to the transfer electrode 106 through the first sub-via V11 penetrating the second insulating layer 108, and the pixel electrode 102 can be electrically connected to the transfer electrode 106 through the second sub-via V12 penetrating the first insulating layer 107 and the second insulating layer 108. Specifically, the connecting line 109 and the compensation line 110 penetrate the second sub-via V12 of the first insulating layer 107 and the second insulating layer 108 and are electrically connected to the transfer electrode 106. The connecting line 109 and the compensation line 110 are then directly contacted and electrically connected to the pixel electrode 102. Optionally, the first sub-via V11 and the second sub-via V12 are integrally formed to constitute a half-via V1, which can improve the fluidity of the alignment liquid PI and improve the uniformity of the alignment film. In some embodiments, in the row direction X, the orthographic projection of the transition electrode 106 on the substrate 101 can be extended by more than 3 μm relative to the orthographic projection of the first sub-via V11 and / or the second sub-via V12 on the substrate 101. This is equivalent to the orthographic projection of the transition electrode 106 on the substrate 101 being extended by more than 3 μm to the left and / or to the right relative to the orthographic projection of the half-via V1 on the substrate 101. This ensures that when the transition electrode 106 breaks at the via junction, the current on the transistor 105 can still reach the connection line 109 and the compensation line 110 through the transition electrode 110 on the side of the first sub-via V11 away from the second sub-via V12 and / or the side of the second sub-via V12 away from the first sub-via V11.
[0086] In some embodiments, in the array substrate provided in the present disclosure, the orthogonal projection of the gate g of transistor 105 on the substrate 101 can be extended by more than 7.5 μm relative to the orthogonal projection of the first electrode s of transistor 105 on the substrate 101. This can accommodate high backlight brightness requirements and effectively prevent backlight diffraction to the active layer, thereby causing a degradation in the characteristics of transistor 105.
[0087] In some embodiments, FIG18 is a schematic diagram of a dummy pixel structure in the left border GL or right border GR of the array substrate of this disclosure (the left and right borders are collectively referred to as the first non-display area in this disclosure). As shown in FIG18, at least one dummy pixel in the first non-display area of this disclosure may include a first dummy pixel electrode 112 and a first dummy common electrode 113, and the first non-display area may be provided with a common electrode bus 114. The first dummy pixel electrode 112 and the first dummy common electrode 113 may both be electrically connected to the common electrode bus 114. Optionally, the first dummy pixel electrode 112 is directly contacted and electrically connected to the protrusion of the common electrode bus 114 toward the center region of the pixel electrode, and the first dummy common electrode 113 is electrically connected to the common electrode bus 114 through a third via V3 penetrating the first insulating layer 107 and the second insulating layer 108. Since the first data line 104 and the last data line 104 of this disclosure only connect to half of the sub-pixels of the display area AA, the other half are connected to the dummy sub-pixels on the left and right sides of the display area AA. Since there are lateral capacitances between the data line 104 and the left and right pixel electrodes 102 and the common electrode 116 within the display area AA, it is necessary to connect the first dummy pixel electrode 112 and the first dummy common electrode 113 on the left and / or right sides of the display area AA to the common electrode bus 114. This ensures that the lateral capacitance between the first data line 104 and / or the last data line 104 and the left and right transparent electrodes is the same as that between the data line 104 within the display area AA, ensuring display uniformity. Furthermore, since the first dummy pixel electrode 112 and the second dummy common electrode 113 are both connected to the common electrode bus 114, there is no voltage difference between the first dummy pixel electrode 112 and the second dummy common electrode 113, and the dummy sub-pixels will not be lit, eliminating the risk of edge lighting.
[0088] In some embodiments, FIG19 is a schematic diagram of a dummy subpixel structure in the upper frame DPO or lower frame DP (hereinafter referred to as the upper and lower frames as the second non-display area) of the array substrate of this disclosure. As shown in FIG19, at least one dummy subpixel in the second non-display area of this disclosure may include a second dummy pixel electrode 115 and a second dummy common electrode 116, and the second non-display area may be provided with a common electrode bus 114. The second dummy pixel electrode 115 is floating, and the second dummy common electrode 116 is electrically connected to the common electrode bus 114. Optionally, the second dummy common electrode 116 is electrically connected to the common electrode bus 114 through a fourth via V4 penetrating the first insulating layer 107 and the second insulating layer 108. Regardless of whether voltage is applied to the transparent electrode, the dummy sub-pixels on the upper and lower sides (i.e., the DP and DPO sides) of the display area AA ensure that the second dummy pixel electrode 115 and the second dummy common electrode 116 remain completely consistent with the display area AA. Therefore, only the second dummy common electrode 116 is connected to the common electrode bus 114 to improve the uniformity of the common voltage signal. The second dummy pixel electrode 115 is designed to float, so that no lateral capacitance is generated between it and the data line 103, reducing the load on the data line 103 and improving the charging rate. Optionally, as shown in FIG19, in order to reduce the load on the data line 103, the present disclosure may also provide a partially exposed cutout structure OW of the common electrode bus 114 on the upper and lower sides.
[0089] In some embodiments, in the array substrate provided in this disclosure, as shown in Figures 2, 9, 10, and 12, the data line 104 can be fabricated using the same mask as the active layer a. This results in the active layer a having a similar pattern SD' to the layer containing the data line 104, and due to exposure diffraction, the SD' pattern extends outwards compared to the pattern in the layer containing the data line 104. The common electrode line 111 can be disposed in the same layer and with the same material as the data line 103, and the common electrode line 111 is electrically connected to the common electrode 116 through a second via V2 penetrating the second insulating layer 108. Other essential components of the array substrate are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0090] Based on the same inventive concept, this disclosure provides a display panel, as shown in FIG20, including an array substrate 001 and a counter substrate 002 placed opposite each other. The array substrate 001 is the array substrate 001 provided in this disclosure embodiment, and the counter substrate 002 may include a black matrix, red color resist, green color resist, blue color resist, and spacers. Since the principle by which this display panel solves the problem is similar to that of the array substrate described above, the implementation of this display panel can refer to the embodiments of the array substrate described above, and repeated details will not be elaborated further. In some embodiments, the black matrix, red color resist, green color resist, blue color resist, and spacers may also be disposed on the array substrate 001; this disclosure does not specifically limit this.
[0091] In some embodiments, as shown in FIG20, the display panel provided in this disclosure may further include a liquid crystal layer 003 between an array substrate 001 and a counter substrate 002, a first polarizer 004 on the side of the array substrate 001 away from the counter substrate 002, and a second polarizer 005 on the side of the counter substrate 002 away from the array substrate 001, wherein the polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0092] Based on the same inventive concept, this disclosure provides a display device, as shown in FIG21, including the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature light-emitting diodes (Mini LEDs, Micro LEDs, etc.).
[0093] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.
[0094] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.
[0095] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0096] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.
Claims
1. An array substrate, wherein, include: A substrate, the substrate including a display area; Pixel electrodes are arranged in an array in the display area; A gate line extends at the row gap of the pixel electrode, the gate line including a groove structure and a bottom surrounding the groove structure; The data line extends at the column gaps of the pixel electrodes; A transistor, wherein the gate of the transistor is electrically connected to the gate line, the first electrode of the transistor is electrically connected to the data line, and the second electrode of the transistor is electrically connected to the pixel electrode. The second electrode of the transistor includes a notch structure, wherein the orthographic projection of the notch structure on the substrate overlaps with the orthographic projection of the groove structure on the substrate, and the orthographic projection opening of the notch structure on the substrate faces the orthographic projection of the bottom on the substrate.
2. The array substrate as claimed in claim 1, wherein, The gate line also includes a first sidewall portion and a second sidewall portion that form the groove structure. The orthographic projection of the second electrode of the transistor on the substrate crosses the orthographic projection of the groove structure on the substrate and overlaps with the orthographic projection portions of the first sidewall portion and the second sidewall portion on the substrate.
3. The array substrate as described in claim 2, wherein, The second electrode of the transistor includes an electrode portion that overlaps with the first sidewall portion on one side of the notch structure, and a compensation portion that overlaps with the second sidewall portion on the other side of the notch structure.
4. The array substrate as claimed in claim 3, wherein, The first electrode of the transistor includes two U-shaped structures arranged along the column direction, and the adjacent sides of the two U-shaped structures are shared. The electrode portion includes two sub-electrode portions, which extend outward from the two U-shaped structures and are connected to each other at the groove structure.
5. The array substrate as claimed in claim 4, wherein, The sub-electrode portion includes a widened portion located outside the U-shaped structure and overlapping with the first sidewall portion. The compensation portion includes two sub-compensation portions extending from the side of the notch structure away from the widened portion to overlap with the second sidewall portion. The sub-compensation portions and the widened portion are substantially collinear along the direction of travel.
6. The array substrate as claimed in claim 4, wherein, The sub-electrode portion includes a widened portion located outside the U-shaped structure and partially overlapping with the first sidewall portion, and the compensation portion includes a main body portion extending from the side of the notch structure away from the widened portion to partially overlapping with the second sidewall portion; The overlap dimension of the main body portion and the second sidewall portion in the column direction is approximately equal to the sum of the overlap dimensions of the two widened portions and the first sidewall portion in the column direction.
7. The array substrate as claimed in claim 6, wherein, The compensation portion further includes a protrusion located on the side of the main body portion facing the bottom and not overlapping with the second sidewall portion, the size of the protrusion in the column direction being approximately the same as the distance between the two widened portions.
8. The array substrate as claimed in claim 1, wherein, It also includes a transition electrode, through which the second electrode of the transistor is electrically connected to the pixel electrode; The gate line also includes a first sidewall portion and a second sidewall portion forming the groove structure. The orthographic projection of the second electrode of the transistor on the substrate overlaps with the orthographic projection of the first sidewall portion and the notch structure on the substrate. The orthographic projection of the transition electrode on the substrate overlaps with the orthographic projection of the second sidewall portion on the substrate.
9. The array substrate as claimed in claim 8, wherein, It also includes a first insulating layer located between the data line layer and the gate line layer, and a second insulating layer located between the data line layer and the transition electrode layer; The ratio of the overlap width of the transition electrode and the second sidewall portion in the column direction to the overlap width of the second electrode and the first sidewall portion of the transistor in the column direction is approximately equal to the ratio of the thickness of the first insulating layer to the sum of the thicknesses of the first insulating layer and the second insulating layer.
10. The array substrate according to any one of claims 1 to 9, wherein, It also includes connecting lines and compensation lines; the transistor includes a first transistor and a second transistor; the pixel electrode includes a first pixel electrode and a second pixel electrode; wherein, The first pixel electrode is located in the spacing column of the data lines connected to the first transistor, and the connecting line is connected between the first pixel electrode and the second electrode of the first transistor; The second pixel electrode is located in the adjacent column of the data line connected to the second transistor, and the compensation line is electrically connected to the second electrode of the second transistor and the second pixel electrode.
11. The array substrate as claimed in claim 10, wherein, It also includes a common electrode line, wherein the orthographic projection of the connecting line on the substrate overlaps with the orthographic projection of the common electrode line on the substrate, and the orthographic projection of the compensation line on the substrate overlaps with the orthographic projection of the common electrode line on the substrate.
12. The array substrate as claimed in claim 10 or 11, wherein, The first pixel electrode includes a first conductive portion and a first connecting portion protruding from the first conductive portion toward the row gap; the second pixel electrode includes a second conductive portion and a second connecting portion protruding from the second conductive portion toward the row gap. The orthographic projection of the connecting line on the substrate overlaps with the orthographic projections of the first connecting portion and the first conductive portion on the substrate. The orthographic projection of the compensation line on the substrate overlaps with the orthographic projections of the second connecting portion and the second conductive portion on the substrate.
13. The array substrate according to any one of claims 10 to 12, wherein, The connecting line, the compensation line, and the gate line are on the same layer.
14. The array substrate according to any one of claims 10 to 13, wherein, The connecting line, the compensation line, and the pixel electrode are on the same layer.
15. The array substrate according to any one of claims 1 to 14, wherein, It also includes a transition electrode, a first insulating layer located between the data line layer and the gate line layer, and a second insulating layer located between the data line layer and the transition electrode layer; The second electrode of the transistor is electrically connected to the transition electrode through a first sub-via penetrating the second insulating layer, and the pixel electrode is electrically connected to the transition electrode through a second sub-via penetrating the first insulating layer and the second insulating layer. The first sub-via and the second sub-via are integrally formed.
16. The array substrate as claimed in claim 15, wherein, In the row direction, the orthogonal projection of the adapter electrode on the substrate extends by more than 3 μm relative to the orthogonal projection of the first sub-via and / or the second sub-via on the substrate.
17. The array substrate according to any one of claims 1 to 16, wherein, The orthogonal projection of the gate of the transistor onto the substrate is at least 7.5 μm longer than the orthogonal projection of the first electrode of the transistor onto the substrate.
18. The array substrate according to any one of claims 1 to 17, wherein, The substrate further includes a first non-display area extending along the column direction on at least one of the two sides of the display area; The array substrate further includes a first dummy pixel electrode, a first dummy common electrode, and a common electrode bus located in the first non-display area, wherein the first dummy pixel electrode and the first dummy common electrode are electrically connected to the common electrode bus.
19. The array substrate according to any one of claims 1 to 18, wherein, The substrate further includes a second non-display area extending along a row direction on at least one of the two sides of the display area; The array substrate further includes a second dummy pixel electrode, a second dummy common electrode, and a common electrode bus located in the second non-display area. The second dummy pixel electrode is floating, and the second dummy common electrode is electrically connected to the common electrode bus.
20. The array substrate according to any one of claims 1 to 19, wherein, Two grid lines are provided in the same row.
21. A display panel, wherein, It includes the array substrate as described in any one of claims 1 to 20, and the opposing substrate positioned opposite the array substrate.
22. A display device, wherein, It includes the display panel as described in claim 21, and a backlight module located on the light-incident side of the display panel.