Detection panel and flat panel detector
Patent Information
- Application Number
- PCT/CN2025/085062
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2026-10-01
Smart Images
Figure CN2025085062_01102026_PF_FP_ABST
Abstract
Description
A detection panel and flat panel detector Technical Field
[0001] This disclosure relates to the field of photoelectric detection technology, and in particular to a detection panel and a flat panel detector. Background Technology
[0002] Flat X-ray Panel Detectors (FPXDs) based on thin-film transistor (TFT) technology are crucial components in digital imaging technology. Due to their advantages such as fast imaging speed, good spatial and density resolution, high signal-to-noise ratio, and direct digital output, they are widely used in medical imaging (such as chest X-rays), industrial inspection (such as metal flaw detection), security inspection, and air transport.
[0003] X-ray flat panel detectors mainly consist of thin-film transistors (TFTs) and photodiodes (PINs). Under X-ray irradiation, the scintillator layer or phosphor layer of the indirect conversion type X-ray flat panel detector converts X-ray photons into visible light. Then, under the action of the PIN, the visible light is converted into an electrical signal. Finally, the electrical signal is read by the thin-film transistor and output to obtain the displayed image. Summary of the Invention
[0004] This disclosure provides a detection panel and a flat panel detector, the specific solutions of which are as follows:
[0005] This disclosure provides a detection panel, comprising:
[0006] A substrate includes a probe region and a peripheral region located around the probe region, the peripheral region including a first peripheral region, the first peripheral region including a first bonding region;
[0007] Multiple first pins are located on one side of the substrate and within the first bonding region;
[0008] Multiple read lines are located on one side of the substrate and in the detection area, and each read line extends to the first bonding area and is electrically connected to the corresponding first pin;
[0009] Multiple first electrostatic protection circuits are located on the side of the first binding area away from the detection area;
[0010] A first electrostatic discharge structure is located on one side of the substrate and on the side of the first electrostatic protection circuit away from the first bonding area and surrounding the detection area. At least one of the first electrostatic protection circuits is electrically connected between the corresponding first pin and the first electrostatic discharge structure.
[0011] In one possible implementation, in the detection panel provided in the embodiments of this disclosure, the first electrostatic protection circuit includes a first transistor and a second transistor. The gate and drain of the first transistor and the source of the second transistor are electrically connected to the corresponding first pins. The source of the first transistor and the gate and drain of the second transistor are both electrically connected to the first electrostatic discharge structure.
[0012] In one possible implementation, the detection panel provided in the embodiments of this disclosure further includes: a plurality of second electrostatic discharge protection circuits located between the detection area and the first binding area, and a second electrostatic discharge structure located between the second electrostatic discharge protection circuits and the first binding area and disposed around the detection area;
[0013] At least one of the second electrostatic protection circuits is electrically connected between the corresponding read line and the second electrostatic discharge structure.
[0014] In one possible implementation, in the detection panel provided in the embodiments of this disclosure, the structure of the second electrostatic protection circuit is the same as that of the first electrostatic protection circuit.
[0015] In one possible implementation, in the detection panel provided in the embodiments of this disclosure, the peripheral area further includes a second peripheral area disposed opposite to the first peripheral area, and the reading line extends to the second peripheral area;
[0016] The flat panel detector also includes a plurality of third electrostatic protection circuits located in the second peripheral area and between the second electrostatic discharge structure and the detection area, at least one of the third electrostatic protection circuits being electrically connected between the corresponding reading line and the second electrostatic discharge structure.
[0017] In one possible implementation, in the detection panel provided in the embodiments of this disclosure, the structure of the third electrostatic protection circuit is the same as that of the first electrostatic protection circuit.
[0018] In one possible implementation, in the detection panel provided in the embodiments of this disclosure, the peripheral area further includes a third peripheral area disposed adjacent to the first peripheral area, the third peripheral area including a second binding area located between the detection area and the first electrostatic discharge structure, the second binding area including a plurality of second pins;
[0019] The flat panel detector further includes: multiple scan lines located in the detection area and intersecting with the read lines, and multiple fourth electrostatic protection circuits located between the second binding area and the first electrostatic discharge structure;
[0020] The scan line extends to the second bonding area and is electrically connected to the corresponding second pin, and at least one of the fourth electrostatic protection circuits is electrically connected between the corresponding second pin and the first electrostatic discharge structure.
[0021] In one possible implementation, the detection panel provided in the embodiments of this disclosure further includes a plurality of fifth electrostatic protection circuits located between the second binding area and the detection area, and the second electrostatic discharge structure is also located between the detection area and the fifth electrostatic protection circuits;
[0022] It also includes a third electrostatic discharge structure located between the fifth electrostatic protection circuit and the second bonding area and surrounding the second electrostatic discharge structure;
[0023] At least one of the fifth electrostatic protection circuits is electrically connected between the corresponding scan line and the third electrostatic discharge structure.
[0024] In one possible implementation, in the detection panel provided in the embodiments of this disclosure, the peripheral area further includes a fourth peripheral area disposed opposite to the third peripheral area, and the scan line extends to the fourth peripheral area;
[0025] The flat panel detector also includes a plurality of sixth electrostatic discharge protection circuits located in the fourth peripheral area and between the second electrostatic discharge structure and the third electrostatic discharge structure, at least one of the sixth electrostatic discharge protection circuits being electrically connected between the corresponding scan line and the third electrostatic discharge structure.
[0026] In one possible implementation, in the detection panel provided in the embodiments of this disclosure, the third electrostatic discharge structure is further located between the second electrostatic discharge structure and the first binding area, and the first electrostatic discharge structure is arranged around the third electrostatic discharge structure.
[0027] In one possible implementation, the detection panel provided in the embodiments of this disclosure further includes a plurality of fifth electrostatic discharge protection circuits located between the second binding area and the detection area, and the second electrostatic discharge structure is also located between the fifth electrostatic discharge protection circuits and the second binding area, and at least one of the fifth electrostatic discharge protection circuits is electrically connected between the corresponding scan line and the second electrostatic discharge structure.
[0028] In one possible implementation, in the detection panel provided in the embodiments of this disclosure, the peripheral area further includes a fourth peripheral area disposed opposite to the third peripheral area, and the scan line extends to the fourth peripheral area;
[0029] The flat panel detector also includes a plurality of sixth electrostatic protection circuits located in the fourth peripheral region and between the second electrostatic discharge structure and the detection region, at least one of the sixth electrostatic protection circuits being electrically connected between the corresponding scan line and the second electrostatic discharge structure.
[0030] In one possible implementation, in the detection panel provided in the embodiments of this disclosure, the first electrostatic discharge structure is arranged around the second electrostatic discharge structure.
[0031] In one possible implementation, in the detection panel provided in the embodiments of this disclosure, the structures of the fourth electrostatic protection circuit, the fifth electrostatic protection circuit, and the sixth electrostatic protection circuit are all the same as the structure of the first electrostatic protection circuit.
[0032] In one possible implementation, in the detection panel provided in the embodiments of this disclosure, the first binding area further includes a third pin, the second binding area further includes a fourth pin, and each electrostatic discharge structure is electrically connected to at least one of the third pin and the fourth pin.
[0033] In one possible implementation, in the detection panel provided in the embodiments of this disclosure, the peripheral area further includes a probe electrode, and each electrostatic discharge structure is electrically connected to the probe electrode.
[0034] In one possible implementation, the detection panel provided in this embodiment further includes: multiple bias voltage lines located in the detection area, and a bias voltage bus located in the peripheral area and surrounding the detection area; the bias voltage lines are electrically connected to the bias voltage bus.
[0035] The bias voltage bus is located between the overall structure consisting of each electrostatic protection circuit and each electrostatic discharge structure and the detection area.
[0036] In one possible implementation, the detection panel provided in the embodiments of this disclosure includes a first metal layer, an active layer, a second metal layer, a third metal layer and a fourth metal layer sequentially stacked along a direction away from the substrate. The first metal layer includes the gate, the second metal layer includes the source and the drain, the third metal layer includes a first transition portion and a second transition portion, and the fourth metal layer includes a light-shielding portion.
[0037] Wherein, the orthogonal projection of the light-shielding part on the substrate covers the orthogonal projection of the active layers of the first transistor and the second transistor on the substrate, the first adapter is electrically connected to the gate and drain of the first transistor, the second adapter is electrically connected to the gate and drain of the second transistor, and the light-shielding part is electrically connected to the second adapter.
[0038] In one possible implementation, in the detection panel provided in the embodiments of this disclosure, each electrostatic discharge structure is located in at least one of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer.
[0039] In one possible implementation, the detection panel provided in the embodiments of this disclosure further includes: a first insulating layer located between the first metal layer and the active layer, a second insulating layer located between the second metal layer and the third metal layer, a third insulating layer located between the third metal layer and the fourth metal layer, a planarization layer located between the third insulating layer and the fourth metal layer, and a fourth insulating layer located between the planarization layer and the fourth metal layer.
[0040] The second adapter is electrically connected to the gate of the second transistor through a via penetrating the first insulating layer and the second insulating layer. The second adapter is electrically connected to the drain of the second transistor through a via penetrating the second insulating layer. The light-shielding part is electrically connected to the second adapter through a via penetrating the fourth insulating layer, the planarization layer and the third insulating layer.
[0041] Accordingly, this disclosure also provides a flat panel detector, which uses the detection panel described in any of the above embodiments of this disclosure for electrostatic discharge protection during the manufacturing process, wherein the first electrostatic discharge protection circuit and the first pin in the flat panel detector are disconnected.
[0042] In one possible implementation, the flat panel detector provided in the embodiments of this disclosure further includes a second electrostatic discharge (ESD) protection circuit, which is disconnected from the reading line.
[0043] In one possible implementation, the flat panel detector provided in the embodiments of this disclosure further includes a first lead, the first lead including a first portion electrically connected to the read line and a second portion electrically connected to the second electrostatic protection circuit, the first portion and the second portion being disconnected.
[0044] In one possible implementation, the flat panel detector provided in the embodiments of this disclosure further includes a third electrostatic discharge (ESD) protection circuit, which is disconnected from the reading line. Attached Figure Description
[0045] Figure 1 is a top view of a detection panel provided in an embodiment of this disclosure;
[0046] Figure 2 is a schematic diagram of the equivalent circuit structure of a pixel P in Figure 1;
[0047] Figure 3 is a schematic diagram of the planar structure of a pixel P in Figure 1;
[0048] Figure 4 is a cross-sectional view of a pixel P in Figure 3 along the CC' direction;
[0049] Figure 5 is a schematic diagram of an equivalent circuit corresponding to the detection area AA and the surrounding area in Figure 1;
[0050] Figure 6 is a partially enlarged schematic diagram of Figure 5;
[0051] Figure 7 shows a layout structure of the local detection area AA and the local third peripheral area B3 in Figure 5;
[0052] Figure 8 shows another layout structure of the local detection area AA and the local third peripheral area B3 in Figure 5;
[0053] Figure 9 is another equivalent circuit diagram corresponding to the detection area AA and the surrounding area in Figure 1;
[0054] Figure 10 is another equivalent circuit diagram corresponding to the detection area AA and the surrounding area in Figure 1;
[0055] Figure 11 is another equivalent circuit diagram corresponding to the detection area AA and the surrounding area in Figure 1;
[0056] Figure 12 is another equivalent circuit diagram corresponding to the detection area AA and the surrounding area in Figure 1;
[0057] Figure 13 is another equivalent circuit diagram corresponding to the detection area AA and the surrounding area in Figure 1;
[0058] Figure 14 shows the structural layout within the dashed box E1 in Figure 12;
[0059] Figure 15 shows the structural layout within the dashed box E2 in Figure 14;
[0060] Figure 16 shows the structural layout within the dashed box F1 in Figure 12;
[0061] Figure 17 shows the structural layout within the dashed box F2 in Figure 16;
[0062] Figure 18 is a schematic diagram of the cross section along the AA' direction in Figure 15;
[0063] Figure 19 is a schematic diagram of the cross section along the BB' direction in Figure 15;
[0064] Figure 20 is a schematic diagram of the structure of a flat panel detector provided in an embodiment of this disclosure;
[0065] Figure 21 is a schematic diagram of another flat panel detector provided in an embodiment of this disclosure;
[0066] Figure 22 shows the structural layout within the dashed box H1 in Figure 21;
[0067] Figure 23 shows the structural layout within the dashed box H2 in Figure 21. Detailed Implementation
[0068] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0069] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.
[0070] The specific implementation methods of the detection panel and flat panel detector provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The thickness and shape of each film layer in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
[0071] This disclosure provides a detection panel, as shown in FIG1, including a substrate 1. The substrate 1 includes a detection area AA and a peripheral area located around the detection area AA. The detection area AA includes multiple scan lines GL (Gate Line) and multiple read lines DL (Data Line). The scan lines GL and read lines DL are insulated and intersecting to define multiple pixels P. As shown in FIG2 and FIG3, FIG2 is a schematic diagram of the equivalent circuit structure of a pixel P in FIG1, and FIG3 is a schematic diagram of the planar structure of a pixel P in FIG1. Each pixel P includes a thin film transistor 2 and a photoelectric conversion device 3 disposed on the substrate 1. The gate G of the thin film transistor 2 is electrically connected to the scan line GL, which is used to control the opening and closing of the thin film transistor 2. The drain D of the thin film transistor 2 is electrically connected to the read line DL for reading the photogenerated carriers generated in the pixel P. The source S of the thin film transistor 2 is electrically connected to the bottom electrode 31 of the photoelectric conversion device 3. The bias voltage line BL (Bias) is also present. The thin-film transistor 2 (TFT-2) is electrically connected to the top electrode 32 of the photoelectric conversion device 3 and provides a negative bias voltage, enabling the photoelectric conversion device 3 to operate in a reverse-biased state where photoelectric conversion can occur. The TFT-2 controls the switching of the entire pixel. When the TFT-2 is turned on, the carriers generated by the photoelectric effect accumulated in the photoelectric conversion device 3 in pixel p are detected and read by the readout IC (ROIC) connected to the readout line DL. When the TFT-2 is turned off, the photoelectric conversion device 3 is illuminated and continues to undergo photoelectric conversion. The photogenerated carriers are accumulated through the capacitance formed between the top electrode 32 and the bottom electrode 31 of the photoelectric conversion device 3, waiting to be released through the readout line DL when the TFT-2 is turned on.
[0072] As shown in Figure 4, which is a cross-sectional view of a pixel P in Figure 3 along the CC' direction, the detection panel provided in this embodiment includes: a first metal layer 4, an active layer Act, a second metal layer 5, a third metal layer 6 and a fourth metal layer 7 sequentially stacked along a direction away from the substrate 1; a first insulating layer 8 located between the first metal layer 4 and the active layer Act; a second insulating layer 9 located between the second metal layer 5 and the third metal layer 6; a third insulating layer 11 located between the third metal layer 6 and the fourth metal layer 7; a planarization layer 12 located between the third insulating layer 11 and the fourth metal layer 7; a fourth insulating layer 13 located between the planarization layer 12 and the fourth metal layer 7; a semiconductor layer 14 located between the third metal layer 6 and the third insulating layer 11; a transparent conductive layer 15 located between the semiconductor layer 14 and the third insulating layer 11; and a fifth insulating layer 16 located on the side of the fourth metal layer 7 away from the substrate 1.
[0073] The first metal layer 4 can be a gate metal layer, mainly used to form the gate G of the thin film transistor 2, the scan line GL electrically connected to the gate G, etc.; the second metal layer 5 can be a source-drain metal layer (SD), mainly used to form the source S, drain D of the thin film transistor 2, the read line DL electrically connected to the drain D, etc.; the third metal layer 6 is mainly used to form the bottom electrode 31 of the photoelectric conversion device 3, etc.; the fourth metal layer 7 can be a light-shielding metal layer (LS), mainly used to form the bias voltage line BL, the light-shielding part, etc.; the semiconductor layer 14 includes the photoelectric conversion layer 33 of the photoelectric conversion device 3, and the transparent conductive layer 15 includes the top electrode 32 of the photoelectric conversion device 3.
[0074] Optionally, the materials of the first metal layer 4, the second metal layer 5 and the third metal layer 6 may include molybdenum, aluminum, silver, copper, titanium, platinum, tungsten, tantalum, tantalum nitride, their alloys and combinations thereof or other suitable materials; the material of the transparent conductive layer 14 may include indium tin oxide (ITO) or indium zinc oxide (IZO) or other suitable transparent materials; the material of the fourth metal layer 7 may include copper, silver, etc.
[0075] Optionally, the materials of the first insulating layer 8, the second insulating layer 9, the third insulating layer 11, the fourth insulating layer 13, and the fifth insulating layer 16 can be inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc.
[0076] Optionally, the material of the planarization layer 12 is generally an organic resin.
[0077] Optionally, the photoelectric conversion layer 33 can have a PIN structure, which includes an N-type semiconductor layer with N-type impurities, an intrinsic semiconductor layer without impurities, and a P-type semiconductor layer with P-type impurities, sequentially stacked on the bottom electrode 31. The photoelectric conversion layer 33 can convert optical signals into electrical signals, and transmit the electrical signals to the thin-film transistor 2 through the bottom electrode 31, and then convert them into image signals after being released through the readout line DL.
[0078] Optionally, the substrate 1 can be a flexible substrate, such as a plastic substrate with excellent heat resistance and durability made of polyvinyl ether phthalate, polyethylene naphthalate, polycarbonate, polyaryl compounds, polyetherimide, polyethersulfone or polyimide; or it can be a rigid substrate, such as a glass substrate, which is not limited here.
[0079] Optionally, the active layer Act material of the thin film transistor 2 can be a-Si or indium gallium zinc oxide (IGZO), and the thin film transistor 2 can be a bottom gate structure as shown in Figure 4, or of course, a top gate structure.
[0080] As can be seen from the above, flat panel detectors are a type of photoelectric conversion and reading device based on a-Si or IGZO TFT technology. During the manufacturing process, there is a risk of ESD (Electro-Static Discharge), which can cause various point or line defects in the detection area AA. If the various point or line defects are severe, they will affect the quality of image acquisition and cause the product to be scrapped.
[0081] Traditional flat panel detectors typically only have ESD protection structures on the scan line GL, but not on the readout line DL. This is because the ROIC, electrically connected to the readout line DL in a flat panel detector, identifies the different photoelectric signals (charge or current signals) at different pixels P in the detection area AA. In other words, the ROIC passively receives and reflects the working state of the flat panel detector. Since the ESD protection structure is usually formed by connecting multiple TFTs, when there is a certain voltage difference between the source and drain of a TFT, the TFT can easily generate a considerable current of a certain magnitude. For a flat panel detector, its ROIC is a current / charge readout IC, so the above current will significantly affect the ROIC's reading of the photoelectric signal of pixel P, interfering with the acquisition of normal image information. Therefore, flat panel detectors usually do not have ESD protection structures at the end of the readout line DL.
[0082] However, since traditional flat panel detectors do not have ESD protection structures on their read lines (DL), the risk of read line defects caused by process ESD is higher than that of scan line defects (GL) in module manufacturing processes such as cutting, IC integration on FPC (IC COF bonding), and photoelectric conversion material integration. This is detrimental to product production costs and yield.
[0083] Therefore, in order to address the risk of read line DL defects caused by process ESD as described above, this disclosure is presented as shown in Figures 1 and 5. Figure 5 is a schematic diagram of the equivalent circuit corresponding to the probe area AA and the peripheral area in Figure 1. The peripheral area includes: a first peripheral area B1, a second peripheral area B2 disposed opposite to the first peripheral area B1, a third peripheral area B3 disposed adjacent to the first peripheral area B1, and a fourth peripheral area B4 disposed opposite to the third peripheral area B3. The first peripheral area B1 includes a first bonding area BD1, and the first bonding area BD1 has multiple first pins 10. Each read line DL of the probe area AA extends to the first bonding area BD1 and is electrically connected to the corresponding first pin 10. The first pin 10 is used to bond with an external drive circuit (ROIC) and provide an operating voltage (Vref) to the read line DL through the ROIC.
[0084] As shown in Figure 5, the detection panel provided in this embodiment further includes: a plurality of first electrostatic discharge protection circuits ESD1 located on the side of the first binding area BD1 away from the detection area AA, and a first electrostatic discharge structure 100 located on the side of the first electrostatic discharge protection circuit ESD1 away from the first binding area BD1 and surrounding the detection area AA, wherein each first electrostatic discharge protection circuit ESD1 is electrically connected between the corresponding first pin 10 and the first electrostatic discharge structure 100.
[0085] The detection panel provided in this embodiment of the present disclosure provides a first electrostatic discharge protection circuit ESD1 between the first pin 10 electrically connected to the read line DL and the first electrostatic discharge structure 100. Since the side of the first pin furthest from the substrate 1 is generally metal, it is easier to conduct static electricity into the pixel area. Thus, when a large electrostatic voltage accumulates on the read line DL, the first electrostatic discharge protection circuit ESD1 designed in this disclosure can conduct the large current generated by the static electricity through the first electrostatic discharge structure 100, thereby protecting the AA pixel in the detection area.
[0086] In some embodiments, in the detection panel provided in this disclosure, as shown in FIG5 and FIG6, FIG6 is a partially enlarged schematic diagram of FIG5, the first electrostatic discharge protection circuit ESD1 may include a first transistor T1 and a second transistor T2. The gate G and drain D of the first transistor T1 and the source S of the second transistor T2 are electrically connected to the corresponding first pin 10. The source S of the first transistor T1 and the gate G and drain D of the second transistor T2 are both electrically connected to the first electrostatic discharge structure 100. The first electrostatic discharge structure 100 is configured such that no voltage is applied during the module manufacturing process of the detection panel, but the same working voltage (Vref) as that on the readout line DL is applied when image detection is performed after each stage of the module manufacturing process.
[0087] Specifically, the first transistor T1 and the second transistor T2 are made of the same material as the thin film transistor 2 in the aforementioned pixel region P, which has the same function. That is, the first transistor T1 and the second transistor T2 are manufactured using the same process as the thin film transistor 2 in the pixel region P, without the need for additional processes or development costs.
[0088] It should be noted that the structure of the first electrostatic discharge protection circuit ESD1 is not limited to the first transistor T1 and the second transistor T2 mentioned above. Any structure in the art that can perform electrostatic discharge on metal wires can be used, but the principle of releasing static electricity is generally the same.
[0089] The electrostatic discharge principle of the first electrostatic protection circuit ESD1 set on the read line DL in Figure 5 is explained below. As shown in Figure 6, according to the circuit structure of the first electrostatic protection circuit ESD1, the gate G and drain D of the first transistor T1 are shorted, and the gate G and drain D of the second transistor T2 are shorted. Therefore, both the first transistor T1 and the second transistor T2 operate in the saturation region. As mentioned earlier, the TFT in the ESD protection structure will also generate a certain amount of current, which will interfere with the Read Out IC's current / charge reading. The formula for the TFT saturation region current is: I ds The current is the source / drain current of the TFT, μ represents the mobility of the TFT active layer, and C is the source / drain current. ox V represents the capacitance between the gate and drain of a TFT. gs V represents the gate-source voltage of the TFT. th V represents the threshold voltage of the TFT. th Typically around 0V. Because the gate G of the first transistor T1 is connected to the read line DL, its gate voltage V... g It is already fixed, that is, V g The operating voltage (Vref) of the ROIC acquisition channel is such that, since this disclosure applies the same operating voltage (Vref) to the first electrostatic discharge structure 100 as to the read line DL, i.e., the voltage on the first electrostatic discharge structure 100 is Vref, the source voltage V of the first transistor T1 is... s Vref, at this time the V of the first transistor T1 gs =0V, therefore I ds It is close to 0, and similarly, the V of the second transistor T2 is close to 0. gs =0V, therefore the first electrostatic discharge protection circuit ESD1 has almost no effect on the current / charge reading of ROIC. Therefore, this disclosure provides a solution for setting an ESD protection structure on the read line DL, which can improve the ESD protection capability of the read line DL.
[0090] In some embodiments, as shown in FIG5, the third peripheral area B3 includes a second binding area BD2 located between the detection area AA and the first electrostatic discharge structure 100. The second binding area BD2 includes a plurality of second pins 20. The scan line GL extends to the second binding area BD2 and is electrically connected to the corresponding second pin 20.
[0091] The detection panel also includes: multiple fifth electrostatic discharge protection circuits (ESD5) located between the second binding area BD2 and the detection area AA, and a second electrostatic discharge structure 200 located between the fifth electrostatic discharge protection circuits (ESD5) and the second binding area BD2 and surrounding the detection area AA; the second electrostatic discharge structure 200 is also located between the detection area AA and the first binding area BD1, and each fifth electrostatic discharge protection circuit (ESD5) is electrically connected between the corresponding scan line GL and the second electrostatic discharge structure 200.
[0092] In some embodiments, as shown in FIG5, in the detection panel provided in the present disclosure, the structure of the fifth electrostatic discharge protection circuit ESD5 can be the same as that of the first electrostatic discharge protection circuit ESD1. That is, the fifth electrostatic discharge protection circuit ESD5 also includes the first transistor T1 and the second transistor T2, and the connection method of the two transistors is the same as that of the two transistors in the first electrostatic discharge protection circuit ESD1.
[0093] Of course, the structure of the fifth electrostatic discharge protection circuit ESD5 can also be different from that of the first electrostatic discharge protection circuit ESD1.
[0094] As shown in Figure 5, this embodiment of the present disclosure provides a fifth electrostatic discharge protection circuit ESD5 between the scan line GL and the second electrostatic discharge structure 200. When a large external electrostatic voltage is introduced onto the scan line GL from the second pin 20, the transistor in the fifth electrostatic discharge protection circuit ESD5 will be turned on first, so that the large current generated by it, which is sufficient to burn out the detector area AA pixel, is conducted out through the second electrostatic discharge structure 200 electrically connected to the fifth electrostatic discharge protection circuit ESD5, thereby protecting the pixel P area circuit.
[0095] In some embodiments, as shown in FIG5, in the detection panel provided in this disclosure, the scan line GL extends to the fourth peripheral region B4. The flat panel detector also includes a plurality of sixth electrostatic discharge (ESD) circuits 6 located in the fourth peripheral region B4 and between the second electrostatic discharge structure 200 and the detection region AA. Each sixth ESD circuit 6 is electrically connected between the corresponding scan line GL and the second electrostatic discharge structure 200. In this way, the sixth ESD circuit 6 can further release the static electricity on the scan line GL, thereby improving the ESD protection capability of the scan line GL.
[0096] In some embodiments, as shown in FIG5, in the detection panel provided in the present disclosure, the first electrostatic discharge structure 100 is disposed around the second electrostatic discharge structure 200.
[0097] In some embodiments, as shown in FIG5, in the detection panel provided in the present disclosure, the structure of the sixth electrostatic discharge protection circuit ESD6 can be the same as that of the first electrostatic discharge protection circuit ESD1, that is, the sixth electrostatic discharge protection circuit ESD6 also includes the first transistor T1 and the second transistor T2, and the connection method of the two transistors is the same as that of the two transistors in the first electrostatic discharge protection circuit ESD1.
[0098] Of course, the structure of the sixth electrostatic discharge protection circuit ESD6 can also be different from that of the first electrostatic discharge protection circuit ESD1.
[0099] As shown in Figure 5, when the detection panel is working normally, i.e., when there is no external static electricity, the transistors in the fifth electrostatic discharge protection circuit ESD5 and the sixth electrostatic discharge protection circuit ESD6 will also turn on or off, generating a certain amount of current. However, this current does not have a substantial impact on the scan line GL, because the scan line GL only needs to provide the on or off voltage to the thin-film transistors 2 of each pixel P in the detection area AA, and is therefore not sensitive to current.
[0100] In some embodiments, as shown in FIG5, in the detection panel provided in the present disclosure, the first bonding area BD1 further includes a third pin 30, and the second bonding area BD2 further includes a fourth pin 40. The first electrostatic discharge structure 100 can be electrically connected to at least one of the third pin 30 and the fourth pin 40, and the first electrostatic discharge structure 100 can be electrically connected to at least one of the third pin 30 and / or at least one of the fourth pin 40. The second electrostatic discharge structure 200 can be electrically connected to at least one of the third pin 30 and the fourth pin 40, and the second electrostatic discharge structure 200 can be electrically connected to at least one of the third pin 30 and / or at least one of the fourth pin 40. In this way, the external driving circuit inputs voltage to the first electrostatic discharge structure 100 and the second electrostatic discharge structure 200 through the third pin 30 and the fourth pin 40.
[0101] In some embodiments, as shown in Figures 5 and 7, Figure 7 is the layout structure of the local detection area AA and the local third peripheral area B3 in Figure 5. The first electrostatic discharge structure 100 can be electrically connected to a third pin 30 and a fourth pin 40, and the second electrostatic discharge structure 200 can be electrically connected to a third pin 30 and a fourth pin 40. In this way, voltage is simultaneously input to the first electrostatic discharge structure 100 through the third pin 30 and the fourth pin 40, and voltage is simultaneously input to the second electrostatic discharge structure 200 through the third pin 30 and the fourth pin 40. On the one hand, this can make the voltage distribution on the first electrostatic discharge structure 100 and the second electrostatic discharge structure 200 uniform. On the other hand, it can prevent voltage from being input to the electrostatic protection circuit through the third pin 30 or the fourth pin 40 when a part of the first electrostatic discharge structure 100 and the second electrostatic discharge structure 200 is disconnected.
[0102] In some embodiments, as shown in FIG8, the first electrostatic discharge structure 100 in FIG5 can also be supplied with voltage through a probe electrode. For example, the peripheral region (third peripheral region B3) also includes a probe electrode 50. The first electrostatic discharge structure 100 can be electrically connected to the probe electrode 50. In this way, when the detection panel performs image detection, the first electrostatic discharge structure 100 can be powered directly by sticking a probe on the probe electrode 50.
[0103] Specifically, the second electrostatic discharge structure 200 in Figure 5 can also be supplied with voltage through the probe electrode. The principle of the probe electrode 50 electrically connected to the first electrostatic discharge structure 100 is the same, and will not be described in detail here.
[0104] In some embodiments, the detection panel provided in this disclosure, as shown in FIG9, differs from FIG5 in that: the detection panel shown in FIG9 further includes a plurality of fourth electrostatic discharge protection circuits ESD4 located between the second bonding area BD2 and the first electrostatic discharge structure 100, each fourth electrostatic discharge protection circuit ESD4 being electrically connected between the corresponding second pin 20 and the first electrostatic discharge structure 100. Based on the structure shown in FIG5, the addition of fourth electrostatic discharge protection circuits ESD4 between the second bonding area BD2 and the first electrostatic discharge structure 100 further enhances the electrostatic discharge protection capability of the flat panel detector during the manufacturing process.
[0105] Optionally, the structure of the fourth electrostatic discharge protection circuit ESD4 can be the same as or different from the structure of the first electrostatic discharge protection circuit ESD1.
[0106] In some embodiments, the detection panel provided in this disclosure, as shown in FIG10, differs from FIG9 in that: the detection panel shown in FIG10 further includes multiple second electrostatic discharge protection circuits ESD2 located between the detection area AA and the first bonding area BD1, and a second electrostatic discharge structure 200 is also located between the second electrostatic discharge protection circuits ESD2 and the first bonding area BD1; each second electrostatic discharge protection circuit ESD2 is electrically connected between the corresponding readout line DL and the second electrostatic discharge structure 200; wherein, the second electrostatic discharge structure 200 is configured such that no voltage is applied during the module manufacturing process of the detection panel, and the same working voltage (Vref) as on the readout line DL is applied during image detection after each stage of the module manufacturing process, so that the second electrostatic discharge protection circuit ESD2 has almost no effect on the current / charge reading of ROIC. For the specific principle, please refer to the aforementioned explanation of the principle that the first electrostatic discharge protection circuit ESD1 has almost no effect on the current / charge reading of ROIC.
[0107] Optionally, the structure of the second electrostatic discharge protection circuit ESD2 can be the same as or different from the structure of the first electrostatic discharge protection circuit ESD1.
[0108] As shown in Figure 10, in this embodiment, a second electrostatic discharge protection circuit ESD2 is added between the first bonding area BD1 and the read line DL. This can further release the static electricity introduced into the read line DL by the first pin 10, and further improve the ESD protection capability of the read line DL.
[0109] In some embodiments, in the detection panel provided in this disclosure, as shown in FIG10, the readout line DL extends to the second peripheral area B2. The flat panel detector also includes a plurality of third electrostatic discharge protection circuits ESD3 located in the second peripheral area B2 and between the second electrostatic discharge structure 200 and the detection area AA. Each third electrostatic discharge protection circuit ESD3 is electrically connected between the corresponding readout line DL and the second electrostatic discharge structure 200. The third electrostatic discharge protection circuit ESD3 has almost no effect on the current / charge reading of ROIC. For the specific principle, please refer to the aforementioned explanation of the principle that the first electrostatic discharge protection circuit ESD1 has almost no effect on the current / charge reading of ROIC.
[0110] Optionally, the structure of the third electrostatic discharge protection circuit ESD3 can be the same as or different from the structure of the first electrostatic discharge protection circuit ESD1.
[0111] As shown in Figure 10, in this embodiment, a third electrostatic discharge protection circuit ESD3 is added to the second peripheral area B2, which can further release the static electricity on the read line DL and further improve the ESD protection capability of the read line DL.
[0112] In some embodiments, in the detection panel provided in this disclosure, as shown in FIG11, the difference between FIG11 and FIG10 is that: the second electrostatic discharge structure 200 in the detection panel shown in FIG11 is also located between the detection area AA and the fifth electrostatic discharge protection circuit ESD5, and also includes a third electrostatic discharge structure 300 located between the fifth electrostatic discharge protection circuit ESD5 and the second binding area BD2 and surrounding the second electrostatic discharge structure 200. The third electrostatic discharge structure 300 is also located between the second electrostatic discharge structure 200 and the first binding area BD1. The first electrostatic discharge structure 100 is arranged around the third electrostatic discharge structure 300. A plurality of sixth electrostatic discharge protection circuits ESD6 are located between the second electrostatic discharge structure 200 and the third electrostatic discharge structure 300. Each of the fifth electrostatic discharge protection circuits ESD5 is electrically connected between the corresponding scan line GL and the third electrostatic discharge structure 300, and each of the sixth electrostatic discharge protection circuits ESD6 is electrically connected between the corresponding scan line GL and the third electrostatic discharge structure 300.
[0113] Specifically, the detection panel shown in Figure 11 can achieve the same electrostatic discharge effect as that in Figure 10. The main difference is that in Figure 10, the second electrostatic protection circuit ESD2, the third electrostatic protection circuit ESD3, the fifth electrostatic protection circuit ESD5, and the sixth electrostatic protection circuit ESD6 are all electrically connected to the second electrostatic discharge structure 200, while in Figure 11, the second electrostatic protection circuit ESD2 and the third electrostatic protection circuit ESD3 are electrically connected to the second electrostatic discharge structure 200, and the fifth electrostatic protection circuit ESD5 and the sixth electrostatic protection circuit ESD6 are electrically connected to the third electrostatic discharge structure 300. This is because, in order to avoid the current of the electrostatic protection circuit affecting the ROIC's reading of the current on the read line DL, the operating voltage of the electrostatic discharge structure electrically connected to the second electrostatic protection circuit ESD2 and the third electrostatic protection circuit ESD3 needs to be set to Vref. The scan line GL is not affected by the current of the electrostatic protection circuit, but in order to avoid the leakage current of the electrostatic protection circuit causing noise in the scan line GL, the operating voltage of the electrostatic discharge structure electrically connected to the fifth electrostatic protection circuit ESD5 and the sixth electrostatic protection circuit ESD6 is generally set to a negative voltage to ensure that the transistor is completely turned off and reduce leakage current. Therefore, the detection panel shown in Figure 11 connects the ESD circuits corresponding to the read line DL and the scan line GL to different electrostatic discharge structures. On the one hand, it avoids the current of the electrostatic protection circuit from affecting the ROIC's reading of the current on the read line DL, and on the other hand, it avoids the generation of noise on the scan line GL.
[0114] It should be noted that although the fifth electrostatic discharge protection circuit ESD5 and the sixth electrostatic discharge protection circuit ESD6 in Figure 10 are electrically connected to the second electrostatic discharge structure 200, and the voltage on the second electrostatic discharge structure 200 is the working voltage Vref, this does not affect the normal operation of the fifth electrostatic discharge protection circuit ESD5 and the sixth electrostatic discharge protection circuit ESD6.
[0115] It should be noted that Figures 5 and 9-11 provided in this embodiment are only a few ways to set ESD circuits on the scan line GL and read line DL as listed in this embodiment. Of course, it is not limited to these, and can be various combinations of the ESD circuits corresponding to the scan line GL and the read line DL. For example, as shown in Figures 12 and 13, only the second electrostatic discharge (ESD) protection circuit ESD2, the third ESD protection circuit ESD3, the fifth ESD protection circuit ESD5, and the sixth ESD protection circuit ESD6 can be set. The difference between Figures 12 and 13 is that in Figure 12, the second ESD protection circuit ESD2 and the third ESD protection circuit ESD3 are electrically connected to the second electrostatic discharge structure 200, and the fifth ESD protection circuit ESD5 and the sixth ESD protection circuit ESD6 are electrically connected to the third electrostatic discharge structure 300. That is, the first electrostatic discharge structure 100 is not required in Figure 12. However, in Figure 13, the second ESD protection circuit ESD2, the third ESD protection circuit ESD3, the fifth ESD protection circuit ESD5, and the sixth ESD protection circuit ESD6 are all electrically connected to the second electrostatic discharge structure 200. That is, the first electrostatic discharge structure 100 and the third electrostatic discharge structure 300 are not required in Figure 13.
[0116] In some embodiments, the detection panel provided in this disclosure, as shown in Figures 5 and 9-13, further includes: multiple bias voltage lines BL located in the detection area AA, and a bias voltage bus 400 (not shown) located in the peripheral area and surrounding the detection area AA; the bias voltage lines BL are electrically connected to the bias voltage bus 400. Specifically, taking the structure shown in Figure 12 as an example, the bias voltage bus 400 is located between the overall structure formed by each electrostatic protection circuit (ESD2, ESD3, ESD5, and ESD6) and each electrostatic discharge structure (second electrostatic discharge structure 200) and the detection area AA, that is, all electrostatic protection circuits and electrostatic discharge structures are arranged around the bias voltage bus 400.
[0117] In some embodiments, in the detection panel provided in the present disclosure, as shown in Figures 14-19, Figure 14 is a structural layout within the dashed frame E1 of Figure 12, Figure 15 is a structural layout within the dashed frame E2 of Figure 14, Figure 16 is a structural layout within the dashed frame F1 of Figure 12, Figure 17 is a structural layout within the dashed frame F2 of Figure 16, Figure 18 is a cross-sectional view along the AA' direction in Figure 15, and Figure 19 is a cross-sectional view along the BB' direction in Figure 15. The third metal layer 6 includes a first transition portion 61 and a second transition portion 62, and the fourth metal layer 7 includes a light-shielding portion 71.
[0118] In this circuit, when the flat panel detector is working, the photoelectric conversion device 3 receives light from the front of the flat panel detector. Therefore, the active layer channel of the transistor needs to be shielded. Thus, the orthogonal projection of the shielding part 71 onto the substrate 1 covers the orthogonal projection of the active layer Act of the first transistor T1 and the second transistor T2 onto the substrate 1. This prevents the active layer Act of the first transistor T1 and the second transistor T2 from generating additional current due to frontal illumination. The first adapter 61 is electrically connected to the gate G and drain D of the first transistor T1, the second adapter 62 is electrically connected to the gate G and drain D of the second transistor T2, and the shielding part 71 is electrically connected to the second adapter 62. Thus, the shielding part 71 is electrically connected to the second electrostatic discharge structure 200, and the voltage on the shielding part 71 is a fixed operating voltage Vref. The reason why the shielding part 71 is connected to a fixed voltage instead of being floating is that the shielding part 71 is located directly above the active layer of the transistor, equivalent to the top gate of the transistor. The voltage value of this top gate will affect the threshold voltage Vref of the transistor to a certain extent. th If the light-shielding part 71 is floating, the top gate voltage is uncontrollable and will be affected by the external environment or trace coupling, causing the threshold voltage V of the transistor in the electrostatic protection circuit on different read lines DL to be affected. th This creates a floating offset, which affects the current of the transistor in the electrostatic discharge (ESD) protection circuit, and consequently, the current / charge readout of the ROIC. To minimize this impact, the light-shielding part 71 is connected to a fixed voltage to prevent voltage fluctuations at the top gate from affecting the threshold voltage V of the transistor in the ESD protection circuit. th This has an impact, which in turn affects the output current on the read line DL.
[0119] In some embodiments, in the detection panel provided in the present disclosure, as shown in FIG5 and FIG9-13, each electrostatic discharge structure (first electrostatic discharge structure 100, second electrostatic discharge structure 200, and third electrostatic discharge structure 300) is located in at least one of the first metal layer 4, second metal layer 5, third metal layer 6, and fourth metal layer 7, that is, the first electrostatic discharge structure 100, second electrostatic discharge structure 200, and third electrostatic discharge structure 300 can be implemented by jumper connection between multiple metal layers.
[0120] In some embodiments, as shown in FIG19, in the detection panel provided in the present disclosure, the second adapter 62 is electrically connected to the gate G of the second transistor T2 through a via penetrating the first insulating layer 8 and the second insulating layer 9, the second adapter 62 is electrically connected to the drain D of the second transistor T2 through a via penetrating the second insulating layer 9, and the light-shielding part 71 is electrically connected to the second adapter 62 through a via penetrating the fourth insulating layer 13, the planarization layer 12 and the third insulating layer 11.
[0121] In summary, the detection panel provided in this embodiment uses the original manufacturing process of a flat panel detector to design an electrostatic protection circuit on the readout line DL, which can avoid the risk of defects in the readout line DL and scan line GL caused by process ESD of the flat panel detector, thus protecting the pixels in the detection area without adding any new processes or development costs.
[0122] It is important to note that the process described above, which sets the voltage on the electrostatic discharge structure to Vref and ensures that the electrostatic protection circuit on the read line DL does not affect ROIC reading, typically refers only to the electrical image inspection process after each stage of the module manufacturing process, such as inspection after cutting or ROIC bonding, and not to the final product's usage by the user. The reasons include: ① The electrostatic protection circuit on the probe panel is usually only used to protect against static electricity during the production process, especially in the module manufacturing process, because the probe panel cannot be grounded during the process. Once the final probe panel is assembled into the final product, it can be grounded, so static electricity can usually be released through grounding, no longer relying on the electrostatic protection circuit on the probe panel; ② The method of reducing the transistor current in the electrostatic protection circuit is only used to ensure that image inspection after each stage can proceed smoothly, that is, only to ensure that product defects can be judged through image acquisition, and not to guarantee absolute image quality; because the transistor's threshold voltage Vref can be affected by process fluctuations, bias loading, etc. th The fluctuations or changes in current I on different read lines DL are due to the current generated by the transistor in the electrostatic protection circuit. ds It is not actually completely zero, and because V th There will be some degree of difference; therefore, in order to completely avoid its interference with the ROIC current / charge reading, this disclosure usually requires disconnecting the electrostatic protection circuit on the reading line DL from the reading line DL after each stage of the module process is completed and before assembling into the final product form. In this way, the electrostatic protection circuit can play the role of electrostatic protection in the process without affecting the image acquisition effect of the final product form.
[0123] Therefore, this disclosure also provides a flat panel detector, which uses the detection panel provided in this disclosure for electrostatic discharge (ESD) protection during the manufacturing process. As shown in FIG20, the first ESD protection circuit ESD1 in the flat panel detector is disconnected from the first pin 10. This avoids interference from the first ESD protection circuit ESD1 on the ROIC current / charge reading in the final product form, thus preventing it from affecting the image acquisition effect of the final product form.
[0124] In some embodiments, the flat panel detector provided in this disclosure, as shown in Figures 21 and 22 (Figure 22 is a structural layout within the dashed box H1 in Figure 21), further includes a second electrostatic discharge (ESD) protection circuit ESD2, which is disconnected from the read line DL. Specifically, the second ESD protection circuit ESD2 on the read line DL is cut off at the end of the module manufacturing process. When cutting off the read line DL, it is necessary to ensure its integrity; it cannot be cut off along with the read line DL. Only the connection between the second ESD protection circuit ESD2 and the read line DL needs to be disconnected.
[0125] In some embodiments, as shown in FIG22, the flat panel detector provided in the present disclosure further includes a first lead L. The first lead L includes a first part L1 electrically connected to the read line DL and a second part L2 electrically connected to the second electrostatic discharge protection circuit ESD2. The first part L1 and the second part L2 are disconnected, that is, they can be cut from the middle position of the first lead L so as not to cut the read line DL.
[0126] In some embodiments, the flat panel detector provided in this disclosure, as shown in Figures 21 and 23, where Figure 23 is a structural layout within the dashed box H2 in Figure 21, also includes a third electrostatic discharge protection circuit ESD3. The third electrostatic discharge protection circuit ESD3 is disconnected from the read line DL. Since one end of the read line DL, which is electrically connected to the third electrostatic discharge protection circuit ESD3, is not connected to any other structure, and in order to avoid switching to the bias voltage bus 400, the read line DL region between the third electrostatic discharge protection circuit ESD3 and the bias voltage bus 400 can be directly cut off.
[0127] Specifically, the disconnection operation between the electrostatic protection circuit and the reading line DL is usually achieved by a laser device.
[0128] It should be noted that Figures 20 and 21 only list the ESD setting schemes on the read line DL corresponding to the two schemes in Figures 5 and 11. Of course, the ESD setting schemes on the read line DL corresponding to Figures 9, 10, 12 and 13 can also be used, as long as the ESD on the read line DL is cut off.
[0129] In some embodiments, as shown in FIG21, the fourth electrostatic discharge protection circuit ESD4 corresponding to the scan line GL may or may not be disconnected from the second pin 20, because the current on the fourth electrostatic discharge protection circuit ESD4 does not have a substantial impact on the scan line GL. This embodiment of the disclosure takes the example of the fourth electrostatic discharge protection circuit ESD4 and the second pin 20 not being disconnected.
[0130] In some embodiments, as shown in FIG21, the fifth electrostatic discharge protection circuit ESD5 and the sixth electrostatic discharge protection circuit ESD6 corresponding to the scan line GL may or may not be disconnected from the scan line GL. In this embodiment, the fifth electrostatic discharge protection circuit ESD5 and the sixth electrostatic discharge protection circuit ESD6 are not disconnected from the scan line GL as an example.
[0131] In specific implementation, the specific structure and film layer description of the flat panel detector provided in the embodiments of this disclosure can be found in the description of the aforementioned detection panel, and will not be repeated here.
[0132] In specific implementations, the flat panel detector provided in the embodiments of this disclosure may also include other film layers well known to those skilled in the art, such as a scintillator layer. The material of the scintillator layer is a material that can convert X-rays into visible light. It is mainly composed of scintillators, which are materials that can emit light after absorbing high-energy particles or rays. In applications, they are usually processed into crystals and called scintillator crystals. The embodiments of this disclosure do not limit the specific material of the scintillator crystal of the scintillator layer. It can be cesium iodide (CsI), cadmium tungstate, barium fluoride, gadolinium oxysulfate (GOS), etc.
[0133] The present disclosure provides a detection panel and a flat panel detector. By setting a first electrostatic protection circuit between the first pin connected to the read line and the first electrostatic discharge structure, since the side of the first pin furthest from the substrate is generally metal, it is easier to conduct static electricity into the pixel area. Thus, when a large electrostatic voltage accumulates on the read line, the first electrostatic protection circuit designed in this disclosure can conduct the large current generated by the static electricity through the first electrostatic discharge structure, thereby protecting the pixels in the detection area.
[0134] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0135] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.
Claims
1. A detection panel, wherein, include: A substrate includes a probe region and a peripheral region located around the probe region, the peripheral region including a first peripheral region, the first peripheral region including a first bonding region; Multiple first pins are located on one side of the substrate and within the first bonding region; Multiple read lines are located on one side of the substrate and in the detection area, and each read line extends to the first bonding area and is electrically connected to the corresponding first pin; Multiple first electrostatic protection circuits are located on the side of the first binding area away from the detection area; A first electrostatic discharge structure is located on one side of the substrate and on the side of the first electrostatic protection circuit away from the first bonding area and surrounding the detection area. At least one of the first electrostatic protection circuits is electrically connected between the corresponding first pin and the first electrostatic discharge structure.
2. The detection panel as claimed in claim 1, wherein, The first electrostatic discharge protection circuit includes a first transistor and a second transistor. The gate and drain of the first transistor and the source of the second transistor are electrically connected to the corresponding first pins. The source of the first transistor and the gate and drain of the second transistor are both electrically connected to the first electrostatic discharge structure.
3. The detection panel as described in claim 2, wherein, It also includes: a plurality of second electrostatic discharge protection circuits located between the detection area and the first binding area, and a second electrostatic discharge structure located between the second electrostatic discharge protection circuits and the first binding area and disposed around the detection area; At least one of the second electrostatic protection circuits is electrically connected between the corresponding read line and the second electrostatic discharge structure.
4. The detection panel as described in claim 3, wherein, The structure of the second electrostatic protection circuit is the same as that of the first electrostatic protection circuit.
5. The detection panel as described in claim 3, wherein, The surrounding area also includes a second surrounding area disposed opposite to the first surrounding area, and the reading line extends to the second surrounding area; The flat panel detector also includes a plurality of third electrostatic protection circuits located in the second peripheral area and between the second electrostatic discharge structure and the detection area, at least one of the third electrostatic protection circuits being electrically connected between the corresponding reading line and the second electrostatic discharge structure.
6. The detection panel as described in claim 5, wherein, The structure of the third electrostatic protection circuit is the same as that of the first electrostatic protection circuit.
7. The detection panel as described in any one of claims 3-6, wherein, The peripheral area also includes a third peripheral area disposed adjacent to the first peripheral area. The third peripheral area includes a second binding area located between the detection area and the first electrostatic discharge structure. The second binding area includes a plurality of second pins. The flat panel detector further includes: multiple scan lines located in the detection area and intersecting with the read lines, and multiple fourth electrostatic protection circuits located between the second binding area and the first electrostatic discharge structure; The scan line extends to the second bonding area and is electrically connected to the corresponding second pin, and at least one of the fourth electrostatic protection circuits is electrically connected between the corresponding second pin and the first electrostatic discharge structure.
8. The detection panel as claimed in claim 7, wherein, It also includes a plurality of fifth electrostatic protection circuits located between the second binding area and the detection area, and the second electrostatic discharge structure is also located between the detection area and the fifth electrostatic protection circuits; It also includes a third electrostatic discharge structure located between the fifth electrostatic protection circuit and the second bonding area and surrounding the second electrostatic discharge structure; At least one of the fifth electrostatic protection circuits is electrically connected between the corresponding scan line and the third electrostatic discharge structure.
9. The detection panel as claimed in claim 8, wherein, The peripheral area also includes a fourth peripheral area disposed opposite to the third peripheral area, and the scan line extends to the fourth peripheral area; The flat panel detector also includes a plurality of sixth electrostatic discharge protection circuits located in the fourth peripheral area and between the second electrostatic discharge structure and the third electrostatic discharge structure, at least one of the sixth electrostatic discharge protection circuits being electrically connected between the corresponding scan line and the third electrostatic discharge structure.
10. The detection panel as claimed in claim 9, wherein, The third electrostatic discharge structure is also located between the second electrostatic discharge structure and the first binding area, and the first electrostatic discharge structure is arranged around the third electrostatic discharge structure.
11. The detection panel as claimed in claim 7, wherein, It also includes a plurality of fifth electrostatic discharge protection circuits located between the second binding area and the detection area, and the second electrostatic discharge structure is also located between the fifth electrostatic discharge protection circuits and the second binding area. At least one of the fifth electrostatic discharge protection circuits is electrically connected between the corresponding scan line and the second electrostatic discharge structure.
12. The detection panel as claimed in claim 11, wherein, The peripheral area also includes a fourth peripheral area disposed opposite to the third peripheral area, and the scan line extends to the fourth peripheral area; The flat panel detector also includes a plurality of sixth electrostatic protection circuits located in the fourth peripheral region and between the second electrostatic discharge structure and the detection region, at least one of the sixth electrostatic protection circuits being electrically connected between the corresponding scan line and the second electrostatic discharge structure.
13. The detection panel as claimed in claim 12, wherein, The first electrostatic discharge structure is arranged around the second electrostatic discharge structure.
14. The detection panel as claimed in claim 9 or 12, wherein, The structures of the fourth, fifth, and sixth electrostatic discharge protection circuits are all the same as those of the first electrostatic discharge protection circuit.
15. The detection panel as claimed in any one of claims 11-13, wherein, The first bonding area further includes a third pin, and the second bonding area further includes a fourth pin. Each electrostatic discharge structure is electrically connected to at least one of the third pin and the fourth pin.
16. The detection panel as claimed in any one of claims 11-13, wherein, The surrounding area also includes a probe electrode, and each electrostatic discharge structure is electrically connected to the probe electrode.
17. The detection panel as claimed in any one of claims 11-13, wherein, It also includes: multiple bias voltage lines located in the detection area, and a bias voltage bus located in the peripheral area and surrounding the detection area; the bias voltage lines are electrically connected to the bias voltage bus; The bias voltage bus is located between the overall structure consisting of each electrostatic protection circuit and each electrostatic discharge structure and the detection area.
18. The detection panel according to any one of claims 2-17, wherein, The device includes a first metal layer, an active layer, a second metal layer, a third metal layer, and a fourth metal layer, which are sequentially stacked along a direction away from the substrate. The first metal layer includes the gate, the second metal layer includes the source and the drain, the third metal layer includes a first transition portion and a second transition portion, and the fourth metal layer includes a light-shielding portion. Wherein, the orthogonal projection of the light-shielding part on the substrate covers the orthogonal projection of the active layers of the first transistor and the second transistor on the substrate, the first adapter is electrically connected to the gate and drain of the first transistor, the second adapter is electrically connected to the gate and drain of the second transistor, and the light-shielding part is electrically connected to the second adapter.
19. The detection panel as claimed in claim 18, wherein, Each electrostatic discharge structure is located in at least one of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer.
20. The detection panel of claim 18, wherein, It also includes: a first insulating layer located between the first metal layer and the active layer, a second insulating layer located between the second metal layer and the third metal layer, a third insulating layer located between the third metal layer and the fourth metal layer, a planarization layer located between the third insulating layer and the fourth metal layer, and a fourth insulating layer located between the planarization layer and the fourth metal layer; The second adapter is electrically connected to the gate of the second transistor through a via penetrating the first insulating layer and the second insulating layer. The second adapter is electrically connected to the drain of the second transistor through a via penetrating the second insulating layer. The light-shielding part is electrically connected to the second adapter through a via penetrating the fourth insulating layer, the planarization layer and the third insulating layer.
21. A flat panel detector, wherein, Electrostatic discharge (ESD) protection during the manufacturing process is performed using a detection panel as described in any one of claims 1-20, wherein the first ESD protection circuit and the first pin in the flat panel detector are disconnected.
22. The flat panel detector as claimed in claim 21, wherein, It also includes a second electrostatic discharge (ESD) protection circuit, which is disconnected from the read line.
23. The flat panel detector as claimed in claim 22, wherein, It also includes a first lead, which includes a first portion electrically connected to the read line and a second portion electrically connected to the second electrostatic protection circuit, wherein the first portion and the second portion are disconnected.
24. The flat panel detector as claimed in claim 21, wherein, It also includes a third electrostatic discharge (ESD) protection circuit, which is disconnected from the read line.