Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a plurality of sub-pixels; at least one of the sub-pixels comprises a pixel drive circuit; the pixel drive circuit at least comprises a second transistor (T2); the second transistor (T2) at least comprises a second active layer (32) and a second gate electrode (42); the overlapping region between the second active layer (32) and the second gate electrode (42) is a channel region (44) of the second transistor (T2); a first region of the second active layer (32) is connected to a first power supply line (62), and a second region of the second active layer (32) is connected to an anode connection electrode (52); in the at least one sub-pixel, the orthographic projection of the anode connection electrode (52) on a substrate at least partially overlaps the orthographic projection of the channel region (44) of the second transistor (T2) on the substrate.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, display devices using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate including a plurality of sub-pixels. At least one sub-pixel includes a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. The driving structure layer includes at least a pixel driving circuit, and the light-emitting structure layer includes at least a light-emitting device. The pixel driving circuit includes at least a second transistor as a driving transistor. The second transistor includes at least a second active layer and a second gate electrode. The second active layer is shaped to extend into a strip shape along a first direction, and the second gate electrode is shaped to extend into a strip shape along a second direction. The first direction and the second direction intersect. The orthographic projection of the second gate electrode on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The overlapping region of the second active layer is the channel region of the second transistor. A first region of the second active layer is connected to a first power line, and a second region of the second active layer is connected to an anode connection electrode. The light-emitting device includes at least an anode, which is connected to the anode connection electrode through an anode via. In at least one sub-pixel, the orthographic projection of the anode connection electrode on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor on the substrate.

[0005] In an exemplary embodiment, the channel region of the second transistor has a channel length, and the overlapping region of the orthographic projection of the anode connection electrode on the substrate and the orthographic projection of the channel region of the second transistor on the substrate has a first length, the first length being 0.4 * channel length to 0.6 * channel length, the channel length and the first length being dimensions in the first direction.

[0006] In an exemplary embodiment, at least one sub-pixel further includes a blocking electrode; in at least one sub-pixel, the orthogonal projection of the first region of the second active layer, the second region of the second active layer, and the channel region of the second transistor onto the substrate is located within the range of the orthogonal projection of the blocking electrode onto the substrate.

[0007] In an exemplary embodiment, at least one sub-pixel further includes a blocking electrode; in at least one sub-pixel, the orthographic projections of the second region of the second active layer and the channel region of the second transistor on the substrate are within the range of the orthographic projection of the blocking electrode on the substrate, the first region of the second active layer includes at least a first portion and a second portion, the second portion is located between the first portion and the channel region of the second transistor, the orthographic projection of the first portion on the substrate at least partially overlaps with the orthographic projection of the blocking electrode on the substrate, and the orthographic projection of the second portion on the substrate is within the range of the orthographic projection of the blocking electrode on the substrate.

[0008] In an exemplary embodiment, the first portion has a first width, the second portion has a second width, the first width is greater than the second width, and the first width and the second width are dimensions in the second direction.

[0009] In an exemplary embodiment, at least one sub-pixel further includes a color filter structure layer disposed on the side of the driving structure layer away from the substrate, and the light-emitting structure layer disposed on the side of the color filter structure layer away from the substrate; in at least one sub-pixel, the color filter structure layer includes at least a blocking structure, and the orthographic projection of the blocking structure on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor on the substrate.

[0010] In an exemplary embodiment, the channel region of the second transistor has a channel length, and the overlapping area of ​​the orthographic projection of the shielding structure onto the substrate and the orthographic projection of the channel region of the second transistor onto the substrate has a second length, the second length being 0.4 * channel length to 0.6 * channel length, wherein the channel length and the second length are dimensions in the first direction.

[0011] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the occluding structure on the substrate does not overlap with the orthographic projection of the anode via on the substrate.

[0012] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the occlusion structure onto the substrate does not overlap with the orthographic projection of the anode connection electrode onto the substrate.

[0013] In an exemplary embodiment, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged sequentially along the first direction. The color filter structure layer of the first sub-pixel includes at least a first filter layer, which is configured to cause the first sub-pixel to emit green light. The color filter structure layer of the second sub-pixel includes at least a second filter layer, which is configured to cause the second sub-pixel to emit red light. The color filter structure layer of the fourth sub-pixel includes at least a third filter layer, which is configured to cause the fourth sub-pixel to emit blue light.

[0014] In an exemplary embodiment, the occlusion structure includes at least a first occlusion block disposed in the first sub-pixel, wherein the orthographic projection of the first occlusion block on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor in the first sub-pixel on the substrate, and the material of the first occlusion block is the same as the material of the second filter layer.

[0015] In an exemplary embodiment, the occlusion structure includes at least a second occlusion block disposed in the second sub-pixel, wherein the orthographic projection of the second occlusion block on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor in the second sub-pixel on the substrate, and the second occlusion block and the second filter layer are an integral structure interconnected with each other.

[0016] In an exemplary embodiment, the occlusion structure includes at least a third occlusion block disposed in the third sub-pixel, wherein the orthographic projection of the third occlusion block on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor in the third sub-pixel on the substrate, and the third occlusion block and the second filter layer are an integral structure interconnected with each other.

[0017] In an exemplary embodiment, the occlusion structure includes at least a fourth occlusion block disposed in the fourth sub-pixel, wherein the orthographic projection of the fourth occlusion block on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor in the fourth sub-pixel on the substrate, and the material of the fourth occlusion block is the same as the material of the second filter layer.

[0018] In an exemplary embodiment, the pixel driving circuit further includes a first transistor as a data writing transistor and a third transistor as a compensation transistor. The first electrode of the first transistor is connected to a data signal line, the second electrode of the first transistor is connected to the gate electrode of the second transistor, the first electrode of the third transistor is connected to the compensation signal line, and the second electrode of the third transistor is connected to the anode connection electrode. In at least one sub-pixel, the color filter structure layer further includes a fifth blocking block. The orthographic projection of the fifth blocking block on the substrate at least partially overlaps with the orthographic projections of the channel regions of the first transistor and the third transistor on the substrate.

[0019] In an exemplary embodiment, in at least one sub-pixel, the orthographic projections of the channel regions of the first transistor and the third transistor onto the substrate are located within the range of the orthographic projection of the fifth occluding block onto the substrate.

[0020] In an exemplary embodiment, the fifth occlusion block in the first sub-pixel, the fifth occlusion block in the second sub-pixel, the fifth occlusion block in the third sub-pixel, and the fifth occlusion block in the fourth sub-pixel are an integral structure that is interconnected.

[0021] In an exemplary embodiment, the materials of the fifth occlusion block in the first sub-pixel, the fifth occlusion block in the second sub-pixel, the fifth occlusion block in the third sub-pixel, and the fifth occlusion block in the fourth sub-pixel are the same as the material of the second filter layer.

[0022] In an exemplary embodiment, the fifth occlusion block in the first sub-pixel, the fifth occlusion block in the second sub-pixel, the fifth occlusion block in the third sub-pixel, the fifth occlusion block in the fourth sub-pixel, and the second filter layer are an integral structure connected to each other.

[0023] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0024] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0026] Figure 1 is a schematic diagram of the structure of a display device;

[0027] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0028] Figure 3. Equivalent circuit diagram of pixel driving circuit in a repeating unit;

[0029] Figure 4 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0030] Figure 5 is a cross-sectional view along direction AA in Figure 4;

[0031] Figure 6 is a schematic diagram of the display substrate after the formation of the first transparent conductive layer pattern;

[0032] Figures 7A and 7B are schematic diagrams of the display substrate after the formation of the first conductive layer pattern;

[0033] Figures 8A and 8B are schematic diagrams of the semiconductor layer pattern formed on the display substrate of this disclosure;

[0034] Figures 9A and 9B are schematic diagrams of the display substrate after the formation of the second conductive layer pattern;

[0035] Figure 10 is a schematic diagram of the display substrate after the formation of the third insulating layer pattern;

[0036] Figures 11A and 11B are schematic diagrams of the display substrate after the formation of the third conductive layer pattern;

[0037] Figures 12A and 12B are schematic diagrams of the display substrate after the color filter structure layer pattern is formed in the present disclosure.

[0038] Figure 13 is a schematic diagram of the display substrate after the planarization layer pattern has been formed;

[0039] Figure 14 is a schematic diagram of the display substrate after the formation of the second transparent conductive layer pattern;

[0040] Figure 15 is a schematic diagram of the display substrate after the pixel definition layer pattern has been formed.

[0041] Explanation of reference numerals in the attached drawings: 11—First electrode plate; 12—Connecting plate; 13—Connecting line; 14—Compensation pad; 15—Power pad; 21—Shielding electrode; 22—Interlayer connection electrode; 23—Compensation connection line; 24—Power connection line; 31—First active layer; 32—Second active layer; 33—Third active layer; 34—Active connection strip; 35—Second electrode plate; 41—First scan signal line; 42—Second gate electrode; 43—Auxiliary power line; 51—First connecting electrode; 52—Second connecting electrode; 53—Third connecting electrode; 54—Fourth connecting electrode; 55—Fifth connecting electrode; 56—Power connection electrode; 61—Data signal line; 62—First power line; 63—Compensation signal line; 64—Compensation connection strip; 71—First filter layer; 72—Second filter layer; 73—Third filter layer; 81—First blocking block; 82—Second blocking block; 83—Third blocking block; 84—Fourth blocking block; 85—Fifth blocking block; 91—First anode; 92—Second anode; 93—Third anode; 94—Fourth anode; 100—Repeating unit; 200—Substrate; 201—First insulating layer; 202—Second insulating layer; 203—Third insulating layer; 204—Fourth insulating layer; 205—Planning layer; 206—Pixel definition layer. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0043] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0044] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0045] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0046] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0047] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0048] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0049] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0050] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0051] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0052] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfered corners, curved edges, and other variations.

[0053] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0054] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is connected to both the data driver and the scan driver. The data driver is connected to multiple data signal lines (D1 to Dn), and the scan driver is connected to multiple scan signal lines (S1 to Sm), where n and m can be natural numbers. The pixel array may include multiple sub-pixels Pxij, each sub-pixel Pxij being connected to a corresponding data signal line and a corresponding scan signal line, where i and j can be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to both the scan signal line and the data signal line. The light-emitting unit may include at least a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. A sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and the j-th data signal line. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, and can provide clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. In an exemplary embodiment, the pixel array may be disposed on a display substrate.

[0055] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, on a plane parallel to the display substrate, the display substrate may include a plurality of repeating units 100 arranged in a matrix, and at least one repeating unit 100 may include a plurality of sub-pixels. In an exemplary embodiment, the repeating unit 100 is a basic unit constituting the display substrate, and the display substrate is formed by repeating and continuously arranging it along at least one direction, that is, the display substrate is spliced ​​together from a plurality of repeating units.

[0056] In an exemplary embodiment, a repeating unit 100 may include four sub-pixels. The four sub-pixels may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, a third sub-pixel P3 that emits a third color light, and a fourth sub-pixel P4 that emits a fourth color light. The four sub-pixels may be arranged in a horizontal side-by-side manner, which can effectively increase the aperture ratio.

[0057] In an exemplary embodiment, in at least one repeating unit 100, a second sub-pixel P2 may be disposed on one side of the first sub-pixel P1 in the first direction X, a third sub-pixel P3 may be disposed on one side of the second sub-pixel P2 in the first direction X, and a fourth sub-pixel P4 may be disposed on one side of the third sub-pixel P3 in the first direction X. In an exemplary embodiment, a plurality of sub-pixels arranged sequentially along the first direction X may be referred to as a pixel row, and a plurality of sub-pixels arranged sequentially along the second direction Y may be referred to as a pixel column. The plurality of pixel rows and the plurality of pixel columns constitute a pixel array arranged in an array, wherein the first direction X intersects the second direction Y.

[0058] In an exemplary embodiment, the first direction X can be the pixel row direction, the second direction Y can be the pixel column direction, and the first direction X and the second direction Y can be perpendicular to each other.

[0059] In an exemplary embodiment, the first sub-pixel P1 can be a green sub-pixel (G) emitting green light, the second sub-pixel P2 can be a red sub-pixel (R) emitting red light, the third sub-pixel P3 can be a white sub-pixel (W) emitting white light, and the fourth sub-pixel P4 can be a blue sub-pixel (B) emitting blue light. In some possible embodiments, the arrangement of GRWBs can be adjusted according to actual needs, and this disclosure does not specifically limit it.

[0060] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving structure layer disposed on the substrate, a color filter structure layer disposed on the side of the driving structure layer away from the substrate, and a light-emitting structure layer disposed on the side of the color filter structure layer away from the substrate. In at least one repeating unit, the driving structure layer may include multiple circuit units, the color filter structure layer may include multiple color filter units, and the light-emitting structure layer may include multiple light-emitting units. The circuit units may include at least a pixel driving circuit configured to output a corresponding current to a light-emitting device. The light-emitting units may include at least a light-emitting device configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel. The color filter unit may include at least a color filter layer configured to cause the corresponding sub-pixel to emit light of the desired color.

[0061] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to a pixel driving circuit. The color filter unit referred to in this disclosure refers to a region divided according to a color filter layer. The light-emitting unit referred to in this disclosure refers to a region divided according to a light-emitting device. The positions of the circuit unit projected onto the substrate, the color filter layer projected onto the substrate, and the light-emitting unit projected onto the substrate may be corresponding or non-corresponding.

[0062] In an exemplary embodiment, the positions of the circuit unit projected onto the substrate, the color filter unit projected onto the substrate, and the light-emitting unit projected onto the substrate are substantially corresponding. The circuit unit, the color filter unit, and the light-emitting unit constitute a sub-pixel. In the following text, sub-pixel will be used to refer to the circuit unit, the color filter unit, and the light-emitting unit.

[0063] Figure 3 shows the equivalent circuit diagram of a pixel driving circuit in a repeating unit. As shown in Figure 3, at least one repeating unit may include four pixel driving circuits, which can be arranged in a horizontal parallel manner, and the pixel driving circuit can be a 3T1C structure.

[0064] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (first transistor T1, second transistor T2 and third transistor T3) and one storage capacitor C. The pixel driving circuit is connected to the scan signal line 41, the data signal line 61, the first power supply line 62 and the compensation signal line 63, respectively.

[0065] In an exemplary embodiment, at least one pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first terminal of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second terminal of the storage capacitor C, respectively.

[0066] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the second node N2. The storage capacitor C is used to store the potential of the gate electrode of the second transistor T2.

[0067] In an exemplary embodiment, the first transistor T1 can be referred to as a data writing transistor. The gate electrode of the first transistor T1 is connected to the scan signal line 41, the first terminal of the first transistor T1 is connected to the data signal line 61, and the second terminal of the first transistor T1 is connected to the first node N1. The second transistor T2 can be referred to as a driving transistor. The gate electrode of the second transistor T2 is connected to the first node N1, the first terminal of the second transistor T2 is connected to the first power supply line 62, and the second terminal of the second transistor T2 is connected to the second node N2. The third transistor T3 can be referred to as a compensation transistor. The gate electrode of the third transistor T3 is connected to the scan signal line 41, the first terminal of the third transistor T3 is connected to the compensation signal line 63, and the second terminal of the third transistor T3 is connected to the second node N2.

[0068] In an exemplary embodiment, the light-emitting device EL can be an OLED, including a stacked first electrode, an organic light-emitting layer, and a second electrode, or it can be a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. The first electrode of the light-emitting device EL is connected to the second node N2, and the second electrode of the light-emitting device EL is connected to the second power line VSS. In an exemplary embodiment, the first electrode can be an anode, and the second electrode can be a cathode; or, the first electrode can be a cathode, and the second electrode can be an anode.

[0069] In an exemplary embodiment, the signal of the first power line 62 is a continuously provided high-level signal, and the signal of the second power line VSS is a continuously provided low-level signal.

[0070] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the third transistor T3 may include both P-type and N-type transistors.

[0071] In an exemplary embodiment, the first transistor T1 to the third transistor T3 can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), or oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs have advantages such as high mobility and fast charging, while OPTs have advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0072] An exemplary embodiment of this disclosure provides a display substrate including a plurality of sub-pixels. At least one sub-pixel includes a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. The driving structure layer includes at least a pixel driving circuit, and the light-emitting structure layer includes at least a light-emitting device. The pixel driving circuit includes at least a second transistor as a driving transistor. The second transistor includes at least a second active layer and a second gate electrode. The second active layer is shaped to extend into a strip shape along a first direction, and the second gate electrode is shaped to extend into a strip shape along a second direction. The first direction and the second direction intersect. The orthographic projection of the second gate electrode onto the substrate at least partially overlaps with the orthographic projection of the second active layer onto the substrate. The overlapping region of the second active layer is the channel region of the second transistor. A first region of the second active layer is connected to a first power line, and a second region of the second active layer is connected to an anode connection electrode. The light-emitting device includes at least an anode, which is connected to the anode connection electrode through an anode via. In at least one sub-pixel, the orthographic projection of the anode connection electrode onto the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor onto the substrate.

[0073] In an exemplary embodiment, the channel region of the second transistor has a channel length, and the overlapping region of the orthographic projection of the anode connection electrode on the substrate and the orthographic projection of the channel region of the second transistor on the substrate has a first length, the first length being 0.4 * channel length to 0.6 * channel length, the channel length and the first length being dimensions in the first direction.

[0074] In an exemplary embodiment, at least one sub-pixel further includes a color filter structure layer disposed on the side of the driving structure layer away from the substrate, and the light-emitting structure layer disposed on the side of the color filter structure layer away from the substrate; in at least one sub-pixel, the color filter structure layer includes at least a blocking structure, and the orthographic projection of the blocking structure on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor on the substrate.

[0075] In an exemplary embodiment, the channel region of the second transistor has a channel length, and the overlapping area of ​​the orthographic projection of the shielding structure onto the substrate and the orthographic projection of the channel region of the second transistor onto the substrate has a second length, the second length being 0.4 * channel length to 0.6 * channel length, wherein the channel length and the second length are dimensions in the first direction.

[0076] In an exemplary embodiment, the orthographic projection of the shielding structure onto the substrate does not overlap with the orthographic projection of the anode via onto the substrate.

[0077] Figure 4 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a repeating unit (four sub-pixels) in a bottom-emitting display substrate. As shown in Figure 4, in the direction parallel to the display substrate, at least one repeating unit may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged sequentially along a first direction X. In the direction perpendicular to the display substrate, the display substrate may include at least a driving structure layer disposed on a substrate, a color filter structure layer disposed on the side of the driving structure layer away from the substrate, and a light-emitting structure layer disposed on the side of the color filter structure layer away from the substrate. The driving structure layer of at least one sub-pixel may include a pixel driving circuit, the color filter structure layer of at least one sub-pixel may include a color filter layer and a blocking structure, and the light-emitting structure layer of at least one sub-pixel may include the anode of a light-emitting device, the anode of which is connected to the pixel driving circuit of the sub-pixel.

[0078] In an exemplary embodiment, at least one repeating unit may include a scan signal line 41, four data signal lines 61, two first power supply lines 62, and a compensation signal line 63, all of which are connected to the pixel driving circuits of the four sub-pixels. The shape of the scan signal line 41 may be a straight line or a broken line extending along the first direction X, and the shapes of the data signal line 61, the first power supply line 62, and the compensation signal line 63 may be a straight line or a broken line extending along the second direction Y.

[0079] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0080] In an exemplary embodiment, two first power lines 62 can be respectively disposed on both sides of the repeating unit in the first direction X, forming a one-to-two structure of the first power lines. A compensation signal line 63 can be disposed between the second sub-pixel P2 and the third sub-pixel P3, forming a one-to-four structure of the compensation signal line. Two of the four data signal lines 61 can be located between the compensation signal line 63 and one first power line 62, and the other two data signal lines 61 can be located between the compensation signal line 63 and another first power line 62.

[0081] In an exemplary embodiment, the pixel driving circuit for at least one sub-pixel may include a first transistor T1 as a data writing transistor, a second transistor T2 as a driving transistor, a third transistor T3 as a compensation transistor, and a transparent storage capacitor. The first transistor T1, the second transistor T2, and the third transistor T3 may each include an active layer, a gate electrode, a first electrode, and a second electrode, and the transparent storage capacitor may include a transparent first electrode plate and a transparent second electrode plate.

[0082] In an exemplary embodiment, in at least one repeating unit, the pixel driving circuits in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit, and the pixel driving circuits in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the repeating unit, the center line of the repeating unit being a broken line that bisects the repeating unit in the first direction X and extends along the second direction Y.

[0083] In an exemplary embodiment, in at least one repeating unit, the data signal line 61 and the first power line 62 in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit, the data signal line 61 in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the repeating unit, and the orthographic projection of the compensation signal line 63 on the substrate at least partially overlaps with the orthographic projection of the center line of the repeating unit on the substrate.

[0084] In an exemplary embodiment, in at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 41.

[0085] In an exemplary embodiment, in at least one repeating unit, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 in a plurality of sub-pixels are connected to the same scan signal line 41.

[0086] In an exemplary embodiment, in at least one pixel row, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 in a plurality of sub-pixels are connected to the same scan signal line 41.

[0087] In an exemplary embodiment, in at least one sub-pixel, the first electrode of the first transistor T1 is connected to the data signal line 61, the first electrode of the second transistor T2 is connected to the first power supply line 62, the first electrode of the third transistor T3 is connected to the compensation signal line 63, the second electrode of the first transistor T1 is connected to the gate electrode of the second transistor T2 and the second plate of the storage capacitor, respectively, and the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the first plate of the storage capacitor, respectively.

[0088] In an exemplary embodiment, at least one sub-pixel may further include a second connection electrode 52 as an anode connection electrode, the second electrode of the second transistor T2 is connected to the first electrode plate through the second connection electrode 52, and the second connection electrode 52 is connected to the anode of the light-emitting device through an anode via YV.

[0089] In an exemplary embodiment, the second transistor T2 may include at least a second active layer 32 and a second gate electrode 42. The second active layer 32 is shaped to extend along a first direction X into a strip shape, and the second gate electrode 42 is shaped to extend along a second direction Y into a strip shape. The orthographic projection of the second gate electrode 42 onto the substrate at least partially overlaps with the orthographic projection of the second active layer 32 onto the substrate, and the overlapping region forms the channel region 44 of the second transistor T2. The first region of the second active layer 32 is connected to the first power line 62, and the second region of the second active layer 32 is connected to the second connection electrode 52.

[0090] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the second connection electrode 52 on the substrate at least partially overlaps with the orthographic projection of the channel region 44 of the second transistor T2 on the substrate.

[0091] In an exemplary embodiment, the channel region 44 of the second transistor T2 may have a channel length L, and the overlapping region of the orthographic projection of the second connection electrode 52 on the substrate and the orthographic projection of the channel region 44 of the second transistor T2 on the substrate has a first length L1, where L1 = 0.4*L to 0.6*L. The channel length L and the first length L1 may be dimensions in the first direction X.

[0092] In an exemplary embodiment, the color filter structure layer of the first sub-pixel P1 may include at least a first filter layer 71 and a first blocking block 81 as a blocking structure. The first filter layer 71 is configured to allow the first sub-pixel P1 to emit green light, and the first blocking block 81 is configured to block the channel region of the second transistor T2 in the first sub-pixel P1. The orthographic projection of the first blocking block 81 on the substrate at least partially overlaps with the orthographic projection of the channel region 44 of the second transistor T2 in the first sub-pixel P1 on the substrate.

[0093] In an exemplary embodiment, the color filter structure layer of the second sub-pixel P2 may include at least a second filter layer 72 and a second blocking block 82 as a blocking structure. The second filter layer 72 is configured to allow the second sub-pixel P2 to emit red light, and the second blocking block 82 is configured to block the channel region of the second transistor T2 in the second sub-pixel P2. The orthographic projection of the second blocking block 82 on the substrate at least partially overlaps with the orthographic projection of the channel region 44 of the second transistor in the second sub-pixel P2 on the substrate.

[0094] In an exemplary embodiment, the color filter structure layer of the third sub-pixel P3 may include at least a third blocking block 83 as a blocking structure. The third blocking block 83 is configured to block the channel region of the second transistor T2 in the third sub-pixel P3. The orthographic projection of the third blocking block 83 on the substrate at least partially overlaps with the orthographic projection of the channel region 44 of the second transistor in the third sub-pixel P3 on the substrate.

[0095] In an exemplary embodiment, the color filter structure layer of the fourth sub-pixel P4 may include at least a third filter layer 73 and a fourth blocking block 84 as a blocking structure. The third filter layer 73 is configured to allow the fourth sub-pixel P4 to emit blue light, and the fourth blocking block 84 is configured to block the channel region of the second transistor T2 in the fourth sub-pixel P4. The orthographic projection of the fourth blocking block 84 on the substrate at least partially overlaps with the orthographic projection of the channel region 44 of the second transistor in the fourth sub-pixel P4 on the substrate.

[0096] In an exemplary embodiment, the materials of the first blocking block 81, the second blocking block 82, the third blocking block 83, and the fourth blocking block 84 are the same as the material of the second filter layer 72.

[0097] In an exemplary embodiment, the second filter layer 72, the second blocking block 82, and the third blocking block 83 can be an integral structure that is interconnected.

[0098] In an exemplary embodiment, at least one of the first blocking block 81, the second blocking block 82, the third blocking block 83, and the fourth blocking block 84 has a second length L2 in the overlapping region of its orthographic projection onto the substrate and the orthographic projection onto the substrate of the channel region 44 of the second transistor. L2 = 0.4*L to 0.6*L, and the second length L2 can be the dimension in the first direction X.

[0099] In an exemplary embodiment, at least one of the first shielding block 81, the second shielding block 82, the third shielding block 83, and the fourth shielding block 84 has an orthographic projection on the substrate that does not overlap with the orthographic projection of the anode via YV on the substrate.

[0100] In an exemplary embodiment, at least one of the first shielding block 81, the second shielding block 82, the third shielding block 83, and the fourth shielding block 84 has an orthographic projection on the substrate that does not overlap with the orthographic projection of the second connecting electrode 52 on the substrate.

[0101] In an exemplary embodiment, in at least one sub-pixel, the color filter structure layer may further include a fifth blocking block 85, the orthographic projection of the fifth blocking block 85 on the substrate at least partially overlapping the orthographic projections of the channel regions of the first transistor T1 and the third transistor T3 on the substrate.

[0102] In an exemplary embodiment, in at least one sub-pixel, the orthographic projections of the channel regions of the first transistor T1 and the third transistor T3 onto the substrate can be located within the range of the orthographic projection of the fifth occluding block 85 onto the substrate.

[0103] In an exemplary embodiment, the fifth occlusion block 85 in the first sub-pixel P1, the fifth occlusion block 85 in the second sub-pixel P2, the fifth occlusion block 85 in the third sub-pixel P3, and the fifth occlusion block 85 in the fourth sub-pixel P4 can be an interconnected integral structure.

[0104] In an exemplary embodiment, the material of the fifth occlusion block 85 in the first sub-pixel P1 to the fourth sub-pixel P4 can be the same as the material of the second filter layer 72.

[0105] In an exemplary embodiment, the second filter layer 72, the fifth occlusion block 85 in the first sub-pixel P1, the fifth occlusion block 85 in the second sub-pixel P2, the fifth occlusion block 85 in the third sub-pixel P3, and the fifth occlusion block 85 in the fourth sub-pixel P4 can be an integral structure that is interconnected.

[0106] Figure 5 is a cross-sectional view along direction AA in Figure 4. In a direction perpendicular to the display substrate, the display substrate may include at least: a first transparent conductive layer disposed on a substrate 200, a first conductive layer disposed on the side of the first transparent conductive layer away from the substrate 200, a first insulating layer 201 disposed on the side of the first conductive layer away from the substrate 200, a semiconductor layer disposed on the side of the first insulating layer 201 away from the substrate 200, a second insulating layer 202 disposed on the side of the semiconductor layer away from the substrate 200, a second conductive layer disposed on the side of the second insulating layer 202 away from the substrate 200, a third insulating layer 203 disposed on the side of the second conductive layer away from the substrate 200, a third conductive layer disposed on the side of the third insulating layer 203 away from the substrate 200, a fourth insulating layer 204 disposed on the side of the third conductive layer away from the substrate 200, a color filter structure layer disposed on the side of the fourth insulating layer 204 away from the substrate 200, a planarization layer 205 disposed on the side of the color filter structure layer away from the substrate 200, a second transparent conductive layer disposed on the side of the planarization layer 205 away from the substrate 200, and a pixel definition layer 206 disposed on the side of the second transparent conductive layer away from the substrate 200.

[0107] As shown in Figure 5, the first transparent conductive layer may include at least a connecting plate 12 and at least a shielding electrode 21, which is directly connected to the connecting plate 12. The semiconductor layer may include at least a second active layer 32, the orthographic projection of the second active layer 32 on the substrate at least partially overlapping the orthographic projection of the shielding electrode 21 on the substrate. The second conductive layer may include at least a second gate electrode 42, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlapping the orthographic projection of the second active layer 32 on the substrate, and the overlapping area forms the channel region of the second transistor T2. The third conductive layer may include at least a second connection electrode 52, a power connection electrode 56, a data signal line 61, and a compensation signal line 63. The second connection electrode 52 is connected to both the second region of the second active layer and the shielding electrode 21 through a via, and the power connection electrode 56 is connected to the first region of the second active layer through a via. The orthographic projection of the second connection electrode 52 on the substrate at least partially overlaps the orthographic projection of the channel region of the second transistor T2 on the substrate. The color filter structure layer may include at least a second blocking block 82 and a third blocking block 83. The orthographic projection of the second blocking block 82 on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor in the second sub-pixel P2 on the substrate. The orthographic projection of the third blocking block 83 on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor in the third sub-pixel P3 on the substrate. The second transparent conductive layer may include at least a second anode 92 and a third anode 93. The second anode 92 and the third anode 93 are respectively connected to the second connection electrode 52 of the sub-pixel through an anode via YV.

[0108] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film layer, coating the film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include coating the organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0109] In an exemplary embodiment, taking four sub-pixels (first sub-pixel P1, second sub-pixel P2, third sub-pixel P3 and fourth sub-pixel P4) as an example, the fabrication process of the display substrate may include the following operations.

[0110] (1) Forming a first transparent conductive layer pattern. In an exemplary embodiment, forming a first transparent conductive layer pattern may include: depositing a first transparent conductive film on a substrate, patterning the first transparent conductive film using a patterning process, and forming a first transparent conductive layer pattern on the substrate, as shown in FIG6. In an exemplary embodiment, the first transparent conductive layer may be referred to as an ITO1 layer.

[0111] In an exemplary embodiment, the first transparent conductive layer pattern of each sub-pixel in the display substrate may include at least a first electrode plate 11 of a storage capacitor, a connecting plate 12, a connecting line 13, a compensation pad 14, and a power pad 15.

[0112] In an exemplary embodiment, the first electrode plate 11 may be rectangular in shape, and the corners of the rectangle may be chamfered, raised, or grooved. The edges of the rectangle may be folded lines. The first electrode plate 11 may be disposed in the middle region of the second direction Y of the sub-pixel. The first electrode plate 11 is configured as a transparent electrode plate to form a transparent storage capacitor.

[0113] In an exemplary embodiment, the connecting plate 12 can be block-shaped (such as rectangular), and the corners of the block shape can be chamfered, protruded or grooved, and the edges of the rectangular shape can be folded lines. The connecting plate 12 can be disposed on one side of the first electrode plate 11 in the second direction Y and connected to the first electrode plate 11. The connecting plate 12 is configured to be connected to the subsequently formed shielding layer.

[0114] In an exemplary embodiment, the connecting line 13 can be a strip extending along the second direction Y. The connecting line 13 can be disposed on the side of the first electrode plate 11 away from the connecting plate 12 and connected to the first electrode plate 11. A connecting block 13-1 can be disposed at the end of the connecting line 13 away from the first electrode plate 11. The connecting block 13-1 can be block-shaped (such as rectangular) and connected to the connecting line 13. The connecting block 13-1 is configured to be connected to the subsequently formed interlayer connection electrode.

[0115] In an exemplary embodiment, in at least one sub-pixel, the first electrode plate 11, the connecting plate 12, and the connecting line 13 can be an integral structure that is interconnected.

[0116] In an exemplary embodiment, the compensation pad 14 may be block-shaped (e.g., rectangular) and may be disposed on the side of the connecting line 13 away from the first electrode plate 11.

[0117] In an exemplary embodiment, the power pad 15 may be block-shaped (e.g., rectangular) and may be disposed on the side of the connecting plate 12 away from the first electrode plate 11.

[0118] In an exemplary embodiment, in at least one repeating unit, the first transparent conductive layer in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit, and the first transparent conductive layer in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the repeating unit.

[0119] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a first conductive film on a substrate on which the aforementioned pattern is formed, patterning the first conductive film using a patterning process, and forming a first conductive layer pattern on a transparent conductive layer, as shown in Figures 7A and 7B, where Figure 7B is a planar schematic diagram of the first conductive layer in Figure 7A. In an exemplary embodiment, the first conductive layer may be referred to as a shielding metal (SHL) layer.

[0120] In an exemplary embodiment, the first conductive layer pattern in each sub-pixel of the display substrate may include at least a shielding electrode 21 and an interlayer connection electrode 22.

[0121] In an exemplary embodiment, the shielding electrode 21 can be block-shaped (e.g., rectangular). The corners of the block shape can be chamfered, protruded, or grooved, and the edges of the rectangular shape can be zigzag lines. The shielding electrode 21 can be disposed in the area where the connecting plate 12 is located. The orthographic projection of the shielding electrode 21 on the substrate at least partially overlaps with the orthographic projection of the connecting plate 12 on the substrate, and directly overlaps with the connecting plate 12. The shielding electrode 21 is configured to provide shielding for the second transistor T2, preventing light from affecting the channel region of the second transistor T2, reducing leakage current, thereby preventing the influence of light on the transistor characteristics and ensuring the electrical performance of the second transistor T2.

[0122] In an exemplary embodiment, the orthographic projection of the shielding electrode 21 on the substrate may be within the range of the orthographic projection of the connecting plate 12 on the substrate.

[0123] In an exemplary embodiment, the interlayer connection electrode 22 may be block-shaped (e.g., rectangular) and may be disposed in the region where the connection block 13-1 of the connection line 13 is located. The orthographic projection of the interlayer connection electrode 22 on the substrate at least partially overlaps with the orthographic projection of the connection block 13-1 on the substrate and directly overlaps with the connection block 13-1. The interlayer connection electrode 22 is configured to be connected to the fourth connection electrode formed subsequently.

[0124] In an exemplary embodiment, the orthographic projection of the connecting block 13-1 on the substrate may be within the range of the orthographic projection of the interlayer connecting electrode 22 on the substrate.

[0125] In an exemplary embodiment, in at least one repeating unit, the first conductive layer may further include a compensation connection line 23 and a power connection line 24.

[0126] In an exemplary embodiment, the compensation connection line 23 can be a strip extending along the first direction X, spanning across some adjacent sub-pixels, and located on the side of the interlayer connection electrode 22 away from the first electrode plate 11. The compensation connection line 23 can be multiplexed as a compensation lateral connection line, providing a compensation signal to the third transistor T3 of the sub-pixel by connecting with subsequently formed compensation signal lines. For example, the compensation connection line 23 can be disposed in the first sub-pixel P1 and the second sub-pixel P2. Alternatively, the compensation connection line 23 can be disposed in the third sub-pixel P3 and the fourth sub-pixel P4.

[0127] In an exemplary embodiment, a compensation connecting block 23-1 may be provided at the end of the compensation connecting line 23. The compensation connecting block 23-1 may be block-shaped (such as rectangular) and connected to the compensation connecting line 23. The orthographic projection of the compensation connecting block 23-1 on the substrate and the orthographic projection of the compensation pad block 14 on the substrate at least partially overlap.

[0128] In an exemplary embodiment, the compensation connection block 23-1 may be disposed in each sub-pixel, and the orthographic projection of the compensation connection block 23-1 on the substrate may include the orthographic projection of the compensation pad block 14 on the substrate.

[0129] In an exemplary embodiment, the power connection line 24 can be a strip extending along the first direction X, spanning across some adjacent sub-pixels, and located on the side of the shielding electrode 21 away from the first electrode plate 11. The power connection line 24 can be multiplexed as a power lateral connection line, providing a first power signal to the second transistor T2 of the sub-pixel by connecting to a subsequently formed first power line.

[0130] In an exemplary embodiment, a power connection block 24-1 may be provided at the end of the power connection line 24. The power connection block 24-1 may be block-shaped (such as rectangular) and connected to the power connection line 24. The orthographic projection of the power connection block 24-1 on the substrate at least partially overlaps with the orthographic projection of the power pad block 15 on the substrate.

[0131] In an exemplary embodiment, the power connection block 24-1 may be disposed in each sub-pixel, and the orthographic projection of the power connection block 24-1 on the substrate may include the orthographic projection of the power pad block 15 on the substrate.

[0132] In an exemplary embodiment, in at least one repeating unit, the first conductive layer in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit, and the first conductive layer in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the repeating unit.

[0133] (3) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the semiconductor film by a patterning process to form a first insulating layer covering the first conductive layer, and a semiconductor layer pattern disposed on the first insulating layer, as shown in Figures 8A and 8B, where Figure 8B is a planar schematic diagram of the semiconductor layer in Figure 8A.

[0134] In an exemplary embodiment, the semiconductor layer pattern in each sub-pixel of the display substrate may include at least a first active layer 31, a second active layer 32, a third active layer 33, an active connecting strip 34, and a second electrode plate 35.

[0135] In an exemplary embodiment, the second electrode 35 may be rectangular in shape, with chamfers, protrusions, or grooves at the corners, and the edges of the rectangle may be folded lines. The orthographic projection of the second electrode 35 onto the substrate at least partially overlaps with the orthographic projection of the first electrode 11 onto the substrate. The second electrode 35 is configured to form another transparent electrode of a transparent storage capacitor, and the first electrode 11 and the second electrode 35 together form a transparent storage capacitor.

[0136] In an exemplary embodiment, the first active layer 31 may be in the shape of an "I" and may be disposed on the side of the second electrode plate 35 away from the connecting plate 12. The first active layer 31 may serve as the active layer of the first transistor T1.

[0137] In an exemplary embodiment, the second active layer 32 may be in the shape of an "L" and may be disposed on the side of the second electrode plate 35 away from the first active layer 31. The second active layer 32 may serve as the active layer of the second transistor T2.

[0138] In an exemplary embodiment, the third active layer 33 may be in the shape of an "I" and may be disposed on one side of the first active layer 31 in the first direction X or the opposite direction of the first direction X. The third active layer 33 may serve as the active layer of the third transistor T3.

[0139] In an exemplary embodiment, the active connecting strip 34 can be a strip shape extending along the second direction Y, and can be disposed between the first active layer 31 and the second electrode plate 35, with both ends of the active connecting strip 34 connected to the first active layer 31 and the second electrode plate 35 respectively.

[0140] In an exemplary embodiment, in at least one sub-pixel, the first active layer 31, the active connecting strip 34, and the second electrode plate 35 can be an integral structure that is interconnected.

[0141] In an exemplary embodiment, the first active layer 31, the second active layer 32, and the third active layer 33 may each include a channel region and a first region and a second region located on both sides of the channel region.

[0142] In an exemplary embodiment, the first region 31-1 of the first active layer may be located on the side of the channel region away from the second electrode plate 35, and the second region 31-2 of the first active layer may be located on the side of the channel region close to the second electrode plate 35, and the active connecting strip 34 is connected.

[0143] In an exemplary embodiment, the first region 32-1 of the second active layer and the second region 32-2 of the second active layer can be located on both sides of the channel region in the first direction X, and the orthogonal projection of the channel region of the second active layer and the second region 32-2 of the second active layer on the substrate can be located within the range of the orthogonal projection of the shielding electrode 21 on the substrate. The shielding electrode 21 can shield the channel region of the second transistor T2 from below, avoid light from affecting the channel, reduce leakage current, and thus avoid the influence of light on the characteristics of the oxide transistor.

[0144] In an exemplary embodiment, in the first sub-pixel P1 and the fourth sub-pixel P4, the orthographic projections of the channel region of the second active layer and the second region 32-2 of the second active layer onto the substrate are within the range of the orthographic projection of the shielding electrode 21 onto the substrate. The first region 32-1 of the second active layer may include at least a first portion 32A and a second portion 32B, and the second portion 32B may be located between the first portion 32A and the channel region of the second active layer. The orthographic projection of the second portion 32B onto the substrate may be within the range of the orthographic projection of the shielding electrode 21 onto the substrate, and the orthographic projection of the first portion 32A onto the substrate at least partially overlaps with the orthographic projection of the shielding electrode 21 onto the substrate.

[0145] In an exemplary embodiment, the orthographic projection of a portion of the first portion 32A (the region near the second portion 32B) onto the substrate overlaps with the orthographic projection of the shielding electrode 21 onto the substrate, while the orthographic projection of another portion of the first portion 32A (the region away from the second portion 32B) onto the substrate does not overlap with the orthographic projection of the shielding electrode 21 onto the substrate, thus the first portion 32A includes a ramp structure.

[0146] In an exemplary embodiment, the first portion 32A may have a first width B1, and the second portion 32B may have a second width B2. The first width B1 may be greater than the second width B2, and the first width B1 and the second width B2 may be dimensions in the second direction Y.

[0147] In an exemplary embodiment, the semiconductor layer is relatively thin. If the first conductive layer is relatively thick, the climbing structure of the semiconductor layer climbing onto the first conductive layer is prone to semiconductor layer breakage, leading to defects. This disclosure improves the climbing ability of the first portion 32A by widening the climbing structure, thereby effectively preventing semiconductor layer breakage and reducing defects.

[0148] In an exemplary embodiment, in the second sub-pixel P2 and the third sub-pixel P3, the orthogonal projection of the second active layer 32 onto the substrate can be located within the range of the orthogonal projection of the shielding electrode 21 onto the substrate. That is, the first region 32-1, the second region 32-2, and the channel region of the second active layer all overlap with the shielding electrode 21. In this way, the first region of the second active layer in the second sub-pixel P2 and the third sub-pixel P3 does not contain a ramp structure, which can minimize the risk of semiconductor layer breakage and reduce the occurrence of defects.

[0149] This disclosure eliminates the ramp structure in the second sub-pixel P2 and the third sub-pixel P3, and widens the ramp structure in the first sub-pixel P1 and the fourth sub-pixel P4. This not only avoids defects but also increases the thickness of the first conductive layer, improves the shielding capability of the shielding electrode, and ensures the stability of the pixel driving circuit.

[0150] In an exemplary embodiment, the first region 33-1 of the third active layer may be located on the side of the channel region away from the second electrode plate 35, and the second region 33-2 of the third active layer may be located on the side of the channel region closer to the second electrode plate 35. The orthographic projection of the first region 33-1 of the third active layer on the substrate at least partially overlaps with the orthographic projection of the compensation connection block 23-1 of the compensation connection line 23 on the substrate, and the orthographic projection of the second region 33-2 of the third active layer 33 on the substrate at least partially overlaps with the orthographic projection of the interlayer connection electrode 22 on the substrate.

[0151] In an exemplary embodiment, the channel region of the third active layer may have a third width, and the first region 33-1 and the second region 33-2 of the third active layer may have a fourth width, which may be greater than the third width. The third width and the fourth width may be dimensions in the first direction X.

[0152] In an exemplary embodiment, the first region and the second region of the third active layer also include a ramp structure. This disclosure enhances the ramping capability by setting the widths of the first region and the second region of the third active layer to be greater than the width of the channel region of the third active layer, thereby widening the ramp structure. This effectively prevents semiconductor layer breakage and reduces the occurrence of defects.

[0153] In an exemplary embodiment, in at least one repeating unit, the semiconductor layers in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit, and the semiconductor layers in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the repeating unit.

[0154] In an exemplary embodiment, the semiconductor layer may be a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0155] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a second insulating layer covering the semiconductor layer; and a second conductive layer pattern disposed on the second insulating layer, as shown in Figures 9A and 9B, where Figure 9B is a planar schematic diagram of the second conductive layer in Figure 9A. In an exemplary embodiment, the second conductive layer may be referred to as a gate metal (GATE) layer.

[0156] In an exemplary embodiment, the second conductive layer pattern in each sub-pixel of the display substrate may include at least a scan signal line 41 and a second gate electrode 42.

[0157] In an exemplary embodiment, the shape of the scan signal line 41 can be a straight line or a broken line extending along the first direction X, and it can be located between the compensation connection line 23 and the interlayer connection electrode 22. The orthographic projection of the scan signal line 41 on the substrate at least partially overlaps with the orthographic projections of the first active layer 31 and the third active layer 33 on the substrate. The area where the scan signal line 41 intersects with the first active layer 31 can serve as the gate electrode of the first transistor T1, and the area where the scan signal line 41 intersects with the third active layer 33 can serve as the gate electrode of the third transistor T3.

[0158] In an exemplary embodiment, in at least one sub-pixel, a scan signal line 41 can simultaneously serve as the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3. The scan signal line 41 can control the simultaneous conduction or simultaneous deactivation of the first transistor T1 and the third transistor T3 in the sub-pixel.

[0159] In an exemplary embodiment, in at least one repeating unit, a scan signal line 41 can simultaneously serve as the gate electrode of the four first transistors T1 and the gate electrode of the four third transistors T3 in the four sub-pixels. The scan signal line 41 can control the simultaneous on or off of the four first transistors T1 and the four third transistors T3 in the repeating unit.

[0160] In an exemplary embodiment, in at least one pixel row of multiple sub-pixels, a scan signal line 41 can simultaneously serve as the gate electrode of multiple first transistors T1 and multiple third transistors T3, and the scan signal line 41 can control the simultaneous on or off of multiple first transistors T1 and multiple third transistors T3 in the pixel row.

[0161] In an exemplary embodiment, the second gate electrode 42 may be in the shape of an "I" or an "L" and may be disposed on the side of the second electrode plate 35 away from the scan signal line 41. The orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second active layer 32 on the substrate. The overlapping area forms the channel region 44 of the second transistor T2. The second gate electrode 42 may serve as the gate electrode of the second transistor T2.

[0162] In an exemplary embodiment, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 35 on the substrate.

[0163] In an exemplary embodiment, the shape of the second gate electrode 42 in the first sub-pixel P1 and the fourth sub-pixel P4 can be "I" shaped, and the shape of the second gate electrode 42 in the second sub-pixel P2 and the third sub-pixel P3 can be "L" shaped.

[0164] In an exemplary embodiment, in at least one sub-pixel, the channel region 44 of the second transistor T2 may have a channel length L, which may be a dimension in the first direction X.

[0165] In an exemplary embodiment, in at least one repeating unit, the second conductive layer may further include two auxiliary power lines 43. The auxiliary power lines 43 may be strip-shaped extending along the second direction Y. The two auxiliary power lines 43 may be respectively disposed in the first sub-pixel P1 and the fourth sub-pixel P4. The auxiliary power lines 43 are configured to connect with the subsequently formed first power lines to form a double-layer trace.

[0166] In an exemplary embodiment, the auxiliary power line 43 in the first sub-pixel P1 may be located on the side opposite to the first direction X of the second electrode plate 35, and the auxiliary power line 43 in the fourth sub-pixel P4 may be located on the side of the first direction X of the second electrode plate 35.

[0167] In an exemplary embodiment, the process further includes a conductor-enhancing process. The conductor-enhancing process involves, after forming the second conductive layer pattern, performing plasma treatment using the second conductive layer as a shield. The semiconductor layer shielded by the second conductive layer serves as the channel region of the transistor, while the semiconductor layer not shielded by the second conductive layer is processed into a conductor-enhanced layer, forming a conductor-enhanced second electrode 35 and conductor-enhanced source / drain regions.

[0168] In an exemplary embodiment, in at least one repeating unit, the second conductive layers in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit, and the second conductive layers in the second sub-pixel P2 and the third sub-pixel P3 can be arranged substantially symmetrically with respect to the center line of the repeating unit.

[0169] (5) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, and patterning the third insulating film using a patterning process to form a third insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG10.

[0170] In an exemplary embodiment, the plurality of vias in each sub-pixel of the display substrate may include at least: a first via V1 to an eighth via V8.

[0171] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer onto the substrate. The third and second insulating layers within the first via V1 are etched away, exposing the surface of the first region of the first active layer. The first via V1 is configured to connect subsequently formed data signal lines to the first region of the first active layer through the via.

[0172] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the second region of the first active layer onto the substrate. The third insulating layer and the second insulating layer within the second via V2 are etched away, exposing the surface of the second region of the first active layer. The second via V2 is configured to connect a subsequently formed third connection electrode to the second region of the first active layer through the via.

[0173] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is within the range of the orthographic projection of the first region of the second active layer on the substrate. The third insulating layer and the second insulating layer within the third via V3 are etched away, exposing the surface of the first region of the second active layer. The third via V3 is configured to allow a subsequently formed first power line or power connection electrode to be connected to the first region of the second active layer through the via.

[0174] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate at least partially overlaps with the orthographic projections of the second region of the second active layer and the shielding electrode 21 onto the substrate, and the fourth via V4 simultaneously exposes the surfaces of the second region of the second active layer and the shielding electrode 21. The fourth via V4 is a transition via consisting of two half-holes. In one half-hole, the third and second insulating layers are etched away, exposing the surface of the second region of the first active layer; in the other half-hole, the third, second, and first insulating layers are etched away, exposing the surface of the shielding electrode 21. In an exemplary embodiment, the fourth via V4 is configured to allow a subsequently formed second connection electrode to be simultaneously connected to the second region of the second active layer and the shielding electrode 21 through this via.

[0175] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate at least partially overlaps with the orthographic projections of the first region of the third active layer and the compensation connection block 23-1 of the compensation connection line 23 onto the substrate. The fifth via V5 simultaneously exposes the surfaces of the first region of the third active layer and the compensation connection block 23-1. The fifth via V5 is a transition via consisting of two half-holes. The third and second insulating layers within one half-hole are etched away, exposing the surface of the first region of the third active layer. The third, second, and first insulating layers within the other half-hole are etched away, exposing the surface of the compensation connection block 23-1. In an exemplary embodiment, the fifth via V5 is configured to allow a subsequently formed fifth connection electrode to be simultaneously connected to the first region of the third active layer and the compensation connection block 23-1 through this via.

[0176] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate at least partially overlaps with the orthographic projections of the second region of the third active layer and the interlayer connection electrode 22 onto the substrate. The sixth via V6 simultaneously exposes the surfaces of the second region of the third active layer and the interlayer connection electrode 22. The sixth via V6 is a transition via consisting of two half-holes. In one half-hole, the third and second insulating layers are etched away, exposing the surface of the second region of the third active layer. In the other half-hole, the third, second, and first insulating layers are etched away, exposing the surface of the interlayer connection electrode 22. In an exemplary embodiment, the sixth via V6 is configured to allow a subsequently formed fourth connection electrode to be simultaneously connected to the second region of the third active layer and the interlayer connection electrode 22 through this via.

[0177] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the range of the orthographic projections of the second electrode 35 and the second gate electrode 42 onto the substrate. The seventh via V7 simultaneously exposes the surfaces of both the second electrode 35 and the second gate electrode 42. The seventh via V7 is a transition via consisting of two half-holes. In one half-hole, the third and second insulating layers are etched away, exposing the surface of the second electrode 35; in the other half-hole, the third insulating layer is etched away, exposing the surface of the second gate electrode 42. In this exemplary embodiment, the seventh via V7 is configured to allow a subsequently formed first connection electrode to be simultaneously connected to the second electrode 35 and the second gate electrode 42 through this via.

[0178] In an exemplary embodiment, in the seventh via V7, the orthographic projection of the second gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second electrode 35 on the substrate. Studies have shown that if the second electrode 35 and the second gate electrode 42 within the seventh via V7 do not overlap, over-etching is likely to occur during the dry etching process of the via. Over-etching exposes the shielding electrode 21, causing the subsequently formed first connection electrode to connect with the shielding electrode 21, resulting in a short circuit and causing dark spot defects. This disclosure effectively avoids short circuits and dark spot defects by ensuring that the second electrode 35 and the second gate electrode 42 overlap within the first transition via.

[0179] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is within the range of the orthographic projection of the power connection block 24-1 of the power connection line 24 on the substrate. The third insulating layer, the second insulating layer and the first insulating layer in the eighth via V8 are etched away to expose the surface of the power connection block 24-1. The eighth via V8 is configured to allow the subsequently formed first power line or power connection electrode to be connected to the power connection block 24-1 through the via.

[0180] In an exemplary embodiment, at least one repeating unit may further include a ninth via V9. The orthographic projection of the ninth via V9 onto the substrate lies within the range of the orthographic projection of the auxiliary power line 43 onto the substrate. The third insulating layer within the ninth via V9 is etched away, exposing the surface of the auxiliary power line 43. The ninth via V9 is configured to allow a subsequently formed first power line to be connected to the auxiliary power line 43 through the via.

[0181] In an exemplary embodiment, a ninth via V9 can be disposed in either the first sub-pixel P1 or the fourth sub-pixel P4. Multiple ninth vias V9 can be present to increase connection reliability.

[0182] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the third conductive thin film using a patterning process to form a third conductive layer disposed on a third insulating layer, as shown in Figures 11A and 11B, where Figure 11B is a planar schematic diagram of the third conductive layer in Figure 11A. In an exemplary embodiment, the third conductive layer may be referred to as a source / drain metal (SD) layer.

[0183] In an exemplary embodiment, the third conductive layer pattern in each sub-pixel of the display substrate includes at least: a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, and a data signal line 61.

[0184] In an exemplary embodiment, the first connecting electrode 51 can be a strip extending along the second direction Y. The first connecting electrode 51 is connected to the second electrode plate 35 and the second gate electrode 42 simultaneously through the seventh via V7, so that the gate electrode of the second transistor T2 and the second electrode plate 35 of the storage capacitor have the same potential. Since the second gate electrode 42 and the second electrode plate 35 overlap in the seventh via V7, the seventh via V7 will not be over-etched and expose the shielding electrode 21, thus effectively avoiding short circuits between the second gate electrode 42 and the second electrode plate 35 and the shielding electrode 21, and effectively avoiding dark spot defects.

[0185] In an exemplary embodiment, the second connection electrode 52 can be block-shaped (e.g., rectangular). The corners of the rectangle can be chamfered, raised, or grooved, and the edges can be zigzag lines. The second connection electrode 52 is connected to both the second region of the second active layer and the shielding electrode 21 via the fourth via V4. Since the shielding electrode 21 overlaps with the connecting plate 12, and the connecting plate 12 is connected to the first electrode plate 11, the second connection electrode 52 ensures that the second electrode of the second transistor T2 and the first electrode plate 11 of the storage capacitor have the same potential at the second node. In an exemplary embodiment, the second connection electrode 52 can serve as the anode connection electrode of this disclosure.

[0186] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the second connection electrode 52 on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor T2 on the substrate. The second connection electrode 52 can block the second transistor T2 from above, preventing light from affecting the channel, reducing leakage current, and thus preventing the influence of light on the characteristics of the oxide transistor.

[0187] In an exemplary embodiment, in at least one sub-pixel, the overlapping region of the orthographic projection of the second connection electrode 52 onto the substrate and the orthographic projection of the channel region of the second transistor T2 onto the substrate may have a first length L1, which may be approximately 0.4L to 0.6L, and the first length L1 may be a dimension in the first direction X.

[0188] In an exemplary embodiment, the third connecting electrode 53 can be block-shaped (e.g., rectangular), and is connected to the second region of the first active layer through the second via V2. Since the second region of the first active layer is connected to the second electrode 35 through the active connecting strip 34, the third connecting electrode 53 enables the second electrode of the first transistor T1 and the second electrode 35 of the storage capacitor to have the same potential at the first node.

[0189] In an exemplary embodiment, since the first connection electrode 51 realizes that the gate electrode of the second transistor T2 and the second plate 35 of the storage capacitor have the same potential, and the third connection electrode 53 realizes that the second electrode of the first transistor T1 and the second plate 35 of the storage capacitor have the same potential, the first connection electrode 51 and the third connection electrode 53 realize that the second electrode of the first transistor T1, the gate electrode of the second transistor T2 and the second plate 35 of the storage capacitor have the same potential, that is, the potential of the first node N1 in the pixel driving circuit.

[0190] In an exemplary embodiment, the fourth connection electrode 54 can be a strip shape extending along the second direction Y. The fourth connection electrode 54 is simultaneously connected to the second region of the third active layer and the interlayer connection electrode 22 through the sixth via V6. Since the interlayer connection electrode 22 is connected to the connection line 13, and the connection line 13 is connected to the first electrode plate 11, the fourth connection electrode 54 enables the second electrode of the third transistor T3 and the first electrode plate 11 of the storage capacitor to have the same potential.

[0191] In an exemplary embodiment, since the second connection electrode 52 enables the second electrode of the second transistor T2 and the first plate 11 of the storage capacitor to have the same potential, and the fourth connection electrode 54 enables the second electrode of the third transistor T3 and the first plate 11 of the storage capacitor to have the same potential, the second connection electrode 52 and the fourth connection electrode 54 enable the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first plate 11 of the storage capacitor to have the same potential, that is, the potential of the second node N2 in the pixel driving circuit.

[0192] In an exemplary embodiment, the fifth connection electrode 55 can be a strip shape extending along the second direction Y. The fifth connection electrode 55 is connected to both the first region of the third active layer and the compensation connection line 23 through the fifth via V5. Since the compensation connection line 23 is configured to be connected to the compensation signal line, the fifth connection electrode 55 enables the compensation signal line to write the compensation signal to the first pole of the third transistor T3 of each sub-pixel.

[0193] In an exemplary embodiment, the data signal line 61 can be a zigzag line extending along the second direction Y of the main body. The data signal line 61 is connected to the first region of the first active layer through the first via V1 in each sub-pixel, so that the data signal line 61 writes the data signal into the first pole of the first transistor T1 in each sub-pixel.

[0194] In an exemplary embodiment, in the first sub-pixel P1 and the third sub-pixel P3, the data signal line 61 can be disposed on one side of the storage capacitor (first electrode 11 and second electrode 35) in the first direction X. In the second sub-pixel P2 and the fourth sub-pixel P4, the data signal line 61 can be disposed on the side opposite to the first direction X of the storage capacitor. The data signal line 61 is a zigzag shape, which not only facilitates the layout of the pixel structure but also reduces parasitic capacitance.

[0195] In an exemplary embodiment, the third conductive layer of at least one repeating unit may further include a power connection electrode 56, a first power line 62, and a compensation signal line 63.

[0196] In an exemplary embodiment, the shape of the first power line 62 can be a straight line or a broken line extending along the second direction Y. On one hand, the first power line 62 is connected to the first region of the second active layer in the first sub-pixel P1 and the fourth sub-pixel P4 through the third via V3, enabling the first power line 62 to write the first power signal into the first terminal of the second transistor T2 in the first sub-pixel P1 and the fourth sub-pixel P4. On the other hand, the first power line 62 is connected to the power connection block 24-1 in the first sub-pixel P1 and the fourth sub-pixel P4 through the eighth via V8, enabling the transmission of the first power signal to the power connection line 24. The power connection line 24 can then transmit the first power signal to the second sub-pixel P2 and the third sub-pixel P3 respectively. Furthermore, the first power line 62 is connected to the auxiliary power line 43 through the ninth via V9. The first power line 62 and the auxiliary power line 43 form a double-layer trace, which ensures the reliability of the first power signal transmission and reduces the resistance of the first power line.

[0197] In an exemplary embodiment, the first power line 62 is disposed on the side of the first sub-pixel P1 away from the second sub-pixel P2 and the side of the fourth sub-pixel P4 away from the third sub-pixel P3, which not only facilitates the layout of the pixel structure but also reduces parasitic capacitance.

[0198] In an exemplary embodiment, the power connection electrode 56 can be a strip extending along the second direction Y, and can be respectively disposed in the second sub-pixel P2 and the third sub-pixel P3. The first end of the power connection electrode 56 is connected to the first region of the second active layer through the third via V3 in the second sub-pixel P2 and the third sub-pixel P3, and the second end of the power connection electrode 56 is connected to the power connection block 24-1 through the eighth via V8 in the second sub-pixel P2 and the third sub-pixel P3. Since the power connection block 24-1 is connected to the power connection line 24, and the power connection line 24 is connected to the first power line 62, the first power line 62 writes the first power signal into the first electrode of the second transistor T2 in the second sub-pixel P2 and the third sub-pixel P3.

[0199] In an exemplary embodiment, the first power line 62 in the first sub-pixel P1 and the fourth sub-pixel P4 can be connected to the first region of the second active layer through the third via V3, and simultaneously connected to one end of the power connection line 24 through the eighth via V8. The power connection electrode 56 in the second sub-pixel P2 and the third sub-pixel P3 can be connected to the first region of the second active layer through the third via V3, and simultaneously connected to the other end of the power connection line 24. That is, the first power line 62 in the first sub-pixel P1 is connected to the first region of the second active layer in the second sub-pixel P2 through the power connection line 24 and the power connection electrode 56, and the first power line 62 in the fourth sub-pixel P4 is connected to the first region of the second active layer in the third sub-pixel P3 through the power connection line 24 and the power connection electrode 56. Thus, the first power line 62 in the first sub-pixel P1 can provide power signals to the pixel driving circuits in the first sub-pixel P1 and the second sub-pixel P2, and the first power line 62 in the fourth sub-pixel P4 can provide power signals to the pixel driving circuits in the third sub-pixel P3 and the fourth sub-pixel P4. This disclosure achieves the writing of power signals into the second transistor T2 of four sub-pixels by setting two power connection lines 24 extending along the first direction X and two first power lines 62 extending along the second direction Y in the repeating unit, forming a one-to-two structure of the first power lines.

[0200] In an exemplary embodiment, the compensation signal line 63 can be a straight line or a broken line extending along the second direction Y of the main body, and can be disposed between the second sub-pixel P2 and the third sub-pixel P3. Two compensation connecting strips 64 can be disposed on the compensation signal line 63, and the two compensation connecting strips 64 can be respectively disposed on both sides of the compensation signal line 63 in the first direction X. The first ends of the two compensation connecting strips 64 are connected to the compensation signal line 63, and the second ends of the two compensation connecting strips 64 are respectively connected to the fifth connecting electrodes 55 in the second sub-pixel P2 and the third sub-pixel P3. Since one compensation connecting line 23 is connected to the first electrode of the third transistor T3 in the first sub-pixel P1 and the second sub-pixel P2 respectively through the fifth connecting electrode 55, and the other compensation connecting line 23 is connected to the first electrode of the third transistor T3 in the third sub-pixel P3 and the fourth sub-pixel P4 respectively through the fifth connecting electrode 55, one compensation signal line 63 can provide compensation signals to the pixel driving circuits of four sub-pixels, forming a one-to-four structure of the compensation signal line.

[0201] This disclosure achieves the following by setting a compensation signal line 63 extending along the second direction Y and two compensation connection lines 23 extending along the first direction X in the repeating unit: a compensation signal line 63 writes the compensation signal into the third transistor T3 of the four sub-pixels respectively. This ensures that the RC delay of the compensation signal is basically the same before it is written into the transistor, thus ensuring display uniformity.

[0202] In an exemplary embodiment, in at least one repeating unit, the compensation signal line 63, the fifth connecting electrode 55 and the compensation connecting strip 64 in the second sub-pixel P2, and the fifth connecting electrode 55 and the compensation connecting strip 64 in the third sub-pixel P3 can be an integral structure that is interconnected.

[0203] In an exemplary embodiment, the third conductive layers in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit, and the third conductive layers in the second sub-pixel P2 and the third sub-pixel P3 can also be arranged substantially symmetrically with respect to the center line of the repeating unit. For example, the positions and shapes of the first connecting electrode 51 to the fifth connecting electrode 55, the power connecting electrode 56, the first power line 62, and the data signal line 61 in the first sub-pixel P1 and the fourth sub-pixel P4 can be arranged substantially symmetrically with respect to the center line of the repeating unit. Similarly, the positions and shapes of the first connecting electrode 51 to the fifth connecting electrode 55, the power connecting electrode 56, the first power line 62, and the data signal line 61 in the second sub-pixel P2 and the third sub-pixel P3 can also be arranged substantially symmetrically with respect to the center line of the repeating unit.

[0204] (7) Forming a color filter structure layer pattern. In an exemplary embodiment, forming a color filter structure layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed to form a fourth insulating layer covering the third conductive layer. Subsequently, a first filter film is coated, and the first filter film is patterned using a patterning process to form a first filter layer. Subsequently, a second filter film is coated, and the second filter film is patterned using a patterning process to form a second filter layer. Subsequently, a third filter film is coated, and the third filter film is patterned using a patterning process to form a third filter layer, as shown in Figures 12A and 12B, where Figure 12B is a planar schematic diagram of the color filter layer in Figure 12A.

[0205] In an exemplary embodiment, the color filter structure layer pattern in each repeating unit of the display substrate may include at least a first filter layer 71, a second filter layer 72, a third filter layer 73, a first blocking block 81, a second blocking block 82, a third blocking block 83, a fourth blocking block 84, and a fifth blocking block 85.

[0206] In an exemplary embodiment, the first filter layer 71 can be block-shaped (e.g., rectangular), with chamfered, raised, or recessed corners, and its edges can be zigzag lines. It can be disposed within the first sub-pixel P1. In an exemplary embodiment, the first filter layer 71 can be a green color filter layer that transmits green light, configured to cause the first sub-pixel P1 to emit green light.

[0207] In an exemplary embodiment, the second filter layer 72 can be block-shaped (e.g., rectangular), with chamfered, raised, or recessed corners and zigzag edges, and can be disposed in the second sub-pixel P2. In an exemplary embodiment, the second filter layer 72 can be a red color filter layer that transmits red light, configured to cause the second sub-pixel P2 to emit red light.

[0208] In an exemplary embodiment, the third filter layer 73 can be block-shaped (e.g., rectangular), with chamfered, raised, or recessed corners and zigzag edges, and can be disposed in the fourth sub-pixel P4. In an exemplary embodiment, the third filter layer 73 can be a blue color filter layer that transmits blue light, configured to cause the fourth sub-pixel P4 to emit blue light.

[0209] In an exemplary embodiment, the shape of the first blocking block 81, which serves as the blocking structure, can be block-shaped (such as rectangular). The corners of the rectangular shape can be chamfered, protruded, or grooved, and the edges of the rectangular shape can be broken lines. The first blocking block 81 can be disposed in the first sub-pixel P1 and located on one side of the second direction Y of the first filter layer 71. The orthographic projection of the first blocking block 81 on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor T2 in the first sub-pixel P1 on the substrate.

[0210] In an exemplary embodiment, the overlapping area of ​​the orthographic projection of the first occluding block 81 onto the substrate and the orthographic projection of the channel region of the second transistor T2 in the first sub-pixel P1 onto the substrate may have a second length L2, which may be approximately 0.4L to 0.6L, and the second length L2 may be a dimension in the first direction X.

[0211] In an exemplary embodiment, the material of the first blocking block 81 and the material of the second filter layer 72 can be the same.

[0212] In an exemplary embodiment, the shape of the second blocking block 82, which is a blocking structure, can be block-shaped (such as rectangular). The corners of the rectangular shape can be chamfered, raised, or grooved, and the edge of the rectangular shape can be a broken line. It can be disposed in the second sub-pixel P2 and can be disposed on one side of the second direction Y of the second filter layer 72. The orthographic projection of the second blocking block 82 on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor T2 in the second sub-pixel P2 on the substrate.

[0213] In an exemplary embodiment, the overlapping region of the orthographic projection of the second occluding block 82 onto the substrate and the orthographic projection of the channel region of the second transistor T2 in the second sub-pixel P2 onto the substrate may have a second length L2, which may be approximately 0.4L to 0.6L.

[0214] In an exemplary embodiment, the material of the second blocking block 82 can be the same as the material of the second filter layer 72.

[0215] In an exemplary embodiment, the shape of the third blocking block 83, which serves as the blocking structure, can be block-shaped (such as rectangular). The corners of the rectangular shape can be chamfered, raised, or grooved, and the edges of the rectangular shape can be broken lines. It can be set in the third sub-pixel P3 and can be set on one side of the second blocking block 82 in the first direction X. The orthographic projection of the third blocking block 83 on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor T2 in the third sub-pixel P3 on the substrate.

[0216] In an exemplary embodiment, the overlapping region of the orthographic projection of the third occluding block 83 onto the substrate and the orthographic projection of the channel region of the second transistor T2 in the third sub-pixel P3 onto the substrate may have a second length L2, which may be approximately 0.4L to 0.6L.

[0217] In an exemplary embodiment, the material of the third blocking block 83 can be the same as the material of the second filter layer 72.

[0218] In an exemplary embodiment, in at least one repeating unit, the second filter layer 72, the second blocking block 82, and the third blocking block 83 can be an integral structure that is interconnected.

[0219] In an exemplary embodiment, the shape of the fourth blocking block 84, which serves as the blocking structure, can be block-shaped (such as rectangular). The corners of the rectangular shape can be chamfered, protruded, or grooved, and the edges of the rectangular shape can be broken lines. The fourth blocking block 84 can be disposed on the fourth sub-pixel P4 and located on one side of the third filter layer 73 in the second direction Y. The orthographic projection of the fourth blocking block 84 on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor T2 in the fourth sub-pixel P4 on the substrate.

[0220] In an exemplary embodiment, the overlapping region of the orthographic projection of the fourth occlusion block 84 onto the substrate and the orthographic projection of the channel region of the second transistor T2 in the fourth sub-pixel P4 onto the substrate may have a second length L2, which may be approximately 0.4L to 0.6L.

[0221] In an exemplary embodiment, the material of the fourth blocking block 84 can be the same as the material of the second filter layer 72.

[0222] In an exemplary embodiment, at least one of the first blocking block 81 to the fourth blocking block 84 has an orthographic projection on the substrate that does not overlap with the orthographic projection of the second connecting electrode 52 on the substrate.

[0223] In an exemplary embodiment, the first to fourth blocking blocks 81, which are made of red colored film material, can cover the channel region of the second transistor T2 and block the second transistor T2 from above. By utilizing the characteristic of the red colored film layer to absorb short-wavelength light, the blocking effect can be improved, the light can be prevented from affecting the channel, the leakage current can be reduced, and the influence of light on the characteristics of the oxide transistor can be avoided, thus effectively ensuring the electrical performance of the second transistor T2.

[0224] In an exemplary embodiment, the second connection electrode 52 is configured to connect to the subsequently formed anode via an anode via. This disclosure, by setting the second connection electrode 52 to overlap a portion (approximately half) of the channel region of the second transistor T2, and the first to fourth blocking blocks 84 to overlap another portion (approximately half) of the channel region of the second transistor T2, and ensuring that the first to fourth blocking blocks 84 do not overlap with the second connection electrode 52, not only effectively blocks the channel region of the second transistor T2, but also maintains a certain distance between the first to fourth blocking blocks 81 and the anode via, preventing the color filter from falling into the anode via and causing the connection between the anode and the second connection electrode 52 to fail.

[0225] In an exemplary embodiment, the shape of the fifth blocking block 85 can be block-shaped (such as rectangular), the corners of the rectangular shape can be chamfered, protruded or grooved, the edge of the rectangular shape can be a broken line, and it can be set in each sub-pixel. The orthographic projection of the fifth blocking block 85 on the substrate at least partially overlaps with the orthographic projections of the first transistor T1 and the third transistor T3 in the same sub-pixel on the substrate.

[0226] In an exemplary embodiment, among the first sub-pixels P1 to the fourth sub-pixels P4, the orthographic projection of the fifth blocking block 85 on the substrate may include the edges on both sides of the scanning signal line 41 in the second direction Y. It can not only block the scanning signal line 41, but also block the channel regions of the first transistor T1 and the third transistor T3. The orthographic projection of the fifth blocking block 85 on the substrate may include the orthographic projection of the channel regions of the first transistor T1 and the third transistor T3 on the substrate, thus covering the channel regions of the first transistor T1 and the third transistor T3 among the first sub-pixels P1 to the fourth sub-pixels P4.

[0227] In an exemplary embodiment, the fifth blocking block 85 may be a red color film layer. That is, the material of the fifth blocking block 85 among the first sub-pixel P1 to the fourth sub-pixel P4 is the same as the material of the second filter layer 72. By utilizing the characteristic of the red color film layer to absorb short-wavelength light, the channel regions of the first transistor T1 and the third transistor T3 can be blocked from above, so as to avoid the light from affecting the channel, reduce the leakage current, and thus avoid the influence of light on the characteristics of the oxide transistor.

[0228] In an exemplary embodiment, the fifth occlusion block 85 in the first sub-pixel P1, the fifth occlusion block 85 in the second sub-pixel P2, the fifth occlusion block 85 in the third sub-pixel P3, and the fifth occlusion block 85 in the fourth sub-pixel P4 can be an interconnected integral structure.

[0229] In an exemplary embodiment, the fifth occlusion block 85 in the first sub-pixel P1, the fifth occlusion block 85 in the second sub-pixel P2, the fifth occlusion block 85 in the third sub-pixel P3, the fifth occlusion block 85 in the fourth sub-pixel P4, and the second filter layer 72 can be an integral structure that is interconnected.

[0230] (8) Forming a planarization layer pattern. In an exemplary embodiment, forming a planarization layer pattern may include: coating a planarization film on a substrate on which the aforementioned pattern is formed, and using a patterning process to pattern the planarization film and the fourth insulating film to form a planarization layer covering the color filter layer, wherein a plurality of vias are formed on the planarization layer, as shown in FIG13.

[0231] In an exemplary embodiment, the plurality of vias in each sub-pixel of the display substrate may include at least an eleventh via V11.

[0232] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the range of the orthographic projection of the second connecting electrode 52 onto the substrate. The planarization layer and the fourth insulating layer within the eleventh via V11 are etched away, exposing the surface of the second connecting electrode 52. The eleventh via V11 is configured to allow a subsequently formed anode to be connected to the second connecting electrode 52 through this via. In an exemplary embodiment, the eleventh via V11 can serve as the anode via of this disclosure.

[0233] In an exemplary embodiment, this process uses a single patterning process to simultaneously form vias on the fourth insulating layer and the planarization layer. That is, the fourth insulating layer and the planarization layer share a single mask process, which effectively reduces the number of patterning processes.

[0234] (9) Forming a second transparent conductive layer pattern. In an exemplary embodiment, forming a second transparent conductive layer pattern may include: depositing a second transparent conductive film on a substrate on which the aforementioned pattern is formed, and patterning the second transparent conductive film using a patterning process to form a second transparent conductive layer pattern disposed on a planarization layer, as shown in FIG14. In an exemplary embodiment, the second transparent conductive layer may be referred to as an ITO2 layer.

[0235] In an exemplary embodiment, the second transparent conductive layer pattern may include a first anode 91 located in the first sub-pixel P1, a second anode 92 located in the second sub-pixel P2, a third anode 93 located in the third sub-pixel P3, and a fourth anode 94 located in the fourth sub-pixel P4. The anode in each sub-pixel is connected to the second connection electrode 52 through the eleventh via V11, thereby realizing the connection between the anode and the pixel driving circuit.

[0236] In an exemplary embodiment, at least one of the first anode 91 to the fourth anode 94 may include a main body portion and a connecting portion connected to each other. The main body portion may be block-shaped (such as rectangular), and the connecting portion may be strip-shaped extending along the second direction Y. It may be disposed on one side of the main body portion in the second direction Y. The connecting portion is connected to the second connecting electrode 52 through the eleventh through hole V11.

[0237] In an exemplary embodiment, the orthographic projection of the anode in each sub-pixel onto the substrate includes the orthographic projections of the first and second electrodes in that sub-pixel onto the substrate. Since the first electrode and the anode have a potential at a second node, and the second electrode has a potential at a first node, the first electrode with the potential at the second node and the second electrode with the potential at the first node form a first capacitor, and the anode with the potential at the second node and the second electrode with the potential at the first node form a second capacitor. The first and second capacitors are connected in parallel, and the parallel structure of the first and second capacitors constitutes a complete storage capacitor. Since the first electrode and the anode are made of transparent conductive material, and the second electrode is made of transparent metal oxide, the storage capacitor is a transparent capacitor. This disclosure utilizes a first transparent conductive layer, a semiconductor layer, and a second transparent conductive layer to form a parallel structure of the first and second capacitors. This parallel structure of the first and second capacitors constitutes a complete storage capacitor, which can effectively increase the capacitance value of the storage capacitor and reduce the electrode area while maintaining the capacitance value, thus effectively reducing the occupied area.

[0238] (10) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a patterning process to form a pixel definition layer pattern, as shown in FIG15.

[0239] In an exemplary embodiment, a pixel opening K is provided on the pixel definition layer of each sub-pixel in the display substrate. The pixel definition film inside the pixel opening K is removed to expose part of the surface of the anode. The orthographic projection of the pixel opening K on the substrate is located within the range of the orthographic projection of the anode on the substrate.

[0240] In an exemplary embodiment, in at least one sub-pixel, the orthographic projection of the pixel opening K onto the substrate at least partially overlaps with the orthographic projections of the first and second electrodes onto the substrate.

[0241] In an exemplary embodiment, the shape of the pixel opening in a plane parallel to the substrate can include any one or more of the following: triangle, rectangle, trapezoid, parallelogram, pentagon, hexagon, circle, and ellipse. In a direction perpendicular to the substrate, the cross-sectional shape of the pixel opening K can be rectangular or trapezoidal, etc.

[0242] In an exemplary embodiment, the shape and area of ​​the pixel openings of the four sub-pixels can be the same, or the shape and area of ​​the pixel openings of the four sub-pixels can be different, in order to adapt to the transmittance of different sub-pixel filters, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, thereby maximizing the lifespan of the four sub-pixel light-emitting devices and ensuring the product lifespan.

[0243] In an exemplary embodiment, subsequent fabrication processes may include: forming an organic light-emitting layer using vapor deposition or inkjet printing; the organic light-emitting layer being connected to an anode through pixel openings; forming a cathode on the organic light-emitting layer; and connecting the cathode to the organic light-emitting layer. An encapsulation structure layer is then formed, which may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is positioned between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0244] Thus, the driving structure layer, the light-emitting structure layer disposed on the driving structure layer, and the encapsulation structure layer disposed on the light-emitting structure layer have been fabricated on the substrate.

[0245] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0246] In an exemplary embodiment, the first and second transparent conductive layers can be made of transparent conductive materials, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first, second, and third conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, third, and fourth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The planarization layer can be made of organic materials, such as resin, and the pixel definition layer can be made of polyimide, acrylic, or polyethylene terephthalate.

[0247] The exemplary embodiments of this disclosure show that by providing an anode connection electrode to shield the second transistor T2 from above, the display substrate can avoid the influence of light on the channel region of the second transistor T2, reduce leakage current, thereby avoiding the influence of light on the characteristics of the oxide second transistor T2 and improving the driving performance of the pixel driving circuit.

[0248] This disclosure provides a shielding structure in the color filter structure layer, which shields the second transistor T2 from above. This further prevents light from affecting the channel region of the second transistor T2, reduces leakage current, avoids the influence of light on the characteristics of the oxide second transistor T2, and further improves the driving performance of the pixel driving circuit.

[0249] This disclosure ensures that the orthographic projection of the shielding structure on the substrate does not overlap with the orthographic projection of the anode via on the substrate, thus maintaining a certain distance between the shielding structure and the anode via, which can effectively prevent the connection failure between the anode and the second connecting electrode.

[0250] This disclosure eliminates the ramp structure of the semiconductor layer in the second sub-pixel P2 and the third sub-pixel P3, and widens the ramp structure of the semiconductor layer in the first sub-pixel P1 and the fourth sub-pixel P4. This not only minimizes the occurrence of defects, but also increases the thickness of the first conductive layer, improves the shielding capability of the shielding electrode, and ensures the stability of the pixel driving circuit.

[0251] This disclosure provides a fifth blocking block in the color filter structure layer. The fifth blocking block can cover the channel regions of the first transistor T1 and the third transistor T3. It can block the channel regions of the first transistor T1 and the third transistor T3 from above, preventing light from affecting the channel, reducing leakage current, and thus avoiding the influence of light on the characteristics of the oxide transistor.

[0252] This disclosure employs a transparent storage capacitor, which consists of a first transparent conductive layer and a transparent semiconductor layer. Since light can pass through the transparent storage capacitor, the storage capacitor can be positioned within the pixel aperture, effectively increasing the capacitance of the storage capacitor and thus effectively increasing the pixel aperture ratio.

[0253] This disclosure saves the number of signal lines and reduces the space occupied by adopting a one-to-two structure of the first power line and a one-to-four structure of the compensation signal line. The structure is simple, the layout is reasonable, the layout space is fully utilized, the space utilization rate is improved, and the resolution is improved.

[0254] The preparation process disclosed herein can be achieved using existing mature preparation equipment, requires minimal modification to existing processes, is highly compatible with existing preparation processes, is simple to implement, has high production efficiency, low production cost, and high yield.

[0255] The structure and its preparation process shown in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs. This disclosure does not limit the scope of the invention.

[0256] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0257] This disclosure also provides a display device, including the display substrate of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0258] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit the invention. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the patent protection scope of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate comprising a plurality of sub-pixels, at least one sub-pixel comprising a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, the driving structure layer comprising at least a pixel driving circuit and the light-emitting structure layer comprising at least a light-emitting device; The pixel driving circuit includes at least a second transistor as a driving transistor. The second transistor includes at least a second active layer and a second gate electrode. The second active layer is shaped to extend along a first direction into a strip shape, and the second gate electrode is shaped to extend along a second direction into a strip shape. The first direction and the second direction intersect. The orthographic projection of the second gate electrode on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The overlapping region of the second active layer is the channel region of the second transistor. The first region of the second active layer is connected to a first power line, and the second region of the second active layer is connected to an anode connection electrode. The light-emitting device includes at least an anode, which is connected to the anode connection electrode through an anode via. In at least one sub-pixel, the orthographic projection of the anode connection electrode on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor on the substrate.

2. The display substrate according to claim 1, wherein, The channel region of the second transistor has a channel length, and the overlapping area of ​​the orthographic projection of the anode connection electrode on the substrate and the orthographic projection of the channel region of the second transistor on the substrate has a first length, the first length being 0.4 * channel length to 0.6 * channel length, the channel length and the first length being dimensions in the first direction.

3. The display substrate according to claim 1, wherein, At least one sub-pixel also includes a blocking electrode; In at least one sub-pixel, the orthogonal projections of the first region of the second active layer, the second region of the second active layer, and the channel region of the second transistor onto the substrate are located within the range of the orthogonal projection of the shielding electrode onto the substrate.

4. The display substrate according to claim 1, wherein, At least one sub-pixel also includes a blocking electrode; In at least one sub-pixel, the orthographic projections of the second region of the second active layer and the channel region of the second transistor onto the substrate are within the range of the orthographic projection of the shielding electrode onto the substrate. The first region of the second active layer includes at least a first portion and a second portion. The second portion is located between the first portion and the channel region of the second transistor. The orthographic projection of the first portion onto the substrate at least partially overlaps with the orthographic projection of the shielding electrode onto the substrate. The orthographic projection of the second portion onto the substrate is within the range of the orthographic projection of the shielding electrode onto the substrate.

5. The display substrate according to claim 4, wherein, The first portion has a first width, the second portion has a second width, the first width is greater than the second width, and the first width and the second width are dimensions in the second direction.

6. The display substrate according to any one of claims 1 to 5, wherein, At least one sub-pixel further includes a color filter structure layer, the color filter structure layer being disposed on the side of the driving structure layer away from the substrate, and the light-emitting structure layer being disposed on the side of the color filter structure layer away from the substrate; In at least one sub-pixel, the color filter structure layer includes at least a masking structure, the orthographic projection of the masking structure onto the substrate at least partially overlapping the orthographic projection of the channel region of the second transistor onto the substrate.

7. The display substrate according to claim 6, wherein, The channel region of the second transistor has a channel length, and the overlapping area of ​​the orthographic projection of the shielding structure onto the substrate and the orthographic projection of the channel region of the second transistor onto the substrate has a second length, which is 0.4 * channel length to 0.6 * channel length. The channel length and the second length are dimensions in the first direction.

8. The display substrate according to claim 6, wherein, In at least one sub-pixel, the orthographic projection of the occluding structure onto the substrate does not overlap with the orthographic projection of the anode via onto the substrate.

9. The display substrate according to claim 8, wherein, In at least one sub-pixel, the orthographic projection of the occluding structure onto the substrate does not overlap with the orthographic projection of the anode connecting electrode onto the substrate.

10. The display substrate according to claim 6, wherein, The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel arranged sequentially along the first direction. The color filter structure layer of the first sub-pixel includes at least a first filter layer, which is configured to cause the first sub-pixel to emit green light. The color filter structure layer of the second sub-pixel includes at least a second filter layer, which is configured to cause the second sub-pixel to emit red light. The color filter structure layer of the fourth sub-pixel includes at least a third filter layer, which is configured to cause the fourth sub-pixel to emit blue light.

11. The display substrate according to claim 10, wherein, The masking structure includes at least a first masking block disposed in the first sub-pixel, wherein the orthographic projection of the first masking block on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor in the first sub-pixel on the substrate, and the material of the first masking block is the same as the material of the second filter layer.

12. The display substrate according to claim 10, wherein, The masking structure includes at least a second masking block disposed in the second sub-pixel. The orthographic projection of the second masking block on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor in the second sub-pixel on the substrate. The second masking block and the second filter layer are an integral structure connected to each other.

13. The display substrate according to claim 10, wherein, The occlusion structure includes at least a third occlusion block disposed in the third sub-pixel. The orthographic projection of the third occlusion block on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor in the third sub-pixel on the substrate. The third occlusion block and the second filter layer are an integral structure interconnected with each other.

14. The display substrate according to claim 10, wherein, The masking structure includes at least a fourth masking block disposed in the fourth sub-pixel. The orthographic projection of the fourth masking block on the substrate at least partially overlaps with the orthographic projection of the channel region of the second transistor in the fourth sub-pixel on the substrate. The material of the fourth masking block is the same as the material of the second filter layer.

15. The display substrate according to claim 10, wherein, The pixel driving circuit further includes a first transistor as a data writing transistor and a third transistor as a compensation transistor. The first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is connected to the gate electrode of the second transistor, the first electrode of the third transistor is connected to the compensation signal line, and the second electrode of the third transistor is connected to the anode connection electrode. In at least one sub-pixel, the color filter structure layer further includes a fifth blocking block, the orthographic projection of the fifth blocking block on the substrate at least partially overlapping the orthographic projections of the channel regions of the first transistor and the third transistor on the substrate.

16. The display substrate according to claim 15, wherein, In at least one sub-pixel, the orthographic projections of the channel regions of the first transistor and the third transistor onto the substrate are located within the range of the orthographic projection of the fifth occluding block onto the substrate.

17. The display substrate according to claim 15, wherein, The fifth occlusion block in the first sub-pixel, the fifth occlusion block in the second sub-pixel, the fifth occlusion block in the third sub-pixel, and the fifth occlusion block in the fourth sub-pixel are interconnected as a single structure.

18. The display substrate according to claim 15, wherein, The materials of the fifth occlusion block in the first sub-pixel, the fifth occlusion block in the second sub-pixel, the fifth occlusion block in the third sub-pixel, and the fifth occlusion block in the fourth sub-pixel are the same as the material of the second filter layer.

19. The display substrate according to claim 15, wherein, The fifth occlusion block in the first sub-pixel, the fifth occlusion block in the second sub-pixel, the fifth occlusion block in the third sub-pixel, the fifth occlusion block in the fourth sub-pixel, and the second filter layer are an integral structure that is interconnected.

20. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 19.

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