Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a display region, a base substrate, a plurality of pixel driving circuits, a plurality of data lines, a plurality of power lines, a plurality of initial signal connection lines, a plurality of first fanout lines, a plurality of second fanout lines, a first source-drain layer, and a second source-drain layer, wherein the orthographic projections of the plurality of first fanout lines on the base substrate extend in a first direction and are distributed at intervals in a second direction; the orthographic projections of the plurality of second fanout lines on the base substrate extend in the second direction and are distributed at intervals in the first direction; the first source-drain layer is located on one side of the base substrate, and the second source-drain layer is located on the side of the first source-drain layer facing away from the base substrate; and the first fanout lines are located in the first source-drain layer, and at least a portion of each of the data lines, at least a portion of each of the power lines, at least a portion of each of the initial signal connection lines, and at least a portion of each of the second fanout lines are located in the second source-drain layer.

Description

Display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, FIP (Fanout In Panel) technology places the fan-out lines used to connect data cables in the display area, thereby reducing the bezel width of the display panel. This technology typically involves adding a third source / drain layer to the display panel, placing the row fan-out lines in the second source / drain layer and the column fan-out lines in the third source / drain layer. However, this structure results in a relatively complex display panel design and significant manufacturing difficulties.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes a display area, and the display panel further includes:

[0005] Substrate;

[0006] Multiple pixel driving circuits, wherein the orthographic projections of the multiple pixel driving circuits on the substrate are distributed in an array along a first direction and a second direction, the first direction and the second direction intersecting;

[0007] Multiple data lines, whose orthogonal projections on the substrate extend along the second direction and are spaced apart along the first direction, are used to provide data signals to the pixel driving circuit.

[0008] Multiple power lines, whose orthogonal projections on the substrate extend along the second direction and are spaced apart along the first direction, and the data lines are used to provide power signals to the pixel driving circuit.

[0009] Multiple initial signal connection lines, whose orthogonal projections on the substrate extend along the second direction and are spaced apart along the first direction, are used to provide initial signals to the pixel driving circuit.

[0010] Multiple first fan-out lines, whose orthogonal projections on the substrate extend along the first direction and are spaced apart along the second direction;

[0011] Multiple second fan-out lines, whose orthographic projection on the substrate extends along the second direction and are spaced apart along the first direction, and at least a portion of the multiple first fan-out lines are connected between the data line and the second fan-out lines, and at least a portion of the first fan-out lines and at least a portion of the second fan-out lines are located in the display area;

[0012] The pixel driving circuit includes a plurality of transistors, and the display panel further includes a first source-drain layer and a second source-drain layer. The first source-drain layer is located on one side of the substrate, and the second source-drain layer is located on the side of the first source-drain layer opposite to the substrate. At least a portion of the structure of the first source-drain layer is bridged between different transistors.

[0013] The first fan-out line is located in the first source-drain layer, and at least a portion of the data line, at least a portion of the power line, at least a portion of the initial signal connection line, and at least a portion of the second fan-out line are located in the second source-drain layer.

[0014] In one exemplary embodiment of this disclosure, the initial signal connection line includes a first connection segment and a second connection segment, wherein the orthographic projections of the first connection segment and the second connection segment on the substrate are alternately distributed along the second direction.

[0015] Wherein, the first connecting segment is located in the first source / drain layer, the second connecting segment is located in the second source / drain layer, the second connecting segment is connected to the first connecting segment through a via, and the orthographic projection of the second connecting segment on the substrate intersects the orthographic projection of the first fan-out line on the substrate.

[0016] In one exemplary embodiment of this disclosure, one or more of the data line, power line, initial signal connection line, and second fan-out line are located in the second source / drain layer.

[0017] In one exemplary embodiment of this disclosure, the display panel includes a plurality of pixel driving circuit groups, the orthographic projections of the plurality of pixel driving circuit groups on the substrate are arrayed along the first direction and the second direction, the pixel driving circuit group includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same pixel driving circuit group are at least partially mirror-symmetrically arranged.

[0018] Among them, two adjacent pixel driving circuit groups are respectively located in the first direction and two adjacent power lines are connected, and the orthogonal projection of the two connected power lines on the substrate is located between the orthogonal projections of the two adjacent data lines on the substrate.

[0019] In one exemplary embodiment of this disclosure, the orthographic projection of the second fan-out line on the substrate is located between two adjacent data lines.

[0020] In an exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit includes a driving transistor, a first transistor, a fifth transistor, and a seventh transistor. The first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the gate of the driving transistor. The first terminal of the fifth transistor is connected to a power supply line, and the second terminal is connected to the first terminal of the driving transistor. The gate of the fifth transistor is connected to an enable signal line. The first terminal of the seventh transistor is connected to a second initial signal line, and the second terminal is connected to the light-emitting unit.

[0021] The enable signal line, the first initial signal line, and the second initial signal line are projected onto the substrate and extend along the first direction.

[0022] Wherein, the orthographic projection of the second initial signal line connected to the adjacent previous row pixel driving circuit on the substrate is at least partially located between the orthographic projection of the enable signal line in the current row pixel driving circuit on the substrate and the orthographic projection of the first initial signal line connected to the adjacent next row pixel driving circuit on the substrate.

[0023] The orthographic projection of the first fan-out line on the substrate is at least partially located between the orthographic projection of the second initial signal line connected to the adjacent previous row pixel driving circuit on the substrate and the orthographic projection of the first initial signal line connected to the adjacent next row pixel driving circuit on the substrate.

[0024] In one exemplary embodiment of this disclosure, the display panel includes a plurality of pixel driving circuit groups, the orthographic projections of the plurality of pixel driving circuit groups on the substrate are arrayed along the first direction and the second direction, the pixel driving circuit group includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same pixel driving circuit group are at least partially mirror-symmetrically arranged.

[0025] The two power lines located in adjacent pixel driving circuit groups in the first direction are spaced apart, and the orthogonal projections of the two power lines located in adjacent pixel driving circuit groups in the first direction on the substrate are located on both sides of the orthogonal projection of the second fan-out line on the substrate.

[0026] In one exemplary embodiment of this disclosure, the orthographic projection of the initial signal connection line on the substrate is located between the orthographic projections of two adjacent data lines on the substrate.

[0027] In one exemplary embodiment of this disclosure, each column of pixel driving circuit is provided with one second fan-out line, or multiple columns of pixel driving circuits are provided with one second fan-out line.

[0028] In an exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit includes a driving transistor and a first transistor, wherein the first electrode of the first transistor is connected to a first initial signal line, and the second electrode is connected to the gate of the driving transistor.

[0029] The display panel also includes:

[0030] An active layer is located between the substrate and the first source / drain layer. The active layer includes a thirteenth active portion, which is used to connect the light-emitting unit.

[0031] A second gate layer is located between the active layer and the first source / drain layer. The second gate layer includes the first initial signal line and a first protrusion. The orthographic projection of the first initial signal line on the substrate extends along the first direction, and the first protrusion is connected to one side of the first initial signal line in the second direction.

[0032] The overlapping area of ​​the orthographic projection of the first fan-out line on the substrate and the orthographic projection of the thirteenth active part on the substrate at least partially overlaps with the orthographic projection of the first protrusion on the substrate.

[0033] In an exemplary embodiment of this disclosure, the active layer further includes: a first active portion and a fifteenth active portion, the first active portion including a first sub-active portion and a second sub-active portion, the first sub-active portion and the second sub-active portion being respectively used to form the channel region of the first transistor, and the fifteenth active portion being connected between the first sub-active portion and the second sub-active portion.

[0034] The second gate layer further includes:

[0035] The second protrusion is connected to one side of the first initial signal line in the second direction, and the orthographic projection of the second protrusion on the substrate and the orthographic projection of the fifteenth active part on the substrate at least partially overlap.

[0036] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit includes a driving transistor and a seventh transistor, wherein the first terminal of the seventh transistor is connected to a second initial signal line, and the second terminal is connected to the light-emitting unit.

[0037] The display panel also includes:

[0038] An active layer is located between the substrate and the first source / drain layer. The active layer includes a ninth active portion, which is used to connect to the gate of the driving transistor.

[0039] A second gate layer is located between the active layer and the first source / drain layer. The second gate layer includes a second initial signal line and a third protrusion. The orthographic projection of the second initial signal line on the substrate extends along the first direction. The third protrusion is connected to one side of the second initial signal line in the second direction.

[0040] The orthographic projection of the third protrusion on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the ninth active part on the substrate.

[0041] In an exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit includes a driving transistor, a second transistor, and a seventh transistor. The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor. The first terminal of the seventh transistor is connected to a second initial signal line, and the second terminal is connected to the light-emitting unit.

[0042] The display panel also includes:

[0043] An active layer is located between the substrate and the first source / drain layer. The active layer includes a second active portion and a fourteenth active portion. The second active portion includes a third sub-active portion and a fourth sub-active portion. The third sub-active portion and the fourth sub-active portion are respectively used to form the channel region of the second transistor. The fourteenth active portion is connected between the third sub-active portion and the fourth sub-active portion.

[0044] A second gate layer is located between the active layer and the first source / drain layer. The second gate layer includes a second initial signal line and a fourth protrusion. The orthographic projection of the second initial signal line on the substrate extends along the first direction. The fourth protrusion is connected to one side of the second initial signal line in the second direction.

[0045] Wherein, the orthographic projection of the fourth protrusion on the substrate and the orthographic projection of the fourteenth active portion on the substrate at least partially overlap.

[0046] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a driving transistor, a first transistor, and a fifth transistor. The first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the gate of the driving transistor. The first terminal of the fifth transistor is connected to a power supply line, and the second terminal is connected to the first terminal of the driving transistor.

[0047] The display panel includes multiple pixel driving circuit groups, and the orthographic projections of the multiple pixel driving circuit groups on the substrate are distributed in an array along the first direction and the second direction. Each pixel driving circuit group includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same pixel driving circuit group are at least partially mirror-symmetrically arranged.

[0048] The display panel also includes:

[0049] An active layer, the active layer including a first active portion and a fifth active portion, the first active portion being used to form the channel region of the first transistor, and the fifth active portion being used to form the channel region of the fifth transistor;

[0050] In the same pixel driving circuit group, two adjacent first active parts are connected on the same layer, and two adjacent fifth active parts are connected on the same layer.

[0051] In one exemplary embodiment of this disclosure, the display panel further includes:

[0052] Multiple initial signal lines, whose orthogonal projections on the substrate extend along the first direction and are spaced apart along the second direction;

[0053] The initial signal connection line is connected via vias to at least partially intersecting with the same initial signal line.

[0054] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a driving transistor and a capacitor, wherein the first electrode of the capacitor is connected to the gate of the driving transistor and the second electrode is connected to a power supply line;

[0055] The display panel also includes:

[0056] A first gate layer is located between the substrate and the first source / drain layer. The first gate layer includes a first conductive portion, which is used to form the gate of the driving transistor and the first electrode of the capacitor.

[0057] A second gate layer is located between the first gate layer and the first source / drain layer. The second gate layer includes a second conductive portion. The orthographic projection of the second conductive portion on the substrate overlaps with the orthographic projection of the first conductive portion on the substrate. The second conductive portion is used to form the second electrode of the capacitor.

[0058] An electrode layer is located on the side of the second source / drain layer away from the substrate. The electrode layer includes a plurality of electrode portions, among which a first electrode portion, a second electrode portion, and a third electrode portion are included.

[0059] The first direction is the row direction, the second direction is the column direction, and among the multiple electrode sections connected to the same row pixel driving circuit, the first electrode section, the third electrode section, the second electrode section, and the third electrode section are alternately distributed in the first direction.

[0060] In two adjacent columns of pixel driving circuits, multiple first electrode portions and multiple second electrode portions are connected to the same column of pixel driving circuits, and the first electrode portions and second electrode portions connected to the same column of pixel driving circuits are alternately distributed in the second direction, and multiple third electrode portions are connected to another column of pixel driving circuits.

[0061] The orthogonal projection area of ​​the opening on the second conductive part of the pixel driving circuit connected to the second electrode part on the substrate is smaller than the orthogonal projection area of ​​the opening on the second conductive part of the pixel driving circuit connected to the first electrode part on the substrate.

[0062] The orthogonal projection area of ​​the opening on the second conductive part of the pixel driving circuit connected to the second electrode part on the substrate is smaller than the orthogonal projection area of ​​the opening on the second conductive part of the pixel driving circuit connected to the third electrode part on the substrate.

[0063] In one exemplary embodiment of this disclosure, the pixel driving circuit includes:

[0064] Drive transistors;

[0065] The first transistor has a first terminal connected to a first initial signal line and a second terminal connected to the gate of the driving transistor, the gate of which is connected to a first reset signal line.

[0066] The second transistor has a first terminal connected to the gate of the driving transistor, a second terminal connected to the first terminal of the driving transistor, and a gate connected to the first gate line.

[0067] The fourth transistor has its first terminal connected to the data line, its second terminal connected to the first terminal of the driving transistor, and its gate connected to the first gate line.

[0068] The fifth transistor has its first terminal connected to the power supply line, its second terminal connected to the first terminal of the driving transistor, and its gate connected to the enable signal line.

[0069] The sixth transistor has its first terminal connected to the second terminal of the driving transistor, the second terminal connected to the light-emitting unit, and its gate connected to the enable signal line.

[0070] The seventh transistor has its first terminal connected to the second initial signal line, its second terminal connected to the second terminal of the sixth transistor, and its gate connected to the second reset signal line.

[0071] In one exemplary embodiment of this disclosure, the display panel further includes:

[0072] An active layer is located between the substrate and the first source / drain layer, and at least a portion of the structure of the active layer is used to form the channel regions of the driving transistor, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor.

[0073] A first gate layer is located between the active layer and the first source / drain layer. The first gate layer includes a first conductive portion, a first reset signal line, a first gate line, an enable signal line, and a second reset signal line. The orthogonal projections of the first reset signal line, the first gate line, the enable signal line, and the second reset signal line on the substrate extend along the first direction.

[0074] Wherein, at least a portion of the structure of the first reset signal line is used to form the gate of the first transistor, at least a portion of the structure of the second reset signal line is used to form the gate of the seventh transistor, at least a portion of the structure of the first gate line is used to form the gates of the second and fourth transistors, at least a portion of the structure of the enable signal line is used to form the gates of the fifth and sixth transistors, and the first conductive portion is used to form the gate of the driving transistor.

[0075] In the same pixel driving circuit, the orthographic projections of the first reset signal line, the first gate line, the enable signal line, and the second reset signal line on the substrate are distributed sequentially at intervals along the second direction, and the orthographic projection of the first conductive part on the substrate is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the enable signal line on the substrate.

[0076] According to one aspect of this disclosure, a display panel is provided, the display panel including a plurality of pixel driving circuit groups, the plurality of pixel driving circuit groups being arrayed along a first direction and a second direction, the first direction and the second direction intersecting;

[0077] The pixel driving circuit group includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same pixel driving circuit group are at least partially mirror-symmetrically arranged.

[0078] The pixel driving circuit includes a driving transistor, a first transistor, and a fifth transistor. The first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the gate of the driving transistor. The first terminal of the fifth transistor is connected to a power supply line, and the second terminal is connected to the first terminal of the driving transistor.

[0079] The display panel also includes:

[0080] Substrate;

[0081] An active layer is located on one side of the substrate. The active layer includes a first active portion and a fifth active portion. The first active portion is used to form the channel region of the first transistor, and the fifth active portion is used to form the channel region of the fifth transistor.

[0082] In the same pixel driving circuit group, two adjacent first active parts are connected on the same layer, and two adjacent fifth active parts are connected on the same layer.

[0083] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0084] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0085] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0086] Figure 1 is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure;

[0087] Figure 2 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0088] Figure 3 is a structural layout of the active layer in the display panel shown in Figure 2;

[0089] Figure 4 is a structural layout of the first gate layer in the display panel shown in Figure 2;

[0090] Figure 5 is a structural layout of the second gate layer in the display panel shown in Figure 2;

[0091] Figure 6 is a structural layout of the first source / drain layer in the display panel shown in Figure 2;

[0092] Figure 7 is a structural layout of the second source / drain layer in the display panel shown in Figure 2;

[0093] Figure 8 is a structural layout of the electrode layer in the display panel shown in Figure 2;

[0094] Figure 9 is a structural layout of the active layer and the first gate layer in the display panel shown in Figure 2;

[0095] Figure 10 is a structural layout of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 2.

[0096] Figure 11 is a structural layout of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 2;

[0097] Figure 12 is a structural layout of the active layer, first gate layer, second gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 2.

[0098] Figure 13 is a partial cross-sectional view of the display panel shown in Figure 2, cut along the dashed line AA;

[0099] Figure 14 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0100] Figure 15 is a structural layout of the active layer in the display panel shown in Figure 14;

[0101] Figure 16 is a structural layout of the first gate layer in the display panel shown in Figure 14;

[0102] Figure 17 is a structural layout of the second gate layer in the display panel shown in Figure 14;

[0103] Figure 18 is a structural layout of the first source / drain layer in the display panel shown in Figure 14;

[0104] Figure 19 is a structural layout of the second source / drain layer in the display panel shown in Figure 14;

[0105] Figure 20 is a structural layout of the electrode layer in the display panel shown in Figure 14;

[0106] Figure 21 is a structural layout of the active layer and the first gate layer in the display panel shown in Figure 14;

[0107] Figure 22 is a structural layout of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 14;

[0108] Figure 23 is a structural layout of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 14;

[0109] Figure 24 is a structural layout of the active layer, first gate layer, second gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 14.

[0110] Figure 25 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0111] Figure 26 is a structural layout of the active layer in the display panel shown in Figure 25;

[0112] Figure 27 is a structural layout of the first gate layer in the display panel shown in Figure 25;

[0113] Figure 28 is a structural layout of the second gate layer in the display panel shown in Figure 25;

[0114] Figure 29 is a structural layout of the first source / drain layer in the display panel shown in Figure 25;

[0115] Figure 30 is a structural layout of the second source / drain layer in the display panel shown in Figure 25;

[0116] Figure 31 is a structural layout of the electrode layer in the display panel shown in Figure 25;

[0117] Figure 32 is a structural layout of the active layer and the first gate layer in the display panel shown in Figure 25;

[0118] Figure 33 is a structural layout of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 25.

[0119] Figure 34 is a structural layout of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 25;

[0120] Figure 35 is a structural layout of the active layer, first gate layer, second gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 25.

[0121] Figure 36 is a schematic diagram of the structure of an exemplary embodiment of the display panel of this disclosure;

[0122] Figure 37 is a timing diagram of each node in a driving method for a display panel according to the present disclosure. Detailed Implementation

[0123] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0124] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0125] In the description of this disclosure, unless otherwise expressly specified and limited, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” refers to two or more; and the term “and / or” includes any and all combinations of one or more associated listed items. In particular, references to “the / described” object or “a” object are also intended to indicate one of a possible plurality of such objects.

[0126] Unless otherwise specified or stated, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0127] Furthermore, it should be understood that the directional terms such as "upper," "lower," "inner," and "outer" described in the exemplary embodiments of this disclosure are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this disclosure. It should also be understood that, in the context of an element or feature being connected to one or more "upper," "lower," "inner," or "outer" elements, it can be directly connected to one or more "upper," "lower," "inner," or "outer" elements, or indirectly connected to one or more "upper," "lower," "inner," or "outer" elements through intermediate elements.

[0128] Figure 1 shows a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. In this configuration, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the first gate drive signal terminal G1; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to node N; the first electrode of the second transistor T2 is connected to node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate drive signal terminal G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, and the gate is connected to the enable signal terminal EM; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the second electrode of the first transistor T1 is connected to node N, the first electrode is connected to the first initial signal terminal Vinit1, and the gate is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to node N, and the second electrode is connected to the first power supply terminal VDD. The pixel driving circuit can be connected to an OLED light-emitting unit. The pixel driving circuit is used to drive the OLED to emit light. The OLED can be connected between the second terminal of the sixth transistor T6 and the second power supply terminal VSS. Among them, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors.

[0129] The pixel driving circuit driving method can include a reset stage, a data writing stage, and a light-emitting stage. In the reset stage, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs a first initial signal to node N. In the data writing stage, the first gate driving signal terminal G1 outputs a low-level signal, the second reset signal terminal Re2 outputs a low-level signal, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit, and simultaneously the data signal terminal Da outputs a data signal to write a compensation voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3. In the light-emitting stage: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in capacitor C. In the pixel driving circuit of this disclosure, the output current of the driving transistor I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Where I is the driving transistor output current; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the driving transistor threshold voltage.

[0130] This exemplary embodiment also provides a display panel, which may include a substrate, an active layer, a first gate layer, a second gate layer, a first source / drain layer, a second source / drain layer, and an electrode layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 2-12, Figure 2 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure, Figure 3 is a structural layout diagram of the active layer in the display panel shown in Figure 2, Figure 4 is a structural layout diagram of the first gate layer in the display panel shown in Figure 2, Figure 5 is a structural layout diagram of the second gate layer in the display panel shown in Figure 2, Figure 6 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 2, Figure 7 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 2, Figure 8 is a structural layout diagram of the electrode layer in the display panel shown in Figure 2, Figure 9 is a structural layout diagram of the active layer and the first gate layer in the display panel shown in Figure 2, Figure 10 is a structural layout diagram of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 2, Figure 11 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 2, and Figure 12 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, the first source / drain layer, and the second source / drain layer in the display panel shown in Figure 2. The display panel shown in Figure 2 includes multiple pixel driving circuit groups Pz distributed along a first direction X and a second direction Y. The first direction X and the second direction Y intersect, where the first direction X can be a row direction and the second direction Y can be a column direction. Each pixel driving circuit group Pz includes two pixel driving circuits Pix distributed along the first direction X. The orthographic projections of the two pixel driving circuits Pix in the same pixel driving circuit group Pz are at least partially mirror-symmetrical on the substrate. Furthermore, the channel regions of the same type of transistors in the two pixel driving circuits Pix in the same pixel driving circuit group Pz are mirror-symmetrical; for example, the channel regions of two first transistors in the same pixel driving circuit group Pz are mirror-symmetrical. The structure of the pixel driving circuit Pix can be as shown in Figure 1.

[0131] As shown in Figures 2, 3, and 9, the active layer may include: a first active section 71, a second active section 72, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a ninth active section 79, a tenth active section 710, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, and a seventeenth active section 717. The first active portion 71 is used to form the channel region of the first transistor T1, wherein the first active portion 71 includes a first sub-active portion 711 and a second sub-active portion 732; the second active portion 72 is used to form the channel region of the second transistor T2, wherein the second active portion 72 includes a third sub-active portion 723 and a fourth sub-active portion 724; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 is connected to... The fifth active part 75 is connected to the end away from the third active part 73; the ninth active part 79 is connected between the first active part 71 and the second active part 72; the tenth active part 710 is connected to the end of the seventh active part 77 away from the sixth active part 76; the thirteenth active part 713 is connected between the seventh active part 77 and the sixth active part 76; the fourteenth active part 714 is connected between the third sub-active part 723 and the fourth sub-active part 724; the fifteenth active part 715 is connected between the first sub-active part 711 and the second sub-active part 732; the sixteenth active part 716 is connected to the end of the fourth active part 74 away from the third active part 73; and the seventeenth active part 717 is connected to the end of the first active part 71 away from the second active part 72. In this exemplary embodiment, the active layer can be formed of polycrystalline silicon material. Correspondingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon thin-film transistors. Both the first transistor and the second transistor have two spaced-apart channel regions. Correspondingly, both the first transistor T1 and the second transistor T2 have two gates, i.e., the first transistor T1 and the second transistor T2 are dual-gate structures. Dual-gate transistors have lower turn-off leakage current. This configuration can reduce the leakage current through the gate of the driving transistor via the first transistor T1 and the second transistor T2, thereby improving the voltage stability of the driving transistor gate.

[0132] As shown in Figures 2, 3, and 9, in the same pixel driving circuit group Pz, the seventeenth active part 717 is connected between two adjacent first active parts 71, and the eighth active part 78 is connected between two adjacent fifth active parts 75.

[0133] As shown in Figures 2, 4, and 9, the first gate layer may include: a first conductive portion 11, a first gate line G1, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The first gate line G1 can be used to provide the first gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthographic projections of the first gate line G1, the enable signal line EM, the first reset signal line Re1, and the second reset signal line Re2 on the substrate can all extend along the first direction X. The orthographic projection of the first gate line G1 on the substrate covers the orthographic projections of the fourth active portion 74 and the second active portion 72 on the substrate. A portion of the structure of the first gate line G1 is used to form the gate of the fourth transistor T4, and a portion of the structure of the first gate line G1 is used to form the gate of the second transistor T2. The orthographic projection of the enable signal line EM onto the substrate covers the orthographic projections of the fifth active portion 75 and the sixth active portion 76 onto the substrate. A portion of the structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 onto the substrate covers the orthographic projection of the first active portion 71 onto the substrate. A portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 onto the substrate covers the orthographic projection of the seventh active portion 77 onto the substrate. A portion of the structure of the first reset signal line Re1 can be used to form the gate of the seventh transistor T7. The second reset signal line Re2 corresponding to the pixel driving circuit in this row can be multiplexed as the first reset signal line in the adjacent next row pixel driving circuit. The orthographic projection of the first conductive portion 11 onto the substrate covers the orthographic projection of the third active portion 73 onto the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to conduct the active layer, that is, the area of ​​the active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first gate layer forms a conductor structure.

[0134] As shown in Figures 2, 5, and 10, the second gate layer may include: a second conductive portion 22, a first connecting portion 23, a fourth conductive portion 24, a second connecting portion 25, a first initial signal line Vinit1, and a second initial signal line Vinit2. The orthographic projections of the first initial signal line Vinit1 and the second initial signal line Vinit2 on the substrate can extend along a first direction X. The first initial signal line Vinit1 provides the first initial signal terminal in Figure 1, and the second initial signal line Vinit2 provides the second initial signal terminal in Figure 1. The orthographic projection of the second conductive portion 22 on the substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate. The second conductive portion 22 forms the second electrode of the capacitor C. The first connecting portion 23 connects between two adjacent second conductive portions 22 in the same pixel driving circuit group Pz, and the second connecting portion 25 connects between two adjacent second conductive portions 22 located in different pixel driving circuit groups Pz. The orthographic projection of the fourth conductive part 24 on the substrate and the orthographic projection of the fourteenth active part 714 on the substrate overlap. The fourth conductive part 24 can be connected to a first initial signal terminal, a second initial signal terminal, a first power supply terminal, and other stable voltage terminals. The fourth conductive part 24 can be used to regulate the voltage of the fourteenth active part 714 to reduce the leakage current of the fourteenth active part 714 to the source and drain of the second transistor T2.

[0135] As shown in Figures 2, 6, and 11, the first source-drain layer may include a first bridging section 41, a second bridging section 42, a third bridging section 43, a fourth bridging section 44, a fifth bridging section 45, a sixth bridging section 46, a seventh bridging section 47, an eleventh bridging section 411, and a first sector output line FIPH. The first bridging portion 41 connects the second initial signal line Vinit2 and the tenth active portion 710 through vias to connect the second initial signal terminal and the first electrode of the seventh transistor. The orthographic projection of the first bridging portion 41 on the substrate extends at least partially along the second direction Y. The second bridging portion 42 can connect the second connecting portion 25 and the fourth conductive portion 24 through vias to connect the fourth conductive portion 24 to the first power supply terminal through the second connecting portion 25. The third bridging portion 43 can connect the first conductive portion 11 and the ninth active portion 79 through vias to connect the gate of the driving transistor T3 and the second electrode of the first transistor T1 and the first electrode of the second transistor T2. An opening 221 is formed on the second conductive portion 22, and the via connecting the first conductive portion 11 and the third bridging portion 43 can be disposed through the opening 221. The fourth bridging section 44 can be connected to the thirteenth active section 713 via vias to connect the second terminals of the sixth and seventh transistors; the fifth bridging section 45 can be connected to the sixteenth active section 716 via vias to connect the first terminal of the fourth transistor; the sixth bridging section 46 can be connected to the seventeenth active section 717 and the first initial signal line Vinit1 via vias to connect the first terminal of the first transistor T1 and the first initial signal terminal; the seventh bridging section 47 can be connected to the first connecting section 23 and the eighth active section 78 via vias to connect the first terminal of the fifth transistor T5 and the second electrode of the capacitor C. The orthographic projection of the eleventh bridging section 411 on the substrate extends at least partially along the second direction Y, and the eleventh bridging section 411 is connected to the first initial signal line Vinit1 via vias. The orthographic projection of the first fan-out line FIPH on the substrate can extend along the first direction X, and the first fan-out line FIPH can serve as a row fan-out line connecting data lines in the FIP (Fanout In Pixel).

[0136] As shown in Figures 2, 7, and 12, the second source / drain layer may include a data line Da, a power line VDD, a second fan-out line FIPV, an eighth bridge section 58, a ninth bridge section 59, and a twelfth bridge section 512. The orthographic projections of the data line Da, power line VDD, and second fan-out line FIPV onto the substrate all extend along the second direction Y. The data line Da provides the data signal terminal shown in Figure 1. The data line Da can be connected to the fifth bridge section 45 via a via to connect the data signal terminal and the first terminal of the fourth transistor T4. The power line VDD provides the first power terminal shown in Figure 1. The power line VDD can be connected to the second bridge section 42 via a via to connect the first power terminal and the first terminal of the fifth transistor T5 and the second terminal of the capacitor C. The eighth bridge section 58 is connected to the fourth bridge section 44 via a via. The orthographic projection of the ninth bridging portion 59 on the substrate extends at least partially along the second direction Y. The ninth bridging portion 59 is connected to two adjacent first bridging portions 41 in the second direction Y via vias. The orthographic projection of the ninth bridging portion 59 on the substrate intersects with the orthographic projection of the first fan-out line FIPH on the substrate. The ninth bridging portion 59 and the first bridging portions 41 connected by vias form the second initial signal connection line Vinit2h. The twelfth bridging portion 512 is connected to two adjacent eleventh bridging portions 411 in the second direction Y via vias. The orthographic projection of the twelfth bridging portion 512 on the substrate intersects with the orthographic projection of the first fan-out line FIPH on the substrate. The twelfth bridging portion 512 and the eleventh bridging portion 411 connected by vias form the first initial signal connection line Vinit1h. The second fan-out line FIPV can be used as a column-direction fan-out line connecting data lines in the FIP (Fanout In Pixel).

[0137] As shown in Figures 2 and 8, the electrode layer may include multiple electrode sections: these multiple electrode sections include a first electrode section R, a second electrode section B, and a third electrode section G. Each electrode section can be connected to an eighth bridge section 58 via a via to connect to the second electrode of the sixth transistor. Among the multiple electrode sections connected to the same row of pixel driving circuits, the first electrode section R, the third electrode section G, the second electrode section B, and the third electrode section G are sequentially and alternately distributed in the first direction. In two adjacent columns of pixel driving circuits, multiple first electrode sections R and multiple second electrode sections B are connected to the same column of pixel driving circuits, and the first electrode sections R and second electrode sections B connected to the same column of pixel driving circuits are sequentially and alternately distributed in the second direction. Multiple third electrode sections G are connected to another column of pixel driving circuits. The third electrode section G can serve as the first electrode of a green light-emitting unit, the first electrode section R can serve as the first electrode of a red light-emitting unit, and the second electrode section B can serve as the first electrode of a blue light-emitting unit.

[0138] Figure 13 shows a partial cross-sectional view of the display panel shown in Figure 2, taken along the dashed line AA. The display panel may further include a first insulating layer 101, a second insulating layer 102, a dielectric layer 103, a passivation layer 104, a first planarization layer 105, and a second planarization layer 106. The substrate 100, active layer, first insulating layer 101, first gate layer, second insulating layer 102, second gate layer, dielectric layer 103, first source / drain layer, passivation layer 104, first planarization layer 105, second source / drain layer, second planarization layer 106, and electrode layer are sequentially stacked. The first insulating layer 101 and the second insulating layer 102 can be single-layer or multi-layer structures, and the material of the first insulating layer 101 and the second insulating layer 102 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the dielectric layer 103 can be a silicon nitride layer; the material of the first planarization layer 105 and the second planarization layer 106 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 104 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The material of the first gate layer and the second gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of either the first or second source / drain layer can be less than the sheet resistance of either the first or second gate layer.

[0139] As shown in Figures 14-24, Figure 14 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure, Figure 15 is a structural layout diagram of the active layer in the display panel shown in Figure 14, Figure 16 is a structural layout diagram of the first gate layer in the display panel shown in Figure 14, Figure 17 is a structural layout diagram of the second gate layer in the display panel shown in Figure 14, Figure 18 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 14, Figure 19 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 14, Figure 20 is a structural layout diagram of the electrode layer in the display panel shown in Figure 14, Figure 21 is a structural layout diagram of the active layer and the first gate layer in the display panel shown in Figure 14, Figure 22 is a structural layout diagram of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 14, Figure 23 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 14, and Figure 24 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, the first source / drain layer, and the second source / drain layer in the display panel shown in Figure 14.

[0140] The difference between the display panel shown in Figure 14 and the display panel shown in Figure 2 is:

[0141] In the display panel shown in Figure 2, the orthographic projection of the second initial signal line Vinit2 connected to the adjacent upper row pixel driving circuit on the substrate is at least partially located between the orthographic projection of the enable signal line EM in the current row pixel driving circuit on the substrate and the orthographic projection of the first initial signal line Vinit1 connected to the adjacent lower row pixel driving circuit on the substrate. The orthographic projection of the first fan-out line FIPH on the substrate is at least partially located between the orthographic projection of the second initial signal line Vinit2 connected to the adjacent upper row pixel driving circuit and the orthographic projection of the first initial signal line Vinit1 connected to the adjacent lower row pixel driving circuit on the substrate. The second initial signal lines Vinit2 and Vinit1 located on both sides of the first fan-out line FIPH can shield the first fan-out line FIPH from interference with other signals. In the display panel shown in Figure 14, the orthographic projection of the second initial signal line Vinit2 connected to the current row pixel driving circuit on the substrate is at least partially located between the orthographic projection of the first gate line G1 in the adjacent lower row pixel driving circuit on the substrate and the orthographic projection of the second reset signal line Re2 in the current row pixel driving circuit on the substrate.

[0142] In the display panel shown in Figure 2, adjacent power lines VDD in adjacent pixel driving circuit groups Pz in the first direction X are connected, and the orthographic projection of the two connected power lines VDD on the substrate lies between the orthographic projections of the two adjacent data lines Da on the substrate. The power lines VDD can shield signal interference between adjacent data lines. In the display panel shown in Figure 14, adjacent power lines VDD in adjacent pixel driving circuit groups Pz in the first direction X are spaced apart. Correspondingly, a tenth bridging portion 410 is added to the first source / drain layer in the display panel shown in Figure 14. The tenth bridging portion 410 is connected to the second conductive portion 22 through a via, and the power lines VDD are connected to the tenth bridging portion 410 through a via.

[0143] In the display panel shown in Figure 2, the first initial signal connection line Vinit1h and the second initial signal connection line Vinit2h form the initial signal connection line Vinith. Each column of pixel driving circuits Pix can be correspondingly provided with one initial signal line Vinith. The orthographic projections of the first initial signal connection line Vinit1h and the second initial signal connection line Vinit2h on the substrate are alternately distributed along the first direction X, and the initial signal connection line Vinith is formed by the first source / drain layer and the second source / drain layer. In the display panel shown in Figure 14, the first initial signal connection line Vinit1h and the second initial signal connection line Vinit2h form the initial signal connection line Vinith. Each column of pixel driving circuits Pz can be correspondingly provided with one initial signal line. The orthographic projections of the first initial signal connection line Vinit1h and the second initial signal connection line Vinit2h on the substrate are alternately distributed along the first direction X, and the initial signal connection line Vinith is formed by the second source / drain layer.

[0144] In the display panel shown in Figure 2, the orthographic projection of the second fan-out line FIPV on the substrate is located between the orthographic projections of two adjacent data lines Da on the substrate. This arrangement increases the distance between two adjacent data lines Da, thereby reducing mutual interference between them. The orthographic projection of the initial signal connection line Vinith on the substrate is at least partially located between the orthographic projections of the data lines Da and VDD on the substrate. In the display panel shown in Figure 14, the orthographic projection of the initial signal connection line Vinith on the substrate is located between the orthographic projections of two adjacent data lines Da on the substrate. The initial signal connection line Vinith is used to shield the interference between two adjacent data lines Da. The orthographic projection of the second fan-out line FIPV on the substrate is located between the orthographic projections of two adjacent power lines VDD on the substrate. The power lines VDD can shield the data lines Da from interference caused by the second fan-out line FIPV.

[0145] As shown in Figures 25-35, Figure 25 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure, Figure 26 is a structural layout diagram of the active layer in the display panel shown in Figure 25, Figure 27 is a structural layout diagram of the first gate layer in the display panel shown in Figure 25, Figure 28 is a structural layout diagram of the second gate layer in the display panel shown in Figure 25, Figure 29 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 25, Figure 30 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 25, Figure 31 is a structural layout diagram of the electrode layer in the display panel shown in Figure 25, Figure 32 is a structural layout diagram of the active layer and the first gate layer in the display panel shown in Figure 25, Figure 33 is a structural layout diagram of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 25, Figure 34 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 25, and Figure 35 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, the first source / drain layer, and the second source / drain layer in the display panel shown in Figure 25.

[0146] The difference between the display panel shown in Figure 25 and the display panel shown in Figure 14 is:

[0147] In the display panel shown in Figure 14, each column of pixel driving circuit group Pz is provided with a corresponding second fan-out line FIPV. In the display panel shown in Figure 25, each column of pixel driving circuit Pix is ​​provided with a corresponding second fan-out line FIPV.

[0148] In the display panel shown in FIG14, the second connecting portion 25 is connected between two adjacent second conductive portions 22 located in different pixel driving circuit groups Pz. In the display panel shown in FIG25, the second connecting portion 25 is not provided, and two adjacent tenth bridging portions 410 located in different pixel driving circuit groups Pz are connected on the same layer.

[0149] It should be noted that, as shown in Figure 2-35, the black squares drawn on the side of the first source / drain layer away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black circles with chamfers drawn on the side of the second source / drain layer away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the rounded rectangles drawn on the side of the electrode layer away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. Vias at different positions can penetrate different insulating layers.

[0150] In this exemplary embodiment, as shown in Figures 2-35, at least a portion of the first fan-out line FIPH and at least a portion of the second fan-out line FIPV are located in the display area. The first fan-out line FIPH is located in the first source-drain layer, and at least a portion of the data line Da, at least a portion of the power line VDD, at least a portion of the initial signal connection line Vinith, and at least a portion of the second fan-out line FIPV are located in the second source-drain layer. This exemplary embodiment achieves FIP technology through a dual source-drain layer, resulting in a relatively simple structure for the display panel.

[0151] In this exemplary embodiment, as shown in FIG2-12, the first bridging portion 41 and the eleventh bridging portion 411 can each form a first connecting line segment, and the ninth bridging portion 59 and the twelfth bridging portion 512 can each form a second connecting line segment. The orthographic projections of the first connecting line segment and the second connecting line segment on the substrate are alternately distributed along the second direction. The first connecting line segment is located in the first source / drain layer, and the second connecting line segment is located in the second source / drain layer. The second connecting line segment is connected to the first connecting line segment through vias, and the orthographic projection of the second connecting line segment on the substrate intersects with the orthographic projection of the first fan-out line on the substrate.

[0152] In this exemplary embodiment, as shown in FIG2-35, the second gate layer may further include a first protrusion 26 connected to one side of the first initial signal line in the second direction Y. The overlapping area of ​​the orthographic projection of the first fan-out line FIPH on the substrate and the orthographic projection of the thirteenth active part 713 on the substrate at least partially overlaps with the orthographic projection of the first protrusion 26 on the substrate. The first protrusion 26 can shield the voltage influence of the first fan-out line FIPH on the thirteenth active part 713.

[0153] In this exemplary embodiment, as shown in FIG2-35, the second gate layer may further include a second protrusion 27, which is connected to one side of the first initial signal line in the second direction. The orthographic projection of the second protrusion 27 on the substrate and the orthographic projection of the fifteenth active portion 715 on the substrate at least partially overlap. The second protrusion 27 can regulate the voltage of the fifteenth active portion 715 to reduce the leakage current of the fifteenth active portion 715 to the source and drain of the first transistor.

[0154] In this exemplary embodiment, as shown in Figures 14-35, the second gate layer may further include a third protrusion 29, which is connected to one side of the second initial signal line in the second direction. The orthographic projection of the third protrusion 29 on the substrate is located between the orthographic projection of the data line Da on the substrate and the orthographic projection of the ninth active portion 79 on the substrate. The third protrusion 29 can shield the data line Da from signal interference to the ninth active portion 79.

[0155] In this exemplary embodiment, as shown in Figures 14-35, the second gate layer may further include a fourth protrusion 28, which is connected to one side of the second initial signal line in the second direction; wherein the orthographic projection of the fourth protrusion 28 on the substrate and the orthographic projection of the fourteenth active portion 714 on the substrate at least partially overlap. The fourth protrusion 28 can regulate the voltage of the fourteenth active portion 714 to reduce the leakage current of the fourteenth active portion 714 to the source and drain of the second transistor.

[0156] In this exemplary embodiment, compared to the red and green light-emitting units, the blue light-emitting unit requires a smaller gate voltage from the driving transistor to be turned on. The data range (voltage range of the data signal) corresponding to the blue light-emitting unit is different from that corresponding to the red light-emitting unit. Furthermore, since multiple first electrode portions R and multiple second electrode portions B are connected to the same column of pixel driving circuits, and the same column of pixel driving circuits are connected to the same data line Da, the data signal on the data line needs to switch even when the display panel displays the same grayscale image during line-by-line scanning. This increases the power consumption of the display panel.

[0157] In this exemplary embodiment, as shown in Figures 25-35, the orthogonal projection area of ​​the opening 221 on the substrate of the second conductive part 22 in the pixel driving circuit connected to the second electrode part B is smaller than the orthogonal projection area of ​​the opening 221 on the substrate of the second conductive part 22 in the pixel driving circuit connected to the first electrode part R; the orthogonal projection area of ​​the opening 221 on the substrate of the second conductive part 22 in the pixel driving circuit connected to the second electrode part B is smaller than the orthogonal projection area of ​​the opening 221 on the substrate of the second conductive part 22 in the pixel driving circuit connected to the third electrode part G. Therefore, the capacitor in the pixel driving circuit driving the blue light-emitting unit is greater than the capacitor in the pixel driving circuit driving the red light-emitting unit, and the capacitor in the pixel driving circuit driving the blue light-emitting unit is greater than the capacitor in the pixel driving circuit driving the green light-emitting unit. The voltage of the data signal required to write the same voltage to the gate of the corresponding driving transistor of the blue light-emitting unit is greater than the voltage required to write the same voltage to the gate of the corresponding driving transistor of the red light-emitting unit, and the voltage of the data signal required to write the same voltage to the gate of the corresponding driving transistor of the blue light-emitting unit is greater than the voltage required to write the same voltage to the gate of the corresponding driving transistor of the green light-emitting unit. Furthermore, this setting allows the data range corresponding to the blue light-emitting unit and the data range corresponding to the red light-emitting unit to be the same, so that the data line does not need to jump when the display panel displays the same grayscale image. This setting can reduce the power consumption of the display panel.

[0158] This exemplary embodiment also provides a display panel, which includes a plurality of pixel driving circuit groups. The orthographic projections of the plurality of pixel driving circuit groups on a substrate are arrayed along a first direction and a second direction, and the first direction and the second direction intersect. Each pixel driving circuit group includes two pixel driving circuits distributed along the first direction, and the two pixel driving circuits in the same pixel driving circuit group are at least partially mirror-symmetrically arranged. Each pixel driving circuit includes a driving transistor, a first transistor, and a fifth transistor. The first electrode of the first transistor is connected to a first initial signal line, and the second electrode is connected to the gate of the driving transistor. The first electrode of the fifth transistor is connected to a power supply line, and the second electrode is connected to the first electrode of the driving transistor. The display panel further includes a substrate and an active layer. The active layer is located on one side of the substrate and includes a first active portion and a fifth active portion. The first active portion is used to form a channel region of the first transistor, and the fifth active portion is used to form a channel region of the fifth transistor. In the same pixel driving circuit group, two adjacent first active portions are connected in the same layer, and two adjacent fifth active portions are connected in the same layer. Other structures of this display panel can be shown in Figures 2-35.

[0159] Figure 36 shows a schematic diagram of an exemplary embodiment of the display panel of this disclosure. The display panel may further include a gating circuit MUX, which is connected between the output terminal Dac of the source driver chip and the data line Da. The gating circuit MUX is used to input the signal from the output terminal Dac of the source driver chip to the data line Da in a time-division multiplexing manner. For example, the gating circuit MUX includes multiple transistors, which are controlled by gating signal terminals Mux1 and Mux2 to input the signal from the output terminal Dac of the source driver chip to the data line Da in a time-division multiplexing manner. The gating circuit MUX may be located in the bezel area, and the pixel driver circuit Pix may be located in the display area CC. This display panel can reduce the number of source driver chips.

[0160] Figure 37 shows the timing diagram of each node in a driving method for the display panel of this disclosure. Re1 is the timing diagram of the first reset signal terminal, Re2 is the timing diagram of the second reset signal terminal, G1 is the timing diagram of the first gate drive signal terminal, Mux1 is the timing diagram of the gating signal terminal Mux1, Mux2 is the timing diagram of the gating signal terminal Mux2, and Da is the timing diagram of the data signal terminal. In the first time period t1, the gating signal terminal Mux2 turns on the transistor connected to it, so that the output terminal Dac of the source drive chip provides a data signal to the data line through the turned-on transistor. In the third time period t3, the data line writes a compensation voltage to node N. In the second time period t2, the signal on the data line is easily interfered with by other signals, causing jumps. The layout structure of the display panel described above can improve the problem of data lines being interfered with by other signals.

[0161] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0162] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0163] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0164] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes a display area, and the display panel further includes: Substrate; Multiple pixel driving circuits, wherein the orthographic projections of the multiple pixel driving circuits on the substrate are distributed in an array along a first direction and a second direction, the first direction and the second direction intersecting; Multiple data lines, whose orthogonal projections on the substrate extend along the second direction and are spaced apart along the first direction, are used to provide data signals to the pixel driving circuit. Multiple power lines, whose orthogonal projections on the substrate extend along the second direction and are spaced apart along the first direction, and the data lines are used to provide power signals to the pixel driving circuit. Multiple initial signal connection lines, whose orthogonal projections on the substrate extend along the second direction and are spaced apart along the first direction, are used to provide initial signals to the pixel driving circuit. Multiple first fan-out lines, whose orthogonal projections on the substrate extend along the first direction and are spaced apart along the second direction; Multiple second fan-out lines, whose orthographic projection on the substrate extends along the second direction and are spaced apart along the first direction, and at least a portion of the multiple first fan-out lines are connected between the data line and the second fan-out lines, and at least a portion of the first fan-out lines and at least a portion of the second fan-out lines are located in the display area; The pixel driving circuit includes a plurality of transistors, and the display panel further includes a first source-drain layer and a second source-drain layer. The first source-drain layer is located on one side of the substrate, and the second source-drain layer is located on the side of the first source-drain layer opposite to the substrate. At least a portion of the structure of the first source-drain layer is bridged between different transistors. The first fan-out line is located in the first source-drain layer, and at least a portion of the data line, at least a portion of the power line, at least a portion of the initial signal connection line, and at least a portion of the second fan-out line are located in the second source-drain layer.

2. The display panel according to claim 1, wherein, The initial signal connection line includes a first connection segment and a second connection segment, and the orthographic projections of the first connection segment and the second connection segment on the substrate are alternately distributed along the second direction. Wherein, the first connecting segment is located in the first source / drain layer, the second connecting segment is located in the second source / drain layer, the second connecting segment is connected to the first connecting segment through a via, and the orthographic projection of the second connecting segment on the substrate intersects the orthographic projection of the first fan-out line on the substrate.

3. The display panel according to claim 1, wherein, One or more of the data line, power line, initial signal connection line, and second fan-out line are located in the second source / drain layer.

4. The display panel according to claim 1, wherein, The display panel includes multiple pixel driving circuit groups, and the orthographic projections of the multiple pixel driving circuit groups on the substrate are distributed in an array along the first direction and the second direction. Each pixel driving circuit group includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same pixel driving circuit group are at least partially mirror-symmetrically arranged. Among them, two adjacent pixel driving circuit groups are respectively located in the first direction and two adjacent power lines are connected, and the orthogonal projection of the two connected power lines on the substrate is located between the orthogonal projections of the two adjacent data lines on the substrate.

5. The display panel according to claim 1, wherein, The orthographic projection of the second fan-out line on the substrate is located between two adjacent data lines.

6. The display panel according to claim 1, wherein, The display panel further includes a light-emitting unit. The pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit includes a driving transistor, a first transistor, a fifth transistor, and a seventh transistor. The first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the gate of the driving transistor. The first terminal of the fifth transistor is connected to a power supply line, and the second terminal is connected to the first terminal of the driving transistor. The gate of the fifth transistor is connected to an enable signal line. The first terminal of the seventh transistor is connected to a second initial signal line, and the second terminal is connected to the light-emitting unit. The enable signal line, the first initial signal line, and the second initial signal line are projected onto the substrate and extend along the first direction. Wherein, the orthographic projection of the second initial signal line connected to the adjacent previous row pixel driving circuit on the substrate is at least partially located between the orthographic projection of the enable signal line in the current row pixel driving circuit on the substrate and the orthographic projection of the first initial signal line connected to the adjacent next row pixel driving circuit on the substrate. The orthographic projection of the first fan-out line on the substrate is at least partially located between the orthographic projection of the second initial signal line connected to the adjacent previous row pixel driving circuit on the substrate and the orthographic projection of the first initial signal line connected to the adjacent next row pixel driving circuit on the substrate.

7. The display panel according to claim 1, wherein, The display panel includes multiple pixel driving circuit groups, and the orthographic projections of the multiple pixel driving circuit groups on the substrate are distributed in an array along the first direction and the second direction. Each pixel driving circuit group includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same pixel driving circuit group are at least partially mirror-symmetrically arranged. The two power lines located in adjacent pixel driving circuit groups in the first direction are spaced apart, and the orthogonal projections of the two power lines located in adjacent pixel driving circuit groups in the first direction on the substrate are located on both sides of the orthogonal projection of the second fan-out line on the substrate.

8. The display panel according to claim 1, wherein, The orthographic projection of the initial signal connection line on the substrate lies between the orthographic projections of the two adjacent data lines on the substrate.

9. The display panel according to claim 1, wherein, Each column of pixel driving circuits is provided with one second fan-out line, or multiple columns of pixel driving circuits are provided with one second fan-out line.

10. The display panel according to any one of claims 1-9, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit includes a driving transistor and a first transistor. The first electrode of the first transistor is connected to a first initial signal line, and the second electrode is connected to the gate of the driving transistor. The display panel also includes: An active layer is located between the substrate and the first source / drain layer. The active layer includes a thirteenth active portion, which is used to connect the light-emitting unit. A second gate layer is located between the active layer and the first source / drain layer. The second gate layer includes the first initial signal line and a first protrusion. The orthographic projection of the first initial signal line on the substrate extends along the first direction, and the first protrusion is connected to one side of the first initial signal line in the second direction. The overlapping area of ​​the orthographic projection of the first fan-out line on the substrate and the orthographic projection of the thirteenth active part on the substrate at least partially overlaps with the orthographic projection of the first protrusion on the substrate.

11. The display panel according to claim 10, wherein, The active layer further includes: a first active portion and a fifteenth active portion, the first active portion including a first sub-active portion and a second sub-active portion, the first sub-active portion and the second sub-active portion being used to form the channel region of the first transistor, and the fifteenth active portion being connected between the first sub-active portion and the second sub-active portion. The second gate layer further includes: The second protrusion is connected to one side of the first initial signal line in the second direction, and the orthographic projection of the second protrusion on the substrate and the orthographic projection of the fifteenth active part on the substrate at least partially overlap.

12. The display panel according to any one of claims 1-9, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit includes a driving transistor and a seventh transistor. The first terminal of the seventh transistor is connected to the second initial signal line, and the second terminal is connected to the light-emitting unit. The display panel also includes: An active layer is located between the substrate and the first source / drain layer. The active layer includes a ninth active portion, which is used to connect to the gate of the driving transistor. A second gate layer is located between the active layer and the first source / drain layer. The second gate layer includes a second initial signal line and a third protrusion. The orthographic projection of the second initial signal line on the substrate extends along the first direction. The third protrusion is connected to one side of the second initial signal line in the second direction. The orthographic projection of the third protrusion on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the ninth active part on the substrate.

13. The display panel according to any one of claims 1-9, wherein, The display panel further includes a light-emitting unit. The pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit includes a driving transistor, a second transistor, and a seventh transistor. The first terminal of the second transistor is connected to the gate of the driving transistor, and the second terminal is connected to the second terminal of the driving transistor. The first terminal of the seventh transistor is connected to the second initial signal line, and the second terminal is connected to the light-emitting unit. The display panel also includes: An active layer is located between the substrate and the first source / drain layer. The active layer includes a second active portion and a fourteenth active portion. The second active portion includes a third sub-active portion and a fourth sub-active portion. The third sub-active portion and the fourth sub-active portion are respectively used to form the channel region of the second transistor. The fourteenth active portion is connected between the third sub-active portion and the fourth sub-active portion. A second gate layer is located between the active layer and the first source / drain layer. The second gate layer includes a second initial signal line and a fourth protrusion. The orthographic projection of the second initial signal line on the substrate extends along the first direction. The fourth protrusion is connected to one side of the second initial signal line in the second direction. Wherein, the orthographic projection of the fourth protrusion on the substrate and the orthographic projection of the fourteenth active portion on the substrate at least partially overlap.

14. The display panel according to any one of claims 1-9, wherein, The pixel driving circuit includes a driving transistor, a first transistor, and a fifth transistor. The first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the gate of the driving transistor. The first terminal of the fifth transistor is connected to a power supply line, and the second terminal is connected to the first terminal of the driving transistor. The display panel includes multiple pixel driving circuit groups, and the orthographic projections of the multiple pixel driving circuit groups on the substrate are distributed in an array along the first direction and the second direction. Each pixel driving circuit group includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same pixel driving circuit group are at least partially mirror-symmetrically arranged. The display panel also includes: An active layer, the active layer including a first active portion and a fifth active portion, the first active portion being used to form the channel region of the first transistor, and the fifth active portion being used to form the channel region of the fifth transistor; In the same pixel driving circuit group, two adjacent first active parts are connected on the same layer, and two adjacent fifth active parts are connected on the same layer.

15. The display panel according to any one of claims 1-9, wherein, The display panel also includes: Multiple initial signal lines, whose orthogonal projections on the substrate extend along the first direction and are spaced apart along the second direction; The initial signal connection line is connected via vias to at least partially intersecting with the same initial signal line.

16. The display panel according to any one of claims 1-9, wherein, The pixel driving circuit also includes a driving transistor and a capacitor, wherein the first electrode of the capacitor is connected to the gate of the driving transistor and the second electrode is connected to a power supply line. The display panel also includes: A first gate layer is located between the substrate and the first source / drain layer. The first gate layer includes a first conductive portion, which is used to form the gate of the driving transistor and the first electrode of the capacitor. A second gate layer is located between the first gate layer and the first source / drain layer. The second gate layer includes a second conductive portion. The orthographic projection of the second conductive portion on the substrate overlaps with the orthographic projection of the first conductive portion on the substrate. The second conductive portion is used to form the second electrode of the capacitor. An electrode layer is located on the side of the second source / drain layer away from the substrate. The electrode layer includes multiple electrode portions, including a first electrode portion and a second electrode portion. The multiple first electrode portions and the multiple second electrode portions are connected to the same column of pixel driving circuits. The orthogonal projection area of ​​the opening on the second conductive part of the pixel driving circuit connected to the second electrode part on the substrate is smaller than the orthogonal projection area of ​​the opening on the second conductive part of the pixel driving circuit connected to the first electrode part on the substrate.

17. The display panel according to any one of claims 1-9, wherein, The pixel driving circuit includes: Drive transistors; The first transistor has a first terminal connected to a first initial signal line and a second terminal connected to the gate of the driving transistor, the gate of which is connected to a first reset signal line. The second transistor has a first terminal connected to the gate of the driving transistor, a second terminal connected to the first terminal of the driving transistor, and a gate connected to the first gate line. The fourth transistor has its first terminal connected to the data line, its second terminal connected to the first terminal of the driving transistor, and its gate connected to the first gate line. The fifth transistor has its first terminal connected to the power supply line, its second terminal connected to the first terminal of the driving transistor, and its gate connected to the enable signal line. The sixth transistor has its first terminal connected to the second terminal of the driving transistor, the second terminal connected to the light-emitting unit, and its gate connected to the enable signal line. The seventh transistor has its first terminal connected to the second initial signal line, its second terminal connected to the second terminal of the sixth transistor, and its gate connected to the second reset signal line.

18. The display panel according to claim 17, wherein, The display panel also includes: An active layer is located between the substrate and the first source / drain layer, and at least a portion of the structure of the active layer is used to form the channel regions of the driving transistor, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor. A first gate layer is located between the active layer and the first source / drain layer. The first gate layer includes a first conductive portion, a first reset signal line, a first gate line, an enable signal line, and a second reset signal line. The orthogonal projections of the first reset signal line, the first gate line, the enable signal line, and the second reset signal line on the substrate extend along the first direction. Wherein, at least a portion of the structure of the first reset signal line is used to form the gate of the first transistor, at least a portion of the structure of the second reset signal line is used to form the gate of the seventh transistor, at least a portion of the structure of the first gate line is used to form the gates of the second and fourth transistors, at least a portion of the structure of the enable signal line is used to form the gates of the fifth and sixth transistors, and the first conductive portion is used to form the gate of the driving transistor. In the same pixel driving circuit, the orthographic projections of the first reset signal line, the first gate line, the enable signal line, and the second reset signal line on the substrate are distributed sequentially at intervals along the second direction, and the orthographic projection of the first conductive part on the substrate is located between the orthographic projection of the first gate line on the substrate and the orthographic projection of the enable signal line on the substrate.

19. A display panel, wherein, The display panel includes multiple pixel driving circuit groups, which are arrayed along a first direction and a second direction, the first direction and the second direction intersecting. The pixel driving circuit group includes two pixel driving circuits distributed in the first direction, and the two pixel driving circuits in the same pixel driving circuit group are at least partially mirror-symmetrically arranged. The pixel driving circuit includes a driving transistor, a first transistor, and a fifth transistor. The first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the gate of the driving transistor. The first terminal of the fifth transistor is connected to a power supply line, and the second terminal is connected to the first terminal of the driving transistor. The display panel also includes: Substrate; An active layer is located on one side of the substrate. The active layer includes a first active portion and a fifth active portion. The first active portion is used to form the channel region of the first transistor, and the fifth active portion is used to form the channel region of the fifth transistor. In the same pixel driving circuit group, two adjacent first active parts are connected on the same layer, and two adjacent fifth active parts are connected on the same layer.

20. A display device, wherein, The display device includes the display panel as described in any one of claims 1-19.

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