Array substrate, display panel, display device, driving method and display method

Abstract

Provided in the embodiments of the present disclosure are an array substrate, a display panel, a display device, a driving method and a display method. The array substrate has a plurality of pixels, each of which comprises a plurality of sub-pixels. The array substrate comprises: a base; a plurality of gate lines, which are located on one side of the base, wherein the plurality of gate lines extend in a first direction and are arranged in a second direction; and a plurality of sub-pixel rows, which are located on one side of the base, wherein the plurality of sub-pixel rows extend in the first direction and are arranged in the second direction; each of the sub-pixel rows comprises a plurality of sub-pixels arranged in the first direction; each gate line is provided between two adjacent sub-pixel rows; and the plurality of sub-pixels of the same pixel are distributed in different sub-pixel rows, and at least parts of at least two adjacent pixels in the second direction are distributed symmetrically or approximately symmetrically relative to the gate line between the two pixels.

Description

Array substrate, display panel, display device, driving method and display method Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an array substrate, a display panel, a display device, a driving method, and a display method. Background Technology

[0002] Employing a dual-gate pixel architecture reduces the number of data lines, thereby reducing the amount of source ICs and lowering display panel costs. However, due to limitations in current backplane manufacturing processes and transistor performance, as well as cost considerations, large-size dual-gate design panels at 4K resolution can only achieve a refresh rate of 60Hz. Summary of the Invention

[0003] This disclosure provides an array substrate, a display panel, a display device, a driving method, and a display method. The array substrate has multiple pixels, each pixel including multiple sub-pixels; wherein, the array substrate includes:

[0004] Substrate;

[0005] Multiple gate lines are located on one side of the substrate; the multiple gate lines extend along a first direction and are arranged along a second direction;

[0006] Multiple sub-pixel rows are located on one side of the substrate, the multiple sub-pixel rows extend along a first direction and are arranged along a second direction; each sub-pixel row includes: multiple sub-pixels arranged along the first direction; a gate line is provided between two adjacent sub-pixel rows;

[0007] In this configuration, multiple sub-pixels of the same pixel are distributed in different sub-pixel rows, and at least a portion of at least two adjacent pixels in the second direction are symmetrically or nearly symmetrically distributed with respect to the gate line between the two pixels.

[0008] In one possible implementation, the array substrate includes: a plurality of data lines; the data lines include: a plurality of first sub-data portions extending along and arranged along the second direction, and second sub-pixel portions extending along the first direction and connecting adjacent first sub-data portions; the extension lines of the first data portions connecting both sides of the second sub-data portions do not overlap;

[0009] The orthographic projection of the first sub-data section onto the substrate overlaps with the orthographic projections of the two sub-pixel rows onto the substrate.

[0010] In one possible implementation, at least two adjacent pixels in the first direction are distributed in a complementary manner.

[0011] In one possible implementation, the array substrate includes: a plurality of pixel units; the pixel unit includes a plurality of pixels, namely: a first pixel, a second pixel, a third pixel, and a fourth pixel;

[0012] The first pixel and the third pixel are distributed along the second direction and are symmetrical or nearly symmetrical about the gate line between them; the second pixel and the fourth pixel are distributed along the second direction and are symmetrical or nearly symmetrical about the gate line between them.

[0013] The first pixel and the second pixel are distributed along the first direction and are complementary in distribution, and the third pixel and the fourth pixel are distributed along the first direction and are complementary in distribution.

[0014] In one possible implementation, the pixel includes: a first sub-pixel, a second sub-pixel, and a third sub-pixel; the first sub-pixel, the second sub-pixel, and the third sub-pixel have different colors; the first sub-pixels of different pixels have the same color, the second sub-pixels of different pixels have the same color, and the third sub-pixels of different pixels have the same color.

[0015] In the first pixel, the first sub-pixel and the second sub-pixel are located in the 4n+1th sub-pixel row, and the third sub-pixel is located in the 4n+2nd sub-pixel row;

[0016] In the second pixel, the third sub-pixel is located in the 4n+1th sub-pixel row, and the first sub-pixel and the second sub-pixel are located in the 4n+2th sub-pixel row;

[0017] In the third pixel, the third sub-pixel is located in the 4n+3rd sub-pixel row, and the first sub-pixel and the second sub-pixel are located in the 4n+4th sub-pixel row;

[0018] In the fourth pixel, the first sub-pixel and the second sub-pixel are located in the 4n+3rd sub-pixel row, and the third sub-pixel is located in the 4n+4th sub-pixel row, where n represents a natural number.

[0019] In one possible implementation, the first sub-pixel of the first pixel and the first sub-pixel of the third pixel are symmetrical or nearly symmetrical about the gate line, the second sub-pixel of the first pixel and the second sub-pixel of the third pixel are symmetrical or nearly symmetrical about the gate line, and the third sub-pixel of the first pixel and the third sub-pixel of the third pixel are symmetrical or nearly symmetrical about the gate line.

[0020] The first sub-pixel of the second pixel and the first sub-pixel of the fourth pixel are symmetrical or nearly symmetrical about the gate line; the second sub-pixel of the second pixel and the second sub-pixel of the fourth pixel are symmetrical or nearly symmetrical about the gate line; the third sub-pixel of the second pixel and the third sub-pixel of the fourth pixel are symmetrical or nearly symmetrical about the gate line.

[0021] In one possible implementation, the lengths of each of the sub-pixels are equal in the first direction;

[0022] The pixels satisfy at least one of the following relationships:

[0023] 0 < d0 ≤ 0.7d1;

[0024] 0 < d0' ≤ 0.7d1';

[0025] 0 < d0" ≤ 0.7d1';

[0026] Wherein, d0 represents the distance between the center of the first sub-pixel and the center of the third sub-pixel in the first direction, d1 represents the maximum length of the sub-pixel in the first direction; d0' represents the length of the second sub-data portion in the first direction, d1' represents the distance between two adjacent first sub-data line portions in the first direction; and d0” represents the distance between the outer edges of the first sub-pixel and the third sub-pixel near the same data line in the first direction.

[0027] In one possible implementation, the pixels satisfy at least one of the following relationships:

[0028] d0 = 0.5d1;

[0029] d0' = 0.5d1';

[0030] d0” = 0.50d1.

[0031] In one possible implementation, a gate line is provided between adjacent rows of subpixels; and a subpixel is spaced between adjacent data lines.

[0032] In one possible implementation, the sub-pixels connected to the same data line have the same color.

[0033] In one possible implementation, in the first pixel, the first sub-pixel is connected to the 4N+1th gate line and the 4M+2nd data line, the second sub-pixel is connected to the 4N+1th gate line and the 4M+3rd data line, and the third sub-pixel is connected to the 4N+2th gate line and the 4M+1st data line;

[0034] In the second pixel, the first sub-pixel is connected to the 4N+2th gate line and the 4M+2nd data line, the second sub-pixel is connected to the 4N+2nd gate line and the 4M+3rd data line, and the third sub-pixel is connected to the 4N+1th gate line and the 4M+4th data line;

[0035] In the third pixel, the first sub-pixel is connected to the 4N+4th gate line and the 4M+2th data line, the second sub-pixel is connected to the 4N+4th gate line and the 4M+3th data line, and the third sub-pixel is connected to the 4N+3th gate line and the 4M+1th data line.

[0036] In the fourth pixel, the first sub-pixel is connected to the 4N+3rd gate line and the 4M+2nd data line, the second sub-pixel is connected to the 4N+3rd gate line and the 4M+3rd data line, and the third sub-pixel is connected to the 4N+4th gate line and the 4M+4th data line, where N and M represent natural numbers.

[0037] In one possible implementation, there are two gate lines between adjacent rows of sub-pixels; and two sub-pixels are spaced apart between adjacent data lines.

[0038] In one possible implementation, the array includes a plurality of pixel groups; the pixel group includes two pixel units distributed along the first direction, namely a first pixel unit and a second pixel unit;

[0039] Wherein, in the first pixel unit:

[0040] The first sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+2nd data line, the second sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+1st data line, and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+1st data line.

[0041] The first sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+2nd data line; the second sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+3rd data line; and the third sub-pixel of the second pixel is connected to the 8N+1th gate line and the 4M+2nd data line.

[0042] The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+1st data line; the second sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+2nd data line; and the third sub-pixel of the third pixel is connected to the 8N+6th gate line and the 4M+2nd data line.

[0043] The first sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+1st data line, the second sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+2nd data line, and the third sub-pixel of the fourth pixel is connected to the 8N+8th gate line and the 4M+3rd data line, where N and M represent natural numbers.

[0044] In one possible implementation, in the second pixel unit:

[0045] The first sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+3rd data line; the second sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+4th data line; and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+2nd data line.

[0046] The first sub-pixel of the second pixel is connected to the 8N+3rd gate line and the 4M+3rd data line; the second sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+4th data line; and the third sub-pixel of the second pixel is connected to the 8N+1th gate line and the 4M+3rd data line.

[0047] The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+2nd data line; the second sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+3rd data line; and the third sub-pixel of the third pixel is connected to the 8N+6th gate line and the 4M+3rd data line.

[0048] The first sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+4th data line, the second sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+3th data line, and the third sub-pixel of the fourth pixel is connected to the 8N+8th gate line and the 4M+4th data line.

[0049] In one possible implementation, the array includes a plurality of pixel groups; the pixel group includes two pixel units distributed along the first direction, namely a first pixel unit and a second pixel unit;

[0050] Wherein, in the first pixel unit:

[0051] The first sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+1th data line, the second sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+1th data line, and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+2th data line.

[0052] The first sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+2nd data line; the second sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+3rd data line; and the third sub-pixel of the second pixel is connected to the 8N+2th gate line and the 4M+2nd data line.

[0053] The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+2nd data line; the second sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+2nd data line; and the third sub-pixel of the third pixel is connected to the 8N+5th gate line and the 4M+1st data line.

[0054] The first sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+1th data line, the second sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+2th data line, and the third sub-pixel of the fourth pixel is connected to the 8N+8th gate line and the 4M+3rd data line, where N and M represent natural numbers.

[0055] In one possible implementation, in the second pixel unit:

[0056] The first sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+2nd data line, the second sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+3rd data line, and the third sub-pixel of the first pixel is connected to the 8N+3rd gate line and the 4M+3rd data line.

[0057] The first sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+4th data line; the second sub-pixel of the second pixel is connected to the 8N+3th gate line and the 4M+4th data line; and the third sub-pixel of the second pixel is connected to the 8N+1th gate line and the 4M+3rd data line.

[0058] The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+3rd data line; the second sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+4th data line; and the third sub-pixel of the third pixel is connected to the 8N+5th gate line and the 4M+2th data line.

[0059] The first sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+3rd data line, the second sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+3rd data line, and the third sub-pixel of the fourth pixel is connected to the 8N+7th gate line and the 4M+4th data line.

[0060] In one possible implementation, the array includes a plurality of pixel groups; the pixel group includes two pixel units distributed along the first direction, namely a first pixel unit and a second pixel unit;

[0061] Wherein, in the first pixel unit:

[0062] The first sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+1th data line, the second sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+1th data line, and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+2th data line.

[0063] The first sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+2nd data line; the second sub-pixel of the second pixel is connected to the 8N+3th gate line and the 4M+3rd data line; and the third sub-pixel of the second pixel is connected to the 8N+1th gate line and the 4M+2nd data line.

[0064] The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+2nd data line; the second sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+2nd data line; and the third sub-pixel of the third pixel is connected to the 8N+5th gate line and the 4M+1st data line.

[0065] The first sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+1st data line, the second sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+2nd data line, and the third sub-pixel of the fourth pixel is connected to the 8N+7th gate line and the 4M+3rd data line, where N and M represent natural numbers.

[0066] In one possible implementation, in the second pixel unit:

[0067] The first sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+2nd data line, the second sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+3rd data line, and the third sub-pixel of the first pixel is connected to the 8N+4th gate line and the 4M+3rd data line.

[0068] The first sub-pixel of the second pixel is connected to the 8N+3rd gate line and the 4M+4th data line; the second sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+4th data line; and the third sub-pixel of the second pixel is connected to the 8N+2th gate line and the 4M+3rd data line.

[0069] The first sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+3rd data line; the second sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+4th data line; and the third sub-pixel of the third pixel is connected to the 8N+6th gate line and the 4M+2th data line.

[0070] The first sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+3rd data line, the second sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+3rd data line, and the third sub-pixel of the fourth pixel is connected to the 8N+8th gate line and the 4M+4th data line.

[0071] In one possible implementation, the array includes a plurality of pixel groups; the pixel group includes two pixel units distributed along the first direction, namely a first pixel unit and a second pixel unit;

[0072] Wherein, in the first pixel unit:

[0073] The first sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+2nd data line, the second sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+1st data line, and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+2nd data line;

[0074] The first sub-pixel of the second pixel is connected to the 8N+3rd gate line and the 4M+1st data line; the second sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+3rd data line; and the third sub-pixel of the second pixel is connected to the 8N+2th gate line and the 4M+3rd data line.

[0075] The first sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+2nd data line; the second sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+1st data line; and the third sub-pixel of the third pixel is connected to the 8N+6th gate line and the 4M+2nd data line.

[0076] The first sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+1st data line, the second sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+3rd data line, and the third sub-pixel of the fourth pixel is connected to the 8N+8th gate line and the 4M+3rd data line, where N and M represent natural numbers.

[0077] In one possible implementation, in the second pixel unit:

[0078] The first sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+2nd data line; the second sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+4th data line; and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+2nd data line.

[0079] The first sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+4th data line; the second sub-pixel of the second pixel is connected to the 8N+3th gate line and the 4M+3th data line; and the third sub-pixel of the second pixel is connected to the 8N+1th gate line and the 4M+3rd data line.

[0080] The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+2nd data line; the second sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+4th data line; and the third sub-pixel of the third pixel is connected to the 8N+5th gate line and the 4M+2nd data line.

[0081] The first sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+4th data line, the second sub-pixel is connected to the 8N+5th gate line and the 4M+3rd data line, and the third sub-pixel is connected to the 8N+7th gate line and the 4M+3rd data line.

[0082] In one possible implementation, the array includes a plurality of pixel groups; the pixel group includes two pixel units distributed along the first direction, namely a first pixel unit and a second pixel unit;

[0083] Wherein, in the first pixel unit:

[0084] The first sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+1th data line, the second sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+2th data line, and the third sub-pixel of the first pixel is connected to the 8N+4th gate line and the 4M+1th data line;

[0085] The first sub-pixel of the second pixel is connected to the 8N+3rd gate line and the 4M+2nd data line; the second sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+2nd data line; and the third sub-pixel of the second pixel is connected to the 8N+1th gate line and the 4M+2nd data line.

[0086] The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+1st data line; the second sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+2nd data line; and the third sub-pixel of the third pixel is connected to the 8N+6th gate line and the 4M+1st data line.

[0087] The first sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+2nd data line, the second sub-pixel is connected to the 8N+6th gate line and the 4M+2nd data line, and the third sub-pixel is connected to the 8N+7th gate line and the 4M+2nd data line, where N and M represent natural numbers.

[0088] In one possible implementation, in the second pixel unit:

[0089] The first sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+3rd data line; the second sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+3rd data line; and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+3rd data line.

[0090] The first sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+3rd data line; the second sub-pixel of the second pixel is connected to the 8N+3rd gate line and the 4M+4th data line; and the third sub-pixel of the second pixel is connected to the 8N+2th gate line and the 4M+4th data line.

[0091] The first sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+3rd data line; the second sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+3rd data line; and the third sub-pixel of the third pixel is connected to the 8N+5th gate line and the 4M+3rd data line.

[0092] The first sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+3rd data line, the second sub-pixel is connected to the 8N+5th gate line and the 4M+4th data line, and the third sub-pixel is connected to the 8N+8th gate line and the 4M+4th data line.

[0093] In one possible implementation, the maximum length of the sub-pixel in the first direction is greater than the maximum width of the sub-pixel in the second direction.

[0094] In one possible implementation, the ratio of the maximum length of the sub-pixel in the first direction to the maximum width in the second direction ranges from 1.1 to 1.5; or, the ratio of the maximum length of the sub-pixel in the first direction to the maximum width in the second direction ranges from 2.3 to 2.85.

[0095] The sub-pixel includes a sub-pixel electrode, wherein the ratio of the maximum length of the sub-pixel electrode in the first direction to the maximum width in the second direction is in the range of 1.1 to 1.5; or, the ratio of the maximum length of the sub-pixel electrode in the first direction to the maximum width in the second direction is in the range of 2.3 to 2.85.

[0096] In one possible implementation, the ratio of the maximum length of the sub-pixel and / or the sub-pixel electrode in the first direction to the maximum width in the second direction is 4:3; or, the ratio of the maximum length of the sub-pixel and / or the sub-pixel electrode in the first direction to the maximum width in the second direction is 8:3.

[0097] This disclosure also provides a display panel, which includes the array substrate as described in this disclosure.

[0098] This disclosure also provides a display device, which includes the display panel as described in this disclosure.

[0099] This disclosure also provides a driving method applied to the array substrate provided in this disclosure, wherein the display cycle includes a plurality of sequentially arranged driving stages; the driving method includes:

[0100] During the 2k-1 driving phase, the 2k-1 gate line is turned on, and the sub-pixels connected to the 2k-1 gate line receive the data voltage provided by the corresponding data line.

[0101] During the 2k driving phase, the 2k gate line is turned on, and the sub-pixels connected to the 2k gate line receive the data voltage provided by the corresponding data line.

[0102] k is a positive integer;

[0103] In the 2k-1 driving phase, the data voltage provided by the data line is the data voltage corresponding to the sub-pixel of the 2k-1 row; in the 2k driving phase, the data voltage provided by the data line is the data voltage corresponding to the sub-pixel of the 2k row.

[0104] This disclosure also provides a driving method applied to the array substrate provided in this disclosure, the driving method comprising:

[0105] Provide scan signals to multiple gate lines such that the scan signal provided by the (2k-1)th gate line is the same as the scan signal provided by the 2kth gate line;

[0106] There is an overlapping time period between the effective voltage time period of the 2k scan signal and the effective voltage time period of the 2k+1 scan signal. During the overlapping time period, the 2k-1 gate line, the 2k gate line, the 2k+1 gate line, and the 2k+2 gate line are turned on, and the sub-pixels located in the 2k-1 row, the 2k row, the 2k+1 row, and the 2k+2 row receive the data voltage provided by the corresponding data lines.

[0107] k is a positive integer.

[0108] This disclosure also provides a driving method applied to the array substrate provided in this disclosure, the driving method comprising:

[0109] Scan signals are provided to multiple grid lines to control the sequential opening of the multiple grid lines during the display cycle;

[0110] Within the display cycle, there are overlapping and non-overlapping time periods among the effective time periods of the scan signals provided by at least two adjacent gate lines of the multiple gate lines that are opened sequentially;

[0111] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0112] This disclosure also provides a display method, wherein one of the driving methods provided in this disclosure is used for driving;

[0113] Alternatively, at the first frame rate, a driving method as described in the embodiments of this disclosure is used for driving, and at the second frame rate, another driving method as described in the embodiments of this disclosure is used for driving, wherein the second frame rate is greater than the first frame rate. Attached Figure Description

[0114] Figure 1 is one of the pixel architecture diagrams of the array substrate provided in the embodiments of this disclosure;

[0115] Figure 2A is one of the schematic diagrams of the array substrate structure provided in the embodiments of this disclosure;

[0116] Figure 2B is a schematic diagram of a single film layer in the layer containing the gate lines in Figure 2A;

[0117] Figure 2C is a schematic diagram of a single film layer containing the data line in Figure 2A;

[0118] Figure 2D is a schematic diagram of a single film layer in the layer containing the sub-pixel electrode in Figure 2A;

[0119] Figure 2E is a schematic diagram of the fabrication of the array substrate film layer provided in the embodiment of this disclosure;

[0120] Figure 3 is a second schematic diagram of the pixel architecture of the array substrate provided in the embodiments of this disclosure;

[0121] Figure 4A is a second schematic diagram of the array substrate structure provided in the embodiment of this disclosure;

[0122] Figure 4B is a schematic diagram of a single film layer in the layer containing the gate lines in Figure 4A;

[0123] Figure 4C is a schematic diagram of a single film layer containing the data line in Figure 4A;

[0124] Figure 4D is a schematic diagram of a single film layer in the sub-pixel electrode layer in Figure 4A;

[0125] Figure 5 is a third schematic diagram of the pixel architecture of the array substrate provided in the embodiments of this disclosure;

[0126] Figure 6 is a fourth schematic diagram of the pixel architecture of the array substrate provided in the embodiments of this disclosure;

[0127] Figure 7 is a fifth schematic diagram of the pixel architecture of the array substrate provided in the embodiments of this disclosure;

[0128] Figure 8 is a sixth schematic diagram of the pixel architecture of the array substrate provided in the embodiments of this disclosure;

[0129] Figure 9 is a seventh schematic diagram of the pixel architecture of the array substrate provided in the embodiments of this disclosure;

[0130] Figure 10 is one of the timing diagrams provided in the embodiments of this disclosure;

[0131] Figure 11 is a second timing diagram provided in an embodiment of this disclosure;

[0132] Figure 12 is the third timing diagram provided in the embodiments of this disclosure. Detailed Implementation

[0133] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0134] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0135] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0136] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0137] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0138] In the relevant array substrate, the number of data lines required overlaps, the amount of source IC used is large, and the display panel cost is high; moreover, the data line bends once in each sub-pixel row, resulting in a large number of data line bends, a large data line load, and a low charging rate.

[0139] In view of this, the present disclosure provides an array substrate, as shown in Figures 1 and 2A-2D, having a plurality of pixels 4, each pixel 4 including a plurality of sub-pixels 40; wherein, the array substrate includes:

[0140] Substrate 1;

[0141] Multiple gate lines GT are located on one side of substrate 1; the multiple gate lines GT extend along a first direction X and are arranged along a second direction Y;

[0142] Multiple sub-pixel rows 400 are located on one side of the substrate 1. The multiple sub-pixel rows 400 extend along a first direction X and are arranged along a second direction Y. The sub-pixel rows 400 include: multiple sub-pixels 40 arranged along the first direction X; a gate line GT is provided between two adjacent sub-pixel rows 400.

[0143] In this configuration, multiple sub-pixels 40 of the same pixel 4 are distributed in different sub-pixel rows 400, and at least a portion of two adjacent pixels 4 in the second direction Y are symmetrically or nearly symmetrically distributed about the gate line GT between the two pixels 4. Optionally, all two adjacent pixels 4 in the second direction Y may be symmetrically or nearly symmetrically distributed about the gate line GT between the two pixels 4. It should be noted that symmetry here may refer to the fact that at least one of the sub-pixel arrangement or sub-pixel shape of the two pixels is symmetrical. For example, when the arrangement is symmetrical, such as referring to Figure 1, with GT(4N+2) as the axis of symmetry, the arrangement of the first pixel 41 and the third pixel 43 of the two pixels is symmetrical about GT(4N+2), that is, the direction away from the axis of symmetry is the arrangement of BRG. Alternatively, the sub-pixels of the first pixel 41 and the third pixel 43 of the two pixels may be symmetrically or nearly symmetrically designed in addition to being arranged on opposite sides. Furthermore, the sub-pixel electrodes of the sub-pixels are also symmetrically or nearly symmetrically designed about the axis of symmetry.

[0144] In this embodiment, multiple sub-pixels 40 of the same pixel 4 are distributed in different sub-pixel rows 400. That is, each sub-pixel row 400 contains at least one gate line GT. One row of pixels contains two sub-pixel rows 400, so one row of pixels contains at least two gate lines GT. This dual gate or more gate line structure can reduce the number of data lines, reduce the amount of source IC used, and reduce the cost of the display panel. Moreover, at least a portion of at least two adjacent pixels 4 in the second direction Y are symmetrically or nearly symmetrically distributed with respect to the gate line GT between the two pixels 4. Compared with the pixel architecture of related technologies, the arrangement relationship of adjacent pixel rows is changed from translation to a symmetrical design with respect to the gate line. This seed pixel distribution method is beneficial to reduce the number of bends of the data line (for example, in this embodiment, the data line bends once every two sub-pixel rows, while in related technologies, the data line bends once in each sub-pixel row), thereby reducing the resistance and capacitive load of the data line and helping to improve the charging rate.

[0145] In one possible implementation, as shown in Figures 1 and 5, the data line DT includes: a plurality of first sub-data sections DT01 extending along and arranged along the second direction Y, and a second sub-data section DT02 extending along the first direction X and connecting adjacent first sub-data sections DT01; the extension lines of the first sub-data sections DT01 connecting the two sides of the second sub-data section DT02 do not coincide; optionally, the orthographic projection of a portion of the first sub-data section DT01 on the substrate 1 overlaps with the orthographic projection of two sub-pixel rows 400 on the substrate 1. That is, the first sub-data line section DT01 vertically spans two sub-pixel rows 400, bending once every two sub-pixel rows 400. Compared to bending once per sub-pixel row, the embodiments of this disclosure can reduce the resistance and capacitance load of the data line, reduce the load on the gate line, and help improve the charging rate. Referring to Figure 1, optionally, the extension line of the first sub-data line portion DT01 corresponding to the first sub-pixel row in the second direction Y can pass through the second sub-pixel row region, for example, through the central region of the sub-pixels included in the second row. The sub-pixels of the second row and the third row can be aligned. Optionally, the sub-pixel electrodes included in the second sub-pixel row and the sub-pixel electrodes included in the third row are aligned in the second direction, for example, edge aligned.

[0146] In one possible implementation, as shown in Figures 1 and 2A-2D, at least two adjacent pixels 4 in the first direction X are arranged in a complementary manner. For example, the first pixel P1 and the second pixel P2 are two adjacent pixels in the first direction X, the three sub-pixels in the first sub-pixel P1 are arranged in an inverted triangle (for example, the line connecting the central regions of the three sub-pixels forms an inverted triangle), and the three sub-pixels in the second pixel 42 are arranged in an equilateral triangle (for example, the line connecting the central regions of the three sub-pixels forms an equilateral triangle), and the two triangles are complementary.

[0147] Optionally, each pixel 4 may include multiple sub-pixels 40. Two adjacent pixels 4 in the second direction Y are symmetrically or nearly symmetrically distributed about the gate line GT between the two pixels 4. This can be that each sub-pixel 40 of two adjacent pixels 4 in the second direction Y is symmetrically or nearly symmetrically distributed about the gate line GT. Two adjacent pixels 4 in the first direction X are complementary. This can be that each sub-pixel 40 of two adjacent pixels 4 in the first direction X is complementary.

[0148] For example, as shown in Figures 1 and 2A-2D, the array substrate includes: a plurality of pixel units S; the plurality of pixel units S are repeatedly arranged in a first direction X and in a second direction Y to form a plurality of pixels on the array substrate; the pixel unit S includes a plurality of pixels 4, namely: a first pixel 41, a second pixel 42, a third pixel 43, and a fourth pixel 44.

[0149] The first pixel 41 and the third pixel 43 are distributed along the second direction Y and are symmetrical or nearly symmetrical about the gate line GT between them; the second pixel 42 and the fourth pixel 44 are distributed along the second direction Y and are symmetrical or nearly symmetrical about the gate line GT between them; the first pixel 41 and the second pixel 42 are distributed along the first direction X and are complementary; the third pixel 43 and the fourth pixel 44 are distributed along the first direction X and are complementary.

[0150] Pixel 4 includes: a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B; the colors of the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are all different; the colors of the first sub-pixel R of different pixels 4 are the same, the colors of the second sub-pixel G of different pixels 4 are the same, and the colors of the third sub-pixel B of different pixels 4 are the same.

[0151] In the first pixel 41, the first sub-pixel R and the second sub-pixel G are located in the 4n+1th sub-pixel row, and the third sub-pixel B is located in the 4n+2th sub-pixel row;

[0152] In the second pixel 42, the third sub-pixel B is located in the 4n+1th sub-pixel row, and the first sub-pixel R and the second sub-pixel G are located in the 4n+2th sub-pixel row;

[0153] In the third pixel 43, the third sub-pixel B is located in the 4n+3rd sub-pixel row, and the first sub-pixel R and the second sub-pixel G are located in the 4n+4th sub-pixel row;

[0154] In the fourth pixel 44, the first sub-pixel R and the second sub-pixel G are located in the 4n+3rd sub-pixel row, and the third sub-pixel B is located in the 4n+4th sub-pixel row, where n represents a natural number.

[0155] For example, when n=0, in the first pixel 41, the first sub-pixel R and the second sub-pixel G are located in the first sub-pixel row, and the third sub-pixel B is located in the second sub-pixel row; in the second pixel 42, the third sub-pixel B is located in the first sub-pixel row, and the first sub-pixel R and the second sub-pixel G are located in the second sub-pixel row; in the third pixel 43, the third sub-pixel B is located in the 4n+3 sub-pixel row, and the first sub-pixel R and the second sub-pixel G are located in the fourth sub-pixel row; in the fourth pixel 44, the first sub-pixel R and the second sub-pixel G are located in the third sub-pixel row, and the third sub-pixel B is located in the fourth sub-pixel row.

[0156] For example, when n=1, in the first pixel 41, the first sub-pixel R and the second sub-pixel G are located in the 5th sub-pixel row, and the third sub-pixel B is located in the 6th sub-pixel row; in the second pixel 42, the third sub-pixel B is located in the 5th sub-pixel row, and the first sub-pixel R and the second sub-pixel G are located in the 6th sub-pixel row; in the third pixel 43, the third sub-pixel B is located in the 7th sub-pixel row, and the first sub-pixel R and the second sub-pixel G are located in the 8th sub-pixel row; in the fourth pixel 44, the first sub-pixel R and the second sub-pixel G are located in the 7th sub-pixel row, and the third sub-pixel B is located in the 8th sub-pixel row; the same applies when n is any other natural number.

[0157] As shown in Figure 1, the first sub-pixel R of the first pixel 41 and the first sub-pixel R of the third pixel 43 are symmetrical or nearly symmetrical about the gate line GT. The second sub-pixel G of the first pixel 41 and the second sub-pixel G of the third pixel 43 are symmetrical or nearly symmetrical about the gate line GT. The third sub-pixel B of the first pixel 41 and the third sub-pixel B of the third pixel 43 are symmetrical or nearly symmetrical about the gate line GT.

[0158] The first sub-pixel R of the second pixel 42 and the first sub-pixel R of the fourth pixel 44 are symmetrical or nearly symmetrical about the grid line GT. The second sub-pixel G of the second pixel 42 and the second sub-pixel G of the fourth pixel 44 are symmetrical or nearly symmetrical about the grid line GT. The third sub-pixel B of the second pixel 42 and the third sub-pixel B of the fourth pixel 44 are symmetrical or nearly symmetrical about the grid line GT.

[0159] Optionally, the first sub-pixel can be a red sub-pixel, the second sub-pixel can be a green sub-pixel, and the third sub-pixel can be a blue sub-pixel; alternatively, the first sub-pixel can also be a sub-pixel of other colors, for example, it can be a green or blue sub-pixel; the second sub-pixel can also be a sub-pixel of other colors, for example, it can be a red or blue sub-pixel; the third sub-pixel can also be a sub-pixel of other colors, for example, it can be a red or green sub-pixel.

[0160] Optionally, referring to Figure 1, if the leftmost data line DT(4M+1) is the first data line closest to the non-display area, virtual pixels can be set in the sub-pixel areas corresponding to some rows. For example, referring to Figure 1, two virtual sub-pixels can be set to the left of the third sub-pixel B(40) of the first pixel 41, which is closest to the non-display area in the second and third sub-pixel rows. The virtual sub-pixels can be de-connected to the data lines to improve etching uniformity. The edge of the virtual sub-pixel can be flush with the edge of the first sub-pixel in the first sub-pixel row. Optionally, multiple virtual sub-pixels can be set on both sides of the display area along the direction of the gate line. The width of the virtual sub-pixel electrode in the direction of the gate line extension can be equal to half the width of the display sub-pixel electrode.

[0161] In a possible implementation, referring to FIG. 3, each sub-pixel 40 has equal length in the first direction X; the pixel 4 satisfies at least one of the following relational expressions:

[0162] 0 < d0 ≤ 0.7d1;

[0163] 0 < d0' ≤ 0.7d1';

[0164] 0 < d0” ≤ 0.7d1;

[0165] wherein, d0 represents the spacing between the center of the first sub-pixel R and the center of the third sub-pixel B in the first direction X, d1 represents the maximum length of the sub-pixel 40 in the first direction, d0' represents the length of the second sub data line portion DT02 in the first direction X, and d1' represents the spacing between two adjacent first sub data line portions DT01 in the first direction X; d0” represents the spacing in the first direction between respective outer edges of the first sub-pixel R and the third sub-pixel B that are close to the same data line DT, for example, the spacing between the left edge of the first sub-pixel R and the left edge of the third sub-pixel B in the first direction. Alternatively, d1' may also be the distance in the first direction X of the region defined by adjacent two gate lines and adjacent two data lines.

[0166] It should be noted that, with respect to the length of a sub-pixel in the first direction, or the width thereof in the second direction, and the center spacing between two adjacent sub-pixels, the sub-pixel herein may refer to the sub-pixel electrode comprised in the sub-pixel, or may refer to the region where the sub-pixel is located, that is, the region defined by the intersection of gate lines and data lines; when measuring the distance, the center of the sub-pixel electrode (i.e., the intersection of diagonal lines) may be measured; in addition, the data line spacing between the data line corresponding to the first sub-pixel R and the third sub-pixel B may satisfy: 0 < d0' ≤ 0.7d1 or 0 < d0' ≤ 0.7d1'; the spacing between the edge of the first sub-pixel R electrode close to the data line side and the edge of the third sub-pixel B close to the data line side may satisfy: 0 < d0” ≤ 0.7d1 or 0 < d0” ≤ 0.7d1'. The above three parameter limitations may be satisfied simultaneously, or at least one of them may be satisfied.

[0167] Alternatively, the pixel satisfies at least one of the following relational expressions:

[0168] d0 = 0.5d1;

[0169] d0' = 0.5d1';

[0170] d0” = 0.50d1. That is, for each sub-pixel 40 of the same pixel, the sub-pixel located in the next sub-pixel row is staggered relative to the sub-pixel located in the previous sub-pixel row, so that each sub-pixel of the pixel 4 is arranged in a triangle.

[0171] In one possible implementation, referring to FIG3, the maximum length d1' of sub-pixel 40 in the first direction X is greater than the maximum width d2' of sub-pixel 40 in the second direction Y. Wherein, d2' represents the spacing between adjacent gate lines GT in the second direction Y; optionally, the ratio of the maximum length d1' of sub-pixel 40 in the first direction X to the maximum width d2' in the second direction Y is in the range of 1.1 to 1.5, for example, it can be 1.2, 1.3, 1.4, etc.; or, the ratio of the maximum length d1' of sub-pixel 40 in the first direction X to the maximum width d2' in the second direction Y is in the range of 2.3 to 2.85. For example, referring to Figure 5, d1' represents the spacing between two adjacent first sub-data line portions DT01 in the first direction X, and d2' can represent the spacing between two adjacent gate line groups in the second direction Y (specifically, the two gate lines between two adjacent sub-pixel rows can be considered as a gate line group), that is, the sub-pixel is the area defined by the intersection of the gate line group and the data line, and the sub-pixel 40 satisfies the range of 2.3 to 2.85, that is, the sub-pixel area (the area defined by the gate line group and the data line satisfies this range). Optionally, the ratio of the maximum length d1' of sub-pixel 40 in the first direction X to the maximum width d2' in the second direction Y is 4:3; or the ratio of the maximum length d1' of sub-pixel 40 in the first direction X to the maximum width d2' in the second direction Y is 8:3. For example, referring to Figure 5, d1' represents the spacing between two adjacent first sub-data line portions DT01 in the first direction X, and d2' represents the spacing between two adjacent gate line groups in the second direction Y. Sub-pixel 40 satisfies the 8:3 range, that is, the sub-pixel region (the region defined by the gate line group and the data line satisfies this range). Continuing to refer to Figure 5, the range or ratio of the sub-pixel electrode can be referred to Figure 3 and its corresponding description, which will not be repeated here. In addition, Figures 6-9 can also be referred to the relevant descriptions in Figure 5 and Figure 3, which will not be repeated here. With this design, compared with the existing single-gate sub-pixel electrode where the ratio of the length in the gate line extension direction to the length in the data line extension direction is 1:3, the number of data signal lines can be reduced, and the manufacturing cost can be reduced.

[0172] Similarly, the length of a subpixel in the first direction, or the width in the second direction, and the center-to-center distance between two adjacent subpixels, can be understood as the area where the subpixel is located, that is, the area defined by the intersection of the gate line and the data line.

[0173] In one possible implementation, referring to Figure 3, the sub-pixel may include a sub-pixel electrode; the maximum length d1 of the sub-pixel electrode P in the first direction X is greater than the maximum width d2 of the sub-pixel electrode P in the second direction Y. Optionally, the ratio of the maximum length d1 of the sub-pixel electrode P in the first direction X to the maximum width d2 in the second direction Y ranges from 1.1 to 1.5, for example, it can be 1.2, 1.3, 1.4, etc. Alternatively, the ratio of the maximum length of the sub-pixel electrode P in the first direction to the maximum width in the second direction ranges from 2.3 to 2.85. This design, compared to the existing single-gate sub-pixel electrode with a 1:3 ratio of length in the gate line extension direction to length in the data line extension direction, can reduce the number of data signal lines and lower manufacturing costs.

[0174] Optionally, in this embodiment of the disclosure, the ratio range of both the sub-pixel electrode and the sub-pixel (the area defined by the gate line and the data line) may be 1.1-1.5, or one of them may be 1.1-1.5, which is not limited here.

[0175] Optionally, a sub-pixel may include a sub-pixel electrode; the maximum length of the sub-pixel in the first direction X and the maximum width in the second direction may be the maximum length of the sub-pixel electrode in the first direction and the maximum width in the second direction. It should be noted that, in this embodiment, the length of the sub-pixel electrode may be: when the sub-pixel electrode is a plate-shaped electrode, the maximum length of the sub-pixel electrode refers to the outline length of the plate-shaped electrode; when the sub-pixel electrode includes a slit and still includes a closed outer contour, the maximum length of the sub-pixel electrode refers to the maximum length of the closed contour of the sub-pixel electrode; when the sub-pixel electrode includes multiple branch electrodes and there is no closed contour around the sub-pixel electrode, the maximum length of the sub-pixel electrode refers to the maximum length of the connecting line of the branch electrodes near the outer end of the sub-pixel electrode, and the width of the sub-pixel electrode is similarly determined, and will not be elaborated further here.

[0176] In one possible implementation, as shown in Figures 1, 2A-2D, the array substrate includes: multiple data lines DT; a gate line GT between adjacent sub-pixel rows 400; and a sub-pixel 40 spaced between adjacent data lines DT.

[0177] In the embodiments of the present disclosure, three sub-pixels of one pixel are arranged in two sub-pixel rows, in a regular triangle or inverted triangle form; the sub-pixels of two horizontally adjacent pixels in one pixel row are in a complementary form of regular triangle and inverted triangle, forming a parallelogram; adjacent pixel rows (i.e., every two sub-pixel rows) are symmetrically distributed along a gate line, for example, if the sub-pixel distribution of the first pixel row is red (R) green (G) / blue (B) + blue (B) / red (R) green (G), then the sub-pixel arrangement of the second pixel row is blue (B) / red (R) green (G) + red (R) green (G) / blue (B), which can also be understood as pixels being repeatedly translated along the diagonal; the horizontal (i.e., first direction) width of the sub-pixel is twice the horizontal width of the sub-pixel in the related pixel architecture, and the vertical (i.e., second direction) height of the sub-pixel is 1 / 2 of the vertical height of the sub-pixel in the related pixel architecture, that is, the aspect ratio of the sub-pixel is 4:3; in the embodiments of the present disclosure, each sub-pixel row comprises one gate line, and one pixel row comprises two rows of sub-pixels, so one row of pixels comprises two gate lines, which is a dual gate structure; the related pixel architecture has one row of pixels comprising one row of sub-pixels, and two adjacent gate lines are comprised between sub-pixel rows; in the related pixel architecture, one data line is comprised every two columns of sub-pixels, and two columns of pixels comprise six columns of sub-pixels, so two columns of pixels comprise three data lines; in the embodiments of the present disclosure, one data line is comprised between adjacent sub-pixel columns, and two columns of pixels occupy the width of three columns of sub-pixels, so two columns of pixels also comprise three data lines; in the embodiments of the present disclosure, the sub-pixel distribution in two adjacent columns of pixels is that the first row comprises red (R) + blue (B) of pixel 1 and green (G) of pixel 2, the second row comprises green (G) of pixel 1 and red (R) + blue (B) of pixel 2, and the sub-pixels of the second row are translated by a distance of 1 / 2 of the sub-pixel width relative to the sub-pixels of the first row, and the three sub-pixels red (R), green (G) and blue (B) of one pixel form a "pin" shape (Chinese character 品) or inverted "pin" shape structure; in the related pixel architecture, the sub-pixels of two adjacent columns of pixels are arranged in the same row as red (R) / green (G) / blue (B) of pixel 1 and red (R) / green (G) / blue (B) of pixel 2.

[0178] In the related array substrate, the sub-pixels of two adjacent columns of pixels are arranged into 1 row and 6 columns, and each sub-pixel has the same size. In the embodiments of the present disclosure, the sub-pixel height can be changed to 1 / 2 of the original height, and the width can be changed to twice the original width, and the arrangement of 6 sub-pixels of two adjacent columns of pixels can be changed into 2 rows and 3 columns, which can ensure that the area occupied by pixels remains unchanged and the resolution is the same, that is, the dual gate architecture can be implemented and the data line load can be reduced without reducing the current resolution. Moreover, multiple sub-pixels 40 of the same pixel 4 are distributed in different sub-pixel rows 400, and the sub-pixel points of two adjacent pixels are divided in the form of 2+1 / 1+2, which can achieve the best color mixing effect of sub-pixels when the width and height of a pixel are the same, and meanwhile, the edge jaggedness is the least obvious when displaying graphics.

[0179] With the development of markets such as e-sports and sports events, the demand for high refresh rate panels is rapidly increasing. However, customers simultaneously want to improve refresh rates without increasing costs. Double Line Gating (DLG) and Hardware Super Resolution (HSR) technologies can double the refresh rate at roughly the same cost. However, in the existing dual-gate pixel architecture design, two or more sub-pixels of different colors are connected to a single data line. Directly using DLG / HSR technology can lead to the problem that while the intended display might show one color sub-pixel, multiple colors are actually displayed, resulting in abnormal color display. In this embodiment, as shown in Figures 1, 2A-2D, and 3, the sub-pixels 40 connected to the same data line 2 have the same color. In this embodiment of the disclosure, the sub-pixels 40 connected to the same data line 2 have the same color. In the frequency multiplication mode (DLG or HSR), the adjacent sub-pixels on the same data line have the same color, which improves the image quality and avoids the situation where the colors of adjacent sub-pixels on the same data line are different in the DLG / HSR mode, which would cause the color to be displayed as a mixture of the two adjacent sub-pixels instead of the expected single color, resulting in abnormal image display.

[0180] In one possible implementation, referring to FIG1, in the first pixel 41, the first sub-pixel R is connected to the 4N+1 gate line GT and the 4M+2 data line DT, the second sub-pixel G is connected to the 4N+1 gate line GT and the 4M+3 data line DT, and the third sub-pixel B is connected to the 4N+2 gate line GT and the 4M+1 data line DT. It should be noted that, in this case, "sub-pixel connected to gate line" means that the gate of the transistor included in the sub-pixel is electrically connected to the gate line; "sub-pixel connected to data line" means that the source or drain of the transistor included in the sub-pixel is electrically connected to the data line.

[0181] In the second pixel 42, the first sub-pixel R is connected to the 4N+2 gate line GT and the 4M+2 data line DT, the second sub-pixel G is connected to the 4N+2 gate line GT and the 4M+3 data line DT, and the third sub-pixel B is connected to the 4N+1 gate line GT and the 4M+4 data line DT.

[0182] In the third pixel 43, the first sub-pixel R is connected to the 4N+4th gate line GT and the 4M+2nd data line DT, the second sub-pixel G is connected to the 4N+4th gate line GT and the 4M+3rd data line DT, and the third sub-pixel B is connected to the 4N+3rd gate line GT and the 4M+1st data line DT.

[0183] In the fourth pixel 44, the first sub-pixel R is connected to the 4N+3rd gate line GT and the 4M+2nd data line DT, the second sub-pixel G is connected to the 4N+3rd gate line GT and the 4M+3rd data line DT, and the third sub-pixel B is connected to the 4N+4th gate line GT and the 4M+4th data line DT, where N and M represent natural numbers.

[0184] For example, when N=0 and M=0, in the first pixel 41, the first sub-pixel R is connected to the first gate line GT and the second data line DT, the second sub-pixel G is connected to the first gate line GT and the third data line DT, and the third sub-pixel B is connected to the second gate line GT and the first data line DT; in the second pixel 42, the first sub-pixel R is connected to the second gate line GT and the second data line DT, the second sub-pixel G is connected to the second gate line GT and the third data line DT, and the third sub-pixel B is connected to the first gate line GT and the fourth data line DT. In the third pixel 43, the first sub-pixel R is connected to the fourth gate line GT and the second data line DT, the second sub-pixel G is connected to the fourth gate line GT and the third data line DT, and the third sub-pixel B is connected to the third gate line GT and the first data line DT; in the fourth pixel 44, the first sub-pixel R is connected to the third gate line GT and the second data line DT, the second sub-pixel G is connected to the third gate line GT and the third data line DT, and the third sub-pixel B is connected to the fourth gate line GT and the fourth data line DT.

[0185] For example, when N=1 and M=1, in the first pixel 41, the first sub-pixel R is connected to the 5th gate line GT and the 6th data line DT, the second sub-pixel G is connected to the 5th gate line GT and the 7th data line DT, and the third sub-pixel B is connected to the 6th gate line GT and the 5th data line DT; in the second pixel 42, the first sub-pixel R is connected to the 6th gate line GT and the 6th data line DT, the second sub-pixel G is connected to the 6th gate line GT and the 7th data line DT, and the third sub-pixel B is connected to the 5th gate line GT and the 8th data line DT; the third pixel 4... In pixel 3, the first sub-pixel R is connected to the 8th gate line GT and the 6th data line DT; the second sub-pixel G is connected to the 8th gate line GT and the 7th data line DT; and the third sub-pixel B is connected to the 7th gate line GT and the 5th data line DT. In pixel 44, the first sub-pixel R is connected to the 7th gate line GT and the 6th data line DT; the second sub-pixel G is connected to the 7th gate line GT and the 7th data line DT; and the third sub-pixel B is connected to the 8th gate line GT and the 8th data line DT. When N and M are other natural numbers, the process is similar and will not be repeated here.

[0186] It should be noted that in the embodiments of this disclosure, the sub-pixels are connected to the gate lines and data lines through transistors T.

[0187] In one possible implementation, referring to Figures 5-9, the array substrate includes: multiple data lines DT; two gate lines GT between adjacent sub-pixel rows 400; optionally, a gate line GT can be disposed above the first sub-pixel row in the scanning direction for the display panel; two sub-pixels 40 are spaced apart between adjacent data lines DT. In this embodiment of the present disclosure, the presence of two gate lines GT between adjacent sub-pixel rows 400 and the spaced interval of two sub-pixels 40 between adjacent data lines DT can realize a four-gate pixel architecture, which can further reduce the number of data lines, reduce the amount of source IC used, and further reduce the cost of the display panel.

[0188] In one possible implementation, referring to Figure 5, the array includes multiple pixel groups SZ; the pixel group SZ includes two pixel units S distributed along a first direction, namely a first pixel unit S1 and a second pixel unit S2; wherein, in the first pixel unit S1:

[0189] The first sub-pixel R of the first pixel 41 is connected to the 8N+2 gate line GT and the 4M+2 data line DT; the second sub-pixel G of the first pixel 41 is connected to the 8N+1 gate line GT and the 4M+1 data line DT; and the third sub-pixel B of the first pixel 41 is connected to the 8N+3 gate line GT and the 4M+1 data line DT.

[0190] The first sub-pixel R of the second pixel 42 is connected to the 8N+4th gate line GT and the 4M+2nd data line DT; the second sub-pixel G of the second pixel 42 is connected to the 8N+4th gate line GT and the 4M+3rd data line DT; and the third sub-pixel B of the second pixel 42 is connected to the 8N+1th gate line GT and the 4M+2nd data line DT.

[0191] The first sub-pixel R of the third pixel 43 is connected to the 8N+7th gate line GT and the 4M+1st data line DT; the second sub-pixel G of the third pixel 43 is connected to the 8N+8th gate line GT and the 4M+2nd data line DT; and the third sub-pixel B of the third pixel 43 is connected to the 8N+6th gate line GT and the 4M+2nd data line DT.

[0192] The first sub-pixel R of the fourth pixel 44 is connected to the 8N+5th gate line GT and the 4M+1st data line DT. The second sub-pixel G of the fourth pixel 44 is connected to the 8N+5th gate line GT and the 4M+2nd data line DT. The third sub-pixel B of the fourth pixel 44 is connected to the 8N+8th gate line GT and the 4M+3rd data line DT. Here, N and M represent natural numbers.

[0193] In the second pixel unit S2:

[0194] The first sub-pixel R of the first pixel 41 is connected to the 8N+2 gate line GT and the 4M+3 data line DT. The second sub-pixel G of the first pixel 41 is connected to the 8N+2 gate line GT and the 4M+4 data line DT. The third sub-pixel B of the first pixel 41 is connected to the 8N+3 gate line GT and the 4M+2 data line DT.

[0195] The first sub-pixel R of the second pixel 42 is connected to the 8N+3 gate line GT and the 4M+3 data line DT. The second sub-pixel B of the second pixel 42 is connected to the 8N+4 gate line GT and the 4M+4 data line DT. The third sub-pixel B of the second pixel 42 is connected to the 8N+1 gate line GT and the 4M+3 data line DT.

[0196] The first sub-pixel R of the third pixel 43 is connected to the 8N+7th gate line GT and the 4M+2nd data line DT. The second sub-pixel G of the third pixel 43 is connected to the 8N+7th gate line GT and the 4M+3rd data line DT. The third sub-pixel B of the third pixel 43 is connected to the 8N+6th gate line GT and the 4M+3rd data line DT.

[0197] The first sub-pixel R of the fourth pixel 44 is connected to the 8N+6th gate line GT and the 4M+4th data line DT. The second sub-pixel G of the fourth pixel 44 is connected to the 8N+5th gate line GT and the 4M+3th data line DT. The third sub-pixel B of the fourth pixel 44 is connected to the 8N+8th gate line GT and the 4M+4th data line DT.

[0198] Referring to Figure 5, for example, when N=0 and M=0;

[0199] In the first pixel unit S1:

[0200] The first sub-pixel R of the first pixel 41 is connected to the second gate line GT and the second data line DT; the second sub-pixel G of the first pixel 41 is connected to the first gate line GT and the first data line DT; the third sub-pixel B of the first pixel 41 is connected to the third gate line GT and the first data line DT; the first sub-pixel R of the second pixel 42 is connected to the fourth gate line GT and the second data line DT; the second sub-pixel G of the second pixel 42 is connected to the fourth gate line GT and the third data line DT; the third sub-pixel B of the second pixel 42 is connected to the first gate line GT and the second data line DT; the third pixel 4... The first sub-pixel R of pixel 3 is connected to the 7th gate line GT and the 1st data line DT; the second sub-pixel G of pixel 43 is connected to the 8th gate line GT and the 2nd data line DT; the third sub-pixel B of pixel 43 is connected to the 6th gate line GT and the 2nd data line DT; the first sub-pixel R of pixel 44 is connected to the 5th gate line GT and the 1st data line DT; the second sub-pixel G of pixel 44 is connected to the 5th gate line GT and the 2nd data line DT; the third sub-pixel B of pixel 44 is connected to the 8th gate line GT and the 3rd data line DT, where N and M represent natural numbers;

[0201] In the second pixel unit S2:

[0202] The first sub-pixel R of the first pixel 41 is connected to the second gate line GT and the third data line DT; the second sub-pixel G of the first pixel 41 is connected to the second gate line GT and the fourth data line DT; and the third sub-pixel B of the first pixel 41 is connected to the third gate line GT and the second data line DT. Similarly, the first sub-pixel R of the second pixel 42 is connected to the third gate line GT and the third data line DT; the second sub-pixel B of the second pixel 42 is connected to the fourth gate line GT and the fourth data line DT; and the third sub-pixel B of the second pixel 42 is connected to the first gate line GT and the third data line DT. The first sub-pixel R of the third pixel 43 is connected to the 7th gate line GT and the 2nd data line DT; the second sub-pixel G of the third pixel 43 is connected to the 7th gate line GT and the 3rd data line DT; and the third sub-pixel B of the third pixel 43 is connected to the 6th gate line GT and the 3rd data line DT. The first sub-pixel R of the fourth pixel 44 is connected to the 6th gate line GT and the 4th data line DT; the second sub-pixel G of the fourth pixel 44 is connected to the 5th gate line GT and the 3rd data line DT; and the third sub-pixel B of the fourth pixel 44 is connected to the 8th gate line GT and the 4th data line DT.

[0203] In one possible implementation, as shown in Figures 5-9, in the same pixel group SZ, the sub-pixel distribution of the first pixel unit S1 and the second pixel unit S2 can be the same, but the connection methods with the gate lines and data lines can be different.

[0204] In one possible implementation, referring to Figure 6, the array includes multiple pixel groups SZ; the pixel group SZ includes two pixel units S distributed along a first direction X, namely a first pixel unit S1 and a second pixel unit S2; wherein, in the first pixel unit S1:

[0205] The first sub-pixel R of the first pixel 41 is connected to the 8N+1 gate line GT and the 4M+1 data line DT; the second sub-pixel G of the first pixel 41 is connected to the 8N+2 gate line GT and the 4M+1 data line DT; and the third sub-pixel B of the first pixel 41 is connected to the 8N+3 gate line GT and the 4M+2 data line DT.

[0206] The first sub-pixel R of the second pixel 42 is connected to the 8N+4th gate line GT and the 4M+2nd data line DT; the second sub-pixel G of the second pixel 42 is connected to the 8N+4th gate line GT and the 4M+3rd data line DT; and the third sub-pixel B of the second pixel 42 is connected to the 8N+2th gate line GT and the 4M+2nd data line DT.

[0207] The first sub-pixel R of the third pixel 43 is connected to the 8N+7th gate line GT and the 4M+2nd data line DT. The second sub-pixel G of the third pixel 43 is connected to the 8N+8th gate line GT and the 4M+2nd data line DT. The third sub-pixel B of the third pixel 43 is connected to the 8N+5th gate line GT and the 4M+1st data line DT.

[0208] The first sub-pixel R of the fourth pixel 44 is connected to the 8N+6th gate line GT and the 4M+1st data line DT. The second sub-pixel G of the fourth pixel 44 is connected to the 8N+6th gate line GT and the 4M+2nd data line DT. The third sub-pixel B of the fourth pixel 44 is connected to the 8N+8th gate line GT and the 4M+3rd data line DT. Here, N and M represent natural numbers.

[0209] In the second pixel unit S2:

[0210] The first sub-pixel R of the first pixel 41 is connected to the 8N+1 gate line GT and the 4M+2 data line DT. The second sub-pixel G of the first pixel 41 is connected to the 8N+2 gate line GT and the 4M+3 data line DT. The third sub-pixel B of the first pixel 41 is connected to the 8N+3 gate line GT and the 4M+3 data line DT.

[0211] The first sub-pixel R of the second pixel 42 is connected to the 8N+4th gate line GT and the 4M+4th data line DT; the second sub-pixel G of the second pixel 42 is connected to the 8N+3th gate line GT and the 4M+4th data line DT; and the third sub-pixel B of the second pixel 42 is connected to the 8N+1th gate line GT and the 4M+3th data line DT.

[0212] The first sub-pixel R of the third pixel 43 is connected to the 8N+7th gate line GT and the 4M+3rd data line DT. The second sub-pixel G of the third pixel 43 is connected to the 8N+8th gate line GT and the 4M+4th data line DT. The third sub-pixel B of the third pixel 43 is connected to the 8N+5th gate line GT and the 4M+2th data line DT.

[0213] The first sub-pixel R of the fourth pixel 44 is connected to the 8N+6th gate line GT and the 4M+3rd data line DT. The second sub-pixel 44 is connected to the 8N+5th gate line GT and the 4M+3rd data line DT. The third sub-pixel B is connected to the 8N+7th gate line GT and the 4M+4th data line DT.

[0214] In one possible implementation, referring to Figure 7, the array includes multiple pixel groups SZ; the pixel group SZ includes two pixel units S distributed along a first direction X, namely a first pixel unit S1 and a second pixel unit S2; wherein, in the first pixel unit S1:

[0215] The first sub-pixel R of the first pixel 41 is connected to the 8N+1 gate line GT and the 4M+1 data line DT; the second sub-pixel G of the first pixel 41 is connected to the 8N+2 gate line GT and the 4M+1 data line DT; and the third sub-pixel B of the first pixel 41 is connected to the 8N+3 gate line GT and the 4M+2 data line DT.

[0216] The first sub-pixel R of the second pixel 42 is connected to the 8N+4th gate line GT and the 4M+2nd data line DT; the second sub-pixel G of the second pixel 42 is connected to the 8N+3th gate line GT and the 4M+3rd data line DT; and the third sub-pixel B of the second pixel 42 is connected to the 8N+1th gate line GT and the 4M+2nd data line DT.

[0217] The first sub-pixel R of the third pixel 43 is connected to the 8N+7th gate line GT and the 4M+2nd data line DT. The second sub-pixel G of the third pixel 43 is connected to the 8N+8th gate line GT and the 4M+2nd data line DT. The third sub-pixel B of the third pixel 43 is connected to the 8N+5th gate line GT and the 4M+1st data line DT.

[0218] The first sub-pixel R of the fourth pixel 44 is connected to the 8N+6th gate line GT and the 4M+1st data line DT; the second sub-pixel G of the fourth pixel 44 is connected to the 8N+5th gate line GT and the 4M+2nd data line DT; and the third sub-pixel B of the fourth pixel 44 is connected to the 8N+7th gate line GT and the 4M+3rd data line DT, where N and M represent natural numbers.

[0219] In the second pixel unit S2:

[0220] The first sub-pixel R of the first pixel 41 is connected to the 8N+2 gate line GT and the 4M+2 data line DT; the second sub-pixel G of the first pixel 1 is connected to the 8N+1 gate line GT and the 4M+3 data line DT; and the third sub-pixel B of the first pixel 41 is connected to the 8N+4 gate line GT and the 4M+3 data line DT.

[0221] The first sub-pixel R of the second pixel 42 is connected to the 8N+3 gate line GT and the 4M+4 data line DT. The second sub-pixel G of the second pixel 42 is connected to the 8N+4 gate line GT and the 4M+4 data line DT. The third sub-pixel B of the second pixel 42 is connected to the 8N+2 gate line GT and the 4M+3 data line DT.

[0222] The first sub-pixel R of the third pixel 43 is connected to the 8N+8th gate line GT and the 4M+3rd data line DT. The second sub-pixel G of the third pixel 43 is connected to the 8N+7th gate line GT and the 4M+4th data line DT. The third sub-pixel B of the third pixel 43 is connected to the 8N+6th gate line GT and the 4M+2th data line DT.

[0223] The first sub-pixel R of the fourth pixel 44 is connected to the 8N+5th gate line GT and the 4M+3rd data line DT. The second sub-pixel G of the fourth pixel 44 is connected to the 8N+6th gate line GT and the 4M+3rd data line DT. The third sub-pixel B of the fourth pixel 44 is connected to the 8N+8th gate line GT and the 4M+4th data line DT.

[0224] In one possible implementation, referring to Figure 8, the array includes multiple pixel groups SZ; the pixel group SZ includes two pixel units S distributed along a first direction X, namely a first pixel unit S1 and a second pixel unit S2; wherein, in the first pixel unit S1:

[0225] The first sub-pixel R of the first pixel 41 is connected to the 8N+2 gate line GT and the 4M+2 data line DT; the second sub-pixel G of the first pixel 41 is connected to the 8N+1 gate line GT and the 4M+1 data line DT; and the third sub-pixel B of the first pixel 41 is connected to the 8N+3 gate line GT and the 4M+2 data line DT.

[0226] The first sub-pixel R of the second pixel 42 is connected to the 8N+3 gate line GT and the 4M+1 data line DT; the second sub-pixel G of the second pixel 42 is connected to the 8N+4 gate line GT and the 4M+3 data line DT; and the third sub-pixel B of the second pixel 42 is connected to the 8N+2 gate line GT and the 4M+3 data line DT.

[0227] The first sub-pixel R of the third pixel 43 is connected to the 8N+8th gate line GT and the 4M+2nd data line DT; the second sub-pixel G of the third pixel 43 is connected to the 8N+7th gate line GT and the 4M+1st data line DT; and the third sub-pixel B of the third pixel 43 is connected to the 8N+6th gate line GT and the 4M+2nd data line DT.

[0228] The first sub-pixel R of the fourth pixel 44 is connected to the 8N+5th gate line GT and the 4M+1st data line DT. The second sub-pixel G of the fourth pixel 44 is connected to the 8N+6th gate line GT and the 4M+3rd data line DT. The third sub-pixel B of the fourth pixel 44 is connected to the 8N+8th gate line GT and the 4M+3rd data line DT. Here, N and M represent natural numbers.

[0229] In the second pixel unit S2:

[0230] The first sub-pixel RR of the first pixel 41 is connected to the 8N+1 gate line GT and the 4M+2 data line DT. The second sub-pixel GR of the first pixel 41 is connected to the 8N+2 gate line GT and the 4M+4 data line DT. The third sub-pixel B of the first pixel 41 is connected to the 8N+3 gate line GT and the 4M+2 data line DT.

[0231] The first sub-pixel R of the second pixel 42 is connected to the 8N+4th gate line GT and the 4M+4th data line DT; the second sub-pixel G of the second pixel 42 is connected to the 8N+3th gate line GT and the 4M+3th data line DT; and the third sub-pixel B of the second pixel 42 is connected to the 8N+1th gate line GT and the 4M+3th data line DT.

[0232] The first sub-pixel R of the third pixel 43 is connected to the 8N+7th gate line GT and the 4M+2nd data line DT. The second sub-pixel G of the third pixel 43 is connected to the 8N+8th gate line GT and the 4M+4th data line DT. The third sub-pixel B of the third pixel 43 is connected to the 8N+5th gate line GT and the 4M+2nd data line DT.

[0233] The first sub-pixel R of the fourth pixel 44 is connected to the 8N+6th gate line GT and the 4M+4th data line DT. The second sub-pixel G of the fourth pixel 44 is connected to the 8N+5th gate line GT and the 4M+3rd data line DT. The third sub-pixel B of the fourth pixel 44 is connected to the 8N+7th gate line GT and the 4M+3rd data line DT.

[0234] In one possible implementation, referring to Figure 9, the array includes multiple pixel groups SZ; each pixel group includes two pixel units S distributed along a first direction, namely a first pixel unit S1 and a second pixel unit S2; wherein, in the first pixel unit S1:

[0235] The first sub-pixel R of the first pixel 41 is connected to the 8N+1 gate line GT and the 4M+1 data line DT; the second sub-pixel G of the first pixel 41 is connected to the 8N+2 gate line GT and the 4M+2 data line DT; and the third sub-pixel B of the first pixel 41 is connected to the 8N+4 gate line GT and the 4M+1 data line DT.

[0236] The first sub-pixel R of the second pixel 42 is connected to the 8N+3 gate line GT and the 4M+2 data line DT; the second sub-pixel G of the second pixel 42 is connected to the 8N+4 gate line GT and the 4M+2 data line DT; and the third sub-pixel B of the second pixel 42 is connected to the 8N+1 gate line GT and the 4M+2 data line DT.

[0237] The first sub-pixel R of the third pixel 43 is connected to the 8N+7th gate line GT and the 4M+1st data line DT; the second sub-pixel G of the third pixel 43 is connected to the 8N+8th gate line GT and the 4M+2nd data line DT; and the third sub-pixel B of the third pixel 43 is connected to the 8N+6th gate line GT and the 4M+1st data line DT.

[0238] The first sub-pixel R of the fourth pixel 44 is connected to the 8N+5th gate line GT and the 4M+2nd data line DT. The second sub-pixel G of the fourth pixel 44 is connected to the 8N+6th gate line GT and the 4M+2nd data line DT. The third sub-pixel B of the fourth pixel 44 is connected to the 8N+7th gate line GT and the 4M+2nd data line DT. Here, N and M represent natural numbers.

[0239] In the second pixel unit S2:

[0240] The first sub-pixel R of the first pixel 41 is connected to the 8N+2 gate line GT and the 4M+3 data line DT. The second sub-pixel G of the first pixel 41 is connected to the 8N+1 gate line GT and the 4M+3 data line DT. The third sub-pixel B of the first pixel 41 is connected to the 8N+3 gate line GT and the 4M+3 data line DT.

[0241] The first sub-pixel R of the second pixel 42 is connected to the 8N+4th gate line GT and the 4M+3rd data line DT. The second sub-pixel G of the second pixel 42 is connected to the 8N+3rd gate line GT and the 4M+4th data line DT. The third sub-pixel B of the second pixel 42 is connected to the 8N+2th gate line GT and the 4M+4th data line DT.

[0242] The first sub-pixel R of the third pixel 43 is connected to the 8N+8th gate line GT and the 4M+3rd data line DT. The second sub-pixel G of the third pixel 43 is connected to the 8N+7th gate line GT and the 4M+3rd data line DT. The third sub-pixel B of the third pixel 43 is connected to the 8N+5th gate line GT and the 4M+3rd data line DT.

[0243] The first sub-pixel R of the fourth pixel 44 is connected to the 8N+6th gate line GT and the 4M+3rd data line DT. The second sub-pixel G is connected to the 8N+5th gate line GT and the 4M+4th data line DT. The third sub-pixel B is connected to the 8N+8th gate line GT and the 4M+4th data line DT.

[0244] In one possible implementation, referring to Figures 2A-2D and 4A-4D, the array substrate may further include a plurality of sub-pixel electrodes P; the sub-pixel 40 includes the sub-pixel electrode P; referring to Figures 2D and 4D, the sub-pixel electrode P includes: a first slit group F1 and a second slit group F2 arranged along the second direction Y; both the first slit group F1 and the second slit group F2 include: a plurality of slits F; the plurality of slits F1 in the first slit group F1 extend in the same direction; the plurality of slits F in the second slit group F2 extend in the same direction; the extension direction of the slits F in the first slit group F1 is different from the extension direction of the slits F in the second slit group F2. In this embodiment of the present disclosure, the sub-pixel electrode P includes the first slit group F1 and the second slit group F2, which can realize dual-domain display.

[0245] In at least one embodiment of this disclosure, referring to FIG2D, the smaller of the angles formed by the slits F of the first slit group F1 and the slits F of the second slit group F2 is greater than 90°. For example, referring to FIG2D, the slits F of the first slit group F1 and the slits F of the second slit group F2 form a first angle β1 with the opening facing to the left and a second angle α1 with the opening facing to the right, wherein the angle of the first angle β1 is greater than the angle of the second angle α1, that is, the second angle α1 is the smaller of the angles formed by the slits F of the first slit group F1 and the slits F of the second slit group F2, wherein the second angle α1 is greater than 90°.

[0246] Optionally, as shown in Figures 2D and 4D, the outer edge of the sub-pixel electrode P in the first direction X can be straight, and the outer edge in the second direction Y can be broken. The shape of the bend can be consistent with the bend shape of the slit. Optionally, the shape of the broken line can be consistent with the shape of the data line.

[0247] In at least one embodiment of this disclosure, referring to FIG4D, the larger of the angles formed by the slits F of the first slit group F1 and the slits F of the second slit group F2 is less than 90°. For example, referring to FIG4D, the slits F of the first slit group F1 and the slits F of the second slit group F2 form a third angle β2 with the opening facing left and a fourth angle α2 with the opening facing right. The angle of the third angle β2 is greater than the angle of the fourth angle α2. That is, the fourth angle α2 is the smaller of the angles formed by the slits F of the first slit group F1 and the slits F of the second slit group F2, wherein the fourth angle α2 is less than 90°.

[0248] Optionally, as shown in Figure 4D, the outer edge of the sub-pixel electrode P in the first direction X can be a straight line, and the outer edge in the second direction Y can also be a straight line.

[0249] In at least one embodiment of this disclosure, referring to FIG2C, the first sub-trace portion DT1 extends along the second direction Y, and may be a structure that extends entirely along the second direction Y, with some parts possibly bent. In at least one embodiment of this disclosure, referring to FIG4C, the first sub-trace portion DT1 extends along the second direction Y, and may be a straight line extending along the second direction Y.

[0250] In at least one embodiment of this disclosure, the bent shape shown in FIG2C can be matched with the bent outer edge of the sub-pixel electrode P along the second direction Y.

[0251] In at least one embodiment of this disclosure, referring to Figures 2A-2D and 4A-4D, the array substrate further includes: a common electrode layer; the common electrode layer includes: a plurality of common electrodes C; the orthographic projection of the common electrode C onto the substrate 1 overlaps with the orthographic projection of the sub-pixel electrode P onto the substrate 1; the length of the common electrode C along the first direction X is greater than the length of the common electrode C along the second direction Y. In this embodiment of the disclosure, the length of the common electrode C along the first direction X is greater than the length of the common electrode C along the second direction Y to adapt to the shape of the pixel electrode P so that an electric field is formed between them.

[0252] Optionally, the orthographic projection of the common electrode C onto the substrate 1 roughly coincides with the orthographic projection of the sub-pixel electrode P onto the substrate; alternatively, the orthographic projection of the outer edge of the common electrode C onto the substrate 1 roughly coincides with the orthographic projection of the outer edge of the sub-pixel electrode P onto the substrate.

[0253] Optionally, the material of the common electrode C can be the same as the material of the sub-pixel electrode P.

[0254] In at least one embodiment of this disclosure, referring to Figures 2A-2D and 4A-4D, the common electrode layer includes: a plurality of common electrode rows extending along a first direction X and arranged along a second direction Y; the common electrode rows include: a plurality of common electrodes C arranged along the first direction X; the array substrate further includes: a first trace C0 on the same layer as the gate line GT and extending along the first direction X; a portion of the first trace C0 is in direct contact with the common electrode C, and each common electrode C in the same common electrode row is electrically connected through the first trace C0, so that the common electrodes C in the same row are connected as one unit.

[0255] In at least one embodiment of this disclosure, referring to Figures 2B and 4B, the common electrode layer includes an auxiliary scan line C00. The orthogonal projection of the auxiliary scan line C00 onto the substrate 1 can coincide with the orthogonal projection of the gate line GT onto the substrate 1, and their patterns can be identical. Optionally, the auxiliary scan line C00 and the gate line GT can be fabricated using a shared mask.

[0256] In at least one embodiment of this disclosure, as shown in FIG2C and FIG2E, transistor T may include: a gate (which may reuse a portion of the gate line GT), a first electrode TA, a second electrode TB, and an active pattern G; a gate insulating layer 91 may be provided between the gate and the active pattern G, and a passivation layer 92 may be provided between the second electrode TB and the sub-pixel electrode P, wherein the passivation layer 92 may have a via K, and the sub-pixel electrode P may be connected to the second electrode TB through the via K.

[0257] Optionally, as shown in Figure 2B, the common electrode C also has a first notch C1 at the position corresponding to the second electrode TB. Optionally, the orthographic projection of the second electrode TB on the substrate 1 overlaps with the orthographic projection of the first notch C1 on the substrate 1 to reduce the overlap capacitance between the two and reduce the impact on the display panel.

[0258] Optionally, as shown in Figure 2B, the gate line GT has a second notch C2 at the position corresponding to the second sub-data section DT02, and the gate line GT has a third notch C3 at the position corresponding to the first sub-data section DT01; the depth a2 of the third notch C3 in the second direction Y is greater than the depth a1 of the second notch C2 in the second direction Y.

[0259] In at least one embodiment of this disclosure, referring to FIG2E, when fabricating the array substrate, a common electrode layer (including a common electrode C and a first trace C0) can be sequentially formed on the surface of the substrate 1, followed by the formation of a gate insulating layer 91, then the formation of an active pattern G, a first electrode TA, and a second electrode TB, followed by the formation of a passivation layer 92 and etching to form a via K, followed by the formation of a pixel electrode layer (including a pixel electrode P).

[0260] Based on the same inventive concept, embodiments of this disclosure also provide a display panel, including an array substrate as provided in embodiments of this disclosure.

[0261] Based on the same inventive concept, embodiments of this disclosure also provide a display device, including a display panel as provided in embodiments of this disclosure.

[0262] Based on the same inventive concept, this disclosure also provides a driving method for an array substrate. Referring to Figure 10, a first-mode driving method can be used, and its display cycle includes multiple sequentially arranged driving stages. The driving method includes:

[0263] During the 2k-1 driving phase, the 2k-1 gate line is turned on, and the sub-pixels connected to the 2k-1 gate line receive the data voltage provided by the corresponding data line.

[0264] During the 2k driving phase, the 2k gate line is turned on, and the sub-pixels connected to the 2k gate line receive the data voltage provided by the corresponding data line.

[0265] k is a positive integer;

[0266] In the 2k-1 driving phase, the data voltage provided by the data line is the data voltage corresponding to the sub-pixel of the 2k-1 row; in the 2k driving phase, the data voltage provided by the data line is the data voltage corresponding to the sub-pixel of the 2k row.

[0267] The array substrate provided in this embodiment can be driven in a first mode. The driving timing in the first driving mode can be as shown in Figure 10. The gate lines are scanned line by line, and the data signal is loaded in the last 1H period of the gate line opening period. The width of the data signal is 1H (H is the charging time of one row of pixels).

[0268] As shown in Figure 10, the display cycle includes multiple driving stages set sequentially; the stage labeled S1 is the first driving stage, the stage labeled S2 is the second driving stage, the stage labeled S3 is the third driving stage, and the stage labeled SK is the Kth stage.

[0269] In the first driving stage S1, the first row gate line GT1 provides a high voltage signal (taking the transistor that is set in the display area and electrically connected to the pixel electrode as an example, when the transistor that is set in the display area and electrically connected to the pixel electrode is a P-type transistor, a low voltage signal is provided as the turn-on voltage of the transistor), the data line DT provides a first data voltage D1, and at least one sub-pixel located in the first row receives the first data voltage D1.

[0270] In the second driving phase S2, the second row gate line GT2 provides a high voltage signal, the data line DT provides a second data voltage D2, and at least one sub-pixel located in the second row receives the second data voltage D2.

[0271] In the third driving phase S3, the third row gate line GT3 provides a high voltage signal, the data line DT provides a third data voltage D3, and at least one sub-pixel located in the third row receives the third data voltage D3.

[0272] During the Kth driving phase SK, the Kth row gate line GTK provides a high voltage signal, the data line DT provides the Kth data voltage DK, and at least one sub-pixel located in the Kth row receives the Kth data voltage DK.

[0273] In at least one embodiment shown in Figure 10, the duration of each driving phase can be 1 hour (one-line charging time);

[0274] S1 is the last 1H time period of the high voltage period of the first scan signal provided by GT1, S2 is the non-overlapping time period of the high voltage period of the first scan signal provided by GT1 and the high voltage period of the second scan signal provided by GT2, S3 is the non-overlapping time period between the high voltage period of the second scan signal provided by GT2 and the high voltage period of the third scan signal provided by GT3, and SK is the non-overlapping time period between the high voltage period of the (K-1)th scan signal provided by the (K-1)th gate line and the high voltage period of the Kth scan signal provided by GTK.

[0275] Based on the same inventive concept, this disclosure also provides a driving method for an array substrate. Referring to Figure 11, a second driving mode, namely the DLG driving mode, can be adopted. The driving method includes:

[0276] Provide scan signals to multiple gate lines such that the scan signal provided by the (2k-1)th gate line is the same as the scan signal provided by the 2kth gate line;

[0277] There is an overlapping time period between the effective voltage time period of the 2k scan signal and the effective voltage time period of the 2k+1 scan signal. During the overlapping time period, the 2k-1 gate line, the 2k gate line, the 2k+1 gate line and the 2k+2 gate line are turned on, and the sub-pixels located in the 2k-1 row, the 2k row, the 2k+1 row and the 2k+2 row receive the data voltage provided by the corresponding data lines.

[0278] k is a positive integer.

[0279] In this embodiment of the disclosure, the array substrate can also adopt the DLG driving mode. The corresponding timing diagram can be seen in Figure 11. Adjacent row gate lines are opened simultaneously in pairs. During the last 2H period of the gate lines being opened, data signals are loaded onto the data lines. The data signal width is 2H, which can correspond to the data of the sub-pixels connected by the odd-numbered or even-numbered row gate lines, or it can be the data of the sub-pixels connected by the adjacent two row gate lines.

[0280] Referring to Figure 11, when the array substrate of at least one embodiment of the present disclosure includes K rows of sub-pixels and K rows of gate lines, and the sub-pixels located in the k-th row are electrically connected to the gate lines in the k-th row (K is an integer greater than 1, and k is a positive integer less than or equal to K);

[0281] The first scan signal provided by the first row of gate line GT1 is the same as the second scan signal provided by the second row of gate line GT2. The third scan signal provided by the third row of gate line GT3 is the same as the fourth scan signal provided by the fourth row of gate line GT4. The K-1 scan signal provided by the K-1 row of gate line GTK-1 is the same as the K-1 scan signal provided by the K-1 row of gate line GTK.

[0282] The display cycle includes multiple driving stages set sequentially; the stage labeled S1 is the first driving stage, the stage labeled S2 is the second driving stage, and the stage labeled Sa is the Kth stage.

[0283] The first driving stage S1 is the overlapping time period between the high voltage period of the second scan signal and the high voltage period of the third scan signal;

[0284] The second driving stage S2 is the overlapping period of the high voltage time period of the fourth scan signal and the high voltage time period of the fifth scan signal provided by the fifth row of gate lines;

[0285] The a-th driving phase Sa is the last 2H time included in the K-th scan signal (a is a positive integer);

[0286] In the first driving phase S1, the data line DT provides the first data voltage D1, GT1, GT2, GT3 and GT4 are turned on, and the sub-pixels located in the first row, the second row, the third row and the fourth row are turned on to receive the first data voltage D1.

[0287] In the second driving phase S2, the data line DT provides the third data voltage D3, GT3, GT4, the fifth row gate line and the sixth row gate line are turned on, and the sub-pixels located in the third row, the fourth row, the fifth row and the sixth row are turned on to receive the third data voltage D3.

[0288] During the a-th driving phase Sa, the data line DT provides the K-1 data voltage DK-1, GTK-1 and GTK are turned on, the sub-pixels located in the K-1 row and the sub-pixels located in the K row are turned on, and receive the K-1 data voltage DK-1.

[0289] In at least one embodiment shown in Figure 11, each driving phase lasts for 2 hours;

[0290] The data voltage received by the sub-pixels in row 2k-1 and row 2k is the same. The data voltage received by the sub-pixels in row 2k-1 and row 2k can be either the data voltage of row 2k-1 or the data voltage of row 2k. In this case, the data voltage of 2H can be charged, which can improve the charging rate for high-resolution products. When the architecture shown in Figure 1 is driven by the driving method in Figure 11, that is, driven by the second mode, GT1 in Figure 11 can be equivalent to GT(4N+2) in Figure 3, and GT2 in Figure 11 can be equivalent to GT(4N+3) in Figure 3. That is, the two gate lines that are turned on at the same time need to be connected to the same data line and the same color pixels. This can avoid display abnormalities. At this time, the gate line of GT(4N+1) can be driven separately. That is, the gate line of GT(4N+1) is driven first, then the gate lines of GT(4N+2) and GT(4N+3) are driven at the same time, and so on, and the gate lines of GT(4N+4) and GT(4N+5) are driven at the same time, and so on.

[0291] Based on the same inventive concept, this disclosure also provides a driving method for an array substrate. Referring to Figure 12, a third mode, namely the HSR driving mode, can be adopted. The driving method includes:

[0292] A scanning signal is provided to multiple grid lines to control the sequential opening of multiple grid lines within the display cycle;

[0293] Within the display cycle, there are overlapping and non-overlapping time periods between the effective time periods of the scan signals provided by at least two adjacent grid lines among the multiple grid lines that are opened sequentially;

[0294] The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

[0295] The array substrate provided in this embodiment can be driven independently using the HSR mode. The timing corresponding to the HSR drive can be as shown in Figure 12. The gate lines are scanned line by line, and the data signal width is 2H, which corresponds to the data of the sub-pixels connected by the odd-numbered or even-numbered gate lines, or it can be the average value of the sub-pixel data connected by two adjacent gate lines.

[0296] As shown in Figure 12, when the array substrate of at least one embodiment of this disclosure includes K rows of sub-pixels and K rows of scan lines, and the sub-pixels located in the k-th row are electrically connected to the scan lines in the k-th row (K is an integer greater than 1, and k is a positive integer less than or equal to K),

[0297] The display period may include a first overlapping time period J1 (optionally 1H), a first non-overlapping time period B1 (optionally 1H), a second overlapping time period J2 (optionally 1H), a second non-overlapping time period B2 (optionally 1H), an a-th overlapping time period Ja, and an a-th non-overlapping time period Ba (a is a positive integer). Here, the first overlapping time period refers to the part of time during which adjacent row grid lines are opened simultaneously, and the non-overlapping time period refers to the time period during which, among the grid lines that are opened sequentially in adjacent rows, the first grid line to be opened closes, and the last grid line to be opened opens.

[0298] During the first overlapping time period J1, the data line DT provides the first data voltage D1, GT1 and GT2 are turned on, and the first row sub-pixels and the second row sub-pixels receive the first data voltage D1.

[0299] During the first non-overlapping time period B1, the data line DT provides the first data voltage D1, GT2 is turned on, and the second row of sub-pixels receives the first data voltage D1, that is, during the first overlapping time period and the first non-overlapping time period, adjacent row sub-pixels receive the same data voltage.

[0300] During the second overlapping time period J2, the data line DT provides the third data voltage D3, GT3 and GT4 are turned on, and the third row sub-pixels and the fourth row sub-pixels receive the third data voltage D3.

[0301] During the second non-overlapping time period B2, data line DT provides the third data voltage D3, GT4 is turned on, and the fourth row sub-pixel receives the third data voltage D3.

[0302] During the overlapping time period Ja, data line DT provides the K-1 data voltage DK-1; GTK-1 and GTK are turned on, the K-1 row sub-pixel and the K row sub-pixel are turned on, and the K-1 row sub-pixel and the K row sub-pixel receive the K-1 data voltage DK-1;

[0303] During the non-overlapping time period Ba, the data line DT provides the (K-1)th data voltage DK; when GTK is turned on, the Kth row sub-pixel is turned on, and the Kth row sub-pixel receives the (K-1)th data voltage DK-1.

[0304] In at least one embodiment shown in FIG12, J1 is a partially overlapping time period between the high voltage time period of the first scan signal and the high voltage time period of the second scan signal.

[0305] B1 is the non-overlapping time period between the high-voltage time period of the first scan signal and the high-voltage time period of the second scan signal;

[0306] J2 is the partially overlapping time period between the high-voltage time period of the third scan signal and the high-voltage time period of the fourth scan signal;

[0307] B2 is the non-overlapping time period between the high-voltage time period of the third scan signal and the high-voltage time period of the fourth scan signal;

[0308] Ja is the partially overlapping time period between the high voltage time period of the M-1th scan signal and the high voltage time period of the Kth scan signal;

[0309] Ba is the non-overlapping time period between the high-voltage time period of the (M-1)th scan signal and the high-voltage time period of the Kth scan signal.

[0310] Referring again to Figure 12, this is equivalent to the pixel corresponding to GT2 being charged with 2H of D1 data signals, the pixel corresponding to GT4 being charged with 2H of D3 data signals, and the pixel corresponding to GT2 being charged with a portion of D1 data signals and a portion of D3 data signals. Optionally, the pixel corresponding to GT2 is charged with 1H of D1 data signals and 1H of D3 data signals. Compared with the first driving method, this scheme can improve the display charging rate in high-resolution products. It should be noted that the three driving modes in this case can be activated simultaneously in one display panel, or a single mode can be activated in one display panel, or at least two modes can be activated in one display panel. For example, the display panel includes a first frame rate and a second frame rate. When the first frame rate is activated, the first mode drives the display panel. When the second frame rate is activated, the second mode and / or the third mode are used, where the second frame rate is greater than the first frame rate. For example, if the first frame rate is 60Hz, the second frame rate is 120Hz or 144Hz, etc.

[0311] The pixel architecture in this disclosure is applicable to display pixel modes such as TN (Twisted Nematic), IPS (In-Plane Switching), ADS (Advanced Super Dimension Switch) / FFS (Fringe Field Switching), and VA (Vertical Alignment).

[0312] The pixel architecture in this disclosure is applicable to backplane processes such as a-Si (amorphous silicon), Oxide (oxide), LTPS (low-temperature polycrystalline silicon), and LTPO (low-temperature polycrystalline oxide).

[0313] In some embodiments, the display panel provided in this disclosure may further include a liquid crystal layer between an array substrate and a counter substrate, a first polarizer on the side of the array substrate away from the counter substrate, and a second polarizer on the side of the counter substrate away from the array substrate, wherein the polarization direction of the first polarizer and the polarization direction of the second polarizer are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the scope of this disclosure.

[0314] Based on the same inventive concept, this disclosure also provides a display device, comprising the display panel described above and a backlight module located on the light-incident side of the display panel. The backlight module can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature LEDs (Mini LEDs, Micro LEDs, etc.).

[0315] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0316] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0317] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0318] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Therefore, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. An array substrate having a plurality of pixels, wherein the pixels include a plurality of sub-pixels; wherein, The array substrate includes: Substrate; Multiple gate lines are located on one side of the substrate; the multiple gate lines extend along a first direction and are arranged along a second direction; Multiple sub-pixel rows are located on one side of the substrate, the multiple sub-pixel rows extend along a first direction and are arranged along a second direction; each sub-pixel row includes: multiple sub-pixels arranged along the first direction; a gate line is provided between two adjacent sub-pixel rows; In this configuration, multiple sub-pixels of the same pixel are distributed in different sub-pixel rows, and at least a portion of at least two adjacent pixels in the second direction are symmetrically or nearly symmetrically distributed with respect to the gate line between the two pixels.

2. The array substrate as claimed in claim 1, wherein, The array substrate includes: multiple data lines; each data line includes: multiple first sub-data portions extending along the second direction and arranged along the second direction, and second sub-pixel portions extending along the first direction and connecting adjacent first sub-data portions; the extension lines of the first data portions connecting both sides of the second sub-data portions do not overlap; The orthographic projection of the first sub-data section onto the substrate overlaps with the orthographic projections of the two sub-pixel rows onto the substrate.

3. The array substrate as described in claim 2, wherein, At least some of the adjacent pixels in the first direction are complementary.

4. The array substrate as described in claim 2 or 3, wherein, The array substrate includes: a plurality of pixel units; the pixel unit includes a plurality of pixels, namely: a first pixel, a second pixel, a third pixel, and a fourth pixel; The first pixel and the third pixel are distributed along the second direction and are symmetrical or nearly symmetrical about the gate line between them; the second pixel and the fourth pixel are distributed along the second direction and are symmetrical or nearly symmetrical about the gate line between them. The first pixel and the second pixel are distributed along the first direction and are complementary in distribution, and the third pixel and the fourth pixel are distributed along the first direction and are complementary in distribution.

5. The array substrate as claimed in claim 4, wherein, The pixel includes: a first sub-pixel, a second sub-pixel, and a third sub-pixel; the colors of the first sub-pixel, the second sub-pixel, and the third sub-pixel are all different; the colors of the first sub-pixels of different pixels are the same, the colors of the second sub-pixels of different pixels are the same, and the colors of the third sub-pixels of different pixels are the same. In the first pixel, the first sub-pixel and the second sub-pixel are located in the 4n+1th sub-pixel row, and the third sub-pixel is located in the 4n+2nd sub-pixel row; In the second pixel, the third sub-pixel is located in the 4n+1th sub-pixel row, and the first sub-pixel and the second sub-pixel are located in the 4n+2th sub-pixel row; In the third pixel, the third sub-pixel is located in the 4n+3rd sub-pixel row, and the first sub-pixel and the second sub-pixel are located in the 4n+4th sub-pixel row; In the fourth pixel, the first sub-pixel and the second sub-pixel are located in the 4n+3rd sub-pixel row, and the third sub-pixel is located in the 4n+4th sub-pixel row, where n represents a natural number.

6. The array substrate as claimed in claim 5, wherein, The first sub-pixel of the first pixel and the first sub-pixel of the third pixel are symmetrical or nearly symmetrical about the gate line; the second sub-pixel of the first pixel and the second sub-pixel of the third pixel are symmetrical or nearly symmetrical about the gate line; the third sub-pixel of the first pixel and the third sub-pixel of the third pixel are symmetrical or nearly symmetrical about the gate line. The first sub-pixel of the second pixel and the first sub-pixel of the fourth pixel are symmetrical or nearly symmetrical about the gate line; the second sub-pixel of the second pixel and the second sub-pixel of the fourth pixel are symmetrical or nearly symmetrical about the gate line; the third sub-pixel of the second pixel and the third sub-pixel of the fourth pixel are symmetrical or nearly symmetrical about the gate line.

7. The array substrate as claimed in claim 5 or 6, wherein, The lengths of each of the sub-pixels are equal in the first direction; The pixels satisfy at least one of the following relationships: 0 < d0 ≤ 0.7d1; 0 < d0' ≤ 0.7d1'; 0 < d0" ≤ 0.7d1'; Wherein, d0 represents the distance between the center of the first sub-pixel and the center of the third sub-pixel in the first direction, d1 represents the maximum length of the sub-pixel in the first direction; d0' represents the length of the second sub-data portion in the first direction, d1' represents the distance between two adjacent first sub-data line portions in the first direction; d0” represents the distance between the outer edges of the first sub-pixel and the third sub-pixel near the same data line in the first direction.

8. The array substrate as claimed in claim 7, wherein, The pixels satisfy at least one of the following relationships: d0 = 0.5d1; d0' = 0.5d1'; d0” = 0.50d1.

9. The array substrate according to any one of claims 5-8, wherein, There is a gate line between adjacent rows of sub-pixels; there is a sub-pixel between adjacent data lines.

10. The array substrate as claimed in claim 9, wherein, The sub-pixels connected to the same data line have the same color.

11. The array substrate as claimed in claim 9 or 10, wherein, In the first pixel, the first sub-pixel is connected to the 4N+1th gate line and the 4M+2nd data line, the second sub-pixel is connected to the 4N+1th gate line and the 4M+3rd data line, and the third sub-pixel is connected to the 4N+2th gate line and the 4M+1st data line; In the second pixel, the first sub-pixel is connected to the 4N+2th gate line and the 4M+2nd data line, the second sub-pixel is connected to the 4N+2nd gate line and the 4M+3rd data line, and the third sub-pixel is connected to the 4N+1th gate line and the 4M+4th data line; In the third pixel, the first sub-pixel is connected to the 4N+4th gate line and the 4M+2th data line, the second sub-pixel is connected to the 4N+4th gate line and the 4M+3th data line, and the third sub-pixel is connected to the 4N+3th gate line and the 4M+1th data line. In the fourth pixel, the first sub-pixel is connected to the 4N+3rd gate line and the 4M+2nd data line, the second sub-pixel is connected to the 4N+3rd gate line and the 4M+3rd data line, and the third sub-pixel is connected to the 4N+4th gate line and the 4M+4th data line, where N and M represent natural numbers.

12. The array substrate according to any one of claims 5-8, wherein, There are two gate lines between adjacent rows of sub-pixels; there are two sub-pixels between adjacent data lines.

13. The array substrate as claimed in claim 12, wherein, The array includes multiple pixel groups; each pixel group includes two pixel units distributed along the first direction, namely a first pixel unit and a second pixel unit. Wherein, in the first pixel unit: The first sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+2nd data line, the second sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+1st data line, and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+1st data line. The first sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+2nd data line; the second sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+3rd data line; and the third sub-pixel of the second pixel is connected to the 8N+1th gate line and the 4M+2nd data line. The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+1st data line; the second sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+2nd data line; and the third sub-pixel of the third pixel is connected to the 8N+6th gate line and the 4M+2nd data line. The first sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+1st data line, the second sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+2nd data line, and the third sub-pixel of the fourth pixel is connected to the 8N+8th gate line and the 4M+3rd data line, where N and M represent natural numbers.

14. The array substrate as claimed in claim 13, wherein, In the second pixel unit: The first sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+3rd data line; the second sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+4th data line; and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+2nd data line. The first sub-pixel of the second pixel is connected to the 8N+3rd gate line and the 4M+3rd data line; the second sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+4th data line; and the third sub-pixel of the second pixel is connected to the 8N+1th gate line and the 4M+3rd data line. The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+2nd data line; the second sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+3rd data line; and the third sub-pixel of the third pixel is connected to the 8N+6th gate line and the 4M+3rd data line. The first sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+4th data line, the second sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+3th data line, and the third sub-pixel of the fourth pixel is connected to the 8N+8th gate line and the 4M+4th data line.

15. The array substrate as claimed in claim 12, wherein, The array includes multiple pixel groups; each pixel group includes two pixel units distributed along the first direction, namely a first pixel unit and a second pixel unit. Wherein, in the first pixel unit: The first sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+1th data line, the second sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+1th data line, and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+2th data line. The first sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+2nd data line; the second sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+3rd data line; and the third sub-pixel of the second pixel is connected to the 8N+2th gate line and the 4M+2nd data line. The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+2nd data line; the second sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+2nd data line; and the third sub-pixel of the third pixel is connected to the 8N+5th gate line and the 4M+1st data line. The first sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+1th data line, the second sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+2th data line, and the third sub-pixel of the fourth pixel is connected to the 8N+8th gate line and the 4M+3rd data line, where N and M represent natural numbers.

16. The array substrate as claimed in claim 15, wherein, In the second pixel unit: The first sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+2nd data line, the second sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+3rd data line, and the third sub-pixel of the first pixel is connected to the 8N+3rd gate line and the 4M+3rd data line. The first sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+4th data line; the second sub-pixel of the second pixel is connected to the 8N+3th gate line and the 4M+4th data line; and the third sub-pixel of the second pixel is connected to the 8N+1th gate line and the 4M+3rd data line. The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+3rd data line; the second sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+4th data line; and the third sub-pixel of the third pixel is connected to the 8N+5th gate line and the 4M+2th data line. The first sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+3rd data line, the second sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+3rd data line, and the third sub-pixel of the fourth pixel is connected to the 8N+7th gate line and the 4M+4th data line.

17. The array substrate as claimed in claim 12, wherein, The array includes multiple pixel groups; each pixel group includes two pixel units distributed along the first direction, namely a first pixel unit and a second pixel unit. Wherein, in the first pixel unit: The first sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+1th data line, the second sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+1th data line, and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+2th data line. The first sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+2nd data line; the second sub-pixel of the second pixel is connected to the 8N+3th gate line and the 4M+3rd data line; and the third sub-pixel of the second pixel is connected to the 8N+1th gate line and the 4M+2nd data line. The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+2nd data line; the second sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+2nd data line; and the third sub-pixel of the third pixel is connected to the 8N+5th gate line and the 4M+1st data line. The first sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+1st data line, the second sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+2nd data line, and the third sub-pixel of the fourth pixel is connected to the 8N+7th gate line and the 4M+3rd data line, where N and M represent natural numbers.

18. The array substrate as claimed in claim 17, wherein, In the second pixel unit: The first sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+2nd data line, the second sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+3rd data line, and the third sub-pixel of the first pixel is connected to the 8N+4th gate line and the 4M+3rd data line. The first sub-pixel of the second pixel is connected to the 8N+3rd gate line and the 4M+4th data line; the second sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+4th data line; and the third sub-pixel of the second pixel is connected to the 8N+2th gate line and the 4M+3rd data line. The first sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+3rd data line; the second sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+4th data line; and the third sub-pixel of the third pixel is connected to the 8N+6th gate line and the 4M+2th data line. The first sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+3rd data line, the second sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+3rd data line, and the third sub-pixel of the fourth pixel is connected to the 8N+8th gate line and the 4M+4th data line.

19. The array substrate as claimed in claim 12, wherein, The array includes multiple pixel groups; each pixel group includes two pixel units distributed along the first direction, namely a first pixel unit and a second pixel unit. Wherein, in the first pixel unit: The first sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+2nd data line, the second sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+1st data line, and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+2nd data line; The first sub-pixel of the second pixel is connected to the 8N+3rd gate line and the 4M+1st data line; the second sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+3rd data line; and the third sub-pixel of the second pixel is connected to the 8N+2th gate line and the 4M+3rd data line. The first sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+2nd data line; the second sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+1st data line; and the third sub-pixel of the third pixel is connected to the 8N+6th gate line and the 4M+2nd data line. The first sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+1st data line, the second sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+3rd data line, and the third sub-pixel of the fourth pixel is connected to the 8N+8th gate line and the 4M+3rd data line, where N and M represent natural numbers.

20. The array substrate as claimed in claim 19, wherein, In the second pixel unit: The first sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+2nd data line; the second sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+4th data line; and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+2nd data line. The first sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+4th data line; the second sub-pixel of the second pixel is connected to the 8N+3th gate line and the 4M+3th data line; and the third sub-pixel of the second pixel is connected to the 8N+1th gate line and the 4M+3rd data line. The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+2nd data line; the second sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+4th data line; and the third sub-pixel of the third pixel is connected to the 8N+5th gate line and the 4M+2nd data line. The first sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+4th data line, the second sub-pixel is connected to the 8N+5th gate line and the 4M+3rd data line, and the third sub-pixel is connected to the 8N+7th gate line and the 4M+3rd data line.

21. The array substrate as claimed in claim 12, wherein, The array includes multiple pixel groups; each pixel group includes two pixel units distributed along the first direction, namely a first pixel unit and a second pixel unit. Wherein, in the first pixel unit: The first sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+1th data line, the second sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+2th data line, and the third sub-pixel of the first pixel is connected to the 8N+4th gate line and the 4M+1th data line; The first sub-pixel of the second pixel is connected to the 8N+3rd gate line and the 4M+2nd data line; the second sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+2nd data line; and the third sub-pixel of the second pixel is connected to the 8N+1th gate line and the 4M+2nd data line. The first sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+1st data line; the second sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+2nd data line; and the third sub-pixel of the third pixel is connected to the 8N+6th gate line and the 4M+1st data line. The first sub-pixel of the fourth pixel is connected to the 8N+5th gate line and the 4M+2nd data line, the second sub-pixel is connected to the 8N+6th gate line and the 4M+2nd data line, and the third sub-pixel is connected to the 8N+7th gate line and the 4M+2nd data line, where N and M represent natural numbers.

22. The array substrate as claimed in claim 21, wherein, In the second pixel unit: The first sub-pixel of the first pixel is connected to the 8N+2th gate line and the 4M+3rd data line; the second sub-pixel of the first pixel is connected to the 8N+1th gate line and the 4M+3rd data line; and the third sub-pixel of the first pixel is connected to the 8N+3th gate line and the 4M+3rd data line. The first sub-pixel of the second pixel is connected to the 8N+4th gate line and the 4M+3rd data line; the second sub-pixel of the second pixel is connected to the 8N+3rd gate line and the 4M+4th data line; and the third sub-pixel of the second pixel is connected to the 8N+2th gate line and the 4M+4th data line. The first sub-pixel of the third pixel is connected to the 8N+8th gate line and the 4M+3rd data line; the second sub-pixel of the third pixel is connected to the 8N+7th gate line and the 4M+3rd data line; and the third sub-pixel of the third pixel is connected to the 8N+5th gate line and the 4M+3rd data line. The first sub-pixel of the fourth pixel is connected to the 8N+6th gate line and the 4M+3rd data line, the second sub-pixel is connected to the 8N+5th gate line and the 4M+4th data line, and the third sub-pixel is connected to the 8N+8th gate line and the 4M+4th data line.

23. The array substrate according to any one of claims 1-22, wherein, The maximum length of the sub-pixel in the first direction is greater than the maximum width of the sub-pixel in the second direction.

24. The array substrate as claimed in claim 23, wherein, The ratio of the maximum length of the sub-pixel in the first direction to the maximum width in the second direction is in the range of 1.1 to 1.5; or, the ratio of the maximum length of the sub-pixel in the first direction to the maximum width in the second direction is in the range of 2.3 to 2.

85. Alternatively, the sub-pixel includes a sub-pixel electrode, wherein the ratio of the maximum length of the sub-pixel electrode in the first direction to the maximum width in the second direction is in the range of 1.1 to 1.5; or, the ratio of the maximum length of the sub-pixel electrode in the first direction to the maximum width in the second direction is in the range of 2.3 to 2.

85.

25. The array substrate as claimed in claim 24, wherein, The ratio of the maximum length of the sub-pixel and / or the sub-pixel electrode in the first direction to the maximum width in the second direction is 4:3; or, the ratio of the maximum length of the sub-pixel and / or the sub-pixel electrode in the first direction to the maximum width in the second direction is 8:

3.

26. A display panel, wherein, Including the array substrate as described in claims 1-25.

27. A display device, wherein, Includes the display panel as described in claim 26.

28. A driving method applied to an array substrate as described in any one of claims 1 to 25, wherein the display cycle includes a plurality of sequentially arranged driving stages; the driving method includes: During the 2k-1 driving phase, the 2k-1 gate line is turned on, and the sub-pixels connected to the 2k-1 gate line receive the data voltage provided by the corresponding data line. During the 2k driving phase, the 2k gate line is turned on, and the sub-pixels connected to the 2k gate line receive the data voltage provided by the corresponding data line. k is a positive integer; In the 2k-1 driving phase, the data voltage provided by the data line is the data voltage corresponding to the sub-pixel of the 2k-1 row; in the 2k driving phase, the data voltage provided by the data line is the data voltage corresponding to the sub-pixel of the 2k row.

29. A driving method applied to an array substrate as described in any one of claims 1 to 25, the driving method comprising: Provide scan signals to multiple gate lines such that the scan signal provided by the (2k-1)th gate line is the same as the scan signal provided by the 2kth gate line; There is an overlapping time period between the effective voltage time period of the 2k scan signal and the effective voltage time period of the 2k+1 scan signal. During the overlapping time period, the 2k-1 gate line, the 2k gate line, the 2k+1 gate line, and the 2k+2 gate line are turned on, and the sub-pixels located in the 2k-1 row, the 2k row, the 2k+1 row, and the 2k+2 row receive the data voltage provided by the corresponding data lines. k is a positive integer.

30. A driving method applied to an array substrate as described in any one of claims 1 to 25, the driving method comprising: Scan signals are provided to multiple grid lines to control the sequential opening of the multiple grid lines during the display cycle; Within the display cycle, there are overlapping and non-overlapping time periods among the effective time periods of the scan signals provided by at least two adjacent gate lines of the multiple gate lines that are opened sequentially; The data voltage received by the data line during at least a portion of the overlapping time period is the same as the data voltage received by the data line during at least a portion of the non-overlapping time period.

31. A display method, wherein, The driving method described in claims 28, 29, and 30 is used for driving. Alternatively, at the first frame rate, the driving method as described in claim 28 is used, and at the second frame rate, the driving method as described in claim 29 and / or claim 30 is used, wherein the second frame rate is greater than the first frame rate.

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