Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a display area (AA) and a non-display area (BB); the display area (AA) is provided with a plurality of sub-pixels (20); the non-display area (BB) is provided with a gating circuit (10), a plurality of driving circuits and a plurality of initial signal lines; at least one of the plurality of driving circuits comprises a plurality of shift registers (31), at least one shift register comprising a driving input terminal and a driving output terminal; the gating circuit (10) is electrically connected to the driving input terminal of the at least one shift register in the at least one of the plurality of driving circuits and the plurality of initial signal lines; the gating circuit (10) comprises a plurality of gating sub-circuits (11); under the control of signals of a first enable terminal (EN1) and a second enable terminal (EN2), the gating sub-circuits (11) are configured to respectively provide to a plurality of gating output terminals signals of a plurality of initial input terminals or signals of a plurality of cascade input terminals.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Technology

[0002] With the rapid development of display technology, display devices are increasingly moving towards higher integration and lower cost. Among these technologies, GOA (Gate Driver on Array) integrates TFT (Thin Film Transistor) gate driving circuitry onto the array substrate of the display device to form a scanning drive for the display. This gate driving circuit typically consists of multiple cascaded shift registers. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate and a display device.

[0005] In a first aspect, this disclosure provides a display substrate, including: a display area and a non-display area located on at least one side of the display area, the display area being provided with a plurality of sub-pixels, the non-display area being provided with a gating circuit, a plurality of driving circuits and a plurality of initial signal lines, at least one of the plurality of driving circuits including: a plurality of shift registers, the at least one shift register including: a driving input terminal and a driving output terminal;

[0006] The drive output terminal of at least one shift register of at least one of the plurality of drive circuits is electrically connected to the plurality of sub-pixels.

[0007] The gating circuit is electrically connected to the drive input terminal of at least one shift register in at least one of the plurality of drive circuits and to the plurality of initial signal lines, respectively.

[0008] The gating circuit includes: multiple gating sub-circuits;

[0009] The gating sub-circuit is electrically connected to a first enable terminal, a second enable terminal, multiple initial input terminals, multiple cascaded input terminals, and multiple gating output terminals, respectively. It is configured to provide signals from multiple initial input terminals or signals from multiple cascaded input terminals to the multiple gating output terminals under the control of the signals from the first enable terminal and the second enable terminal.

[0010] In an exemplary embodiment, multiple shift registers located in at least one driving circuit are divided into N shift register groups, and multiple shift registers located in the same shift register group are cascaded with each other;

[0011] The m-th gating output terminal connected to the n-th gating sub-circuit is electrically connected to the driving input terminal of the first shift register in the n-th shift register group of the m-th driving circuit, where 1≤m≤M, 1≤n≤N, M is the number of gating output terminals connected to the gating sub-circuit, and N is the number of gating sub-circuits included in the gating circuit.

[0012] In an exemplary embodiment, the number of initial input terminals connected to the gating sub-circuit is M, and the number of cascaded input terminals connected to the gating sub-circuit is M;

[0013] At least one gating sub-circuit has its m-th initial input terminal electrically connected to the m-th initial signal line;

[0014] The first gating sub-circuit is connected to the mth cascaded input terminal, which is electrically connected to the mth target power line. The signal of the mth target power line is a constant voltage signal, and the voltage value is equal to the voltage value of the invalid level signal of the mth initial signal line.

[0015] The m-th cascaded input terminal of the k-th gating sub-circuit is electrically connected to the drive output terminal of the last shift register in the (k-1)-th shift register group of the m-th drive circuit, where 2≤k≤N.

[0016] In an exemplary embodiment, at least one gating sub-circuit includes: a first node control sub-circuit, a second node control sub-circuit, a first output sub-circuit, and a second output sub-circuit;

[0017] The first node control sub-circuit is electrically connected to the gating input terminal, the first enable terminal, the gating reset signal terminal, the first power supply terminal, the second power supply terminal, the gating clock terminal, and the first node, respectively, and is configured to provide a signal from one of the signal terminals of the first enable terminal, the first power supply terminal, and the second power supply terminal to the first node under the control of the gating input terminal, the gating clock terminal, and the gating reset signal terminal.

[0018] The second node control sub-circuit is electrically connected to the gating input terminal, the second enable terminal, the gating reset signal terminal, the first power supply terminal, the second power supply terminal, the gating clock terminal, and the second node, respectively, and is configured to provide a signal from one of the signal terminals of the second enable terminal, the first power supply terminal, and the second power supply terminal to the second node under the control of the gating input terminal, the gating clock terminal, and the gating reset signal terminal.

[0019] The first output sub-circuit is electrically connected to the first node, the M initial input terminals and the M gating output terminals respectively, and is configured to provide the signals of the M initial input terminals to the M gating output terminals under the control of the signal of the first node;

[0020] The second output sub-circuit is electrically connected to the second node, the M cascaded input terminals and the M gating output terminals respectively, and is configured to provide the signals of the M cascaded input terminals to the M gating output terminals under the control of the signal of the second node.

[0021] In an exemplary embodiment, the first node control subcircuit includes: a first write subcircuit, a second write subcircuit, a third write subcircuit, and a first gating reset subcircuit;

[0022] The first write sub-circuit is electrically connected to the gating input terminal, the first enable terminal, the second power supply terminal, the gating clock terminal, the first node, the third node, the fourth node, the fifth node, and the sixth node, respectively. It is configured to provide the first enable terminal signal to the first node, the third node, the fourth node, and the fifth node under the control of the signal of the gating input terminal and the second power supply terminal, and to provide the gating clock terminal signal to the sixth node under the control of the signal of the fifth node, and to store the voltage difference between the signals of the fifth node and the sixth node.

[0023] The second write sub-circuit is electrically connected to the gating clock terminal, the second power supply terminal, the first node, and the third node, respectively, and is configured to provide the second power supply terminal signal to the third node under the control of the signals of the gating clock terminal and the first node;

[0024] The third write sub-circuit is electrically connected to the gating clock terminal, the first power supply terminal, the third node, and the seventh node, respectively. It is configured to provide the signal of the first power supply terminal to the other node of the third node and the seventh node under the control of the signal of one of the nodes of the third node and the seventh node, and to store the voltage difference between the signal of the seventh node and the gating clock terminal.

[0025] The first gating reset sub-circuit is electrically connected to the gating reset signal terminal, the first power supply terminal, the third node, and the fourth node, respectively, and is configured to provide the first power supply terminal signal to the third node and the fourth node under the control of the signal from the gating reset signal terminal.

[0026] In an exemplary embodiment, the first write sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor;

[0027] The control electrode of the first transistor is electrically connected to the gating input terminal, the first electrode of the first transistor is electrically connected to the first enable terminal, and the second electrode of the first transistor is electrically connected to the third node.

[0028] The control electrode of the second transistor is electrically connected to the gating input terminal, the first electrode of the second transistor is electrically connected to the first enable terminal, and the second electrode of the second transistor is electrically connected to the fourth node.

[0029] The control electrode of the third transistor is electrically connected to the second power supply terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the first node.

[0030] The control electrode of the fourth transistor is electrically connected to the second power supply terminal, the first electrode of the fourth transistor is electrically connected to the fourth node, and the second electrode of the fourth transistor is electrically connected to the fifth node.

[0031] The control electrode and the first electrode of the fifth transistor are electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the first node.

[0032] The control electrode of the sixth transistor is electrically connected to the fifth node, the first electrode of the sixth transistor is electrically connected to the sixth node, and the second electrode of the sixth transistor is electrically connected to the strobe clock terminal.

[0033] The first terminal of the first capacitor is electrically connected to the fifth node, and the second terminal of the first capacitor is electrically connected to the sixth node.

[0034] In an exemplary embodiment, the second write sub-circuit includes a seventh transistor and an eighth transistor;

[0035] The control terminal of the seventh transistor is electrically connected to the gating clock terminal, the first terminal of the seventh transistor is electrically connected to the second power supply terminal, and the second terminal of the seventh transistor is electrically connected to the eighth node.

[0036] The control electrode of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the eighth node, and the second electrode of the eighth transistor is electrically connected to the third node.

[0037] In an exemplary embodiment, the third write sub-circuit includes: a ninth transistor, a tenth transistor, and a second capacitor;

[0038] The control electrode of the ninth transistor is electrically connected to the seventh node, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the first power supply terminal.

[0039] The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the first power supply terminal, and the second electrode of the tenth transistor is electrically connected to the seventh node.

[0040] The first terminal of the second capacitor is electrically connected to the strobe clock terminal, and the second terminal of the second capacitor is electrically connected to the seventh node.

[0041] In an exemplary embodiment, the first gating reset sub-circuit includes an eleventh transistor and a twelfth transistor;

[0042] The control electrode of the eleventh transistor is electrically connected to the gating reset signal terminal, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the third node.

[0043] The control terminal of the twelfth transistor is electrically connected to the gating and reset signal terminal, the first terminal of the twelfth transistor is electrically connected to the first power supply terminal, and the second terminal of the twelfth transistor is electrically connected to the fourth node.

[0044] In an exemplary embodiment, the second node control subcircuit includes: a fourth write subcircuit, a fifth write subcircuit, a sixth write subcircuit, and a second gating reset subcircuit;

[0045] The fourth write sub-circuit is electrically connected to the gating input terminal, the second enable terminal, the second power supply terminal, the gating clock terminal, the second node, the ninth node, the tenth node, the eleventh node, and the twelfth node, respectively. It is configured to provide the second enable terminal signal to the second node, the ninth node, the tenth node, and the eleventh node under the control of the signal of the gating input terminal and the second power supply terminal, and to provide the gating clock terminal signal to the twelfth node under the control of the signal of the eleventh node, and to store the voltage difference between the signals of the eleventh node and the twelfth node.

[0046] The fifth write sub-circuit is electrically connected to the gating clock terminal, the second power supply terminal, the second node, and the ninth node, respectively, and is configured to provide the second power supply terminal signal to the ninth node under the control of the signals of the gating clock terminal and the second node.

[0047] The sixth write sub-circuit is electrically connected to the gating clock terminal, the first power supply terminal, the ninth node, and the thirteenth node, respectively. It is configured to provide the signal of the first power supply terminal to the other node of the ninth node and the thirteenth node under the control of the signal of one of the nodes, and to store the voltage difference between the signal of the thirteenth node and the gating clock terminal.

[0048] The second gating reset sub-circuit is electrically connected to the gating reset signal terminal, the second power supply terminal, the ninth node, and the tenth node, respectively, and is configured to provide the second power supply terminal signal to the ninth node and the tenth node under the control of the signal from the gating reset signal terminal.

[0049] In an exemplary embodiment, the fourth write sub-circuit includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a third capacitor;

[0050] The control terminal of the thirteenth transistor is electrically connected to the gating input terminal, the first terminal of the thirteenth transistor is electrically connected to the second enable terminal, and the second terminal of the thirteenth transistor is electrically connected to the ninth node.

[0051] The control terminal of the fourteenth transistor is electrically connected to the gating input terminal, the first terminal of the fourteenth transistor is electrically connected to the second enable terminal, and the second terminal of the fourteenth transistor is electrically connected to the tenth node.

[0052] The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, the first electrode of the fifteenth transistor is electrically connected to the ninth node, and the second electrode of the fifteenth transistor is electrically connected to the second node.

[0053] The control terminal of the sixteenth transistor is electrically connected to the second power supply terminal, the first terminal of the sixteenth transistor is electrically connected to the tenth node, and the second terminal of the sixteenth transistor is electrically connected to the eleventh node.

[0054] The control electrode and the first electrode of the seventeenth transistor are electrically connected to the eleventh node, and the second electrode of the seventeenth transistor is electrically connected to the second node.

[0055] The control electrode of the eighteenth transistor is electrically connected to the eleventh node, the first electrode of the eighteenth transistor is electrically connected to the twelfth node, and the second electrode of the eighteenth transistor is electrically connected to the strobe clock terminal.

[0056] The first terminal of the third capacitor is electrically connected to the eleventh node, and the second terminal of the third capacitor is electrically connected to the twelfth node.

[0057] In an exemplary embodiment, the fifth write sub-circuit includes: a nineteenth transistor and a twentieth transistor;

[0058] The control terminal of the nineteenth transistor is electrically connected to the gating clock terminal, the first terminal of the nineteenth transistor is electrically connected to the second power supply terminal, and the second terminal of the nineteenth transistor is electrically connected to the fourteenth node.

[0059] The control electrode of the twentieth transistor is electrically connected to the second node, the first electrode of the twentieth transistor is electrically connected to the fourteenth node, and the second electrode of the twentieth transistor is electrically connected to the ninth node.

[0060] In an exemplary embodiment, the sixth write sub-circuit includes: a twenty-first transistor, a twenty-second transistor, and a fourth capacitor;

[0061] The control electrode of the 21st transistor is electrically connected to the 13th node, the first electrode of the 21st transistor is electrically connected to the 9th node, and the second electrode of the 21st transistor is electrically connected to the first power supply terminal.

[0062] The control electrode of the 22nd transistor is electrically connected to the 9th node, the first electrode of the 22nd transistor is electrically connected to the first power supply terminal, and the second electrode of the 22nd transistor is electrically connected to the 13th node.

[0063] The first terminal of the fourth capacitor is electrically connected to the strobe clock terminal, and the second terminal of the fourth capacitor is electrically connected to the thirteenth node.

[0064] In an exemplary embodiment, the second gating reset sub-circuit includes: a twenty-third transistor and a twenty-fourth transistor;

[0065] The control terminal of the 23rd transistor is electrically connected to the gating and reset signal terminal, the first terminal of the 23rd transistor is electrically connected to the second power supply terminal, and the second terminal of the 23rd transistor is electrically connected to the ninth node.

[0066] The control terminal of the 24th transistor is electrically connected to the gating and reset signal terminal, the first terminal of the 24th transistor is electrically connected to the second power supply terminal, and the second terminal of the 24th transistor is electrically connected to the 10th node.

[0067] In an exemplary embodiment, the first output sub-circuit includes: M initial output transistors;

[0068] The control electrode of the m-th initial output transistor is electrically connected to the first node, the first electrode of the m-th initial output transistor is electrically connected to the m-th initial input terminal, and the second electrode of the m-th initial output transistor is electrically connected to the m-th gating output terminal.

[0069] In an exemplary embodiment, the second output sub-circuit includes: M cascaded output transistors;

[0070] The control terminal of the m-th cascaded output transistor is electrically connected to the second node, the first terminal of the m-th cascaded output transistor is electrically connected to the m-th cascaded input terminal, and the second terminal of the m-th cascaded output transistor is electrically connected to the m-th gating output terminal.

[0071] In an exemplary embodiment, in at least one gating sub-circuit, the first node control sub-circuit includes: a first transistor to a twelfth transistor, a first capacitor and a second capacitor; the second node control sub-circuit includes: a thirteenth transistor and a twenty-fourth transistor, a third capacitor and a fourth capacitor; the first output sub-circuit includes: M initial output transistors; and the second output sub-circuit includes: M cascaded output transistors.

[0072] The control electrode of the first transistor is electrically connected to the gating input terminal, the first electrode of the first transistor is electrically connected to the first enable terminal, and the second electrode of the first transistor is electrically connected to the third node.

[0073] The control electrode of the second transistor is electrically connected to the gating input terminal, the first electrode of the second transistor is electrically connected to the first enable terminal, and the second electrode of the second transistor is electrically connected to the fourth node.

[0074] The control electrode of the third transistor is electrically connected to the second power supply terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the first node.

[0075] The control electrode of the fourth transistor is electrically connected to the second power supply terminal, the first electrode of the fourth transistor is electrically connected to the fourth node, and the second electrode of the fourth transistor is electrically connected to the fifth node.

[0076] The control electrode and the first electrode of the fifth transistor are electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the first node.

[0077] The control electrode of the sixth transistor is electrically connected to the fifth node, the first electrode of the sixth transistor is electrically connected to the sixth node, and the second electrode of the sixth transistor is electrically connected to the strobe clock terminal.

[0078] The control terminal of the seventh transistor is electrically connected to the gating clock terminal, the first terminal of the seventh transistor is electrically connected to the second power supply terminal, and the second terminal of the seventh transistor is electrically connected to the eighth node.

[0079] The control electrode of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the eighth node, and the second electrode of the eighth transistor is electrically connected to the third node.

[0080] The control electrode of the ninth transistor is electrically connected to the seventh node, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the first power supply terminal.

[0081] The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the first power supply terminal, and the second electrode of the tenth transistor is electrically connected to the seventh node.

[0082] The control electrode of the eleventh transistor is electrically connected to the gating reset signal terminal, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the third node.

[0083] The control terminal of the twelfth transistor is electrically connected to the gating reset signal terminal, the first terminal of the twelfth transistor is electrically connected to the first power supply terminal, and the second terminal of the twelfth transistor is electrically connected to the fourth node.

[0084] The control terminal of the thirteenth transistor is electrically connected to the gating input terminal, the first terminal of the thirteenth transistor is electrically connected to the second enable terminal, and the second terminal of the thirteenth transistor is electrically connected to the ninth node.

[0085] The control terminal of the fourteenth transistor is electrically connected to the gating input terminal, the first terminal of the fourteenth transistor is electrically connected to the second enable terminal, and the second terminal of the fourteenth transistor is electrically connected to the tenth node.

[0086] The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, the first electrode of the fifteenth transistor is electrically connected to the ninth node, and the second electrode of the fifteenth transistor is electrically connected to the second node.

[0087] The control terminal of the sixteenth transistor is electrically connected to the second power supply terminal, the first terminal of the sixteenth transistor is electrically connected to the tenth node, and the second terminal of the sixteenth transistor is electrically connected to the eleventh node.

[0088] The control electrode and the first electrode of the seventeenth transistor are electrically connected to the eleventh node, and the second electrode of the seventeenth transistor is electrically connected to the second node.

[0089] The control electrode of the eighteenth transistor is electrically connected to the eleventh node, the first electrode of the eighteenth transistor is electrically connected to the twelfth node, and the second electrode of the eighteenth transistor is electrically connected to the strobe clock terminal.

[0090] The control terminal of the nineteenth transistor is electrically connected to the gating clock terminal, the first terminal of the nineteenth transistor is electrically connected to the second power supply terminal, and the second terminal of the nineteenth transistor is electrically connected to the fourteenth node.

[0091] The control electrode of the twentieth transistor is electrically connected to the second node, the first electrode of the twentieth transistor is electrically connected to the fourteenth node, and the second electrode of the twentieth transistor is electrically connected to the ninth node.

[0092] The control electrode of the 21st transistor is electrically connected to the 13th node, the first electrode of the 21st transistor is electrically connected to the 9th node, and the second electrode of the 21st transistor is electrically connected to the first power supply terminal.

[0093] The control electrode of the 22nd transistor is electrically connected to the 9th node, the first electrode of the 22nd transistor is electrically connected to the first power supply terminal, and the second electrode of the 22nd transistor is electrically connected to the 13th node.

[0094] The control terminal of the 23rd transistor is electrically connected to the gating and reset signal terminal, the first terminal of the 23rd transistor is electrically connected to the second power supply terminal, and the second terminal of the 23rd transistor is electrically connected to the ninth node.

[0095] The control terminal of the 24th transistor is electrically connected to the gating and reset signal terminal, the first terminal of the 24th transistor is electrically connected to the second power supply terminal, and the second terminal of the 24th transistor is electrically connected to the 10th node.

[0096] The control electrode of the m-th initial output transistor is electrically connected to the first node, the first electrode of the m-th initial output transistor is electrically connected to the m-th initial input terminal, and the second electrode of the m-th initial output transistor is electrically connected to the m-th gating output terminal.

[0097] The control electrode of the m-th cascaded output transistor is electrically connected to the second node, the first electrode of the m-th cascaded output transistor is electrically connected to the m-th cascaded input terminal, and the second electrode of the m-th cascaded output transistor is electrically connected to the m-th gating output terminal.

[0098] The first terminal of the first capacitor is electrically connected to the fifth node, and the second terminal of the first capacitor is electrically connected to the sixth node.

[0099] The first terminal of the second capacitor is electrically connected to the gating clock terminal, and the second terminal of the second capacitor is electrically connected to the seventh node.

[0100] The first terminal of the third capacitor is electrically connected to the eleventh node, and the second terminal of the third capacitor is electrically connected to the twelfth node.

[0101] The first terminal of the fourth capacitor is electrically connected to the strobe clock terminal, and the second terminal of the fourth capacitor is electrically connected to the thirteenth node.

[0102] In an exemplary embodiment, the signals of the first enable terminal and the second enable terminal are inverse signals.

[0103] In an exemplary embodiment, at least one gating sub-circuit is also electrically connected to the gating input terminal and the gating clock terminal.

[0104] The signal at the gating input terminal and the signal at the gating clock terminal connected to at least one gating sub-circuit are inverse signals for a certain period of time.

[0105] In an exemplary embodiment, it further includes: a selection circuit, the selection circuit including: N selection sub-circuits, the N selection sub-circuits being cascaded together, and at least one gating sub-circuit being electrically connected to a gating input terminal;

[0106] The nth selector circuit is electrically connected to the gating input of the nth gating circuit.

[0107] In an exemplary embodiment, at least one selector circuit has a structure that is at least partially identical to that of at least one shift register in at least one drive circuit.

[0108] In an exemplary embodiment, the first enable terminal and the second enable terminal of the nth select sub-circuit are electrically connected to each other.

[0109] In an exemplary embodiment, it further includes: a selection chip;

[0110] The selection chip is electrically connected to at least one of the signal terminals of the first enable terminal and the second enable terminal, which are connected to at least one gating sub-circuit.

[0111] Secondly, this disclosure also provides a display device, including: the aforementioned display substrate.

[0112] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0113] Overview of the attached figures

[0114] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0115] Figure 1 is a schematic diagram of a display device;

[0116] Figure 2A is a schematic diagram of a planar structure of a display substrate;

[0117] Figure 2B is a schematic diagram of a planar structure of a display substrate;

[0118] Figure 2C is a schematic diagram of a planar structure of a display substrate;

[0119] Figure 3 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0120] Figure 4 is a timing diagram of the pixel driving circuit provided in Figure 3;

[0121] Figure 5A is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0122] Figure 5B is a schematic diagram of the gating sub-circuit connection;

[0123] Figure 6 is a schematic diagram of the gating circuit;

[0124] Figure 7 is a schematic diagram of the drive circuit;

[0125] Figure 8 is a schematic diagram showing the connection between the gating circuit and one of the driving circuits;

[0126] Figure 9 is a schematic diagram of the gating sub-circuit;

[0127] Figure 10 is a schematic diagram of the structure of a gating sub-circuit provided in an exemplary embodiment;

[0128] Figure 11 is the equivalent circuit diagram of the first node control sub-circuit;

[0129] Figure 12 is the equivalent circuit diagram of the second node control sub-circuit;

[0130] Figure 13 is the equivalent circuit diagram of the first output sub-circuit;

[0131] Figure 14 is the equivalent circuit diagram of the second output sub-circuit;

[0132] Figure 15 shows the equivalent circuit diagram of the gating sub-circuit;

[0133] Figure 16 is the first driving timing diagram of the gating sub-circuit provided in Figure 15;

[0134] Figure 17 is the second driving timing diagram of the gating sub-circuit provided in Figure 15;

[0135] Figure 18 is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment;

[0136] Figure 19 is a schematic diagram of the structure of a display substrate provided in another exemplary embodiment.

[0137] Detailed Explanation

[0138] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0139] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0140] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0141] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0142] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0143] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0144] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0145] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0146] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a gate driver, and a pixel array. The timing controller is connected to the data driver and the gate driver. The data driver is connected to multiple data signal lines (D1 to Dn), and the gate driver is connected to multiple gate lines (G1 to Gm). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers.

[0147] In an exemplary embodiment, when the display device is a liquid crystal display device, at least one sub-pixel may include: a switching transistor, a pixel electrode, a common electrode, and a liquid crystal layer. The switching transistor may be connected to a gate line and a data signal line, respectively.

[0148] In an exemplary embodiment, when the display device is an organic light-emitting diode display device, at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to a gate line and a data signal line, respectively.

[0149] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages that will be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel-row basis, where n can be a natural number.

[0150] In an exemplary embodiment, the gate driver can generate a scan signal to be provided to the gate line by receiving a clock signal, a gate start signal, etc., from a timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to the gate line. For example, the gate driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal.

[0151] Figure 2A is a schematic diagram of a planar structure of a display substrate (Figure 1), Figure 2B is a schematic diagram of a planar structure of a display substrate (Figure 22), and Figure 2C is a schematic diagram of a planar structure of a display substrate (Figure 23). As shown in Figures 2A to 2C, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light.

[0152] In an exemplary embodiment, when the display device is an organic light-emitting diode (OLED) display device, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to a gate line and a data signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the gate line and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0153] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 may be a green sub-pixel (G) that emits green light.

[0154] In an exemplary embodiment, the shape of the sub-pixel can be rectangular, rhomboid, pentagonal or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side or in a triangular pattern, which is not limited in this disclosure.

[0155] In an exemplary embodiment, a pixel unit may include three sub-pixels. These three sub-pixels may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement, etc., and this disclosure does not limit the specific arrangement. Figures 2A and 2B are illustrated using the example of a pixel unit comprising three sub-pixels. In Figure 2A, the three sub-pixels are arranged horizontally side-by-side, and in Figure 2B, the three sub-pixels are arranged in a triangular arrangement.

[0156] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged horizontally side-by-side, vertically side-by-side, or in a square, etc., and this disclosure does not limit the arrangement. Figure 2C illustrates an example where a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square.

[0157] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure, and this disclosure does not limit it in any way.

[0158] Figure 3 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 3, the pixel driving circuit may include seven transistors (first transistor M1 to seventh transistor M7) and one capacitor C. Specifically, the gate electrode of the first transistor M1 is electrically connected to the first reset signal line Reset1, the first terminal of the first transistor M1 is electrically connected to the first initial signal line INIT1, and the second terminal of the first transistor M1 is electrically connected to either the first node N1 or the third node N3. The gate electrode of the second transistor M2 is electrically connected to the second scan signal line Gate2, the first terminal of the second transistor M2 is electrically connected to the first node N1, and the second terminal of the second transistor M2 is electrically connected to the third node N3. The gate electrode of the third transistor M3 is electrically connected to the first node N1, the first terminal of the third transistor M3 is electrically connected to the second node N2, and the second terminal of the third transistor M3 is electrically connected to the third node N3. The gate electrode of the fourth transistor M4 is electrically connected to the first scan signal line Gate1, and the first terminal of the fourth transistor M4 is electrically connected to the data signal line Data. The second terminal of the fourth transistor M4 is electrically connected to the second node N2; the gate electrode of the fifth transistor M5 is electrically connected to the light-emitting signal line EM, the first terminal of the fifth transistor M5 is electrically connected to the high-level power supply line VDD, and the second terminal of the fifth transistor M5 is electrically connected to the second node N2; the gate electrode of the sixth transistor M6 is electrically connected to the light-emitting signal line EM, the first terminal of the sixth transistor M6 is electrically connected to the third node N3, and the second terminal of the sixth transistor M6 is electrically connected to the fourth node N4; the gate electrode of the seventh transistor M7 is electrically connected to the second reset signal line Reset2, the first terminal of the seventh transistor M7 is electrically connected to the second initial signal line INIT2, and the second terminal of the seventh transistor M7 is electrically connected to the fourth node N4; the first plate of capacitor C is electrically connected to the first node N1, and the second plate of capacitor C is electrically connected to the high-level power supply line VDD. Figure 3 illustrates this using the example of the second terminal of the first transistor M1 being electrically connected to the first node N1.

[0159] In an exemplary embodiment, the signal of the second reset signal line Reset2 may be the same as the signal of the first scan signal line Gate1, or it may also be the same as the signal of the first reset signal line Reset1.

[0160] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), or oxide thin-film transistors (OPTs), or a combination of both. The active pattern of the LTPS is made of low-temperature polysilicon (LTPS), while the active pattern of the OPT is made of oxide. LTPS TFTs have advantages such as high mobility and fast charging, while OPTs have advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate to form an LTPO display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0161] In an exemplary embodiment, at least one of the first transistor M1 and the second transistor M2 has a transistor type opposite to that of at least one of the third transistor M3 to the seventh transistor M7. For example, the first transistor M1 and the second transistor M2 can be N-type transistors, and the third transistor M3 to the seventh transistor M7 can be P-type transistors; alternatively, the second transistor M2 can be an N-type transistor, and the first transistor M1 and the third transistor M3 to the seventh transistor M7 can be P-type transistors.

[0162] In an exemplary embodiment, the N-type transistor can be an oxide transistor, and the P-type transistor can be a low-temperature polysilicon transistor.

[0163] In an exemplary embodiment, the voltage value of the signal on the first initial signal line INIT1 is constant and is a DC signal; the voltage value of the signal on the first initial signal line INIT1 can be -3V.

[0164] In an exemplary embodiment, the voltage value of the signal on the second initial signal line INIT2 is constant and is a DC signal; the voltage value of the signal on the second initial signal line INIT2 can be 0V.

[0165] In an exemplary embodiment, the light-emitting device L can be electrically connected to the fourth node N4 and the low-level power line VSS, respectively.

[0166] In an exemplary embodiment, the high-level power line VDD continuously provides a high-level signal, and the low-level power line VSS continuously provides a low-level signal.

[0167] In an exemplary embodiment, the gate line may include: a first scan signal line, a second scan signal line, a first reset signal line, a second reset signal line, and a light emission signal line.

[0168] Figure 4 is a timing diagram of the pixel driving circuit shown in Figure 3. The following describes an exemplary embodiment of this disclosure through the operation of the pixel driving circuit in the display stage as illustrated in Figure 3. Figure 4 is illustrated with the example of the second transistor M2 being an N-type transistor, the first transistor M1, the third transistor M3 to the seventh transistor M7 being P-type transistors, and the signal of the second reset signal line Reset2 being the same as the signal of the first reset signal line Reset1. The pixel driving circuit in Figure 3 includes the first transistor M1 to the seventh transistor M7, a capacitor C, and nine signal lines (data signal line Data, first scan signal line Gate1, second scan signal line Gate2, first reset signal line Reset1, second reset signal line Reset2, first initial signal line INIT1, second initial signal line INIT2, light emission signal line EM, and high-level power supply line VDD).

[0169] Referring to Figures 3 and 4, the operation of the pixel driving circuit can include:

[0170] In the first stage P1, called the initialization stage, the signals of the first reset signal line Reset1 and the second reset signal line Reset2 are high-level signals, the first transistor M1 is turned on, and the signal of the first initial signal line INIT1 is written to the first node N1 or the third node N3 through the turned-on first transistor M1 to initialize (reset) the first node N1 or the third node N3, clearing its internal pre-stored voltage and completing the initialization. The seventh transistor M7 is turned on, and the signal of the second initial signal line INIT2 is written to the fourth node N4 through the turned-on seventh transistor M7 to initialize (reset) the first electrode of the light-emitting device L, clearing its internal pre-stored voltage and completing the initialization.

[0171] The second stage, P2, is called the data writing stage or threshold compensation stage. The first scan signal line, Gate1, is low, and the second scan signal line, Gate2, is high. The data signal line, Data, outputs a data voltage. During this stage, since the first node, N1, is low, the third transistor, M3, is turned on. With the first scan signal line, Gate1, low, the fourth transistor, M4, is turned on. With the second scan signal line, Gate2, high, the second transistor, M2, is turned on. The data voltage output from Data is supplied to the first node, N1, via the turned-on fourth transistor, M4, N2, M3, and M2. The difference between the data voltage output from Data and the threshold voltage of the third transistor, M3, is charged into capacitor C until the voltage at the first node, N1, is Vd - |Vth|, where Vd is the data voltage output from Data and Vth is the threshold voltage of the third transistor, M3.

[0172] The third stage, P3, is called the light-emitting stage. The signal on the light-emitting signal line EM is a low-level signal, and the fifth transistor M5 and the sixth transistor M6 are turned on. The power supply voltage output by the high-level power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, third transistor M3, and sixth transistor M6, driving the light-emitting device L to emit light.

[0173] During the pixel driving circuit operation, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage at the first node N1 is Vd - |Vth|, the driving current of the third transistor M3 is:

[0174] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0175] Where I is the driving current flowing through the third transistor M3, which is also the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0176] In an exemplary embodiment, the light-emitting device L may include any one of an organic light-emitting diode (OLED), a quantum dot light-emitting diode, and an inorganic light-emitting diode. For example, the light-emitting device may be a micrometer-scale light-emitting device, such as a micro light-emitting diode (Micro LED), a sub-millimeter light-emitting diode (Mini LED), or a micro organic light-emitting diode (Micro OLED), etc., and this disclosure does not limit this. For example, taking an organic light-emitting diode (OLED) as an example, the light-emitting device L may include a first electrode (e.g., as an anode), an organic light-emitting layer, and a second electrode (e.g., as a cathode) stacked together.

[0177] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be common layers connected together, and the emissive layers of adjacent sub-pixels may have a small amount of overlap or may be isolated.

[0178] In an exemplary embodiment, the gate driver includes at least one gate driving circuit. The number of gate driving circuits depends on the number of gate lines. Taking a display substrate including the pixel driving circuit shown in FIG3 as an example, the gate driving circuit includes: a first driving circuit, a second driving circuit, and a third driving circuit. The first driving circuit is electrically connected to a first scan signal line, a first reset signal line, and a second reset signal line. The second driving circuit is electrically connected to a second scan signal line. The third driving circuit is electrically connected to a light-emitting signal line.

[0179] In an exemplary embodiment, at least one driving circuit in the gate driver may include a plurality of shift registers.

[0180] Display products comprise multiple driving circuits and multiple sub-pixels. When a display product shows an image, the multiple driving circuits generate driving signals to achieve the display. The display product refreshes the screen in every frame, meaning a driving signal needs to be generated for each display frame, resulting in a high refresh rate. However, for some special screen conditions (e.g., always-on display, static images, or images with infrequent updates), driving signals are not required in at least some display frames, meaning a lower refresh rate is needed. Since multiple driving circuits in a single display product generate driving signals in every frame regardless of the displayed image, different refresh rates cannot be achieved within the same display area, leading to higher power consumption.

[0181] Therefore, this disclosure provides a display substrate and a display device.

[0182] Figure 5A is a structural schematic diagram of the display substrate provided in an embodiment of this disclosure, and Figure 5B is a connection schematic diagram of the gating sub-circuit. As shown in Figure 5A, the display substrate provided in an embodiment of this disclosure includes: a display area AA and a non-display area BB located on at least one side of the display area AA. The display area AA is provided with a plurality of sub-pixels 20. The non-display area BB is provided with a gating circuit 10, a plurality of driving circuits GOA-1 to GOA-M, and a plurality of initial signal lines STVL1 to STVLM, wherein M is greater than or equal to 1. At least one of the plurality of driving circuits includes: a plurality of shift registers, and at least one shift register includes: a driving input terminal and a driving output terminal.

[0183] In an exemplary embodiment, the drive output terminal of at least one shift register of at least one of the plurality of drive circuits is electrically connected to the plurality of sub-pixels 20. Exemplarily, the drive output terminal of at least one shift register of at least one of the plurality of drive circuits is electrically connected to at least one gate line connected to the plurality of sub-pixels 20.

[0184] In an exemplary embodiment, in a display substrate including the pixel driving circuit provided in FIG3, the plurality of driving circuits may include: a first driving circuit, a second driving circuit, and a third driving circuit.

[0185] In an exemplary embodiment, as shown in FIG5A, the gating circuit 10 is electrically connected to the drive input terminal of at least one shift register in at least one of the multiple drive circuits and multiple initial signal lines STVL1 to STVLM.

[0186] In an exemplary embodiment, as shown in FIG5B, the gating circuit includes multiple gating sub-circuits. Each gating sub-circuit is electrically connected to a first enable terminal EN1, a second enable terminal EN2, multiple initial input terminals SIN1 to SINM, multiple cascaded input terminals CIN1 to CINM, and multiple gating output terminals HOUT1 to HOUTM, respectively. It is configured to, under the control of the signals from the first enable terminal EN1 and the second enable terminal EN2, provide signals from either the initial input terminals SIN1 to SINM or the cascaded input terminals CIN1 to CINM to the multiple gating output terminals HOUT1 to HOUTM. FIG5B is illustrated using an example where the number of gating output terminals connected to the gating sub-circuit is M, the number of initial input terminals connected to the gating sub-circuit is M, and the number of cascaded input terminals connected to the gating sub-circuit is M.

[0187] This disclosure achieves different refresh rates in different areas of the display substrate by setting a gating circuit to control whether the signals to the drive input terminal of at least one shift register in at least one drive circuit are multiple initial signal lines. That is, high and low refresh rates can coexist in the same frame. Furthermore, the embodiments of this disclosure are not limited to achieving different refresh rates in a fixed area of ​​the display substrate, but can achieve dynamic refresh in any area, thereby reducing the power consumption of the display substrate.

[0188] In an exemplary embodiment, Figure 6 is a schematic diagram of the gating circuit. The gating circuit 10 includes N gating sub-circuits. At least one gating sub-circuit is connected to the m-th gating output terminal, which is electrically connected to the m-th driving circuit. For example, the first gating output terminal HOUT1 connected to at least one gating sub-circuit is electrically connected to the first driving circuit GOA-1, the second gating output terminal HOUT2 connected to at least one gating sub-circuit is electrically connected to the second driving circuit GOA-2, and so on, with the M-th gating output terminal HOUM connected to at least one gating sub-circuit being electrically connected to the M-th driving circuit GOA-M.

[0189] In an exemplary embodiment, as shown in FIG6, the m-th initial input terminal of at least one gating sub-circuit is electrically connected to the m-th initial signal line. Exemplarily, the first initial input terminal SIN1 of at least one gating sub-circuit is electrically connected to the first initial signal line STVL1, the second initial input terminal SIN2 of at least one gating sub-circuit is electrically connected to the second initial signal line STVL2, and so on. The M-th gating output terminal HOUTM of at least one gating sub-circuit is electrically connected to the M-th driving circuit GOA-M.

[0190] In an exemplary embodiment, the effective level signal of the m-th initial signal line can turn on at least one transistor in at least one shift register in the m-th drive circuit.

[0191] In an exemplary embodiment, Figure 7 is a schematic diagram of the driving circuit. As shown in Figure 7, multiple shift registers 31 located in at least one driving circuit are divided into N shift register groups 30, and multiple shift registers 31 located in the same shift register group 30 are cascaded with each other. Cascading multiple shift registers 31 located in the same shift register group 30 means that the driving input terminal of at least one shift register in the same shift register group is electrically connected to the driving output terminal of at least one shift register. Here, GOA(a,b,c) refers to the c-th shift register in the b-th shift register group of the a-th driving circuit. kn refers to the number of shift registers included in the n-th shift register group of at least one driving circuit.

[0192] In an exemplary embodiment, the number of shift registers in at least two shift register groups located in at least one drive circuit may be the same or different. This disclosure does not limit this.

[0193] In an exemplary embodiment, the number of shift registers included in the nth shift register group in different driving circuits may be the same or different, and can be determined according to the number of rows of sub-pixels connected to the different shift registers. The number of rows of sub-pixels connected to the nth shift register group in at least two of the different driving circuits is the same, which ensures normal display of the display substrate. For example, taking three driving circuits, when the shift register in at least one of the first to third driving circuits is connected to one row of sub-pixels, the number of shift registers included in the nth shift register group in the different driving circuits is the same. When the shift register in the first driving circuit is connected to two rows of sub-pixels, and the shift registers in the second and third driving circuits are connected to one row of sub-pixels, the number of shift registers included in at least one shift register group in the first driving circuit is half the number of shift registers included in at least one shift register group in the second and third driving circuits. This disclosure does not impose any limitations on this.

[0194] In an exemplary embodiment, the number of shift register areas in at least one shift register group in at least one driving circuit can be 8, 12, 16 or 20, and this disclosure does not limit this in any way.

[0195] In an exemplary embodiment, Figure 8 is a schematic diagram of the connection between the gating circuit and one of the driving circuits, and Figure 8 is a schematic diagram of the connection between the gating circuit and the m-th driving circuit. As shown in Figure 8, the m-th gating output terminal HOUTm of the n-th gating sub-circuit 11 is electrically connected to the driving input terminal of the first shift register GOA(m,n,1) in the n-th shift register group of the m-th driving circuit, where 1≤m≤M and 1≤n≤N. Exemplarily, the m-th gating output terminal HOUTm of the first gating sub-circuit 11 is electrically connected to the driving input terminal of the first shift register GOA(m,1,1) in the first shift register group of the m-th driving circuit, the m-th gating output terminal HOUTm of the second gating sub-circuit 11 is electrically connected to the driving input terminal of the first shift register GOA(m,2,1) in the second shift register group of the m-th driving circuit, and so on.

[0196] In an exemplary embodiment, as shown in FIG8, at least one gating sub-circuit is electrically connected to a first power supply terminal VGH and a second power supply terminal VGL. The signal at the first power supply terminal VGH is a constant voltage signal and is a high-level signal, while the signal at the second power supply terminal VGL is a constant voltage signal and is a low-level signal.

[0197] In an exemplary embodiment, as shown in FIG8, the m-th cascaded input terminal CINm connected to the first gating sub-circuit 11 is electrically connected to the m-th target power line VLm. The signal of the m-th target power line VLm is a constant voltage signal, and the voltage value is equal to the voltage value of the invalid level signal of the m-th initial signal line STVLm.

[0198] In an exemplary embodiment, when the invalid level signal of the m-th initial signal line STVLm is a high level signal, the signal of the m-th target power line VLm is also a high level signal. The signal of the m-th target power line VLm can be the same as the signal at the first power supply terminal. Here, an invalid level signal on a signal line refers to a signal that disconnects the transistor connected to the control electrode from the signal line.

[0199] In an exemplary embodiment, when the invalid level signal of the m-th initial signal line STVLm is a low level signal, the signal of the m-th target power line VLm is a low level signal, and the signal of the m-th target power line VLm can be the same as the signal of the second power terminal.

[0200] For example, taking a display substrate including the pixel driving circuit shown in FIG3 as an example, the first driving circuit is a first driving circuit, the second driving circuit is a second driving circuit, and the third driving circuit is a third driving circuit. The first driving circuit is electrically connected to the first scan signal line, the first reset signal line, and the second reset signal line of the pixel driving circuit of at least one sub-pixel. The second driving circuit is electrically connected to the second scan signal line. The third driving circuit is electrically connected to the light emission signal line. At this time, the first cascaded input terminal connected to the first gating sub-circuit is electrically connected to the first target power line, and the signal of the first target power line is a high-level signal. The second cascaded input terminal connected to the first gating sub-circuit is electrically connected to the second target power line, and the signal of the second target power line is a low-level signal. The third cascaded input terminal connected to the first gating sub-circuit is electrically connected to the third target power line, and the signal of the third target power line is a high-level signal.

[0201] In an exemplary embodiment, as shown in FIG8, the m-th cascaded input terminal connected to the k-th gating sub-circuit is electrically connected to the drive output terminal of the last shift register in the (k-1)-th shift register group of the m-th driver circuit, where 2≤k≤N. Exemplarily, the m-th cascaded input terminal CINm connected to the second gating sub-circuit is electrically connected to the drive input terminal of the last shift register GOA(m,1,k1) in the first shift register group of the m-th driver circuit, and the m-th cascaded input terminal CINm connected to the third gating sub-circuit is electrically connected to the drive input terminal of the last shift register GOA(m,2,k2) in the second shift register group of the m-th driver circuit, and so on.

[0202] Figure 9 is a schematic diagram of the gating sub-circuit. In an exemplary embodiment, at least one gating sub-circuit includes: a first node control sub-circuit, a second node control sub-circuit, a first output sub-circuit, and a second output sub-circuit.

[0203] In an exemplary embodiment, as shown in FIG9, the first node control sub-circuit is electrically connected to the gating input terminal HIN, the first enable terminal EN1, the gating reset signal terminal HRST, the first power supply terminal VGH, the second power supply terminal VGL, the gating clock terminal HCK, and the first node N1, respectively. It is configured to provide a signal from one of the signal terminals of the first enable terminal EN1, the first power supply terminal VGH, and the second power supply terminal VGL to the first node N1 under the control of the gating input terminal HIN, the gating clock terminal HCK, and the gating reset signal terminal HRST.

[0204] In an exemplary embodiment, as shown in FIG9, the second node control sub-circuit is electrically connected to the gating input terminal HIN, the second enable terminal EN2, the gating reset signal terminal HRST, the first power supply terminal VGH, the second power supply terminal VGL, the gating clock terminal HCK, and the second node N2, respectively, and is configured to provide a signal from one of the signal terminals of the second enable terminal EN2, the first power supply terminal VGH, and the second power supply terminal VGL to the second node N2 under the control of the gating input terminal HIN, the gating clock terminal HCK, and the gating reset signal terminal HRST.

[0205] In an exemplary embodiment, as shown in FIG9, the first output sub-circuit is electrically connected to the first node N1, the M initial input terminals SIN1 to SINM and the M gating output terminals HOUT1 to HOUTM respectively, and is configured to provide the signals of the M initial input terminals SIN1 to SINM to the M gating output terminals HOUT1 to HOUTM under the control of the signal of the first node N1.

[0206] In an exemplary embodiment, as shown in FIG9, the second output sub-circuit is electrically connected to the second node N2, the M cascaded input terminals CIN1 to CINM and the M gating output terminals HOUT1 to HOUTM respectively, and is configured to provide the signals of the M cascaded input terminals CIN1 to CINM to the M gating output terminals HOUT1 to HOUTM under the control of the signal of the second node N2.

[0207] In an exemplary embodiment, FIG10 is a schematic diagram of the structure of a gating sub-circuit provided in an exemplary embodiment. As shown in FIG10, the first node control sub-circuit includes: a first write sub-circuit, a second write sub-circuit, a third write sub-circuit, and a first gating reset sub-circuit.

[0208] In an exemplary embodiment, as shown in FIG10, the first write sub-circuit is electrically connected to the gating input terminal HIN, the first enable terminal EN1, the second power supply terminal VGL, the gating clock terminal HCK, the first node N1, the third node N3, the fourth node N4, the fifth node N5, and the sixth node N6, respectively. It is configured to provide the signal of the first enable terminal EN1 to the first node N1, the third node N3, the fourth node N4, and the fifth node N5 under the control of the signal of the gating input terminal HIN and the second power supply terminal VGL, and to provide the signal of the gating clock terminal HCK to the sixth node N6 under the control of the signal of the fifth node N5, and to store the voltage difference between the signals of the fifth node N5 and the sixth node N6.

[0209] In an exemplary embodiment, as shown in FIG10, the second write sub-circuit is electrically connected to the gating clock terminal HCK, the second power supply terminal VGL, the first node N1 and the third node N3, respectively, and is configured to provide the signal of the second power supply terminal VGL to the third node N3 under the control of the signals of the gating clock terminal HCK and the first node N1.

[0210] In an exemplary embodiment, as shown in FIG10, the third write sub-circuit is electrically connected to the gating clock terminal HCK, the first power supply terminal VGH, the third node N3 and the seventh node N7, respectively. It is configured to provide the signal of the first power supply terminal VGH to the other node of the third node N3 and the seventh node N7 under the control of the signal of one of the nodes of the third node N3 and the seventh node N7, and to store the voltage difference between the signal of the seventh node N7 and the signal of the gating clock terminal HCK.

[0211] In an exemplary embodiment, as shown in FIG10, the first gating reset sub-circuit is electrically connected to the gating reset signal terminal HRST, the first power supply terminal VGH, the third node N3 and the fourth node N4 respectively, and is configured to provide the first power supply terminal VGH signal to the third node N3 and the fourth node N4 under the control of the signal of the gating reset signal terminal HRST.

[0212] In an exemplary embodiment, FIG10 is a schematic diagram of the structure of the second node control sub-circuit. As shown in FIG10, the second node control sub-circuit includes: a fourth write sub-circuit, a fifth write sub-circuit, a sixth write sub-circuit, and a second gating reset sub-circuit.

[0213] In an exemplary embodiment, as shown in FIG10, the fourth write sub-circuit is electrically connected to the gating input terminal HIN, the second enable terminal EN2, the second power supply terminal VGL, the gating clock terminal HCK, the second node N2, the ninth node N9, the tenth node N10, the eleventh node N11, and the twelfth node N12, respectively. It is configured to provide the signal of the second enable terminal EN2 to the second node N2, the ninth node N9, the tenth node N10, and the eleventh node N11 under the control of the signal of the gating input terminal HIN and the second power supply terminal VGL, and to provide the signal of the gating clock terminal HCK to the twelfth node N12 under the control of the signal of the eleventh node N11, and to store the voltage difference between the signals of the eleventh node N11 and the twelfth node N12.

[0214] In an exemplary embodiment, as shown in FIG10, the fifth write sub-circuit is electrically connected to the gating clock terminal HCK, the second power supply terminal VGL, the second node N2 and the ninth node N9, respectively, and is configured to provide the signal of the second power supply terminal VGL to the ninth node N9 under the control of the signals of the gating clock terminal HCK and the second node N2.

[0215] In an exemplary embodiment, as shown in FIG10, the sixth write sub-circuit is electrically connected to the gating clock terminal HCK, the first power supply terminal VGH, the ninth node N9, and the thirteenth node N13, respectively. It is configured to provide the signal of the first power supply terminal VGH to the other node of the ninth node N9 and the thirteenth node N13 under the control of the signal of one of the nodes N9 and N13, and to store the voltage difference between the signal of the thirteenth node N13 and the signal of the gating clock terminal HCK.

[0216] In an exemplary embodiment, as shown in FIG10, the second gating reset sub-circuit is electrically connected to the gating reset signal terminal HRST, the second power supply terminal VGL, the ninth node N9, and the tenth node N10, respectively, and is configured to provide the signal of the second power supply terminal VGL to the ninth node N9 and the tenth node N10 under the control of the signal of the gating reset signal terminal HRST.

[0217] Figure 11 is an equivalent circuit diagram of the first node control sub-circuit. In an exemplary embodiment, as shown in Figure 11, the first write sub-circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a first capacitor C1. Specifically, the control electrode of the first transistor T1 is electrically connected to the gating input terminal HIN, the first electrode of the first transistor T1 is electrically connected to the first enable terminal EN1, and the second electrode of the first transistor T1 is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the gating input terminal HIN, the first electrode of the second transistor T2 is electrically connected to the first enable terminal EN1, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the second power supply terminal VGL, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the first node N1; the fourth transistor T4... The control electrode is electrically connected to the second power supply terminal VGL; the first electrode of the fourth transistor T4 is electrically connected to the fourth node N4; the second electrode of the fourth transistor T4 is electrically connected to the fifth node N5; the control electrode and the first electrode of the fifth transistor T5 are electrically connected to the fifth node N5; the second electrode of the fifth transistor T5 is electrically connected to the first node N1; the control electrode of the sixth transistor T6 is electrically connected to the fifth node N5; the first electrode of the sixth transistor T6 is electrically connected to the sixth node N6; the second electrode of the sixth transistor T6 is electrically connected to the gating clock terminal HCK; the first terminal of the first capacitor C1 is electrically connected to the fifth node N5; the second terminal of the first capacitor C1 is electrically connected to the sixth node N6.

[0218] The setting of the first capacitor C1 in this disclosure can ensure the stability of the first node, the third node, the fourth node and the fifth node, and can improve the reliability of the gating sub-circuit.

[0219] In an exemplary embodiment, as shown in FIG11, the second write sub-circuit includes a seventh transistor T7 and an eighth transistor T8. The control electrode of the seventh transistor T7 is electrically connected to the gating clock terminal HCK, the first electrode of the seventh transistor T7 is electrically connected to the second power supply terminal VGL, and the second electrode of the seventh transistor T7 is electrically connected to the eighth node N8. The control electrode of the eighth transistor T8 is electrically connected to the first node N1, the first electrode of the eighth transistor T8 is electrically connected to the eighth node N8, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3.

[0220] In an exemplary embodiment, as shown in FIG11, the third write sub-circuit includes: a ninth transistor T9, a tenth transistor T10, and a second capacitor C2. The control electrode of the ninth transistor T9 is electrically connected to the seventh node N7, the first electrode of the ninth transistor T9 is electrically connected to the third node N3, and the second electrode of the ninth transistor T9 is electrically connected to the first power supply terminal VGH. The control electrode of the tenth transistor T10 is electrically connected to the third node N3, the first electrode of the tenth transistor T10 is electrically connected to the first power supply terminal VGH, and the second electrode of the tenth transistor T10 is electrically connected to the seventh node N7. The first terminal of the second capacitor C2 is electrically connected to the gating clock terminal HCK, and the second terminal of the second capacitor C2 is electrically connected to the seventh node N7.

[0221] The placement of the second capacitor C2 in this disclosure can ensure the stability of the seventh node and improve the reliability of the gating sub-circuit.

[0222] In an exemplary embodiment, as shown in FIG11, the first gating and reset sub-circuit includes an eleventh transistor T11 and a twelfth transistor T12. The control electrode of the eleventh transistor T11 is electrically connected to the gating and reset signal terminal HRST, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the third node N3. The control electrode of the twelfth transistor T12 is electrically connected to the gating and reset signal terminal HRST, the first electrode of the twelfth transistor T12 is electrically connected to the first power supply terminal VGH, and the second electrode of the twelfth transistor T12 is electrically connected to the fourth node N4.

[0223] Figure 12 is an equivalent circuit diagram of the second node control sub-circuit. In an exemplary embodiment, as shown in Figure 12, the fourth write sub-circuit includes: a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a third capacitor C3. Specifically, the control electrode of the thirteenth transistor T13 is electrically connected to the gating input terminal HIN, the first electrode of the thirteenth transistor T13 is electrically connected to the second enable terminal EN2, and the second electrode of the thirteenth transistor T13 is electrically connected to the ninth node N9; the control electrode of the fourteenth transistor T14 is electrically connected to the gating input terminal HIN, the first electrode of the fourteenth transistor T14 is electrically connected to the second enable terminal EN2, and the second electrode of the fourteenth transistor T14 is electrically connected to the tenth node N10; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, the first electrode of the fifteenth transistor T15 is electrically connected to the ninth node N9, and the second electrode of the fifteenth transistor T15 is electrically connected to the second node N2; the control electrode of the sixteenth transistor T16... The first terminal of the sixteenth transistor T16 is electrically connected to the tenth node N10, and the second terminal of the sixteenth transistor T16 is electrically connected to the eleventh node N11. The control terminal and the first terminal of the seventeenth transistor T17 are electrically connected to the eleventh node N11, and the second terminal of the seventeenth transistor T17 is electrically connected to the second node N2. The control terminal of the eighteenth transistor T18 is electrically connected to the eleventh node N11, the first terminal of the eighteenth transistor T18 is electrically connected to the twelfth node N12, and the second terminal of the eighteenth transistor T18 is electrically connected to the gating clock terminal HCK. The first terminal of the third capacitor C3 is electrically connected to the eleventh node N11, and the second terminal of the third capacitor C3 is electrically connected to the twelfth node N12.

[0224] The placement of the third capacitor C3 in this disclosure can ensure the stability of the second, ninth, tenth, and eleventh nodes, and improve the reliability of the gating sub-circuit.

[0225] In an exemplary embodiment, as shown in FIG12, the fifth write sub-circuit includes: a nineteenth transistor T19 and a twentieth transistor T20. The control electrode of the nineteenth transistor T19 is electrically connected to the gating clock terminal HCK, the first electrode of the nineteenth transistor T19 is electrically connected to the second power supply terminal VGL, and the second electrode of the nineteenth transistor T19 is electrically connected to the fourteenth node N14. The control electrode of the twentieth transistor T20 is electrically connected to the second node N2, the first electrode of the twentieth transistor T20 is electrically connected to the fourteenth node N14, and the second electrode of the twentieth transistor T20 is electrically connected to the ninth node N9.

[0226] In an exemplary embodiment, as shown in FIG12, the sixth write sub-circuit includes: a twenty-first transistor T21, a twenty-second transistor T22, and a fourth capacitor C4. The control electrode of the twenty-first transistor T21 is electrically connected to the thirteenth node N13, the first electrode of the twenty-first transistor T21 is electrically connected to the ninth node N9, and the second electrode of the twenty-first transistor T21 is electrically connected to the first power supply terminal VGH; the control electrode of the twenty-second transistor T22 is electrically connected to the ninth node N9, the first electrode of the twenty-second transistor T22 is electrically connected to the first power supply terminal VGH, and the second electrode of the twenty-second transistor T22 is electrically connected to the thirteenth node N13; the first terminal of the fourth capacitor C4 is electrically connected to the gating clock terminal HCK, and the second terminal of the fourth capacitor C4 is electrically connected to the thirteenth node N13.

[0227] In an exemplary embodiment, as shown in FIG12, the second gating reset sub-circuit includes: a twenty-third transistor T23 and a twenty-fourth transistor T24. The control electrode of the twenty-third transistor T23 is electrically connected to the gating reset signal terminal HRST, the first electrode of the twenty-third transistor T23 is electrically connected to the second power supply terminal VGL, and the second electrode of the twenty-third transistor T23 is electrically connected to the ninth node N9. Similarly, the control electrode of the twenty-fourth transistor T24 is electrically connected to the gating reset signal terminal HRST, the first electrode of the twenty-fourth transistor T24 is electrically connected to the second power supply terminal VGL, and the second electrode of the twenty-fourth transistor T24 is electrically connected to the tenth node N10.

[0228] In an exemplary embodiment, FIG13 is an equivalent circuit diagram of the first output sub-circuit. As shown in FIG13, the first output sub-circuit includes M initial output transistors ST1 to STM. Among them, the control electrode of the m-th initial output transistor STm is electrically connected to the first node N1, the first electrode of the m-th initial output transistor STm is electrically connected to the m-th initial input terminal SINm, and the second electrode of the m-th initial output transistor STm is electrically connected to the m-th gating output terminal HOUTm. For example, the control electrode of the first initial output transistor ST1 is electrically connected to the first node N1, the first electrode of the first initial output transistor ST1 is electrically connected to the first initial input terminal SIN1, the second electrode of the first initial output transistor ST1 is electrically connected to the first gating output terminal HOUT1, the control electrode of the second initial output transistor ST2 is electrically connected to the first node N1, the first electrode of the second initial output transistor ST2 is electrically connected to the second initial input terminal SIN2, the second electrode of the second initial output transistor ST2 is electrically connected to the second gating output terminal HOUT2, and so on, until the control electrode of the Mth initial output transistor STM is electrically connected to the first node N1, the first electrode of the Mth initial output transistor STM is electrically connected to the Mth initial input terminal SINM, and the second electrode of the Mth initial output transistor STM is electrically connected to the Mth gating output terminal HOUTM.

[0229] In an exemplary embodiment, Figure 14 is an equivalent circuit diagram of the second output sub-circuit. As shown in Figure 14, the second output sub-circuit includes M cascaded output transistors CT1 to CTM. The control terminal of the m-th cascaded output transistor CTm is electrically connected to the second node N2, the first terminal of the m-th cascaded output transistor CTm is electrically connected to the m-th cascaded input terminal CINm, and the second terminal of the m-th cascaded output transistor CTm is electrically connected to the m-th gating output terminal HOUTm. For example, the control electrode of the first cascaded output transistor CT1 is electrically connected to the first node N1, the first electrode of the first cascaded output transistor CT1 is electrically connected to the first cascaded input terminal CIN1, the second electrode of the first cascaded output transistor CT1 is electrically connected to the first gating output terminal HOUT1, the control electrode of the second cascaded output transistor CT2 is electrically connected to the first node N1, the first electrode of the second cascaded output transistor CT2 is electrically connected to the second cascaded input terminal CIN2, the second electrode of the second cascaded output transistor CT2 is electrically connected to the second gating output terminal HOUT2, and so on, until the control electrode of the Mth cascaded output transistor CTM is electrically connected to the first node N1, the first electrode of the Mth cascaded output transistor CTM is electrically connected to the Mth cascaded input terminal CINM, and the second electrode of the Mth cascaded output transistor CTM is electrically connected to the Mth gating output terminal HOUTM.

[0230] In an exemplary embodiment, FIG15 is an equivalent circuit diagram of the gating sub-circuit. As shown in FIG15, in at least one gating sub-circuit, the first node control sub-circuit includes: the first transistor T1 to the twelfth transistor T12, the first capacitor C1 and the second capacitor C2; the second node control sub-circuit includes: the thirteenth transistor T13 and the twenty-fourth transistor T24, the third capacitor C3 and the fourth capacitor C4; the first output sub-circuit includes: M initial output transistors ST1 to STM; and the second output sub-circuit includes: M cascaded output transistors CT1 to CTM. Specifically, the control electrode of the first transistor T1 is electrically connected to the gating input terminal HIN, the first electrode of the first transistor T1 is electrically connected to the first enable terminal EN1, and the second electrode of the first transistor T1 is electrically connected to the third node N3; the control electrode of the second transistor T2 is electrically connected to the gating input terminal HIN, the first electrode of the second transistor T2 is electrically connected to the first enable terminal EN1, and the second electrode of the second transistor T2 is electrically connected to the fourth node N4; the control electrode of the third transistor T3 is electrically connected to the second power supply terminal VGL, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the first node N1; the control electrode of the fourth transistor T4 is electrically connected to the second power supply terminal VGL, the first electrode of the fourth transistor T4 is electrically connected to the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected to the fifth node N5; the control electrode and the first electrode of the fifth transistor T5 are respectively electrically connected to the fifth node N5, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1; the control electrode of the sixth transistor T6 is electrically connected to the fifth node N5, the first electrode of the sixth transistor T6 is electrically connected to the sixth node N6, and the sixth… The second terminal of transistor T6 is electrically connected to the gating clock terminal HCK; the control terminal of the seventh transistor T7 is electrically connected to the gating clock terminal HCK, the first terminal of the seventh transistor T7 is electrically connected to the second power supply terminal VGL, and the second terminal of the seventh transistor T7 is electrically connected to the eighth node N8; the control terminal of the eighth transistor T8 is electrically connected to the first node N1, the first terminal of the eighth transistor T8 is electrically connected to the eighth node N8, and the second terminal of the eighth transistor T8 is electrically connected to the third node N3; the control terminal of the ninth transistor T9 is electrically connected to the seventh node N7, the first terminal of the ninth transistor T9 is electrically connected to the third node N3, and the second terminal of the ninth transistor T9 is electrically connected to the first power supply terminal VGH; the control terminal of the tenth transistor T10 is electrically connected to the third node N3, the first terminal of the tenth transistor T10 is electrically connected to the first power supply terminal VGH, and the second terminal of the tenth transistor T10 is electrically connected to the seventh node N7; the control terminal of the eleventh transistor T11 is electrically connected to the gating reset signal terminal HRST, the first terminal of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second terminal of the eleventh transistor T11 is electrically connected to the third node N3.The control terminal of the twelfth transistor T12 is electrically connected to the strobe reset signal terminal HRST, the first terminal of the twelfth transistor T12 is electrically connected to the first power supply terminal VGH, and the second terminal of the twelfth transistor T12 is electrically connected to the fourth node N4; the control terminal of the thirteenth transistor T13 is electrically connected to the strobe input terminal HIN, the first terminal of the thirteenth transistor T13 is electrically connected to the second enable terminal EN2, and the second terminal of the thirteenth transistor T13 is electrically connected to the ninth node N9; the control terminal of the fourteenth transistor T14 is electrically connected to the strobe input terminal HIN, the first terminal of the fourteenth transistor T14 is electrically connected to the second enable terminal EN2, and the second terminal of the fourteenth transistor T14 is electrically connected to the tenth node N10; the control terminal of the fifteenth transistor T15 is electrically connected to the second… The power supply terminal VGL is electrically connected. The first terminal of the fifteenth transistor T15 is electrically connected to the ninth node N9, and the second terminal of the fifteenth transistor T15 is electrically connected to the second node N2. The control terminal of the sixteenth transistor T16 is electrically connected to the second power supply terminal VGL. The first terminal of the sixteenth transistor T16 is electrically connected to the tenth node N10, and the second terminal of the sixteenth transistor T16 is electrically connected to the eleventh node N11. The control terminal and the first terminal of the seventeenth transistor T17 are both electrically connected to the eleventh node N11, and the second terminal of the seventeenth transistor T17 is electrically connected to the second node N2. The control terminal of the eighteenth transistor T18 is electrically connected to the eleventh node N11, and the first terminal of the eighteenth transistor T18 is electrically connected to the twelfth node N12. The second terminal of transistor T18 is electrically connected to the gating clock terminal HCK; the control terminal of the nineteenth transistor T19 is electrically connected to the gating clock terminal HCK, the first terminal of the nineteenth transistor T19 is electrically connected to the second power supply terminal VGL, and the second terminal of the nineteenth transistor T19 is electrically connected to the fourteenth node N14; the control terminal of the twentieth transistor T20 is electrically connected to the second node N2, the first terminal of the twentieth transistor T20 is electrically connected to the fourteenth node N14, and the second terminal of the twentieth transistor T20 is electrically connected to the ninth node N9; the control terminal of the twenty-first transistor T21 is electrically connected to the thirteenth node N13, the first terminal of the twenty-first transistor T21 is electrically connected to the ninth node N9, and the second terminal of the twenty-first transistor T21 is electrically connected to the first power supply terminal VGH. Electrical connections: The control electrode of the twenty-second transistor T22 is electrically connected to the ninth node N9; the first electrode of the twenty-second transistor T22 is electrically connected to the first power supply terminal VGH; and the second electrode of the twenty-second transistor T22 is electrically connected to the thirteenth node N13. The control electrode of the twenty-third transistor T23 is electrically connected to the gating and reset signal terminal HRST; the first electrode of the twenty-third transistor T23 is electrically connected to the second power supply terminal VGL; and the second electrode of the twenty-fourth transistor T24 is electrically connected to the gating and reset signal terminal HRST; the first electrode of the twenty-fourth transistor T24 is electrically connected to the second power supply terminal VGL; and the second electrode of the twenty-fourth transistor T24 is electrically connected to the tenth node N10.The control terminal of the m-th initial output transistor ST is electrically connected to the first node N1. The first terminal of the m-th initial output transistor STm is electrically connected to the m-th initial input terminal SINm. The second terminal of the m-th initial output transistor STm is electrically connected to the m-th gating output terminal HOUTm. The control terminal of the m-th cascaded output transistor CTm is electrically connected to the second node N2. The first terminal of the m-th cascaded output transistor CTm is electrically connected to the m-th cascaded input terminal CINm. The second terminal of the m-th cascaded output transistor CTm is electrically connected to the m-th gating output terminal HOUTm. OUTm is electrically connected; the first terminal of the first capacitor C1 is electrically connected to the fifth node N5, and the second terminal of the first capacitor C1 is electrically connected to the sixth node N6; the first terminal of the second capacitor C2 is electrically connected to the gating clock terminal HCK, and the second terminal of the second capacitor C2 is electrically connected to the seventh node N7; the first terminal of the third capacitor C3 is electrically connected to the eleventh node N11, and the second terminal of the third capacitor C3 is electrically connected to the twelfth node N12; the first terminal of the fourth capacitor C4 is electrically connected to the gating clock terminal HCK, and the second terminal of the fourth capacitor C4 is electrically connected to the thirteenth node N13.

[0231] In an exemplary embodiment, any one of the first capacitors C1 to the fourth capacitor C4 can be a capacitor device manufactured through a process, for example, by fabricating dedicated capacitor electrodes. Multiple capacitor electrodes can be implemented using metal layers, semiconductor layers (e.g., doped polysilicon), etc. Alternatively, any one of the first capacitors C1 to the fourth capacitor C4 can be a parasitic capacitance between multiple devices, implemented using the transistor itself and other devices or circuits. The connection method of any one of the first capacitors C1 to the fourth capacitor C4 includes, but is not limited to, the methods described above; other applicable connection methods can be used, as long as the level of the corresponding node is stored. Here, the exemplary embodiments of this disclosure do not limit this.

[0232] In an exemplary embodiment, transistors can be categorized into N-type transistors and P-type transistors based on their characteristics. When a transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage). When a transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).

[0233] In an exemplary embodiment, the first transistor T1 to the twenty-fourth transistor T24, the M initial output transistors, and the M cascaded output transistors are all P-type transistors.

[0234] In an exemplary embodiment, the signal used to select the clock terminal HCK is a square wave signal that repeats between high and low voltages. Exemplarily,

[0235] In an exemplary embodiment, the content displayed on the display substrate includes multiple display frames. In at least one display frame, the signal at the strobe reset signal terminal HRST is an invalid level signal, and the eleventh transistor T11, the twelfth transistor T12, the twenty-third transistor T23, and the twenty-fourth transistor T24 are turned off. The signal at the first power supply terminal VGH does not affect the signal at the first node N1, and the signal at the second power supply terminal VGL does not affect the signal at the second node N2. Between at least two display frames, the signal at the strobe reset signal terminal HRST is an valid level signal (i.e., a low level signal), and the eleventh transistor T11, the twelfth transistor T12, the twenty-third transistor T23, and the twenty-fourth transistor T24 are turned on. The signal at the first power supply terminal VGH is written to the first node N1, all M initial output transistors are turned off, the signal at the mth initial input terminal cannot be written to the mth strobe output terminal, the signal at the second power supply terminal VGL is written to the second node N2, all M cascaded output transistors are turned off, and the signal at the mth cascaded input terminal is written to the mth strobe output terminal.

[0236] In an exemplary implementation, since the m-th cascaded input CINm of the first gating sub-circuit is electrically connected to the m-th target power line VLm, and the m-th cascaded input of the k-th gating sub-circuit is electrically connected to the drive output of the last shift register in the (k-1)-th shift register group of the m-th drive circuit, all shift registers in the m-th drive circuit are cascaded between at least two display frames, and an invalid level signal is written to the drive input of the first shift register. At this time, the m-th drive circuit has no output.

[0237] In an exemplary embodiment, the signals of the first enable terminal EN1 and the second enable terminal EN2 are inverted signals. This inversion of signals allows the m-th gating output terminal in at least one gating sub-circuit to output one of the signals from the m-th initial input terminal and the m-th cascaded input terminal. Taking the n-th gating sub-circuit as an example, when the m-th gating output terminal of the n-th gating sub-circuit outputs the signal from the m-th initial input terminal, the first shift register in the n-th shift register group of the m-th driving circuit connected to the n-th gating sub-circuit is not cascaded with the last shift register in the (n-1)-th shift register group of the m-th driving circuit. This allows the regions containing the sub-pixels connected to the n-th shift register group of the m-th driving circuit and the regions containing the sub-pixels connected to the (n-1)-th shift register group of the m-th driving circuit to achieve different refresh rates. When the m-th gating output of the n-th gating sub-circuit outputs the signal of the m-th cascaded input, the first shift register in the n-th shift register group of the m-th driving circuit connected to the gating sub-circuit and the last shift register in the (n-1)-th shift register group of the m-th driving circuit are cascaded together, so that the area where the sub-pixel connected to the n-th shift register group of the m-th driving circuit is located has the same refresh rate as the area where the sub-pixel connected to the (n-1)-th shift register group of the m-th driving circuit is located.

[0238] In an exemplary embodiment, the signal at the gating input terminal HIN and the signal at the gating clock terminal HCK in at least one gating sub-circuit can be inverse signals for a portion of the time period.

[0239] In an exemplary embodiment, in at least one gating sub-circuit, since the signal at the second power supply terminal VGL is a low-level signal, the third transistor T3, the fourth transistor T4, the fifteenth transistor T15, and the sixteenth transistor T16 are continuously turned on. When the third transistor T3 is turned on, the first node N1 and the third node N3 are connected; when the fourth transistor T4 is turned on, the fourth node N4 and the fifth node N5 are connected; when the fifteenth transistor T15 is turned on, the second node N2 and the ninth node N9 are connected; when the sixteenth transistor T16 is turned on, the tenth node N10 and the eleventh node N11 are turned on.

[0240] Figure 16 is a driving timing diagram of the gating sub-circuit provided in Figure 15. Figure 16 illustrates the example of at least one gating sub-circuit outputting signals from multiple initial input terminals. Since the signals from the multiple initial input terminals and the multiple cascaded input terminals depend on the partitioning of the display substrate and are not fixed, and the signals from the gating output terminals are distinct from those from the multiple initial input terminals and the multiple cascaded input terminals, the signal timing of the multiple initial input terminals, the multiple cascaded input terminals, and the multiple gating output terminals is not shown in Figure 16. In Figure 16, VL represents the voltage value of the low-level signal of the first enable terminal EN1, and VH represents the voltage value of the high-level signal of the second enable terminal EN2.

[0241] In at least one display frame, referring to Figure 16, the operation of the gating sub-circuit provided in Figure 15 may include:

[0242] In the first stage S11, the early write stage, the signals of the first enable terminal EN1 and the strobe input terminal HIN are low-level signals, and the signals of the second enable terminal EN2 and the strobe clock terminal HCK are high-level signals. The first transistor T1, the second transistor T2, the thirteenth transistor T13, and the fourteenth transistor T14 are turned on, while the seventh transistor T7 and the nineteenth transistor T19 are turned off.

[0243] The first transistor T1 and the second transistor T2 are turned on. The low-level signal of the first enable terminal EN1 is written to the third node N3 and the fourth node N4. Since the third transistor T3 is turned on, the signal of the third node N3 is written to the first node N1. Since the fourth transistor T4 is turned on, the signal of the fourth node N4 is written to the fifth node N5. The signals of the first node N1, the third node N3, the fourth node N4, and the fifth node N5 are low-level signals. The fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10, and multiple initial output transistors ST1 to STM are turned on. With multiple initial output transistors ST1 to STM turned on, the signal of the m-th initial input terminal SINm is written to the m-th gating output terminal HOUTm. The tenth transistor T10 is turned on, and the high-level signal of the first power supply terminal VGH is written to the seventh node N7. The voltage difference between the high-level signal of the gating clock terminal HCK stored in the second capacitor C2 and the high-level signal of the seventh node N7 causes the ninth transistor T9 to turn off, and the high-level signal of the first power supply terminal VGH cannot be written to the third node N3. When the sixth transistor T6 is turned on, the high-level signal of the select clock terminal HCK is written to the sixth node N6. The first capacitor C1 stores the voltage difference between the high-level signal of the sixth node N6 and the high-level signal of the fifth node N5.

[0244] The thirteenth transistor T13 and the fourteenth transistor T14 are turned on, and the high-level signal of the second enable terminal EN2 is written to the ninth node N9 and the tenth node N10. Since the fifteenth transistor T15 is turned on, the signal of the ninth node N9 is written to the second node N2. Since the sixteenth transistor T16 is turned on, the signal of the tenth node N10 is written to the eleventh node N11. The signals of the second node N2, the ninth node N9, the tenth node N10 and the eleventh node N11 are high-level signals. The seventeenth transistor T17, the eighteenth transistor T18, the twentieth transistor T20, the twenty-second transistor T22 and multiple cascaded output transistors CT1 to CTM are disconnected. The signal of the mth cascaded input terminal CINm cannot be written to the mth strobe output terminal HOUTm.

[0245] In the second stage, S12, the output stage, the signals of the first enable terminal EN1 and the strobe clock terminal HCK are low-level signals, and the signals of the second enable terminal EN2 and the strobe input terminal HIN are high-level signals. The first transistor T1, the second transistor T2, the thirteenth transistor T13, and the fourteenth transistor T14 are turned off, while the seventh transistor T7 and the nineteenth transistor T19 are turned on.

[0246] The eighth transistor T8 is continuously turned on. The low-level signal of the second power supply terminal VGL is written to the third node N3 through the turned-on seventh transistor T7 and the eighth transistor T8. Since the third transistor T3 is turned on, the signal of the third node N3 is written to the first node N1. The first node N1 and the third node N3 are continuously pulled low. The sixth transistor T6 is continuously turned on. The low-level signal of the gating clock terminal HCK is written to the sixth node N6. Under the action of the first capacitor C1, the signal of the fifth node N5 is continuously pulled low. Since the fourth transistor T4 is turned on, the fourth node N4 and the fifth node N5 are connected. Therefore, the signal of the fourth node N4 is continuously pulled low. The fifth transistor T5 is turned on. The low-level signal of the fifth node N5 is written to the first node N1. Multiple initial output transistors ST1 to STM are turned on. The signal of the m-th initial input terminal SINm is written to the m-th gating output terminal HOUTm. When the tenth transistor T10 is turned on, the high-level signal of the first power supply terminal VGH is written to the seventh node N7. When the ninth transistor T9 is turned off, the high-level signal of the first power supply terminal VGH cannot be written to the third node N3, which allows the third node N3 to maintain a low-level signal.

[0247] Since the absolute value of the voltage of the first node N1 in this stage is greater than the voltage of the first node N1 in the first stage, the conduction degree of the multiple initial output transistors ST1 to STM in this stage is greater than that of the multiple initial output transistors ST1 to STM in the first stage, and all the multiple initial output transistors ST1 to STM in this stage are turned on.

[0248] The 22nd transistor T22 remains off, causing the signal at the clock input HCK to change from a high level in the previous stage to a low level in this stage. Under the influence of the fourth capacitor C4, the signal at the 13th node N13 becomes low, and the 21st transistor T21 turns on. The high-level signal at the first power supply terminal VGH is written to the 9th node N9. Since the 15th transistor T15 is on, the signal at the 9th node N9 is written to the 2nd node N2. The signals at the 2nd node N2 and the 9th node N9 are both high-level signals. The 20th transistor T20, the 22nd transistor T22, and multiple cascaded output transistors CT1 to CTM are disconnected. The 19th transistor T19 turns on, causing the low-level signal at the second power supply terminal VGL to be written to the 14th node N14. Since the 20th transistor T20 is off, the signal at the 14th node N14 cannot be written to the 2nd node N2 and the 9th node N9. In this stage, the signals at the 2nd node N2 and the 9th node N9 remain high-level signals. The multiple cascaded output transistors CT1 to CTM are disconnected, and the signal at the m-th cascaded input terminal CINm cannot be written to the m-th strobe output terminal HOUTm.

[0249] In the third stage, S13, the first enable terminal EN1 is a low-level signal, while the strobe input terminal HIN, the second enable terminal EN2, and the strobe clock terminal HCK are high-level signals. The first transistor T1, the second transistor T2, the thirteenth transistor T13, the fourteenth transistor T14, the seventh transistor T7, and the nineteenth transistor T19 are disconnected.

[0250] The eighth transistor T8 remains on, and the low-level signal of the eighth node N8 is written to the third node N3. Since the third transistor T3 is on, the signal of the third node N3 is written to the first node N1. The first node N1 and the third node N3 are continuously pulled low. The sixth transistor T6 just begins to turn on, and the signal of the gating clock terminal HCK changes from a low level signal to a high level signal. The high-level signal of the gating clock terminal HCK is written to the sixth node N6. Under the action of the first capacitor C1, the signal of the fifth node N5 is continuously pulled high. Since the fourth transistor T4 is on, the fourth node N4 and the fifth node N5 are connected. Therefore, the signal of the fourth node N4 is continuously pulled high. The fifth transistor T5 is off. Since the signal of the first node N1 is a low level signal, multiple stage initial output transistors ST1 to STM are turned on, and the signal of the m-th initial input terminal CINm is written to the m-th gating output terminal HOUTm. When the tenth transistor T10 is turned on, the high-level signal of the first power supply terminal VGH is written to the seventh node N7. When the ninth transistor T9 is turned off, the high-level signal of the first power supply terminal VGH cannot be written to the third node N3, which allows the third node N3 to maintain a low-level signal.

[0251] Transistor T22 is turned off, and the signal at the clock input HCK changes from a low level in the previous stage to a high level in this stage. Under the influence of capacitor C4, the signal at node N13 becomes high, and transistor T21 is turned off. Because transistor T15 is turned on, the signal at node N9 is written to node N2. The signals at nodes N2 and N9 are both high. Transistors T20, T22, and multiple cascaded output transistors CT1 to CTM are disconnected. In this stage, the signals at nodes N2 and N9 remain high. With multiple cascaded output transistors CT1 to CTM disconnected, the signal at the m-th cascaded input CINm cannot be written to the m-th clock output HOUTm.

[0252] Figure 17 is a second driving timing diagram of the gating sub-circuit provided in Figure 15. Figure 17 illustrates the example of a gating sub-circuit outputting signals from multiple cascaded inputs. Since the signals from the multiple initial inputs and multiple cascaded inputs depend on the partitioning of the display substrate and are uncertain, and the signals from the gating outputs are distinct from those from the initial inputs and multiple cascaded inputs, the signal timing of the multiple initial inputs, multiple cascaded inputs, and multiple gating outputs is not shown in Figure 17. In Figure 17, VL represents the voltage value of the low-level signal of the second enable terminal EN2, and VH represents the voltage value of the high-level signal of the first enable terminal EN1.

[0253] In at least one display frame, referring to Figure 17, the operation of the gating sub-circuit provided in Figure 15 may include:

[0254] In the first stage S21, the early write stage, the signals of the second enable terminal EN2 and the strobe input terminal HIN are low-level signals, while the signals of the first enable terminal EN1 and the strobe clock terminal HCK are high-level signals. The first transistor T1, the second transistor T2, the thirteenth transistor T13, and the fourteenth transistor T14 are turned on, while the seventh transistor T7 and the nineteenth transistor T19 are turned off.

[0255] The first transistor T1 and the second transistor T2 are turned on. The high-level signal of the first enable terminal EN1 is written to the third node N3 and the fourth node N4. Since the third transistor T3 is turned on, the signal of the third node N3 is written to the first node N1. Since the fourth transistor T4 is turned on, the signal of the fourth node N4 is written to the fifth node N5. The signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are high-level signals. The fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the tenth transistor T10 and multiple initial output transistors ST1 to STM are disconnected. The signal of the m-th initial input terminal SINm cannot be written to the m-th gating output terminal HOUTm.

[0256] Transistors T13 (13th) and T14 (14th) are turned on, and the low-level signal of the second enable terminal EN2 is written to nodes N9 (9th) and N10 (10th). Since transistor T15 (15th) is turned on, the signal of node N9 is written to node N2 (2nd). Since transistor T16 (16th) is turned on, the signal of node N10 is written to node N11 (11th). The signals of nodes N2 (2nd), N9 (9th), N10 (10th), and N11 (11th) are low-level. Transistors T17 (17th), T18 (18th), T20 (20th), T22 (22nd), and multiple cascaded transistors CT1 to CTM are turned on. With multiple cascaded transistors CT1 to CTM turned on, the signal of the m-th cascaded input terminal CINm is written to the m-th strobe output terminal HOUTm. When the 22nd transistor T22 is turned on, the high-level signal of the first power supply terminal VGH is written to the 13th node N13. The fourth capacitor C4 stores the voltage difference between the high-level signal of the gating clock terminal HCK and the high-level signal of the 13th node N13. When the 21st transistor T21 is turned off, the high-level signal of the first power supply terminal VGH cannot be written to the 9th node N9. When the 18th transistor T18 is turned on, the high-level signal of the gating clock terminal HCK is written to the 12th node N12. The third capacitor C3 stores the voltage difference between the high-level signal of the 12th node N12 and the high-level signal of the 11th node N11.

[0257] In the second stage (S22), the output stage, the signals of the second enable terminal EN2 and the strobe clock terminal HCK are low-level signals, while the signals of the first enable terminal EN1 and the strobe input terminal HIN are high-level signals. The first transistor T1, the second transistor T2, the thirteenth transistor T13, and the fourteenth transistor T14 are off, while the seventh transistor T7 and the nineteenth transistor T19 are on.

[0258] The tenth transistor T10 remains off, and the signal at the gating clock terminal HCK changes from a high level in the previous stage to a low level in this stage. Under the action of the second capacitor C2, the signal at the seventh node N7 becomes a low level signal, the ninth transistor T9 turns on, and the high level signal at the first power supply terminal VGH is written to the third node N3. Since the third transistor T3 is on, the signal at the third node N3 is written to the first node N1. The signals at the first node N1 and the third node N3 are high level signals. The eighth transistor T8, the tenth transistor T10, and multiple initial output transistors ST1 are disconnected from the STM. The seventh transistor T7 turns on, and the low level signal at the second power supply terminal VGL is written to the eighth node N8. Since the eighth transistor T8 is off, the signal at the eighth node N8 cannot be written to the first node N1 and the third node N3. In this stage, the signals at the first node N1 and the third node N3 remain high level signals. Multiple initial output transistors ST1 are disconnected from the STM, and the signal at the m-th initial input terminal SINm cannot be written to the m-th gating output terminal HOUTm.

[0259] The twentieth transistor T20 is turned on, and the low-level signal of the second power supply terminal VGL is written to the ninth node N9 through the turned-on nineteenth transistor T19 and the twentieth transistor T20. Since the fifteenth transistor T15 is turned on, the signal of the ninth node N9 is written to the second node N2. The signals of the second node N2 and the ninth node N9 are continuously pulled low. The eighteenth transistor T18 is continuously turned on, and the low-level signal of the gating clock terminal HCK is written to the twelfth node N12. Under the action of the third capacitor C3, the signal of the eleventh node N11 is continuously pulled low. Since the sixteenth transistor T16 is turned on, the tenth node N10 and the eleventh node N11 are connected. Therefore, the signal of the tenth node N10 is pulled low. The seventeenth transistor T17 is turned on, and the low-level signal of the eleventh node N11 is written to the second node N2. Multiple cascaded output transistors CT1 to CTM are turned on, and the signal of the mth cascaded input terminal CINm is written to the mth gating output terminal HOUTm. When the 22nd transistor T22 is turned on, the high-level signal of the first power supply terminal VGH is written to the 13th node N13. When the 21st transistor T21 is turned off, the high-level signal of the first power supply terminal VGH cannot be written to the 9th node N9, which allows the 9th node N9 to maintain a low-level signal.

[0260] Since the absolute value of the voltage of the signal at the second node N2 in this stage is greater than the voltage value of the signal at the second node N2 in the first stage, the conduction degree of the multiple cascaded output transistors CT1 to DTM in this stage is greater than the conduction degree of the multiple cascaded output transistors CT1 to CTM in the first stage. Therefore, all the multiple cascaded output transistors CT1 to CTM in this stage are turned on.

[0261] In the third stage, the signals at S23 and the second enable terminal EN2 are low-level signals, while the signals at the strobe input terminal HIN, the first enable terminal EN1, and the strobe clock terminal HCK are high-level signals. The first transistor T1, the second transistor T2, the thirteenth transistor T13, the fourteenth transistor T14, the seventh transistor T7, and the nineteenth transistor T19 are disconnected.

[0262] The tenth transistor T10 remains off, and the signal at the gating clock terminal HCK changes from a low level in the previous stage to a high level in this stage. Under the action of the second capacitor C2, the signal at the seventh node N7 becomes a high level signal, and the ninth transistor T9 is off. Because the third transistor T3 is on, the signal at the third node N3 is written to the first node N1. The signals at the first node N1 and the third node N3 are high level signals. The eighth transistor T8, the tenth transistor T10, and multiple initial output transistors ST1 are disconnected from the STM. In this stage, the signals at the first node N1 and the third node N3 remain high level signals. With multiple initial output transistors ST1 disconnected from the STM, the signal at the m-th initial input terminal SINm cannot be written to the m-th gating output terminal HOUTm.

[0263] The twentieth transistor T20 remains on, and the low-level signal of the fourteenth node N14 is written to the ninth node N9. Since the fifteenth transistor T15 is on, the signal of the ninth node N9 is written to the second node N2. The second node N2 and the ninth node N9 are continuously pulled low. The eighteenth transistor T18 just begins to turn on, and the signal of the gating clock terminal HCK changes from a low level signal to a high level signal. The high level signal of the gating clock terminal HCK is written to the twelfth node N12. Under the action of the third capacitor C3, the signal of the eleventh node N11 is continuously pulled high. Since the sixteenth transistor T16 is on, the tenth node N10 and the eleventh node N11 are connected. Therefore, the signal of the tenth node N10 is continuously pulled high. The seventeenth transistor T17 is off. Since the signal of the second node N2 is a low level signal, multiple cascaded output transistors CT1 to CTM are turned on. The signal of the mth cascaded input terminal CINm is written to the mth gating output terminal HOUTm. When the 22nd transistor T22 is turned on, the high-level signal of the first power supply terminal VGH is written to the 13th node N13. When the 21st transistor T21 is turned off, the high-level signal of the first power supply terminal VGH cannot be written to the 9th node N9, which allows the 9th node N9 to maintain a low-level signal.

[0264] In an exemplary embodiment, the signal at the gating input terminal connected to at least one gating sub-circuit is a single pulse signal within a display frame. The duration of this single pulse signal can be the duration for which the output signal of at least one shift register in at least one shift register group of at least one driving circuit connected to at least one gating sub-circuit is at an active level. For example, the duration of the single pulse signal can be the duration for which the output signal of one shift register in at least one shift register group of at least one driving circuit connected to at least one gating sub-circuit is at an active level, or it can be the sum of the durations for which the output signals of all shift registers in at least one shift register group of at least one driving circuit connected to at least one gating sub-circuit are at an active level. This disclosure does not impose any limitations on this.

[0265] In an exemplary embodiment, FIG18 is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment. As shown in FIG18, the display substrate further includes: a selection circuit 40, which includes: N selection sub-circuits 41, which are cascaded together. The nth selection sub-circuit 41 in the selection circuit 40 is electrically connected to the selection input terminal HIN of the nth selection sub-circuit 11 in the selection circuit 10.

[0266] In an exemplary embodiment, at least one selector circuit has a structure that is at least partially identical to that of at least one shift register in at least one drive circuit. This at least partial similarity in structure between the selector circuit and the shift register in at least one drive circuit simplifies the fabrication process of the display substrate.

[0267] In an exemplary embodiment, the nth selection sub-circuit may also be electrically connected to one of the signal terminals of the first enable terminal EN1 and the second enable terminal EN2 connected to the nth gating sub-circuit.

[0268] In an exemplary embodiment, FIG19 is a schematic diagram of the structure of a display substrate provided in another exemplary embodiment. As shown in FIG19, the display substrate may further include a selection chip 50. The selection chip 50 is electrically connected to at least one of the signal terminals of the first enable terminal EN1 and the second enable terminal EN2 of the at least one gating sub-circuit 11.

[0269] In an exemplary embodiment, when the selection chip is connected to one of the signal terminals of the first enable terminal EN1 and the second enable terminal EN2 of at least one gating sub-circuit 11, the display substrate further includes an inverter configured to generate a signal for the other signal terminal of the first enable terminal EN1 and the second enable terminal EN2.

[0270] In an exemplary embodiment, the display area of ​​the display substrate can be divided into at least one display area according to the refresh rate, and the at least one display area is connected to multiple selection sub-circuits through multiple driving circuits. The refresh rate of the at least one display area can be a first refresh rate or a second refresh rate.

[0271] In one exemplary embodiment, the refresh rate refers to the number of times the display substrate refreshes data per second. The first refresh rate can range from 1Hz to 60Hz. The second refresh rate can range from 60Hz to 480Hz.

[0272] In an exemplary embodiment, when all display areas of the display substrate achieve the first refresh rate, this can be achieved by writing the signal of the mth cascaded input terminal to the mth gating output terminal connected by multiple gating sub-circuits.

[0273] In an exemplary embodiment, when all display areas of the display substrate achieve the second refresh rate, the signal of the m-th initial input terminal can be written through the m-th gating output terminal connected to the first gating sub-circuit, and the signal of the m-th cascaded input terminal can be written through the m-th gating output terminal connected to the remaining gating sub-circuit (excluding the first gating sub-circuit).

[0274] In an exemplary embodiment, the display area of ​​the display substrate is divided into a first display area and a second display area according to the refresh rate. When the refresh rate of the first display area is the first refresh rate and the refresh rate of the second display area is the second refresh rate, the signal of the mth cascaded input terminal is written to the mth gating output terminal connected to the plurality of gating sub-circuits connected to the first display area, the signal of the mth initial input terminal is written to the mth gating output terminal connected to the first gating sub-circuit connected to the second display area, and the signal of the mth cascaded input terminal is written to the mth gating output terminal connected to the remaining gating sub-circuits connected to the second display area.

[0275] In an exemplary embodiment, the display area of ​​the display substrate is divided into a first display area and a second display area according to the refresh rate. The refresh rate of the first display area is the second refresh rate, and the refresh rate of the second display area is the first refresh rate. When the refresh rate of the second display area is the first refresh rate, the m-th gating output terminal connected to the first gating sub-circuit connected to the first display area writes the signal of the m-th initial input terminal, the m-th gating output terminal connected to the remaining gating sub-circuit connected to the first display area writes the signal of the m-th cascaded input terminal, the m-th gating output terminal connected to the first gating sub-circuit connected to the second display area writes the signal of the m-th initial input terminal, and the m-th gating output terminal connected to the remaining gating sub-circuit connected to the second display area writes the signal of the m-th cascaded input terminal.

[0276] In an exemplary embodiment, the display area of ​​the display substrate is divided into a first display area, a second display area, and a third display area according to the refresh rate. When the refresh rate of the first display area and the third display area is the first refresh rate, and the refresh rate of the second display area is the second refresh rate, the signal of the mth cascaded input terminal is written to the mth gating output terminal connected to the plurality of gating sub-circuits connected to the first display area, the signal of the mth initial input terminal is written to the mth gating output terminal connected to the first gating sub-circuit connected to the second display area, and the signal of the mth cascaded input terminal is written to the mth gating output terminal connected to the remaining gating sub-circuits connected to the second display area. Similarly, the signal of the mth initial input terminal is written to the mth gating output terminal connected to the first gating sub-circuit connected to the third display area, and the signal of the mth cascaded input terminal is written to the mth gating output terminal connected to the remaining gating sub-circuits connected to the third display area.

[0277] In an exemplary embodiment, the display area of ​​the display substrate is divided into a first display area, a second display area, and a third display area according to the refresh rate. The refresh rates of the first display area and the third display area are the second refresh rate. When the refresh rate of the second display area is the first refresh rate, the signal of the m-th initial input terminal is written to the m-th gating output terminal connected to the first gating sub-circuit connected to the first display area, and the signal of the m-th cascaded input terminal is written to the m-th gating output terminal connected to the remaining gating sub-circuit connected to the first display area. The signal of the m-th initial input terminal is written to the m-th gating output terminal connected to the first gating sub-circuit connected to the second display area, and the signal of the m-th cascaded input terminal is written to the m-th gating output terminal connected to the remaining gating sub-circuit connected to the second display area. The signal of the m-th initial input terminal is written to the m-th gating output terminal connected to the first gating sub-circuit connected to the third display area, and the signal of the m-th cascaded input terminal is written to the m-th gauging output terminal connected to the remaining gating sub-circuit connected to the third display area.

[0278] When the display area of ​​the display substrate is divided into at least four display areas according to the refresh rate, the connection method of the gating output terminal of the gating sub-circuit connected to different display areas can refer to the connection method when the display area of ​​the display substrate is divided into the first display area, the second display area and the third display area according to the refresh rate.

[0279] This disclosure also provides a display device, including: a display substrate provided in any of the foregoing embodiments.

[0280] In an exemplary embodiment, the display device can be any product or component with display function, such as a liquid crystal display (LCD), electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0281] The accompanying drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0282] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0283] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: A display area and a non-display area located on at least one side of the display area, the display area being provided with a plurality of sub-pixels, the non-display area being provided with a gating circuit, a plurality of driving circuits and a plurality of initial signal lines, at least one of the plurality of driving circuits including: a plurality of shift registers, at least one shift register including: a driving input terminal and a driving output terminal; The drive output terminal of at least one shift register of at least one of the plurality of drive circuits is electrically connected to the plurality of sub-pixels. The gating circuit is electrically connected to the drive input terminal of at least one shift register in at least one of the plurality of drive circuits and to the plurality of initial signal lines, respectively. The gating circuit includes: multiple gating sub-circuits; The gating sub-circuit is electrically connected to a first enable terminal, a second enable terminal, multiple initial input terminals, multiple cascaded input terminals, and multiple gating output terminals, respectively. It is configured to provide signals from multiple initial input terminals or signals from multiple cascaded input terminals to the multiple gating output terminals under the control of the signals from the first enable terminal and the second enable terminal.

2. The display substrate according to claim 1, wherein, Multiple shift registers located in at least one driving circuit are divided into N shift register groups, and multiple shift registers located in the same shift register group are cascaded together. The m-th gating output terminal connected to the n-th gating sub-circuit is electrically connected to the driving input terminal of the first shift register in the n-th shift register group of the m-th driving circuit, where 1≤m≤M, 1≤n≤N, M is the number of gating output terminals connected to the gating sub-circuit, and N is the number of gating sub-circuits included in the gating circuit.

3. The display substrate according to claim 2, wherein, The number of initial input terminals connected to the gating sub-circuit is M, and the number of cascaded input terminals connected to the gating sub-circuit is M; At least one gating sub-circuit is connected to the m-th initial input terminal, which is electrically connected to the m-th initial signal line. The first gating sub-circuit is connected to the mth cascaded input terminal, which is electrically connected to the mth target power line. The signal of the mth target power line is a constant voltage signal, and the voltage value is equal to the voltage value of the invalid level signal of the mth initial signal line. The m-th cascaded input terminal of the k-th gating sub-circuit is electrically connected to the drive output terminal of the last shift register in the (k-1)-th shift register group of the m-th drive circuit, where 2≤k≤N.

4. The display substrate according to claim 3, wherein, At least one gating sub-circuit includes: a first node control sub-circuit, a second node control sub-circuit, a first output sub-circuit, and a second output sub-circuit; The first node control sub-circuit is electrically connected to the gating input terminal, the first enable terminal, the gating reset signal terminal, the first power supply terminal, the second power supply terminal, the gating clock terminal, and the first node, respectively, and is configured to provide a signal from one of the signal terminals of the first enable terminal, the first power supply terminal, and the second power supply terminal to the first node under the control of the gating input terminal, the gating clock terminal, and the gating reset signal terminal. The second node control sub-circuit is electrically connected to the gating input terminal, the second enable terminal, the gating reset signal terminal, the first power supply terminal, the second power supply terminal, the gating clock terminal, and the second node, respectively, and is configured to provide a signal from one of the signal terminals of the second enable terminal, the first power supply terminal, and the second power supply terminal to the second node under the control of the gating input terminal, the gating clock terminal, and the gating reset signal terminal. The first output sub-circuit is electrically connected to the first node, the M initial input terminals and the M gating output terminals respectively, and is configured to provide the signals of the M initial input terminals to the M gating output terminals under the control of the signal of the first node; The second output sub-circuit is electrically connected to the second node, the M cascaded input terminals and the M gating output terminals respectively, and is configured to provide the signals of the M cascaded input terminals to the M gating output terminals under the control of the signal of the second node.

5. The display substrate according to claim 4, wherein, The first node control sub-circuit includes: a first write sub-circuit, a second write sub-circuit, a third write sub-circuit, and a first gating reset sub-circuit; The first write sub-circuit is electrically connected to the gating input terminal, the first enable terminal, the second power supply terminal, the gating clock terminal, the first node, the third node, the fourth node, the fifth node, and the sixth node, respectively. It is configured to provide the first enable terminal signal to the first node, the third node, the fourth node, and the fifth node under the control of the signal of the gating input terminal and the second power supply terminal, and to provide the gating clock terminal signal to the sixth node under the control of the signal of the fifth node, and to store the voltage difference between the signals of the fifth node and the sixth node. The second write sub-circuit is electrically connected to the gating clock terminal, the second power supply terminal, the first node, and the third node, respectively, and is configured to provide the second power supply terminal signal to the third node under the control of the signals of the gating clock terminal and the first node; The third write sub-circuit is electrically connected to the gating clock terminal, the first power supply terminal, the third node, and the seventh node, respectively. It is configured to provide the signal of the first power supply terminal to the other node of the third node and the seventh node under the control of the signal of one of the nodes of the third node and the seventh node, and to store the voltage difference between the signal of the seventh node and the gating clock terminal. The first gating reset sub-circuit is electrically connected to the gating reset signal terminal, the first power supply terminal, the third node, and the fourth node, respectively, and is configured to provide the first power supply terminal signal to the third node and the fourth node under the control of the signal from the gating reset signal terminal.

6. The display substrate according to claim 5, wherein, The first write sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor; The control electrode of the first transistor is electrically connected to the gating input terminal, the first electrode of the first transistor is electrically connected to the first enable terminal, and the second electrode of the first transistor is electrically connected to the third node. The control electrode of the second transistor is electrically connected to the gating input terminal, the first electrode of the second transistor is electrically connected to the first enable terminal, and the second electrode of the second transistor is electrically connected to the fourth node. The control electrode of the third transistor is electrically connected to the second power supply terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the first node. The control electrode of the fourth transistor is electrically connected to the second power supply terminal, the first electrode of the fourth transistor is electrically connected to the fourth node, and the second electrode of the fourth transistor is electrically connected to the fifth node. The control electrode and the first electrode of the fifth transistor are electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the first node. The control electrode of the sixth transistor is electrically connected to the fifth node, the first electrode of the sixth transistor is electrically connected to the sixth node, and the second electrode of the sixth transistor is electrically connected to the strobe clock terminal. The first terminal of the first capacitor is electrically connected to the fifth node, and the second terminal of the first capacitor is electrically connected to the sixth node.

7. The display substrate according to claim 5, wherein, The second write sub-circuit includes: a seventh transistor and an eighth transistor; The control terminal of the seventh transistor is electrically connected to the gating clock terminal, the first terminal of the seventh transistor is electrically connected to the second power supply terminal, and the second terminal of the seventh transistor is electrically connected to the eighth node. The control electrode of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the eighth node, and the second electrode of the eighth transistor is electrically connected to the third node.

8. The display substrate according to claim 5, wherein, The third write sub-circuit includes: a ninth transistor, a tenth transistor, and a second capacitor; The control electrode of the ninth transistor is electrically connected to the seventh node, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the first power supply terminal. The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the first power supply terminal, and the second electrode of the tenth transistor is electrically connected to the seventh node. The first terminal of the second capacitor is electrically connected to the strobe clock terminal, and the second terminal of the second capacitor is electrically connected to the seventh node.

9. The display substrate according to claim 8, wherein, The first gating reset circuit includes: an eleventh transistor and a twelfth transistor; The control electrode of the eleventh transistor is electrically connected to the gating reset signal terminal, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the third node. The control terminal of the twelfth transistor is electrically connected to the gating and reset signal terminal, the first terminal of the twelfth transistor is electrically connected to the first power supply terminal, and the second terminal of the twelfth transistor is electrically connected to the fourth node.

10. The display substrate according to claim 4, wherein, The second node control sub-circuit includes: a fourth write sub-circuit, a fifth write sub-circuit, a sixth write sub-circuit, and a second gating reset sub-circuit; The fourth write sub-circuit is electrically connected to the gating input terminal, the second enable terminal, the second power supply terminal, the gating clock terminal, the second node, the ninth node, the tenth node, the eleventh node, and the twelfth node, respectively. It is configured to provide the second enable terminal signal to the second node, the ninth node, the tenth node, and the eleventh node under the control of the signal of the gating input terminal and the second power supply terminal, and to provide the gating clock terminal signal to the twelfth node under the control of the signal of the eleventh node, and to store the voltage difference between the signals of the eleventh node and the twelfth node. The fifth write sub-circuit is electrically connected to the gating clock terminal, the second power supply terminal, the second node, and the ninth node, respectively, and is configured to provide the second power supply terminal signal to the ninth node under the control of the signals of the gating clock terminal and the second node. The sixth write sub-circuit is electrically connected to the gating clock terminal, the first power supply terminal, the ninth node, and the thirteenth node, respectively. It is configured to provide the signal of the first power supply terminal to the other node of the ninth node and the thirteenth node under the control of the signal of one of the nodes, and to store the voltage difference between the signal of the thirteenth node and the gating clock terminal. The second gating reset sub-circuit is electrically connected to the gating reset signal terminal, the second power supply terminal, the ninth node, and the tenth node, respectively, and is configured to provide the second power supply terminal signal to the ninth node and the tenth node under the control of the signal from the gating reset signal terminal.

11. The display substrate according to claim 10, wherein, The fourth write sub-circuit includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a third capacitor; The control terminal of the thirteenth transistor is electrically connected to the gating input terminal, the first terminal of the thirteenth transistor is electrically connected to the second enable terminal, and the second terminal of the thirteenth transistor is electrically connected to the ninth node. The control terminal of the fourteenth transistor is electrically connected to the gating input terminal, the first terminal of the fourteenth transistor is electrically connected to the second enable terminal, and the second terminal of the fourteenth transistor is electrically connected to the tenth node. The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, the first electrode of the fifteenth transistor is electrically connected to the ninth node, and the second electrode of the fifteenth transistor is electrically connected to the second node. The control terminal of the sixteenth transistor is electrically connected to the second power supply terminal, the first terminal of the sixteenth transistor is electrically connected to the tenth node, and the second terminal of the sixteenth transistor is electrically connected to the eleventh node. The control electrode and the first electrode of the seventeenth transistor are electrically connected to the eleventh node, and the second electrode of the seventeenth transistor is electrically connected to the second node. The control electrode of the eighteenth transistor is electrically connected to the eleventh node, the first electrode of the eighteenth transistor is electrically connected to the twelfth node, and the second electrode of the eighteenth transistor is electrically connected to the strobe clock terminal. The first terminal of the third capacitor is electrically connected to the eleventh node, and the second terminal of the third capacitor is electrically connected to the twelfth node.

12. The display substrate according to claim 10, wherein, The fifth write sub-circuit includes: the nineteenth transistor and the twentieth transistor; The control terminal of the nineteenth transistor is electrically connected to the gating clock terminal, the first terminal of the nineteenth transistor is electrically connected to the second power supply terminal, and the second terminal of the nineteenth transistor is electrically connected to the fourteenth node. The control electrode of the twentieth transistor is electrically connected to the second node, the first electrode of the twentieth transistor is electrically connected to the fourteenth node, and the second electrode of the twentieth transistor is electrically connected to the ninth node.

13. The display substrate according to claim 10, wherein, The sixth write sub-circuit includes: a twenty-first transistor, a twenty-second transistor, and a fourth capacitor; The control electrode of the 21st transistor is electrically connected to the 13th node, the first electrode of the 21st transistor is electrically connected to the 9th node, and the second electrode of the 21st transistor is electrically connected to the first power supply terminal. The control electrode of the 22nd transistor is electrically connected to the 9th node, the first electrode of the 22nd transistor is electrically connected to the first power supply terminal, and the second electrode of the 22nd transistor is electrically connected to the 13th node. The first terminal of the fourth capacitor is electrically connected to the strobe clock terminal, and the second terminal of the fourth capacitor is electrically connected to the thirteenth node.

14. The display substrate according to claim 10, wherein, The second gating reset circuit includes: a twenty-third transistor and a twenty-fourth transistor; The control terminal of the 23rd transistor is electrically connected to the gating and reset signal terminal, the first terminal of the 23rd transistor is electrically connected to the second power supply terminal, and the second terminal of the 23rd transistor is electrically connected to the ninth node. The control terminal of the 24th transistor is electrically connected to the gating and reset signal terminal, the first terminal of the 24th transistor is electrically connected to the second power supply terminal, and the second terminal of the 24th transistor is electrically connected to the 10th node.

15. The display substrate according to claim 4, wherein, The first output sub-circuit includes: M initial output transistors; The control electrode of the m-th initial output transistor is electrically connected to the first node, the first electrode of the m-th initial output transistor is electrically connected to the m-th initial input terminal, and the second electrode of the m-th initial output transistor is electrically connected to the m-th gating output terminal.

16. The display substrate according to claim 4, wherein, The second output sub-circuit includes: M cascaded output transistors; The control terminal of the m-th cascaded output transistor is electrically connected to the second node, the first terminal of the m-th cascaded output transistor is electrically connected to the m-th cascaded input terminal, and the second terminal of the m-th cascaded output transistor is electrically connected to the m-th gating output terminal.

17. The display substrate according to claim 4, wherein, In at least one gating sub-circuit, the first node control sub-circuit includes: a first transistor to a twelfth transistor, a first capacitor and a second capacitor; the second node control sub-circuit includes: a thirteenth transistor and a twenty-fourth transistor, a third capacitor and a fourth capacitor; the first output sub-circuit includes: M initial output transistors; and the second output sub-circuit includes: M cascaded output transistors. The control electrode of the first transistor is electrically connected to the gating input terminal, the first electrode of the first transistor is electrically connected to the first enable terminal, and the second electrode of the first transistor is electrically connected to the third node. The control electrode of the second transistor is electrically connected to the gating input terminal, the first electrode of the second transistor is electrically connected to the first enable terminal, and the second electrode of the second transistor is electrically connected to the fourth node. The control electrode of the third transistor is electrically connected to the second power supply terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the first node. The control electrode of the fourth transistor is electrically connected to the second power supply terminal, the first electrode of the fourth transistor is electrically connected to the fourth node, and the second electrode of the fourth transistor is electrically connected to the fifth node. The control electrode and the first electrode of the fifth transistor are electrically connected to the fifth node, and the second electrode of the fifth transistor is electrically connected to the first node. The control electrode of the sixth transistor is electrically connected to the fifth node, the first electrode of the sixth transistor is electrically connected to the sixth node, and the second electrode of the sixth transistor is electrically connected to the strobe clock terminal. The control terminal of the seventh transistor is electrically connected to the gating clock terminal, the first terminal of the seventh transistor is electrically connected to the second power supply terminal, and the second terminal of the seventh transistor is electrically connected to the eighth node. The control electrode of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the eighth node, and the second electrode of the eighth transistor is electrically connected to the third node. The control electrode of the ninth transistor is electrically connected to the seventh node, the first electrode of the ninth transistor is electrically connected to the third node, and the second electrode of the ninth transistor is electrically connected to the first power supply terminal. The control electrode of the tenth transistor is electrically connected to the third node, the first electrode of the tenth transistor is electrically connected to the first power supply terminal, and the second electrode of the tenth transistor is electrically connected to the seventh node. The control electrode of the eleventh transistor is electrically connected to the gating reset signal terminal, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the third node. The control terminal of the twelfth transistor is electrically connected to the gating reset signal terminal, the first terminal of the twelfth transistor is electrically connected to the first power supply terminal, and the second terminal of the twelfth transistor is electrically connected to the fourth node. The control terminal of the thirteenth transistor is electrically connected to the gating input terminal, the first terminal of the thirteenth transistor is electrically connected to the second enable terminal, and the second terminal of the thirteenth transistor is electrically connected to the ninth node. The control terminal of the fourteenth transistor is electrically connected to the gating input terminal, the first terminal of the fourteenth transistor is electrically connected to the second enable terminal, and the second terminal of the fourteenth transistor is electrically connected to the tenth node. The control electrode of the fifteenth transistor is electrically connected to the second power supply terminal, the first electrode of the fifteenth transistor is electrically connected to the ninth node, and the second electrode of the fifteenth transistor is electrically connected to the second node. The control terminal of the sixteenth transistor is electrically connected to the second power supply terminal, the first terminal of the sixteenth transistor is electrically connected to the tenth node, and the second terminal of the sixteenth transistor is electrically connected to the eleventh node. The control electrode and the first electrode of the seventeenth transistor are electrically connected to the eleventh node, and the second electrode of the seventeenth transistor is electrically connected to the second node. The control electrode of the eighteenth transistor is electrically connected to the eleventh node, the first electrode of the eighteenth transistor is electrically connected to the twelfth node, and the second electrode of the eighteenth transistor is electrically connected to the strobe clock terminal. The control terminal of the nineteenth transistor is electrically connected to the gating clock terminal, the first terminal of the nineteenth transistor is electrically connected to the second power supply terminal, and the second terminal of the nineteenth transistor is electrically connected to the fourteenth node. The control electrode of the twentieth transistor is electrically connected to the second node, the first electrode of the twentieth transistor is electrically connected to the fourteenth node, and the second electrode of the twentieth transistor is electrically connected to the ninth node. The control electrode of the 21st transistor is electrically connected to the 13th node, the first electrode of the 21st transistor is electrically connected to the 9th node, and the second electrode of the 21st transistor is electrically connected to the first power supply terminal. The control electrode of the 22nd transistor is electrically connected to the 9th node, the first electrode of the 22nd transistor is electrically connected to the first power supply terminal, and the second electrode of the 22nd transistor is electrically connected to the 13th node. The control terminal of the 23rd transistor is electrically connected to the gating and reset signal terminal, the first terminal of the 23rd transistor is electrically connected to the second power supply terminal, and the second terminal of the 23rd transistor is electrically connected to the ninth node. The control terminal of the 24th transistor is electrically connected to the gating and reset signal terminal, the first terminal of the 24th transistor is electrically connected to the second power supply terminal, and the second terminal of the 24th transistor is electrically connected to the 10th node. The control electrode of the m-th initial output transistor is electrically connected to the first node, the first electrode of the m-th initial output transistor is electrically connected to the m-th initial input terminal, and the second electrode of the m-th initial output transistor is electrically connected to the m-th gating output terminal. The control electrode of the m-th cascaded output transistor is electrically connected to the second node, the first electrode of the m-th cascaded output transistor is electrically connected to the m-th cascaded input terminal, and the second electrode of the m-th cascaded output transistor is electrically connected to the m-th gating output terminal. The first terminal of the first capacitor is electrically connected to the fifth node, and the second terminal of the first capacitor is electrically connected to the sixth node. The first terminal of the second capacitor is electrically connected to the gating clock terminal, and the second terminal of the second capacitor is electrically connected to the seventh node. The first terminal of the third capacitor is electrically connected to the eleventh node, and the second terminal of the third capacitor is electrically connected to the twelfth node. The first terminal of the fourth capacitor is electrically connected to the strobe clock terminal, and the second terminal of the fourth capacitor is electrically connected to the thirteenth node.

18. The display substrate according to claim 1, wherein, The signals at the first enable terminal and the second enable terminal are inverse signals.

19. The display substrate according to claim 2 or 3, wherein, At least one gating sub-circuit is also electrically connected to the gating input and the gating clock. The signal at the gating input terminal and the signal at the gating clock terminal connected to at least one gating sub-circuit are inverse signals for a certain period of time.

20. The display substrate according to claim 19, further comprising: The selection circuit includes N selection sub-circuits, which are cascaded together, and at least one gating sub-circuit is also electrically connected to the gating input terminal. The nth selector circuit is electrically connected to the gating input of the nth gating circuit.

21. The display substrate according to claim 20, wherein, At least one selector circuit has a structure that is at least partially identical to that of at least one shift register in at least one drive circuit.

22. The display substrate according to claim 20, wherein, The first enable terminal and the second enable terminal of the nth selector circuit are electrically connected.

23. The display substrate according to claim 22, further comprising: Select a chip; The selection chip is electrically connected to at least one of the signal terminals of the first enable terminal and the second enable terminal, which are connected to at least one gating sub-circuit.

24. A display device, comprising: The display substrate as described in any one of claims 1 to 23.

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