Shift register unit, display device, and driving method

Abstract

Embodiments of the present disclosure provide a shift register unit, a display device, and a driving method. The shift register unit comprises: a first anti-leakage circuit, coupled to a first node, and configured to control a signal on the first node in response to signals from a first driving input terminal and a clock signal terminal; a first control circuit, configured to provide a signal from a first cascade input terminal to the first node in response to the signal from the first cascade input terminal, and to provide a signal from a first reference voltage signal terminal to the first node in response to signals from a reset signal terminal and a second cascade input terminal; a second control circuit, configured to provide a signal from the first reference voltage signal terminal to the first node in response to a signal on a second node; a third control circuit, configured to control a signal on the second node in response to signals from the first cascade input terminal, a first power supply terminal, and the first node; and an output control circuit, configured to provide a signal from the clock signal terminal to a cascade output terminal and a driving output terminal in response to a signal on the first node.

Description

Shift register unit, display device and driving method Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to shift register units, display devices, and driving methods. Background Technology

[0002] With the rapid development of display technology, display panels are showing a trend towards high integration and low cost. Among them, Gate Driver on Array (GOA) technology integrates the gate driving circuit on the array substrate of the display panel to form a scanning drive for the display panel. Currently, the gate driving circuit is usually composed of multiple cascaded shift register units. Summary of the Invention

[0003] The shift register unit provided in some embodiments of this disclosure includes:

[0004] A first leakage protection circuit, coupled to the first node, is configured to control the signal on the first node in response to signals at the first drive input terminal and the clock signal terminal.

[0005] A first control circuit, coupled to the first node, is configured to provide a signal from the first cascaded input terminal to the first node in response to a signal from the first cascaded input terminal, and to provide a signal from the first reference voltage signal terminal to the first node in response to a signal from the reset signal terminal and a signal from the second cascaded input terminal.

[0006] A second control circuit, coupled to the first node and the second node, is configured to provide a signal from the first reference voltage signal terminal to the first node in response to a signal on the second node.

[0007] A third control circuit, coupled to the first node and the second node, is configured to control the signal on the second node in response to the first cascade input, the first power supply, and the signal on the first node.

[0008] A fourth control circuit, coupled to the second node, is configured to, in response to a signal on the second node, provide the signal from the first reference voltage signal terminal to the cascaded output terminal and the signal from the second reference voltage signal terminal to the drive output terminal.

[0009] An output control circuit, coupled to the first node, is configured to provide a signal from the clock signal terminal to the cascaded output terminal and the drive output terminal in response to a signal on the first node.

[0010] In some possible implementations provided in this disclosure, the first leakage protection circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor;

[0011] The gate of the first transistor is coupled to the first drive input terminal, the first terminal of the first transistor is coupled to the third reference voltage signal terminal, and the second terminal of the first transistor is coupled to the second terminal of the second transistor.

[0012] The gate of the second transistor is coupled to the clock signal terminal, and the first terminal of the second transistor is coupled to the initialization signal terminal;

[0013] The gate of the third transistor is coupled to the second terminal of the first transistor, the first terminal of the third transistor is coupled to the fourth reference voltage signal terminal, and the second terminal of the third transistor is coupled to the first terminal of the fourth transistor.

[0014] The gate of the fourth transistor is coupled to the first terminal of the fourth transistor, and the second terminal of the fourth transistor is coupled to the first node;

[0015] The first plate of the first capacitor is coupled to the gate of the third transistor, and the second plate of the first capacitor is coupled to the second electrode of the third transistor.

[0016] In some possible implementations provided in this disclosure, the first control circuit includes: a first control transistor, a second control transistor, and a third control transistor;

[0017] The gate of the first control transistor is coupled to the first cascaded input terminal, the first electrode of the first control transistor is coupled to the first cascaded input terminal, and the second electrode of the first control transistor is coupled to the first node.

[0018] The gate of the second control transistor is coupled to the second cascaded input terminal, the first terminal of the second control transistor is coupled to the first node, and the second terminal of the second control transistor is coupled to the first reference voltage signal terminal.

[0019] The gate of the third control transistor is coupled to the reset signal terminal, the first terminal of the third control transistor is coupled to the first node, and the second terminal of the third control transistor is coupled to the first reference voltage signal terminal.

[0020] In some possible implementations provided in this disclosure, the first control circuit includes: a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, an eighth control transistor, and a ninth control transistor;

[0021] The gate of the fourth control transistor is coupled to the first cascaded input terminal, the first terminal of the fourth control transistor is coupled to the first cascaded input terminal, and the second terminal of the fourth control transistor is coupled to the first terminal of the fifth control transistor.

[0022] The gate of the fifth control transistor is coupled to the first cascaded input terminal, and the second terminal of the fifth control transistor is coupled to the first node;

[0023] The gate of the sixth control transistor is coupled to the second cascaded input terminal, the first terminal of the sixth control transistor is coupled to the first node, and the second terminal of the sixth control transistor is coupled to the first terminal of the seventh control transistor.

[0024] The gate of the seventh control transistor is coupled to the second cascaded input terminal, and the second terminal of the seventh control transistor is coupled to the first reference voltage signal terminal.

[0025] The gate of the eighth control transistor is coupled to the reset signal terminal, the first terminal of the eighth control transistor is coupled to the first node, and the second terminal of the eighth control transistor is coupled to the first terminal of the ninth control transistor.

[0026] The gate of the ninth control transistor is coupled to the reset signal terminal, and the second terminal of the ninth control transistor is coupled to the first reference voltage signal terminal.

[0027] In some possible implementations provided in this disclosure, the second control circuit includes: a tenth control transistor;

[0028] The gate of the tenth control transistor is coupled to the second node, the first terminal of the tenth control transistor is coupled to the first node, and the second terminal of the tenth control transistor is coupled to the first reference voltage signal terminal.

[0029] In some possible implementations provided in this disclosure, the second control circuit includes: an eleventh control transistor and a twelfth control transistor;

[0030] The gate of the eleventh control transistor is coupled to the second node, the first terminal of the eleventh control transistor is coupled to the first node, and the second terminal of the eleventh control transistor is coupled to the first terminal of the twelfth control transistor.

[0031] The gate of the twelfth control transistor is coupled to the second node, and the second terminal of the twelfth control transistor is coupled to the first reference voltage signal terminal.

[0032] In some possible implementations provided in this disclosure, the third control circuit includes: a thirteenth control transistor, a fourteenth control transistor, and a fifteenth control transistor;

[0033] The gate of the thirteenth control transistor is coupled to the first power supply terminal, the first electrode of the thirteenth control transistor is coupled to the first power supply terminal, and the second electrode of the thirteenth control transistor is coupled to the second node.

[0034] The gate of the fourteenth control transistor is coupled to the first cascaded input terminal, the first terminal of the fourteenth control transistor is coupled to the second node, and the second terminal of the fourteenth control transistor is coupled to the first reference voltage signal terminal.

[0035] The gate of the fifteenth control transistor is coupled to the first node, the first terminal of the fifteenth control transistor is coupled to the second node, and the second terminal of the fifteenth control transistor is coupled to the first reference voltage signal terminal.

[0036] In some possible implementations provided in this disclosure, the fourth control circuit includes: a sixteenth control transistor and a seventeenth control transistor;

[0037] The gate of the sixteenth control transistor is coupled to the second node, the first terminal of the sixteenth control transistor is coupled to the cascaded output terminal, and the second terminal of the sixteenth control transistor is coupled to the first reference voltage signal terminal.

[0038] The gate of the seventeenth control transistor is coupled to the second node, the first terminal of the seventeenth control transistor is coupled to the drive output terminal, and the second terminal of the seventeenth control transistor is coupled to the second reference voltage signal terminal.

[0039] In some possible embodiments provided in this disclosure, the output control circuit includes: a first output transistor, a second output transistor, and a second capacitor;

[0040] The gate of the first output transistor is coupled to the first node, the first terminal of the first output transistor is coupled to the clock signal terminal, and the second terminal of the first output transistor is coupled to the cascaded output terminal.

[0041] The gate of the second output transistor is coupled to the first node, the first terminal of the second output transistor is coupled to the clock signal terminal, and the second terminal of the second output transistor is coupled to the drive output terminal.

[0042] The first electrode of the second capacitor is coupled to the gate of the second output transistor, and the second electrode of the second capacitor is coupled to the drive output terminal.

[0043] In some possible implementations provided in this disclosure, a second leakage protection circuit is also included, coupled to the first node and the first control circuit, and configured to provide a signal from the fifth reference voltage signal terminal to the first control circuit in response to a signal on the first node.

[0044] In some possible implementations provided in this disclosure, the second leakage protection circuit includes: a fifth transistor;

[0045] The gate of the fifth transistor is coupled to the first node, the first terminal of the fifth transistor is coupled to the fifth reference voltage signal terminal, and the second terminal of the fifth transistor is coupled to the first control circuit.

[0046] In some possible implementations provided in this disclosure, a fifth control circuit is further included, configured to provide a signal from the second reference voltage signal terminal to the drive output terminal in response to a signal from the second drive input terminal.

[0047] In some possible implementations provided in this disclosure, the fifth control circuit includes: an eighteenth control transistor;

[0048] The gate of the eighteenth control transistor is coupled to the second drive input terminal, the first terminal of the eighteenth control transistor is coupled to the drive output terminal, and the second terminal of the eighteenth control transistor is coupled to the second reference voltage signal terminal.

[0049] Some possible implementations provided in this disclosure also include:

[0050] A sixth control circuit, coupled to the first node and the third node, is configured to provide a signal from the first reference voltage signal terminal to the first node in response to a signal on the third node.

[0051] A seventh control circuit, coupled to the first node and the third node, is configured to control the signal on the third node in response to the first cascade input, the second power supply, and the signal on the first node.

[0052] The eighth control circuit, coupled to the third node, is configured to, in response to a signal on the third node, provide the signal from the first reference voltage signal terminal to the cascaded output terminal and the signal from the second reference voltage signal terminal to the drive output terminal.

[0053] In some possible implementations provided in this disclosure, the sixth control circuit includes: a nineteenth control transistor;

[0054] The gate of the nineteenth control transistor is coupled to the third node, the first terminal of the nineteenth control transistor is coupled to the first node, and the second terminal of the nineteenth control transistor is coupled to the first reference voltage signal terminal.

[0055] In some possible implementations provided in this disclosure, the sixth control circuit includes: a twentieth control transistor and a twenty-first control transistor;

[0056] The gate of the twentieth control transistor is coupled to the third node, the first terminal of the twentieth control transistor is coupled to the first node, and the second terminal of the twentieth control transistor is coupled to the first terminal of the twentieth eleventh transistor.

[0057] The gate of the 21st control transistor is coupled to the third node, and the second terminal of the 21st control transistor is coupled to the first reference voltage signal terminal.

[0058] In some possible implementations provided in this disclosure, the seventh control circuit includes: a twenty-second control transistor, a twenty-third control transistor, and a twenty-fourth control transistor;

[0059] The gate of the twelfth control transistor is coupled to the second power supply terminal, the first terminal of the twelfth control transistor is coupled to the second power supply terminal, and the second terminal of the twelfth control transistor is coupled to the third node.

[0060] The gate of the 23rd control transistor is coupled to the first cascaded input terminal, the first terminal of the 23rd control transistor is coupled to the third node, and the second terminal of the 23rd control transistor is coupled to the first reference voltage signal terminal.

[0061] The gate of the 24th control transistor is coupled to the first node, the first terminal of the 24th control transistor is coupled to the third node, and the second terminal of the 24th control transistor is coupled to the first reference voltage signal terminal.

[0062] In some possible implementations provided in this disclosure, the eighth control circuit includes: a twenty-fifth control transistor and a twenty-sixth control transistor;

[0063] The gate of the 25th control transistor is coupled to the third node, the first terminal of the 25th control transistor is coupled to the cascaded output terminal, and the second terminal of the 25th control transistor is coupled to the first reference voltage signal terminal.

[0064] The gate of the 26th control transistor is coupled to the third node, the first terminal of the 26th control transistor is coupled to the drive output terminal, and the second terminal of the 26th control transistor is coupled to the second reference voltage signal terminal.

[0065] The display device provided in this disclosure includes the shift register unit described above.

[0066] The driving method for a shift register unit provided in this disclosure includes:

[0067] In the first stage, the first leakage protection circuit responds to the signal at the first drive input terminal and controls the signal on the first node; the first control circuit responds to the signal at the first cascade input terminal and provides the signal at the first cascade input terminal to the first node; the third control circuit responds to the signals at the first cascade input terminal, the first power supply terminal, and the first node and controls the signal on the second node; the output control circuit responds to the signal on the first node and provides the signal at the clock signal terminal to the cascade output terminal and the drive output terminal.

[0068] In the second stage, the first control circuit responds to the signal at the reset signal terminal and provides the signal at the first reference voltage signal terminal to the first node; the third control circuit responds to the signals at the first power supply terminal and the first node and controls the signals at the second node; the output control circuit responds to the signals at the first node and provides the signal at the clock signal terminal to the cascaded output terminal and the drive output terminal.

[0069] In the third stage, the third control circuit responds to the signals at the first power supply terminal and the first node, and controls the signals at the second node; the output control circuit responds to the signals at the first node, and provides the signals at the clock signal terminal to the cascaded output terminal and the drive output terminal.

[0070] In the fourth stage, the first leakage protection circuit responds to the signal at the clock signal terminal and controls the signal at the first node; the third control circuit responds to the signals at the first power supply terminal and the first node and controls the signal at the second node; the output control circuit responds to the signal at the first node and provides the signal at the clock signal terminal to the cascaded output terminal and the drive output terminal.

[0071] In the fifth stage, the first control circuit responds to the signal at the second cascade input terminal and provides the signal at the first reference voltage signal terminal to the first node; the second control circuit responds to the signal at the second node and provides the signal at the first reference voltage signal terminal to the first node; the third control circuit responds to the signal at the first power supply terminal and controls the signal at the second node; the fourth control circuit responds to the signal at the second node and provides the signal at the first reference voltage signal terminal to the cascade output terminal and the signal at the second reference voltage signal terminal to the drive output terminal.

[0072] In the sixth stage, the first leakage protection circuit responds to the signal at the clock signal terminal and controls the signal on the first node; the second control circuit responds to the signal on the second node and provides the signal at the first reference voltage signal terminal to the first node; the third control circuit responds to the signal at the first power supply terminal and controls the signal on the second node; the fourth control circuit responds to the signal on the second node and provides the signal at the first reference voltage signal terminal to the cascaded output terminal and the signal at the second reference voltage signal terminal to the drive output terminal. Attached Figure Description

[0073] Figure 1 is a schematic diagram of some structures of the display device provided in the embodiments of this disclosure;

[0074] Figure 2 is a schematic diagram of some structures of the shift register unit provided in the embodiments of this disclosure;

[0075] Figure 3 is a flowchart of the driving method provided in an embodiment of this disclosure;

[0076] Figure 4 is a timing diagram of some signals provided in the embodiments of this disclosure;

[0077] Figure 5 shows some other structural schematic diagrams of the shift register unit provided in the embodiments of this disclosure;

[0078] Figure 6 is a schematic diagram of some of the structures of the shift register unit provided in the embodiments of this disclosure;

[0079] Figure 7 shows some other signal timing diagrams provided in the embodiments of this disclosure;

[0080] Figure 8 is a schematic diagram of some of the structures of the shift register unit provided in the embodiments of this disclosure;

[0081] Figure 9 is a schematic diagram of some of the structures of the shift register unit provided in the embodiments of this disclosure;

[0082] Figure 10 is a schematic diagram of some of the structures of the shift register unit provided in the embodiments of this disclosure;

[0083] Figure 11 is a schematic diagram of some of the structures of the shift register unit provided in the embodiments of this disclosure;

[0084] Figure 12 is a schematic diagram of some of the structures of the shift register unit provided in the embodiments of this disclosure;

[0085] Figure 13 is a schematic diagram of some of the structures of the shift register unit provided in the embodiments of this disclosure. Detailed Implementation

[0086] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0087] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0088] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0089] In this embodiment of the disclosure, as shown in FIG1, the display device may include a display panel 10 and a timing controller 20. The display panel 10 may include a plurality of pixel units arranged in an array; exemplarily, each pixel unit includes multiple sub-pixels of different colors. Each sub-pixel may include a transistor and a pixel electrode. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, allowing for color mixing of red, green, and blue to achieve color display. Alternatively, a pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, allowing for color mixing of red, green, blue, and white to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0090] In some embodiments of this disclosure, as shown in FIG1, the display panel 10 further includes: multiple gate lines GA, multiple data lines DA, a gate driving circuit 101, and a source driving circuit 102; wherein, the gate driving circuit 101 is coupled to the gate lines GA, and the source driving circuit 102 is coupled to the data lines DA. The timing controller 20 can input control signals to the gate driving circuit 101, thereby causing the gate driving circuit 101 to input signals to the gate lines GA to drive the scanning gate lines GA. Furthermore, the timing controller 20 can acquire the original display data of the image to be displayed in the current display frame and send the required display data to the source driving circuit 102, enabling the source driving circuit 102 to apply data voltage to the data lines DA in the display panel according to the display data, thereby charging the sub-pixels and enabling the image display function.

[0091] For example, multiple source driver circuits 102 can be configured, with different source driver circuits coupled to different data lines. For instance, as shown in Figure 1, two source driver circuits 110 can be configured, with one source driver circuit 102 coupled to half of the data lines and the other source driver circuit 102 coupled to the other half of the data lines. Of course, three, four, or more source driver circuits 110 can also be configured, which can be designed and determined according to the actual application requirements, and are not limited here.

[0092] It should be noted that the gate driving circuit can be configured as shown in Figure 1, located on both sides of the display panel. The gate driving circuits on both sides of the display panel can drive the same gate line, or a gate driving circuit can be located on only one side of the display panel, or the gate driving circuits on both sides of the display panel can drive gate lines corresponding to different rows of sub-pixels respectively. In this embodiment, the number of gate driving circuits in the display panel is not further limited and can be determined according to the needs of the actual application.

[0093] In existing technologies, gate drive circuits typically consist of multiple cascaded shift register units. Each shift register unit is electrically connected to at least one gate line. Each shift register unit can apply a valid level signal to its corresponding gate line, thereby controlling multiple gate lines in the display panel to sequentially open for line-by-line scanning. However, each shift register unit generally consists of multiple transistors. Because the threshold voltage of the transistors in a shift register unit is non-uniform (i.e., the threshold voltage drifts), leakage current can easily occur in the shift register unit, affecting the output signal and consequently the display quality.

[0094] Based on the above problems, the shift register unit SR provided in this embodiment of the present disclosure, as shown in Figure 2, includes:

[0095] The first leakage protection circuit 110 is coupled to the first node N1 and is configured to control the signal on the first node N1 in response to the signals of the first drive input terminal G(n-1) and the clock signal terminal CK.

[0096] The first control circuit 120, coupled to the first node N1, is configured to provide the signal of the first cascade input terminal Out_C(n-1) to the first node N1 in response to the signal of the first cascade input terminal Out_C(n-1), and to provide the signal of the first reference voltage signal terminal VGL1 to the first node in response to the signals of the reset signal terminal TRST and the second cascade input terminal Out_C(n+1).

[0097] The second control circuit 130, coupled to the first node N1 and the second node N2, is configured to provide the signal of the first reference voltage signal terminal VGL1 to the first node N1 in response to a signal on the second node N2.

[0098] The third control circuit 140, coupled to the first node N1 and the second node N2, is configured to control the signal on the second node N2 in response to the first cascade input terminal Out_C(n-1), the first power supply terminal VDD1 and the signal on the first node N1.

[0099] The fourth control circuit 150, coupled to the second node N2, is configured to, in response to a signal on the second node N2, provide the signal of the first reference voltage signal terminal VGL1 to the cascaded output terminal Out_C(n), and provide the signal of the second reference voltage signal terminal VGL2 to the drive output terminal G(n).

[0100] The output control circuit 160, coupled to the first node N1, is configured to provide the clock signal terminal CK to the cascaded output terminal Out_C(n) and the drive output terminal G(n) in response to the signal on the first node N1.

[0101] This disclosure describes an embodiment that uses the cooperation of a first leakage protection circuit, a first control circuit, a second control circuit, a third control circuit, a fourth control circuit, and an output control circuit to avoid leakage problems in the first node of the shift register unit. Specifically, the first leakage protection circuit responds to the signals at the first drive input terminal and the clock signal terminal to control the signal at the first node, thereby preventing voltage instability of the signal at the first node and thus avoiding affecting the signal output by the shift register unit, thereby improving display quality.

[0102] In some embodiments of this disclosure, as shown in FIG2, the first leakage protection circuit 110 includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a first capacitor C1; wherein, the gate of the first transistor T1 is coupled to the first drive input terminal G(n-1), the first electrode of the first transistor T1 is coupled to the third reference voltage signal terminal VH3, and the second electrode of the first transistor T1 is coupled to the second electrode of the second transistor T2; the gate of the second transistor T2 is coupled to the clock signal terminal CK, and the first electrode of the second transistor T2 is coupled to the initialization signal terminal RE; the gate of the third transistor T3 is coupled to the second electrode of the first transistor T1, the first electrode of the third transistor T3 is coupled to the fourth reference voltage signal terminal Tou4, and the second electrode of the third transistor T3 is coupled to the first electrode of the fourth transistor T4; the gate of the fourth transistor T4 is coupled to the first electrode of the fourth transistor T4, and the second electrode of the fourth transistor T4 is coupled to the first node N1; the first plate of the first capacitor C1 is coupled to the gate of the third transistor T3, and the second plate of the first capacitor C1 is coupled to the second electrode of the third transistor T3.

[0103] For example, the first transistor T1 can be turned on under the control of the effective level of the first drive input signal transmitted at the first drive input terminal G(n-1), and can be turned off under the control of the ineffective level of the first drive input signal. For example, if the first transistor T1 is set as an N-type transistor, then the effective level of the first drive input signal is a high level, and the ineffective level of the first drive input signal is a low level. Alternatively, if the first transistor T1 is set as a P-type transistor, then the effective level of the first drive input signal is a low level, and the ineffective level of the first drive input signal is a high level.

[0104] For example, the second transistor T2 can be turned on under the control of the effective level of the clock signal transmitted at the clock signal terminal CK, and can be turned off under the control of the ineffective level of the clock signal. For example, if the second transistor T2 is set as an N-type transistor, then the effective level of the clock signal is high and the ineffective level of the clock signal is low. Alternatively, if the second transistor T2 is set as a P-type transistor, then the effective level of the clock signal is low and the ineffective level of the clock signal is high.

[0105] In some embodiments of this disclosure, as shown in FIG2, the first control circuit 120 includes: a first control transistor M1, a second control transistor M2, and a third control transistor M3; wherein, the gate of the first control transistor M1 is coupled to the first cascade input terminal Out_C(n-1), the first terminal of the first control transistor M1 is coupled to the first cascade input terminal Out_C(n-1), and the second terminal of the first control transistor M1 is coupled to the first node N1; the gate of the second control transistor M2 is coupled to the second cascade input terminal Out_C(n+1), the first terminal of the second control transistor M2 is coupled to the first node N1, and the second terminal of the second control transistor M2 is coupled to the first reference voltage signal terminal VGL1; the gate of the third control transistor M3 is coupled to the reset signal terminal TRST, the first terminal of the third control transistor M3 is coupled to the first node N1, and the second terminal of the third control transistor M3 is coupled to the first reference voltage signal terminal VGL1.

[0106] For example, the first control transistor M1 can be turned on under the control of the valid level of the first cascaded input signal transmitted at the first cascaded input terminal Out_C(n-1), and can be turned off under the control of the invalid level of the first cascaded input signal. For example, if the first control transistor M1 is set to an N-type transistor, then the valid level of the first cascaded input signal is a high level, and the invalid level of the first cascaded input signal is a low level. Alternatively, if the first control transistor M1 is set to a P-type transistor, then the valid level of the first cascaded input signal is a low level, and the invalid level of the first cascaded input signal is a high level.

[0107] For example, the second control transistor M2 can be turned on under the control of the valid level of the second cascaded input signal transmitted at the second cascaded input terminal Out_C(n+1), and can be turned off under the control of the invalid level of the second cascaded input signal. For example, if the second control transistor M2 is set to an N-type transistor, then the valid level of the second cascaded input signal is a high level, and the invalid level of the second cascaded input signal is a low level. Alternatively, if the second control transistor M2 is set to a P-type transistor, then the valid level of the second cascaded input signal is a low level, and the invalid level of the second cascaded input signal is a high level.

[0108] For example, the third control transistor M3 can be turned on under the control of the valid level of the reset signal transmitted at the reset signal terminal TRST, and can be turned off under the control of the invalid level of the reset signal. For example, if the third control transistor M3 is set as an N-type transistor, then the valid level of the reset signal is a high level, and the invalid level of the reset signal is a low level. Alternatively, if the third control transistor M3 is set as a P-type transistor, then the valid level of the reset signal is a low level, and the invalid level of the reset signal is a high level.

[0109] In some embodiments of this disclosure, as shown in FIG2, the second control circuit 130 includes: a tenth control transistor M10; wherein, the gate of the tenth control transistor M10 is coupled to the second node N2, the first terminal of the tenth control transistor M10 is coupled to the first node N1, and the second terminal of the tenth control transistor M10 is coupled to the first reference voltage signal terminal VGL1.

[0110] For example, the tenth control transistor M10 can be turned on under the control of the effective level of the signal transmitted on the second node N2, and can be turned off under the control of the ineffective level of the signal transmitted on the second node N2. For example, if the tenth control transistor M10 is set as an N-type transistor, then the effective level of the signal transmitted on the second node N2 is a high level, and the ineffective level of the signal transmitted on the second node N2 is a low level. Alternatively, if the tenth control transistor M10 is set as a P-type transistor, then the effective level of the signal transmitted on the second node N2 is a low level, and the ineffective level of the signal transmitted on the second node N2 is a high level.

[0111] In some embodiments of this disclosure, as shown in FIG2, the third control circuit 140 includes: a thirteenth control transistor M13, a fourteenth control transistor M14, and a fifteenth control transistor M15; wherein, the gate of the thirteenth control transistor M13 is coupled to the first power supply terminal VDD1, the first terminal of the thirteenth control transistor M13 is coupled to the first power supply terminal VDD1, and the second terminal of the thirteenth control transistor M13 is coupled to the second node N2; the gate of the fourteenth control transistor M14 is coupled to the first cascaded input terminal Out_C(n-1), the first terminal of the fourteenth control transistor M14 is coupled to the second node N2, and the second terminal of the fourteenth control transistor M14 is coupled to the first reference voltage signal terminal VGL1; the gate of the fifteenth control transistor M15 is coupled to the first node N1, the first terminal of the fifteenth control transistor M15 is coupled to the second node N2, and the second terminal of the fifteenth control transistor M15 is coupled to the first reference voltage signal terminal VGL1.

[0112] For example, the thirteenth control transistor M13 can be turned on under the control of the effective level of the first power supply signal transmitted at the first power supply terminal VDD1, and can be turned off under the control of the ineffective level of the first power supply signal. For example, if the thirteenth control transistor M13 is set as an N-type transistor, then the effective level of the first power supply signal is a high level, and the ineffective level of the first power supply signal is a low level. Alternatively, if the thirteenth control transistor M13 is set as a P-type transistor, then the effective level of the first power supply signal is a low level, and the ineffective level of the first power supply signal is a high level.

[0113] For example, the fourteenth control transistor M14 can be turned on under the control of the valid level of the first cascade input signal transmitted at the first cascade input terminal Out_C(n-1), and can be turned off under the control of the invalid level of the first cascade input signal. For example, if the fourteenth control transistor M14 is set as an N-type transistor, then the valid level of the first cascade input signal is a high level, and the invalid level of the first cascade input signal is a low level. Alternatively, if the fourteenth control transistor M14 is set as a P-type transistor, then the valid level of the first cascade input signal is a low level, and the invalid level of the first cascade input signal is a high level.

[0114] For example, the fifteenth control transistor M15 can be turned on under the control of the effective level of the signal transmitted on the first node N1, and can be turned off under the control of the ineffective level of the signal transmitted on the first node N1. For example, if the fifteenth control transistor M15 is set as an N-type transistor, then the effective level of the signal transmitted on the first node N1 is a high level, and the ineffective level of the signal transmitted on the first node N1 is a low level. Alternatively, if the fifteenth control transistor M15 is set as a P-type transistor, then the effective level of the signal transmitted on the first node N1 is a low level, and the ineffective level of the signal transmitted on the first node N1 is a high level.

[0115] In some embodiments of this disclosure, as shown in FIG2, the fourth control circuit 150 includes: a sixteenth control transistor M16 and a seventeenth control transistor M17; wherein, the gate of the sixteenth control transistor M16 is coupled to the second node N2, the first terminal of the sixteenth control transistor M16 is coupled to the cascaded output terminal Out_C(n), and the second terminal of the sixteenth control transistor M16 is coupled to the first reference voltage signal terminal VGL1; the gate of the seventeenth control transistor M17 is coupled to the second node N2, the first terminal of the seventeenth control transistor M17 is coupled to the drive output terminal G(n), and the second terminal of the seventeenth control transistor M17 is coupled to the second reference voltage signal terminal VGL2.

[0116] For example, the sixteenth control transistor M16 and the seventeenth control transistor M17 can be turned on under the control of the effective level of the signal transmitted on the second node N2, and can be turned off under the control of the ineffective level of the signal transmitted on the second node N2. For example, if the sixteenth control transistor M16 and the seventeenth control transistor M17 are N-type transistors, then the effective level of the signal transmitted on the second node N2 is a high level, and the ineffective level of the signal transmitted on the second node N2 is a low level. Alternatively, if the sixteenth control transistor M16 and the seventeenth control transistor M17 are P-type transistors, then the effective level of the signal transmitted on the second node N2 is a low level, and the ineffective level of the signal transmitted on the second node N2 is a high level.

[0117] In some embodiments of this disclosure, as shown in FIG2, the output control circuit 160 includes: a first output transistor MC1, a second output transistor MC2, and a second capacitor C2; wherein, the gate of the first output transistor MC1 is coupled to the first node N1, the first electrode of the first output transistor MC1 is coupled to the clock signal terminal CK, and the second electrode of the first output transistor MC1 is coupled to the cascaded output terminal G(n); the gate of the second output transistor MC2 is coupled to the first node N1, the first electrode of the second output transistor MC2 is coupled to the clock signal terminal CK, and the second electrode of the second output transistor MC2 is coupled to the drive output terminal G(n); the first electrode of the second capacitor C2 is coupled to the gate of the second output transistor MC2, and the second electrode of the second capacitor C2 is coupled to the drive output terminal G(n).

[0118] For example, the first output transistor MC1 and the second output transistor MC2 can be turned on under the control of the effective level of the signal transmitted on the first node N1, and can be turned off under the control of the ineffective level of the signal transmitted on the first node N1. For example, if the first output transistor MC1 and the second output transistor MC2 are configured as N-type transistors, then the effective level of the signal transmitted on the first node N1 is high, and the ineffective level of the signal transmitted on the first node N1 is low. Alternatively, if the first output transistor MC1 and the second output transistor MC2 are configured as P-type transistors, then the effective level of the signal transmitted on the first node N1 is low, and the ineffective level of the signal transmitted on the first node N1 is high.

[0119] In some embodiments of this disclosure, as shown in FIG2, a fifth control circuit 170 is further included, configured to provide a signal of the second reference voltage signal terminal VGL2 to the drive output terminal G(n) in response to a signal of the second drive input terminal G(n+1).

[0120] In some embodiments of this disclosure, as shown in FIG2, the fifth control circuit 170 includes: an eighteenth control transistor M18; wherein, the gate of the eighteenth control transistor M18 is coupled to the second drive input terminal G(n+1), the first terminal of the eighteenth control transistor M18 is coupled to the drive output terminal G(n), and the second terminal of the eighteenth control transistor M18 is coupled to the second reference voltage signal terminal VGL2.

[0121] For example, the eighteenth control transistor M18 can be turned on under the control of the effective level of the second drive input signal transmitted at the second drive input terminal G(n+1), and can be turned off under the control of the ineffective level of the second drive input signal. For example, if the eighteenth control transistor M18 is configured as an N-type transistor, then the effective level of the second drive input signal is high, and the ineffective level of the second drive input signal is low. Alternatively, if the eighteenth control transistor M18 is configured as a P-type transistor, then the effective level of the second drive input signal is low, and the ineffective level of the second drive input signal is high.

[0122] For example, the first electrode of the transistor described above can be its source, and the second electrode can be its drain. Alternatively, the first electrode can be its drain, and the second electrode can be its source. No limitation is made here.

[0123] For example, the active layer material of the transistor in the shift register unit can be any one or more of metal oxide, amorphous silicon (a-Si), polycrystalline silicon (p-Si), and low temperature polycrystalline silicon (LTPS), wherein the active layer material of the transistor in the shift register unit is preferably a metal oxide transistor.

[0124] For example, the active layer material of the transistor in the shift register unit may include: metal oxide materials and / or metal oxide nitride materials. Metal oxide materials include, but are not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. Metal oxide nitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. The active layer material can be amorphous, partially crystalline, single-crystal or polycrystalline, and can also be a single-layer or multi-layer structure.

[0125] As shown in FIG3, in this embodiment of the present disclosure, a method for driving a shift register unit is provided, which may include the following steps:

[0126] S100, First stage: The first leakage protection circuit responds to the signal at the first drive input terminal and controls the signal at the first node; the first control circuit responds to the signal at the first cascade input terminal and provides the signal at the first cascade input terminal to the first node; the third control circuit responds to the signals at the first cascade input terminal, the first power supply terminal, and the first node and controls the signal at the second node; the output control circuit responds to the signal at the first node and provides the signal at the clock signal terminal to the cascade output terminal and the drive output terminal.

[0127] S200, Second stage: The first control circuit responds to the signal at the reset signal terminal and provides the signal at the first reference voltage signal terminal to the first node; the third control circuit responds to the signals at the first power supply terminal and the first node and controls the signals at the second node; the output control circuit responds to the signals at the first node and provides the signal at the clock signal terminal to the cascaded output terminal and the drive output terminal.

[0128] S300, the third stage, the third control circuit responds to the signals on the first power supply terminal and the first node, and controls the signals on the second node; the output control circuit responds to the signals on the first node, and provides the clock signal terminal to the cascaded output terminal and the drive output terminal.

[0129] S400, fourth stage: the first leakage protection circuit responds to the signal at the clock signal terminal and controls the signal at the first node; the third control circuit responds to the signals at the first power supply terminal and the first node and controls the signal at the second node; the output control circuit responds to the signal at the first node and provides the signal at the clock signal terminal to the cascaded output terminal and the drive output terminal.

[0130] S500, Fifth Stage: The first control circuit responds to the signal at the second cascade input terminal and provides the signal at the first reference voltage signal terminal to the first node; the second control circuit responds to the signal at the second node and provides the signal at the first reference voltage signal terminal to the first node; the third control circuit responds to the signal at the first power supply terminal and controls the signal at the second node; the fourth control circuit responds to the signal at the second node and provides the signal at the first reference voltage signal terminal to the cascade output terminal and the signal at the second reference voltage signal terminal to the drive output terminal.

[0131] S600, sixth stage: the first leakage protection circuit responds to the signal at the clock signal terminal and controls the signal on the first node; the second control circuit responds to the signal on the second node and provides the signal at the first reference voltage signal terminal to the first node; the third control circuit responds to the signal at the first power supply terminal and controls the signal on the second node; the fourth control circuit responds to the signal on the second node and provides the signal at the first reference voltage signal terminal to the cascaded output terminal and the signal at the second reference voltage signal terminal to the drive output terminal.

[0132] The following description uses the structure of the shift register unit shown in Figure 2 as an example, and in conjunction with the signal timing diagram shown in Figure 4, to describe the working process of the shift register unit provided in the embodiments of this disclosure.

[0133] As shown in Figure 4, out_c(n-1) represents the first cascaded input signal of the first cascaded input terminal Out_C(n-1), ck represents the clock signal of the clock signal terminal CK, trst represents the reset signal of the reset signal terminal TRST, vgl1 represents the first reference voltage signal of the first reference voltage signal terminal VGL1, vdd1 represents the first power supply signal of the first power supply terminal VDD1, vh3 represents the third reference voltage signal of the third reference voltage signal terminal VH3, re represents the initialization signal of the initialization signal terminal RE, tou4 represents the fourth reference voltage signal of the fourth reference voltage signal terminal Tou4, g (n-1) represents the first drive input signal of the first drive input terminal G(n-1), g(n) represents the drive output signal of the drive output terminal G(n), g(n+1) represents the second drive input signal of the second drive input terminal G(n+1), out_c(n) represents the cascade output signal of the cascade output terminal Out_C(n), out_c(n+1) represents the second cascade input signal of the second cascade input terminal Out_C(n+1), an represents the signal on node A(n), bn represents the signal on node B(n), n1 represents the signal on the first node N1, and n2 represents the signal on the second node N2.

[0134] As shown in Figure 4, F1 and F3 represent the display stage, F2 represents the touch scanning stage, and F4 represents the blank stage.

[0135] In the first stage t1, the first transistor T1 is turned on under the control of the high level of the first drive input signal g(n-1), providing the third reference voltage signal vh3 of the third reference voltage signal terminal VH3 to the gate of the third transistor T3, that is, to node A(n). Then the voltage value of the signal an on A(n) is Vh-Vth_T1, where Vh represents the voltage value of the third reference voltage signal vh3 of the third reference voltage signal terminal VH3, and Vth_T1 represents the threshold voltage of the first transistor T1; the second transistor T2 is turned off under the control of the low level of the clock signal ck; since the fourth reference voltage signal tou4 of the fourth reference voltage signal terminal Tou4 is a low level signal, and the signal an on A(n) is... If the voltage value is Vh-Vth_T1, then the gate-source voltage difference of the third transistor T3 is greater than the threshold voltage of the third transistor T3, so the third transistor T3 is turned on. The turned-on third transistor T3 provides the fourth reference voltage signal tou4 from the fourth reference voltage signal terminal Tou4 to node B(n). Then the voltage value of the signal bn at node B(n) is Vl, that is, the signal bn at node B(n) is low level, where Vl represents the voltage value of the fourth reference voltage signal tou4 at the fourth reference voltage signal terminal Tou4. The fourth transistor T4 is turned off under the control of the low level of the signal bn at node B(n). The first control transistor M1 transmits the first cascade input at the first cascade input terminal Out_C(n-1). When the signal out_c(n-1) is high, the first control transistor M1 is turned on, providing the first cascaded input signal out_c(n-1) to the first node N1. The voltage value of signal n1 at the first node N1 is then Vh - Vth_M1, where Vh can also represent the voltage value of the first cascaded input signal out_c(n-1) at the first cascaded input terminal Out_C(n-1), and Vth_M1 represents the threshold voltage of the first control transistor M1. The second control transistor M2 is turned off when the second cascaded input signal out_c(n+1) transmitted at the second cascaded input terminal Out_C(n+1) is low. The third control transistor M3 is turned off when the reset signal TRST is transmitted... The reset signal trst is turned off when it is low; the tenth control transistor M10 is turned off when the signal transmitted on the second node N2 is low; the thirteenth control transistor M13 can be turned on when the first power signal vdd1 transmitted on the first power supply terminal VDD1 is high, and the turned-on thirteenth control transistor M13 provides the first power signal vdd1 to the second node N2; the fourteenth control transistor M14 is turned on when the first cascade input signal out_c(n-1) transmitted on the first cascade input terminal Out_C(n-1) is high, and the turned-on fourteenth control transistor M14 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the second node N2;The fifteenth control transistor M15 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on fifteenth control transistor M15 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the second node N2; then the voltage value of the signal n2 on the second node N2 is Vl, where Vl can also represent the voltage value of the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1; the sixteenth control transistor M16 and the seventeenth control transistor M17 are turned off under the control of the low level of the signal transmitted on the second node N2; the eighteenth control transistor M18 is turned off under the control of the low level of the second drive input signal g(n+1) transmitted on the second drive input terminal G(n+1); the first output transistor M... C1 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on first output transistor MC1 provides the clock signal ck transmitted from the clock signal terminal CK to the cascaded output terminal Out_C(n). Since the clock signal ck transmitted from the clock signal terminal CK is low, the cascaded output signal out_c(n) of the cascaded output terminal Out_C(n) is low. The second output transistor MC2 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on second output transistor MC2 provides the clock signal ck transmitted from the clock signal terminal CK to the drive output terminal G(n). Since the clock signal ck transmitted from the clock signal terminal CK is low, the drive output signal g(n) of the drive output terminal G(n) is low.

[0136] In the second stage t2, the first transistor T1 is cut off under the control of the low level of the first drive input signal g(n-1); the second transistor T2 is cut off under the control of the low level of the clock signal ck; then the voltage value of the signal an on A(n) remains at Vh-Vth_T1; since the fourth reference voltage signal tou4 at the fourth reference voltage signal terminal Tou4 is a low level signal, and the voltage value of the signal an on A(n) is Vh-Vth_T1, the gate-source voltage difference of the third transistor T3 is greater than the threshold voltage of the third transistor T3, so the third transistor T3 is turned on. The turned-on third transistor T3 provides the fourth reference voltage signal tou4 at the fourth reference voltage signal terminal Tou4 to node B(n). If the voltage value of signal bn at node B(n) is Vl, then signal bn at node B(n) is at a low level; the fourth transistor T4 is cut off under the control of the low level of signal bn at node B(n); the first control transistor M1 is cut off under the control of the low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1); the second control transistor M2 is cut off under the control of the low level of the second cascade input signal out_c(n+1) transmitted at the second cascade input terminal Out_C(n+1); the third control transistor M3 is turned on under the control of the high level of the reset signal trst transmitted at the reset signal terminal TRST, and the turned-on third control transistor... Transistor M3 provides the first reference voltage signal vgl1 from the first reference voltage signal terminal VGL1 to the first node N1. The voltage value of signal n1 on the first node N1 gradually changes from Vh-Vth_M1 to Vl. The tenth control transistor M10 is turned off under the control of the low level of the signal transmitted on the second node N2. The thirteenth control transistor M13 can be turned on under the control of the high level of the first power signal vdd1 transmitted from the first power terminal VDD1. The turned-on thirteenth control transistor M13 provides the first power signal vdd1 to the second node N2; therefore, the voltage value of signal n2 on the second node N2 is Vl. The fourteenth control transistor M14 is at the first cascade input terminal Out_C(n-1). The first cascaded input signal out_c(n-1) is cut off under the control of a low level; the fifteenth control transistor M15 is initially turned on under the control of a high level of the signal transmitted on the first node N1, and the turned-on fifteenth control transistor M15 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the second node N2; then the voltage value of the signal n2 on the second node N2 is Vl; then after the voltage value of the signal n1 on the first node N1 gradually changes from Vh-Vth_M1 to Vl, the fifteenth control transistor M15 is turned off; the sixteenth control transistor M16 and the seventeenth control transistor M17 are cut off under the control of a low level of the signal transmitted on the second node N2.The eighteenth control transistor M18 is cut off under the control of the low level of the second drive input signal g(n+1) transmitted at the second drive input terminal G(n+1); the first output transistor MC1 is turned on under the control of the high level of the signal transmitted at the first node N1. The turned-on first output transistor MC1 provides the clock signal ck transmitted at the clock signal terminal CK to the cascaded output terminal Out_C(n). Since the clock signal ck transmitted at the clock signal terminal CK is at a low level, the cascaded output signal out_c(n) of the cascaded output terminal Out_C(n) is at a low level; the second output transistor MC2 is turned on under the control of the high level of the signal transmitted at the first node N1. The turned-on second output transistor MC2 provides the clock signal ck transmitted at the clock signal terminal CK to the drive output terminal G(n). Since the clock signal ck transmitted at the clock signal terminal CK is at a low level, the drive output signal g(n) of the drive output terminal G(n) is at a low level.

[0137] In the third stage t3, the first transistor T1 is cut off under the control of the low level of the first drive input signal g(n-1); the second transistor T2 is cut off under the control of the low level of the clock signal ck; the fourth reference voltage signal tou4 at the fourth reference voltage signal terminal Tou4 is at a high level, but the process of loading the fourth reference voltage signal tou4 from a low level to a high level is not completed instantaneously, and the voltage value of the signal an on A(n) is initially maintained at Vh-Vth_T1 of the previous stage. Therefore, the gate-source voltage difference of the third transistor T3 is initially greater than the threshold voltage of the third transistor T3, so the third transistor T3 is turned on. The turned-on third transistor T3 will turn on the fourth reference voltage signal. The fourth reference voltage signal tou4 at terminal Tou4 is provided to node B(n), so the voltage value of signal bn at node B(n) is Vh, that is, signal bn at node B(n) is at a high level. Here, Vh can also represent the voltage value of the fourth reference voltage signal tou4 at terminal Tou4. Then, the voltage value of signal an at A(n) in the previous stage is Vh-Vth_T1. Due to the coupling effect of the first capacitor C1, the voltage value of signal an at A(n) is Vh-Vth_T1+ΔV1, where ΔV1 represents the coupling change value caused by the first capacitor C1. The fourth transistor T4 is turned on under the control of the high level of signal bn at node B(n). The turned-on fourth transistor T4 When the signal bn at node B(n) is provided to the first node N1, the voltage value of the signal n1 at the first node N1 is Vh-Vth_T4, where Vth_T4 represents the threshold voltage of the fourth transistor T4; the first control transistor M1 is cut off under the control of the low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1); the second control transistor M2 is cut off under the control of the low level of the second cascade input signal out_c(n+1) transmitted at the second cascade input terminal Out_C(n+1); the third control transistor M3 is cut off under the control of the low level of the reset signal trst transmitted at the reset signal terminal TRST; the tenth control transistor M10 is cut off in the second section. The thirteenth control transistor M13 is turned off under the control of the low level of the signal transmitted on the first power supply terminal VDD1; the thirteenth control transistor M13 can be turned on under the control of the high level of the first power supply signal vdd1 transmitted on the first power supply terminal VDD1, and the turned-on thirteenth control transistor M13 provides the first power supply signal vdd1 to the second node N2; the fourteenth control transistor M14 is turned off under the control of the low level of the first cascade input signal out_c(n-1) transmitted on the first cascade input terminal Out_C(n-1); the fifteenth control transistor M15 is turned on under the control of the high level of the signal transmitted on the first node N1, and the turned-on fifteenth control transistor M15 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the second node N2;The voltage value of signal n2 on the second node N2 is Vl; the sixteenth control transistor M16 and the seventeenth control transistor M17 are cut off under the control of the low level of the signal transmitted on the second node N2; the eighteenth control transistor M18 is cut off under the control of the low level of the second drive input signal g(n+1) transmitted at the second drive input terminal G(n+1); the first output transistor MC1 is turned on under the control of the high level of the signal transmitted on the first node N1, and the turned-on first output transistor MC1 provides the clock signal ck transmitted at the clock signal terminal CK to the cascaded output. Since the clock signal ck transmitted from the clock signal terminal CK is low, the cascade output signal out_c(n) of the cascade output terminal Out_C(n) is low. The second output transistor MC2 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on second output transistor MC2 provides the clock signal ck transmitted from the clock signal terminal CK to the drive output terminal G(n). Since the clock signal ck transmitted from the clock signal terminal CK is low, the drive output signal g(n) of the drive output terminal G(n) is low.

[0138] In the fourth stage t4, the first transistor T1 is cut off under the control of the low level of the first drive input signal g(n-1); the second transistor T2 is turned on under the control of the high level of the clock signal ck. The turned-on second transistor T2 provides the initialization signal re of the initialization signal terminal RE to the gate of the third transistor T3, that is, to node A(n). Since the initialization signal re of the initialization signal terminal RE is low, the signal an on A(n) is also low, so the voltage value of the signal an on A(n) is Vl, where Vl can also represent the voltage value of the initialization signal re of the initialization signal terminal RE; the third transistor T3 is controlled by the low level of the signal an on A(n). When the signal bn at node B(n) is low, the signal bn at node B(n) is cut off. The fourth transistor T4 is then cut off under the control of the low level of the signal bn at node B(n). Since the voltage value of the signal n1 at the first node N1 in the previous stage is Vh-Vth_T4, due to the coupling effect of the second capacitor C2, the voltage value of the signal n1 at the first node N1 changes to Vh-Vth_T4+ΔV2, where V2 represents the coupling change value caused by the second capacitor C2. The first control transistor M1 is cut off under the control of the low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1). The second control transistor M2 is cut off at the second cascade input terminal... The second cascaded input signal out_c(n+1) transmitted at Out_C(n+1) is cut off under the control of a low level of the second cascaded input signal out_c(n+1); the third control transistor M3 is cut off under the control of a low level of the reset signal trst transmitted at the reset signal terminal TRST; the tenth control transistor M10 is cut off under the control of a low level of the signal transmitted at the second node N2; the thirteenth control transistor M13 can be turned on under the control of a high level of the first power signal vdd1 transmitted at the first power supply terminal VDD1, and the turned-on thirteenth control transistor M13 provides the first power signal vdd1 to the second node N2; the fourteenth control transistor M14 is cut off under the control of a high level of the first power signal vdd1 transmitted at the first cascaded input terminal Out_C(n-1). The cascaded input signal out_c(n-1) is cut off under the control of a low level; the fifteenth control transistor M15 is turned on under the control of a high level of the signal transmitted on the first node N1, and the turned-on fifteenth control transistor M15 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the second node N2; then the voltage value of the signal n2 on the second node N2 is Vl; the sixteenth control transistor M16 and the seventeenth control transistor M17 are cut off under the control of a low level of the signal transmitted on the second node N2; the eighteenth control transistor M18 is cut off under the control of a low level of the second drive input signal g(n+1) transmitted on the second drive input terminal G(n+1);The first output transistor MC1 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on first output transistor MC1 provides the clock signal ck transmitted from the clock signal terminal CK to the cascaded output terminal Out_C(n). Since the clock signal ck transmitted from the clock signal terminal CK is at a high level, the cascaded output signal out_c(n) of the cascaded output terminal Out_C(n) is at a high level. The second output transistor MC2 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on second output transistor MC2 provides the clock signal ck transmitted from the clock signal terminal CK to the drive output terminal G(n). Since the clock signal ck transmitted from the clock signal terminal CK is at a high level, the drive output signal g(n) of the drive output terminal G(n) is at a high level.

[0139] In the fifth stage t5, the first transistor T1 is cut off under the control of the low level of the first drive input signal g(n-1); the second transistor T2 is cut off under the control of the low level of the clock signal ck; since the signal an on A(n) remains low, the third transistor T3 is cut off under the control of the low level of the signal an on A(n); the signal bn on node B(n) is low; the fourth transistor T4 is cut off under the control of the low level of the signal bn on node B(n); initially, the voltage value of the signal n1 on the first node N1 is maintained at Vh-Vth_T4. +△V2; The first control transistor M1 is cut off under the control of the low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1); The second control transistor M2 is turned on under the control of the high level of the second cascade input signal out_c(n+1) transmitted at the second cascade input terminal Out_C(n+1), and the turned-on second control transistor M2 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the first node N1; The third control transistor M3 is reset under the control of the reset signal transmitted at the reset signal terminal TRST. The signal trst is cut off under the control of a low level; the tenth control transistor M10 is turned on under the control of a high level of the signal transmitted on the second node N2, and the turned-on tenth control transistor M10 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the first node N1; then the signal n1 on the first node N1 is gradually pulled low; the thirteenth control transistor M13 can be turned on under the control of a high level of the first power signal vdd1 transmitted on the first power terminal VDD1, and the turned-on thirteenth control transistor M13 provides the first power signal vdd1 to the first node N1. Provided to the second node N2; then the voltage value of signal n2 on the second node N2 is Vh-Vth_M13, where Vh can also represent the voltage value of the first power supply signal vdd1 at the first power supply terminal VDD1, and Vth_M13 represents the threshold voltage of the thirteenth control transistor M13; the fourteenth control transistor M14 is turned off under the control of the low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1); the fifteenth control transistor M15 is turned off under the control of the low level of the signal transmitted on the first node N1;The sixteenth control transistor M16 and the seventeenth control transistor M17 are turned on under the control of the high level of the signal transmitted on the second node N2. The turned-on sixteenth control transistor M16 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the cascade output terminal Out_C(n). Since the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 is at a low level, the cascade output signal out_c(n) of the cascade output terminal Out_C(n) is at a low level. The turned-on seventeenth control transistor M17 provides the second reference voltage signal vgl2 of the second reference voltage signal terminal VGL2 to the drive output terminal G(n). Since the second reference voltage signal vgl2 of the second reference voltage signal terminal VGL2 is at a low level, the drive output signal g(n) of the drive output terminal G(n) is at a low level. The eighteenth control transistor M18 is turned on under the control of the high level of the second drive input signal g(n+1) transmitted on the second drive input terminal G(n+1). The turned-on eighteenth control transistor M18 provides the second reference voltage signal vgl2 of the second reference voltage signal terminal VGL2 to the drive output terminal G(n+1). Voltage signal vgl2 is provided to the drive output terminal G(n); the first output transistor MC1 and the second output transistor MC2 are initially turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on first output transistor MC1 provides the clock signal ck transmitted from the clock signal terminal CK to the cascaded output terminal Out_C(n). Since the clock signal ck transmitted from the clock signal terminal CK is at a low level, the cascaded output signal out_c(n) of the cascaded output terminal Out_C(n) is at a low level; the second output transistor MC2 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on second output transistor MC2 provides the clock signal ck transmitted from the clock signal terminal CK to the drive output terminal G(n). Since the clock signal ck transmitted from the clock signal terminal CK is at a low level, the drive output signal g(n) of the drive output terminal G(n) is at a low level; then, after the signal n1 on the first node N1 is gradually pulled low, the first output transistor MC1 and the second output transistor MC2 are turned off under the control of the low level of the signal transmitted on the first node N1.

[0140] In stage t6, the first transistor T1 is cut off under the control of the low level of the first drive input signal g(n-1); the second transistor T2 is turned on under the control of the high level of the clock signal ck. The turned-on second transistor T2 provides the initialization signal re of the initialization signal terminal RE to the gate of the third transistor T3, that is, to node A(n). Since the initialization signal re of the initialization signal terminal RE is low, the signal an on A(n) is also low, so the voltage value of the signal an on A(n) is Vl; the third transistor T3 is cut off under the control of the low level of the signal an on A(n); so the signal bn on node B(n) is low; the fourth transistor T4 is cut off under the control of the low level of the signal bn on node B(n); the first control transistor M1 is cut off under the control of the low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1); the second control transistor M2 is cut off under the control of the low level of the second cascade input signal out_c(n+1) transmitted at the second cascade input terminal Out_C(n+1). The first control transistor M10 is turned off under the control of a low level; the third control transistor M3 is turned off under the control of a low level of the reset signal trst transmitted at the reset signal terminal TRST; the tenth control transistor M10 is turned on under the control of a high level of the signal transmitted at the second node N2, and the turned-on tenth control transistor M10 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the first node N1; then the voltage value of the signal n1 at the first node N1 is Vl; the thirteenth control transistor M13 can be turned on under the control of a high level of the first power signal vdd1 transmitted at the first power terminal VDD1, and the turned-on thirteenth control transistor M13 provides the first power signal vdd1 to the second node N2; then the voltage value of the signal n2 at the second node N2 is Vh-Vth_M13; the fourteenth control transistor M14 is turned off under the control of a low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1); the fifteenth control transistor M15 is turned off under the control of a low level of the signal transmitted at the first node N1.The sixteenth control transistor M16 and the seventeenth control transistor M17 are turned on under the control of the high level of the signal transmitted on the second node N2. The turned-on sixteenth control transistor M16 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the cascaded output terminal Out_C(n). Since the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 is at a low level, the cascaded output signal out_c(n) of the cascaded output terminal Out_C(n) is at a low level. The turned-on seventeenth control transistor M17 provides the second reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the cascaded output terminal Out_C(n). The second reference voltage signal vgl2 of the voltage signal terminal VGL2 is provided to the drive output terminal G(n). Since the second reference voltage signal vgl2 of the second reference voltage signal terminal VGL2 is at a low level, the drive output signal g(n) of the drive output terminal G(n) is at a low level. The eighteenth control transistor M18 is turned off under the control of the low level of the second drive input signal g(n+1) transmitted at the second drive input terminal G(n+1). The first output transistor MC1 and the second output transistor MC2 are turned off under the control of the low level of the signal transmitted on the first node N1.

[0141] This disclosure provides other structural diagrams of a shift register unit, as shown in Figure 5, which are modifications of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; similarities will not be repeated here.

[0142] In some embodiments of this disclosure, as shown in FIG5, it further includes:

[0143] The sixth control circuit 180, coupled to the first node N1 and the third node N3, is configured to provide the signal of the first reference voltage signal terminal VGL1 to the first node N1 in response to a signal on the third node N3.

[0144] The seventh control circuit 190, coupled to the first node N1 and the third node N3, is configured to control the signal on the third node N3 in response to the signals on the first cascade input terminal Out_C(n-1), the second power supply terminal VDD2 and the first node N1.

[0145] The eighth control circuit 200, coupled to the third node N3, is configured to, in response to a signal on the third node N3, provide the signal of the first reference voltage signal terminal VGL1 to the cascaded output terminal Out_C(n), and provide the signal of the second reference voltage signal terminal VGL2 to the drive output terminal G(n).

[0146] In some embodiments of this disclosure, as shown in FIG5, the sixth control circuit 180 includes: a nineteenth control transistor M19; wherein, the gate of the nineteenth control transistor M19 is coupled to the third node N3, the first terminal of the nineteenth control transistor M19 is coupled to the first node N1, and the second terminal of the nineteenth control transistor M19 is coupled to the first reference voltage signal terminal VGL1.

[0147] For example, the nineteenth control transistor M19 can be turned on under the control of the effective level of the signal transmitted on the third node N3, and can be turned off under the control of the ineffective level of the signal transmitted on the third node N3. For example, if the nineteenth control transistor M19 is set as an N-type transistor, then the effective level of the signal transmitted on the third node N3 is a high level, and the ineffective level of the signal transmitted on the third node N3 is a low level. Alternatively, if the nineteenth control transistor M19 is set as a P-type transistor, then the effective level of the signal transmitted on the third node N3 is a low level, and the ineffective level of the signal transmitted on the third node N3 is a high level.

[0148] In some embodiments of this disclosure, as shown in FIG5, the seventh control circuit 190 includes: a twenty-second control transistor M22, a twenty-third control transistor M23, and a twenty-fourth control transistor M24; wherein, the gate of the twenty-second control transistor M22 is coupled to the second power supply terminal VDD2, the first terminal of the twenty-second control transistor M22 is coupled to the second power supply terminal VDD2, and the second terminal of the twenty-second control transistor M22 is coupled to the third node N3; the gate of the twenty-third control transistor M23 is coupled to the first cascaded input terminal Out_C(n-1), the first terminal of the twenty-third control transistor M23 is coupled to the third node N3, and the second terminal of the twenty-third control transistor M23 is coupled to the first reference voltage signal terminal VGL1; the gate of the twenty-fourth control transistor M24 is coupled to the first node N1, the first terminal of the twenty-fourth control transistor M24 is coupled to the third node N3, and the second terminal of the twenty-fourth control transistor M24 is coupled to the first reference voltage signal terminal VGL1.

[0149] For example, the twenty-second control transistor M22 can be turned on under the control of the effective level of the second power supply signal transmitted at the second power supply terminal VDD2, and can be turned off under the control of the ineffective level of the second power supply signal. For example, if the twenty-second control transistor M22 is set as an N-type transistor, then the effective level of the second power supply signal is a high level, and the ineffective level of the second power supply signal is a low level. Alternatively, if the twenty-second control transistor M22 is set as a P-type transistor, then the effective level of the second power supply signal is a low level, and the ineffective level of the second power supply signal is a high level.

[0150] For example, the twenty-third control transistor M23 can be turned on under the control of the valid level of the first cascade input signal transmitted at the first cascade input terminal Out_C(n-1), and can be turned off under the control of the invalid level of the first cascade input signal. For example, if the twenty-third control transistor M23 is set as an N-type transistor, then the valid level of the first cascade input signal is a high level, and the invalid level of the first cascade input signal is a low level. Alternatively, if the twenty-third control transistor M23 is set as a P-type transistor, then the valid level of the first cascade input signal is a low level, and the invalid level of the first cascade input signal is a high level.

[0151] For example, the twenty-fourth control transistor M24 can be turned on under the control of the effective level of the signal transmitted on the first node N1, and can be turned off under the control of the ineffective level of the signal transmitted on the first node N1. For example, if the twenty-fourth control transistor M24 is set as an N-type transistor, then the effective level of the signal transmitted on the first node N1 is a high level, and the ineffective level of the signal transmitted on the first node N1 is a low level. Alternatively, if the twenty-fourth control transistor M24 is set as a P-type transistor, then the effective level of the signal transmitted on the first node N1 is a low level, and the ineffective level of the signal transmitted on the first node N1 is a high level.

[0152] In some embodiments of this disclosure, as shown in FIG5, the eighth control circuit 200 includes: a twenty-fifth control transistor M25 and a twenty-sixth control transistor M26; wherein, the gate of the twenty-fifth control transistor M25 is coupled to the third node N3, the first terminal of the twenty-fifth control transistor M25 is coupled to the cascaded output terminal Out_C(n), and the second terminal of the twenty-fifth control transistor M25 is coupled to the first reference voltage signal terminal VGL1; the gate of the twenty-sixth control transistor M26 is coupled to the third node N3, the first terminal of the twenty-sixth control transistor M26 is coupled to the drive output terminal G(n), and the second terminal of the twenty-sixth control transistor M26 is coupled to the second reference voltage signal terminal VGL2.

[0153] For example, the twenty-fifth control transistor M25 and the twenty-sixth control transistor M26 can be turned on under the control of the effective level of the signal transmitted on the third node N3, and can be turned off under the control of the ineffective level of the signal transmitted on the third node N3. For example, if the twenty-fifth control transistor M25 and the twenty-sixth control transistor M26 are configured as N-type transistors, then the effective level of the signal transmitted on the third node N3 is high, and the ineffective level of the signal transmitted on the third node N3 is low. Alternatively, if the twenty-fifth control transistor M25 and the twenty-sixth control transistor M26 are configured as P-type transistors, then the effective level of the signal transmitted on the third node N3 is low, and the ineffective level of the signal transmitted on the third node N3 is high.

[0154] For example, multiple cascaded shift register units can constitute a gate drive circuit, as shown in Figure 6. The gate drive circuit is composed of shift register units SR1, SR2, SR3, SR4...SRn and SRn+1 cascaded together. The clock signal terminal CK in shift register units SR1, SR3,...SRn is coupled to clock signal line ck1, and the clock signal terminal CK in shift register units SR2, SR4...SRn+1 is coupled to clock signal line ck2. The first power supply terminal VDD1 in shift register units SR1, SR2, SR3, SR4...SRn and SRn+1 is coupled to the first power supply line Vdd1. The second power supply terminal VDD2 in shift register units SR1, SR2, SR3, SR4...SRn and SRn+1 is coupled to the second power supply line Vdd2. The reset signal terminal TRST in shift register units SR1, SR2, SR3, SR4...SRn and SRn+1 is... The first reference voltage signal terminal VGL1 in shift register units SR1, SR2, SR3, SR4...SRn and SRn+1 is coupled to the first reference voltage signal line Vgl1; the second reference voltage signal terminal VGL2 in shift register units SR1, SR2, SR3, SR4...SRn and SRn+1 is coupled to the second reference voltage signal line Vgl2; the third reference voltage signal terminal VH3 in shift register units SR1, SR2, SR3, SR4...SRn and SRn+1 is coupled to the third reference voltage signal line Vh3; the fourth reference voltage signal terminal Tou4 in shift register units SR1, SR2, SR3, SR4...SRn and SRn+1 is coupled to the fourth reference voltage signal line Tu4; the initialization signal terminal RE in shift register units SR1, SR2, SR3, SR4...SRn and SRn+1 is coupled to the initialization signal line Re.

[0155] For example, the first drive input G(n-1) and the first cascade input Out_C(n-1) in the first-stage shift register unit SR1 are coupled to the frame start signal line STV; the second drive input G(n+1) and the second cascade input Out_C(n+1) in the first-stage shift register unit SR1 are coupled to the drive output G(n) and the cascade output Out_C(n) in the second-stage shift register unit SR2, respectively (not shown in the figure); the drive output G(n) and the cascade output Out_C(n) in the first-stage shift register unit SR1 are coupled to the gate line GA1.

[0156] The first drive input G(n-1) and the first cascade input Out_C(n-1) of the second-stage shift register unit SR2 are coupled to the drive output G(n) and the cascade output Out_C(n) of the first-stage shift register unit SR1, respectively. The second drive input G(n+1) and the second cascade input Out_C(n+1) of the second-stage shift register unit SR2 are coupled to the drive output G(n) and the cascade output Out_C(n) of the third-stage shift register unit SR3, respectively (not shown in the figure). The drive output G(n) and the cascade output Out_C(n) of the second-stage shift register unit SR2 are coupled to the gate line GA2.

[0157] The first drive input G(n-1) and the first cascade input Out_C(n-1) of the third-stage shift register unit SR3 are coupled to the drive output G(n) and the cascade output Out_C(n) of the second-stage shift register unit SR2, respectively. The second drive input G(n+1) and the second cascade input Out_C(n+1) of the third-stage shift register unit SR3 are coupled to the drive output G(n) and the cascade output Out_C(n) of the fourth-stage shift register unit SR4, respectively (not shown in the figure). The drive output G(n) and the cascade output Out_C(n) of the third-stage shift register unit SR3 are coupled to the gate line GA3.

[0158] The first drive input G(n-1) and the first cascade input Out_C(n-1) of the fourth-stage shift register unit SR4 are coupled to the drive output G(n) and the cascade output Out_C(n) of the third-stage shift register unit SR3, respectively. The second drive input G(n+1) and the second cascade input Out_C(n+1) of the fourth-stage shift register unit SR4 are coupled to the drive output G(n) and the cascade output Out_C(n) of the fifth-stage shift register unit SR5, respectively (not shown in the figure). The drive output G(n) and the cascade output Out_C(n) of the fourth-stage shift register unit SR4 are coupled to the gate line GA4.

[0159] The first drive input G(n-1) and the first cascade input Out_C(n-1) of the nth stage shift register unit SRn are coupled to the drive output G(n) and the cascade output Out_C(n) of the (n-1)th stage shift register unit SRn-1, respectively. The second drive input G(n+1) and the second cascade input Out_C(n+1) of the nth stage shift register unit SRn are coupled to the drive output G(n) and the cascade output Out_C(n) of the (n+1)th stage shift register unit SR3, respectively (not shown in the figure). The drive output G(n) and the cascade output Out_C(n) of the nth stage shift register unit SRn are coupled to the gate line GA(n).

[0160] The first drive input G(n-1) and the first cascade input Out_C(n-1) of the (n+1)th stage shift register unit SRn+1 are coupled to the drive output G(n) and the cascade output Out_C(n) of the nth stage shift register unit SRn, respectively. The second drive input G(n+1) and the second cascade input Out_C(n+1) of the (n+1)th stage shift register unit SRn+1 are coupled to the drive output G(n) and the cascade output Out_C(n) of the (n+2)th stage shift register unit SRn+2, respectively (not shown in the figure). The drive output G(n) and the cascade output Out_C(n) of the (n+1)th stage shift register unit SRn+1 are coupled to the gate line GA(n+1).

[0161] The signal timing diagram corresponding to the shift register unit shown in Figure 5 is illustrated in Figures 4 and 7. Taking the structure of the shift register unit shown in Figure 5 as an example, and referring to the working process of the signal timing diagram shown in Figure 4, the above description can be used as a reference, and will not be repeated here.

[0162] The following description uses the structure of the shift register unit shown in Figure 5 as an example, and in conjunction with the signal timing diagram shown in Figure 7, to describe the working process of the shift register unit provided in the embodiments of this disclosure.

[0163] As shown in Figure 7, out_c(n-1) represents the first cascaded input signal of the first cascaded input terminal Out_C(n-1), ck represents the clock signal of the clock signal terminal CK, trst represents the reset signal of the reset signal terminal TRST, vgl1 represents the first reference voltage signal of the first reference voltage signal terminal VGL1, vdd2 represents the second power supply signal of the second power supply terminal VDD2, vh3 represents the third reference voltage signal of the third reference voltage signal terminal VH3, re represents the initialization signal of the initialization signal terminal RE, tou4 represents the fourth reference voltage signal of the fourth reference voltage signal terminal Tou4, g (n-1) represents the first drive input signal of the first drive input terminal G(n-1), g(n) represents the drive output signal of the drive output terminal G(n), g(n+1) represents the second drive input signal of the second drive input terminal G(n+1), out_c(n) represents the cascade output signal of the cascade output terminal Out_C(n), out_c(n+1) represents the second cascade input signal of the second cascade input terminal Out_C(n+1), an represents the signal on node A(n), bn represents the signal on node B(n), n1 represents the signal on the first node N1, and n3 represents the signal on the third node N3.

[0164] As shown in Figure 7, F1 and F3 represent the display stage, F2 represents the touch scanning stage, and F4 represents the blank stage.

[0165] In the first stage t1, the first transistor T1 is turned on under the control of the high level of the first drive input signal g(n-1), providing the third reference voltage signal vh3 of the third reference voltage signal terminal VH3 to the gate of the third transistor T3, that is, to node A(n). Then the voltage value of the signal an on A(n) is Vh-Vth_T1, where Vh represents the voltage value of the third reference voltage signal vh3 of the third reference voltage signal terminal VH3, and Vth_T1 represents the threshold voltage of the first transistor T1. The second transistor T2 is turned off under the control of the low level of the clock signal ck. Since the fourth reference voltage signal tou4 of the fourth reference voltage signal terminal Tou4 is a low level signal, and the voltage value of the signal an on A(n) is Vh-Vth_T1, the voltage value of the signal an on A(n) is Vh-Vth_T1. If the voltage value is Vh-Vth_T1, then the gate-source voltage difference of the third transistor T3 is greater than the threshold voltage of the third transistor T3, so the third transistor T3 is turned on. The turned-on third transistor T3 provides the fourth reference voltage signal tou4 from the fourth reference voltage signal terminal Tou4 to node B(n). Then the voltage value of the signal bn at node B(n) is Vl, that is, the signal bn at node B(n) is low level, where Vl represents the voltage value of the fourth reference voltage signal tou4 at the fourth reference voltage signal terminal Tou4. The fourth transistor T4 is turned off under the control of the low level of the signal bn at node B(n). The first control transistor M1 transmits the first cascade input signal at the first cascade input terminal Out_C(n-1). Under the control of the high level of out_c(n-1), the first control transistor M1 is turned on, and the first cascade input signal out_c(n-1) is provided to the first node N1. Then, the voltage value of signal n1 on the first node N1 is Vh-Vth_M1, where Vh can also represent the voltage value of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1), and Vth_M1 represents the threshold voltage of the first control transistor M1. The second control transistor M2 is turned off under the control of the low level of the second cascade input signal out_c(n+1) transmitted at the second cascade input terminal Out_C(n+1). The third control transistor M3 is turned off under the control of the reset signal transmitted at the reset signal terminal TRST. The nineteenth control transistor M19 is cut off under the control of the low level of the signal transmitted on the third node N3; the twenty-second control transistor M22 can be turned on under the control of the high level of the second power signal vdd2 transmitted on the second power supply terminal VDD2, and the turned-on control transistor M22 provides the second power signal vdd2 to the third node N3; the twenty-third control transistor M23 is turned on under the control of the high level of the first cascade input signal out_c(n-1) transmitted on the first cascade input terminal Out_C(n-1), and the turned-on control transistor M14 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the third node N3;The twenty-fourth control transistor M24 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on fifteenth control transistor M15 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the third node N3; then the voltage value of the signal n3 on the third node N3 is Vl, where Vl can also represent the voltage value of the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1; the twenty-fifth control transistor M25 and the twenty-sixth control transistor M26 are turned off under the control of the low level of the signal transmitted on the third node N3; the eighteenth control transistor M18 is turned off under the control of the low level of the second drive input signal g(n+1) transmitted on the second drive input terminal G(n+1); the first output transistor... The first output transistor MC1 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on first output transistor MC1 provides the clock signal ck transmitted from the clock signal terminal CK to the cascaded output terminal Out_C(n). Since the clock signal ck transmitted from the clock signal terminal CK is at a low level, the cascaded output signal out_c(n) of the cascaded output terminal Out_C(n) is at a low level. The second output transistor MC2 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on second output transistor MC2 provides the clock signal ck transmitted from the clock signal terminal CK to the drive output terminal G(n). Since the clock signal ck transmitted from the clock signal terminal CK is at a low level, the drive output signal g(n) of the drive output terminal G(n) is at a low level.

[0166] In the second stage t2, the first transistor T1 is cut off under the control of the low level of the first drive input signal g(n-1); the second transistor T2 is cut off under the control of the low level of the clock signal ck; then the voltage value of the signal an on A(n) remains at Vh-Vth_T1; since the fourth reference voltage signal tou4 at the fourth reference voltage signal terminal Tou4 is a low level signal, and the voltage value of the signal an on A(n) is Vh-Vth_T1, the gate-source voltage difference of the third transistor T3 is greater than the threshold voltage of the third transistor T3, so the third transistor T3 is turned on. The turned-on third transistor T3 provides the fourth reference voltage signal tou4 at the fourth reference voltage signal terminal Tou4 to node B(n). The voltage value of signal bn at node B(n) is Vl, meaning signal bn at node B(n) is at a low level; the fourth transistor T4 is cut off under the control of the low level of signal bn at node B(n); the first control transistor M1 is cut off under the control of the low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1); the second control transistor M2 is cut off under the control of the low level of the second cascade input signal out_c(n+1) transmitted at the second cascade input terminal Out_C(n+1); the third control transistor M3 is turned on under the control of the high level of the reset signal trst transmitted at the reset signal terminal TRST, and the turned-on third control transistor M3 will... The first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 is provided to the first node N1, and the voltage value of the signal n1 on the first node N1 gradually changes from Vh-Vth_M1 to Vl; the nineteenth control transistor M19 is turned off under the control of the low level of the signal transmitted on the third node N3; the twenty-second control transistor M22 can be turned on under the control of the high level of the second power signal vdd2 transmitted on the second power terminal VDD2, and the turned-on twenty-second control transistor M22 provides the second power signal vdd2 to the third node N3; then the voltage value of the signal n3 on the third node N3 is Vl; the twenty-third control transistor M23 transmits the signal n3 at the first cascade input terminal Out_C(n-1)... The first cascaded input signal out_c(n-1) is cut off under the control of a low level; the twenty-fourth control transistor M24 is initially turned on under the control of a high level of the signal transmitted on the first node N1, and the turned-on twenty-fourth control transistor M24 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the third node N3; then the voltage value of the signal n3 on the third node N3 is Vl; then after the voltage value of the signal n1 on the first node N1 gradually changes from Vh-Vth_M1 to Vl, the twenty-fourth control transistor M24 is turned off; the twenty-fifth control transistor M25 and the twenty-sixth control transistor M26 are cut off under the control of a low level of the signal transmitted on the third node N3;The eighteenth control transistor M18 is cut off under the control of the low level of the second drive input signal g(n+1) transmitted at the second drive input terminal G(n+1); the first output transistor MC1 is turned on under the control of the high level of the signal transmitted at the first node N1. The turned-on first output transistor MC1 provides the clock signal ck transmitted at the clock signal terminal CK to the cascaded output terminal Out_C(n). Since the clock signal ck transmitted at the clock signal terminal CK is at a low level, the cascaded output signal out_c(n) of the cascaded output terminal Out_C(n) is at a low level; the second output transistor MC2 is turned on under the control of the high level of the signal transmitted at the first node N1. The turned-on second output transistor MC2 provides the clock signal ck transmitted at the clock signal terminal CK to the drive output terminal G(n). Since the clock signal ck transmitted at the clock signal terminal CK is at a low level, the drive output signal g(n) of the drive output terminal G(n) is at a low level.

[0167] In the third stage t3, the first transistor T1 is cut off under the control of the low level of the first drive input signal g(n-1); the second transistor T2 is cut off under the control of the low level of the clock signal ck; the fourth reference voltage signal tou4 at the fourth reference voltage signal terminal Tou4 is at a high level, but the process of loading the fourth reference voltage signal tou4 from a low level to a high level is not completed instantaneously, and the voltage value of the signal an on A(n) is initially maintained at Vh-Vth_T1 of the previous stage. Therefore, the gate-source voltage difference of the third transistor T3 is initially greater than the threshold voltage of the third transistor T3, so the third transistor T3 is turned on. The turned-on third transistor T3 will turn on the fourth reference voltage signal terminal. The fourth reference voltage signal tou4 of Tou4 is provided to node B(n), so the voltage value of signal bn at node B(n) is Vh, that is, signal bn at node B(n) is at a high level. Here, Vh can also represent the voltage value of the fourth reference voltage signal tou4 at the fourth reference voltage signal terminal Tou4; then the voltage value of signal an at A(n) in the previous stage is Vh-Vth_T1. Due to the coupling effect of the first capacitor C1, the voltage value of signal an at A(n) is Vh-Vth_T1+ΔV1, where ΔV1 represents the coupling change value brought about by the first capacitor C1; the fourth transistor T4 is turned on under the control of the high level of signal bn at node B(n), and the turned-on fourth transistor T4 will connect node The signal bn on B(n) is provided to the first node N1, then the voltage value of the signal n1 on the first node N1 is Vh-Vth_T4, where Vth_T4 represents the threshold voltage of the fourth transistor T4; the first control transistor M1 is turned off under the control of the low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1); the second control transistor M2 is turned off under the control of the low level of the second cascade input signal out_c(n+1) transmitted at the second cascade input terminal Out_C(n+1); the third control transistor M3 is turned off under the control of the low level of the reset signal trst transmitted at the reset signal terminal TRST; the nineteenth control transistor M19 is on the third node N3 The 22nd control transistor M22 is turned off under the control of a low level of the transmitted signal; the 22nd control transistor M22 can be turned on under the control of a high level of the second power supply signal vdd2 transmitted at the second power supply terminal VDD2, and the turned-on 22nd control transistor M22 provides the second power supply signal vdd2 to the third node N3; the 23rd control transistor M23 is turned off under the control of a low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1); the 24th control transistor M24 is turned on under the control of a high level of the signal transmitted at the first node N1, and the turned-on 24th control transistor M24 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the third node N3;The voltage value of signal n3 on the third node N3 is Vl; the twenty-fifth control transistor M25 and the twenty-sixth control transistor M26 are cut off under the control of the low level of the signal transmitted on the third node N3; the eighteenth control transistor M18 is cut off under the control of the low level of the second drive input signal g(n+1) transmitted at the second drive input terminal G(n+1); the first output transistor MC1 is turned on under the control of the high level of the signal transmitted on the first node N1, and the turned-on first output transistor MC1 provides the clock signal ck transmitted at the clock signal terminal CK to the cascaded output. At the output terminal Out_C(n), since the clock signal ck transmitted from the clock signal terminal CK is at a low level, the cascaded output signal out_c(n) of the cascaded output terminal Out_C(n) is at a low level; the second output transistor MC2 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on second output transistor MC2 provides the clock signal ck transmitted from the clock signal terminal CK to the drive output terminal G(n). Since the clock signal ck transmitted from the clock signal terminal CK is at a low level, the drive output signal g(n) of the drive output terminal G(n) is at a low level.

[0168] In the fourth stage t4, the first transistor T1 is cut off under the control of the low level of the first drive input signal g(n-1); the second transistor T2 is turned on under the control of the high level of the clock signal ck. The turned-on second transistor T2 provides the initialization signal re of the initialization signal terminal RE to the gate of the third transistor T3, that is, to node A(n). Since the initialization signal re of the initialization signal terminal RE is low, the signal an on A(n) is also low, so the voltage value of the signal an on A(n) is Vl, where Vl can also represent the voltage value of the initialization signal re of the initialization signal terminal RE; the third transistor T3 is cut off under the control of the low level of the signal an on A(n). If the signal bn at node B(n) is low, the fourth transistor T4 will be cut off under the control of the low level of the signal bn at node B(n). Since the voltage value of the signal n1 at the first node N1 in the previous stage is Vh-Vth_T4, due to the coupling effect of the second capacitor C2, the voltage value of the signal n1 at the first node N1 changes to Vh-Vth_T4+ΔV2, where V2 represents the coupling change value brought by the second capacitor C2. The first control transistor M1 is cut off under the control of the low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1). The second control transistor M2 is cut off at the second cascade input terminal Out_C(n-1). The second cascaded input signal out_c(n+1) transmitted by C(n+1) is cut off under the control of a low level; the third control transistor M3 is cut off under the control of a low level of the reset signal trst transmitted by the reset signal terminal TRST; the nineteenth control transistor M19 is cut off under the control of a low level of the signal transmitted on the third node N3; the twenty-second control transistor M22 can be turned on under the control of a high level of the second power supply signal vdd2 transmitted by the second power supply terminal VDD2, and the turned-on twenty-second control transistor M22 provides the second power supply signal vdd2 to the third node N3; the twenty-third control transistor M23 transmits the first cascaded input signal out_c(n-1) transmitted by the first cascaded input terminal Out_C(n-1)... The input signal out_c(n-1) is cut off under the control of a low level; the twenty-fourth control transistor M24 is turned on under the control of a high level of the signal transmitted on the first node N1, and the turned-on twenty-fourth control transistor M24 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the third node N3; then the voltage value of the signal n3 on the third node N3 is Vl; the twenty-fifth control transistor M25 and the twenty-sixth control transistor M26 are cut off under the control of a low level of the signal transmitted on the third node N3; the eighteenth control transistor M18 is cut off under the control of a low level of the second drive input signal g(n+1) transmitted on the second drive input terminal G(n+1);The first output transistor MC1 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on first output transistor MC1 provides the clock signal ck transmitted from the clock signal terminal CK to the cascaded output terminal Out_C(n). Since the clock signal ck transmitted from the clock signal terminal CK is at a high level, the cascaded output signal out_c(n) of the cascaded output terminal Out_C(n) is at a high level. The second output transistor MC2 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on second output transistor MC2 provides the clock signal ck transmitted from the clock signal terminal CK to the drive output terminal G(n). Since the clock signal ck transmitted from the clock signal terminal CK is at a high level, the drive output signal g(n) of the drive output terminal G(n) is at a high level.

[0169] In the fifth stage t5, the first transistor T1 is cut off under the control of the low level of the first drive input signal g(n-1); the second transistor T2 is cut off under the control of the low level of the clock signal ck; since the signal an on A(n) remains low, the third transistor T3 is cut off under the control of the low level of the signal an on A(n); the signal bn on node B(n) is low; the fourth transistor T4 is cut off under the control of the low level of the signal bn on node B(n); initially, the voltage value of the signal n1 on the first node N1 is maintained at Vh-Vth_T4+ △V2; The first control transistor M1 is cut off under the control of the low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1); The second control transistor M2 is turned on under the control of the high level of the second cascade input signal out_c(n+1) transmitted at the second cascade input terminal Out_C(n+1), and the turned-on second control transistor M2 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the first node N1; The third control transistor M3 transmits the reset signal t at the reset signal terminal TRST. The nineteenth control transistor M19 is turned on under the control of the low level of the signal transmitted on the third node N3. The turned-on nineteenth control transistor M19 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the first node N1; then the signal n1 on the first node N1 is gradually pulled low; the twenty-second control transistor M22 can be turned on under the control of the high level of the second power signal vdd2 transmitted on the second power terminal VDD2. The turned-on twenty-second control transistor M22 provides the second power signal vdd2 to the first node N1; then the signal n1 on the first node N1 is gradually pulled low; the twenty-second control transistor M22 can be turned on under the control of the high level of the second power signal vdd2 transmitted on the second power terminal VDD2. The turned-on twenty-second control transistor M22 provides the second power signal vdd2 to the first node N1. The power supply is supplied to the third node N3; then the voltage value of the signal n3 on the third node N3 is Vh-Vth_M13, where Vh can also represent the voltage value of the second power supply signal vdd2 at the second power supply terminal VDD2, and Vth_M13 represents the threshold voltage of the twenty-second control transistor M22; the twenty-third control transistor M23 is cut off under the control of the low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1); the twenty-fourth control transistor M24 is cut off under the control of the low level of the signal transmitted on the first node N1;The 25th control transistor M25 and the 26th control transistor M26 are turned on under the control of the high level of the signal transmitted on the third node N3. The turned-on 25th control transistor M25 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the cascade output terminal Out_C(n). Since the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 is at a low level, the cascade output signal out_c(n) of the cascade output terminal Out_C(n) is at a low level. The turned-on 26th control transistor M26 provides the second reference voltage signal vgl2 of the second reference voltage signal terminal VGL2 to the drive output terminal G(n). Since the second reference voltage signal vgl2 of the second reference voltage signal terminal VGL2 is at a low level, the drive output signal g(n) of the drive output terminal G(n) is at a low level. The 18th control transistor M18 is turned on under the control of the high level of the second drive input signal g(n+1) transmitted on the second drive input terminal G(n+1). The turned-on 18th control transistor M18 provides the second reference voltage signal vgl2 of the second reference voltage signal terminal VGL2 to the drive output terminal G(n+1). A reference voltage signal vgl2 is provided to the drive output terminal G(n); the first output transistor MC1 and the second output transistor MC2 are initially turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on first output transistor MC1 provides the clock signal ck transmitted from the clock signal terminal CK to the cascaded output terminal Out_C(n). Since the clock signal ck transmitted from the clock signal terminal CK is at a low level, the cascaded output signal out_c(n) of the cascaded output terminal Out_C(n) is at a low level; the second output transistor MC2 is turned on under the control of the high level of the signal transmitted on the first node N1. The turned-on second output transistor MC2 provides the clock signal ck transmitted from the clock signal terminal CK to the drive output terminal G(n). Since the clock signal ck transmitted from the clock signal terminal CK is at a low level, the drive output signal g(n) of the drive output terminal G(n) is at a low level; then, after the signal n1 on the first node N1 is gradually pulled low, the first output transistor MC1 and the second output transistor MC2 are turned off under the control of the low level of the signal transmitted on the first node N1.

[0170] In stage t6, the first transistor T1 is turned off under the control of the low level of the first drive input signal g(n-1); the second transistor T2 is turned on under the control of the high level of the clock signal ck. The turned-on second transistor T2 provides the initialization signal re of the initialization signal terminal RE to the gate of the third transistor T3, that is, to node A(n). Since the initialization signal re of the initialization signal terminal RE is low, the signal an on A(n) is also low, so the voltage value of the signal an on A(n) is Vl; the third transistor T3 is turned off under the control of the low level of the signal an on A(n); so the signal bn on node B(n) is low; the fourth transistor T4 is turned off under the control of the low level of the signal bn on node B(n); the first control transistor M1 is turned off under the control of the low level of the first cascade input signal out_c(n-1) transmitted at the first cascade input terminal Out_C(n-1); the second control transistor M2 is turned off under the control of the low level of the second cascade input signal out_c(n+1) transmitted at the second cascade input terminal Out_C(n+1). The 19th control transistor M19 is turned on under the control of the high level of the signal transmitted on the third node N3. The turned-on 19th control transistor M19 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the first node N1. Then the voltage value of the signal n1 on the first node N1 is Vl. The 22nd control transistor M22 can be turned on under the control of the high level of the second power signal vdd2 transmitted on the second power terminal VDD2. The turned-on 22nd control transistor M22 provides the second power signal vdd2 to the third node N3. Then the voltage value of the signal n3 on the third node N3 is Vh-Vth_M13. The 23rd control transistor M23 is turned off under the control of the low level of the first cascade input signal out_c(n-1) transmitted on the first cascade input terminal Out_C(n-1). The 24th control transistor M24 is turned off under the control of the low level of the signal transmitted on the first node N1.The 25th control transistor M25 and the 26th control transistor M26 are turned on under the control of the high level of the signal transmitted on the third node N3. The turned-on 25th control transistor M25 provides the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the cascaded output terminal Out_C(n). Since the first reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 is at a low level, the cascaded output signal out_c(n) of the cascaded output terminal Out_C(n) is at a low level. The turned-on 26th control transistor M26 then provides the second reference voltage signal vgl1 of the first reference voltage signal terminal VGL1 to the cascaded output terminal Out_C(n). The second reference voltage signal vgl2 of the reference voltage signal terminal VGL2 is provided to the drive output terminal G(n). Since the second reference voltage signal vgl2 of the second reference voltage signal terminal VGL2 is at a low level, the drive output signal g(n) of the drive output terminal G(n) is at a low level. The eighteenth control transistor M18 is turned off under the control of the low level of the second drive input signal g(n+1) transmitted at the second drive input terminal G(n+1). The first output transistor MC1 and the second output transistor MC2 are turned off under the control of the low level of the signal transmitted on the first node N1.

[0171] This disclosure provides further structural diagrams of a shift register unit, as shown in Figure 8, which are modifications of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; similarities will not be repeated here.

[0172] In some embodiments of this disclosure, as shown in FIG8, the first control circuit 120 includes: a fourth control transistor M4, a fifth control transistor M5, a sixth control transistor M6, a seventh control transistor M7, an eighth control transistor M8, and a ninth control transistor M9; wherein, the gate of the fourth control transistor M4 is coupled to the first cascade input terminal Out_C(n-1), the first terminal of the fourth control transistor M4 is coupled to the first cascade input terminal Out_C(n-1), and the second terminal of the fourth control transistor M4 is coupled to the first terminal of the fifth control transistor M5; the gate of the fifth control transistor M5 is coupled to the first cascade input terminal Out_C(n-1), and the second terminal of the fifth control transistor M5 is coupled to the first node N1; the gate of the sixth control transistor M6 is coupled to the second ... first node N1, and the second terminal of the fifth control transistor M5 is coupled to the first node N1. The input terminal Out_C(n+1) is coupled; the first terminal of the sixth control transistor M6 is coupled to the first node N1; the second terminal of the sixth control transistor M6 is coupled to the first terminal of the seventh control transistor M7; the gate of the seventh control transistor M7 is coupled to the second cascade input terminal Out_C(n+1); the second terminal of the seventh control transistor M7 is coupled to the first reference voltage signal terminal VGL1; the gate of the eighth control transistor M8 is coupled to the reset signal terminal TRST; the first terminal of the eighth control transistor M8 is coupled to the first node N1; the second terminal of the eighth control transistor M8 is coupled to the first terminal of the ninth control transistor M9; the gate of the ninth control transistor M9 is coupled to the reset signal terminal TRST; the second terminal of the ninth control transistor M9 is coupled to the first reference voltage signal terminal VGL1.

[0173] For example, the fourth control transistor M4 and the fifth control transistor M5 can be turned on under the control of the valid level of the first cascade input signal transmitted at the first cascade input terminal Out_C(n-1), and can be turned off under the control of the invalid level of the first cascade input signal. For example, if the fourth control transistor M4 and the fifth control transistor M5 are configured as N-type transistors, then the valid level of the first cascade input signal is high, and the invalid level of the first cascade input signal is low. Alternatively, if the fourth control transistor M4 and the fifth control transistor M5 are configured as P-type transistors, then the valid level of the first cascade input signal is low, and the invalid level of the first cascade input signal is high.

[0174] For example, the sixth control transistor M6 and the seventh control transistor M7 can be turned on under the control of the valid level of the second cascaded input signal transmitted at the second cascaded input terminal Out_C(n+1), and can be turned off under the control of the invalid level of the second cascaded input signal. For example, if the sixth control transistor M6 and the seventh control transistor M7 are configured as N-type transistors, then the valid level of the second cascaded input signal is high, and the invalid level of the second cascaded input signal is low. Alternatively, if the sixth control transistor M6 and the seventh control transistor M7 are configured as P-type transistors, then the valid level of the second cascaded input signal is low, and the invalid level of the second cascaded input signal is high.

[0175] For example, the eighth control transistor M8 and the ninth control transistor M9 can be turned on under the control of the effective level of the reset signal transmitted at the reset signal terminal TRST, and can be turned off under the control of the ineffective level of the reset signal. For example, if the eighth control transistor M8 and the ninth control transistor M9 are configured as N-type transistors, then the effective level of the reset signal is high and the ineffective level of the reset signal is low. Alternatively, if the eighth control transistor M8 and the ninth control transistor M9 are configured as P-type transistors, then the effective level of the reset signal is low and the ineffective level of the reset signal is high.

[0176] In some embodiments of this disclosure, as shown in FIG8, the second control circuit 130 includes an eleventh control transistor M11 and a twelfth control transistor M12; wherein, the gate of the eleventh control transistor M11 is coupled to the second node N2, the first terminal of the eleventh control transistor M11 is coupled to the first node N1, and the second terminal of the eleventh control transistor M11 is coupled to the first terminal of the twelfth control transistor M12; the gate of the twelfth control transistor M12 is coupled to the second node N2, and the second terminal of the twelfth control transistor M12 is coupled to the first reference voltage signal terminal VGL1.

[0177] For example, the eleventh control transistor M11 and the twelfth control transistor M12 can be turned on under the control of the effective level of the signal transmitted on the second node N2, and can be turned off under the control of the ineffective level of the signal transmitted on the second node N2. For example, if the eleventh control transistor M11 and the twelfth control transistor M12 are N-type transistors, then the effective level of the signal transmitted on the second node N2 is a high level, and the ineffective level of the signal transmitted on the second node N2 is a low level. Alternatively, if the eleventh control transistor M11 and the twelfth control transistor M12 are P-type transistors, then the effective level of the signal transmitted on the second node N2 is a low level, and the ineffective level of the signal transmitted on the second node N2 is a high level.

[0178] For example, in this embodiment of the present disclosure, the leakage problem in the first node of the shift register unit is avoided by the cooperation of the first anti-leakage circuit, the first control circuit, the second control circuit, the third control circuit, the fourth control circuit, and the output control circuit. Furthermore, the first control circuit includes a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, an eighth control transistor, and a ninth control transistor; and the second control circuit includes an eleventh control transistor and a twelfth control transistor. Thus, the leakage problem in the first node of the shift register unit can be further avoided, thereby further ensuring the stability of the output signal of the shift register unit and improving the display quality.

[0179] This disclosure provides further structural diagrams of a shift register unit, as shown in Figure 9, which are modifications of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below; similarities will not be repeated here.

[0180] In some embodiments of this disclosure, as shown in FIG9, the sixth control circuit 180 includes: a twentieth control transistor M20 and a twenty-first control transistor M21; wherein, the gate of the twentieth control transistor M20 is coupled to a third node N3, the first terminal of the twentieth control transistor M20 is coupled to a first node N1, and the second terminal of the twentieth control transistor M20 is coupled to the first terminal of the twenty-first control transistor M21; the gate of the twenty-first control transistor M21 is coupled to the third node N3, and the second terminal of the twenty-first control transistor M21 is coupled to a first reference voltage signal terminal VGL1.

[0181] For example, the twentieth control transistor M20 and the eleventh control transistor M21 can be turned on under the control of the effective level of the signal transmitted on the third node N3, and can be turned off under the control of the ineffective level of the signal transmitted on the third node N3. For example, if the twentieth control transistor M20 and the eleventh control transistor M21 are configured as N-type transistors, then the effective level of the signal transmitted on the third node N3 is high, and the ineffective level of the signal transmitted on the third node N3 is low. Alternatively, if the twentieth control transistor M20 and the eleventh control transistor M21 are configured as P-type transistors, then the effective level of the signal transmitted on the third node N3 is low, and the ineffective level of the signal transmitted on the third node N3 is high.

[0182] For example, in this embodiment of the present disclosure, the leakage problem in the first node of the shift register unit is avoided by the cooperation of the first anti-leakage circuit, the first control circuit, the second control circuit, the third control circuit, the fourth control circuit, the fifth control circuit, the sixth control circuit, the seventh control circuit, the eighth control circuit, and the output control circuit. Furthermore, by making the first control circuit include the fourth control transistor, the fifth control transistor, the sixth control transistor, the seventh control transistor, the eighth control transistor, and the ninth control transistor; by making the second control circuit include the eleventh control transistor and the twelfth control transistor; and by making the sixth control circuit include the twentieth control transistor and the twenty-first control transistor, the leakage problem in the first node of the shift register unit can be further avoided, thereby further ensuring the stability of the output signal of the shift register unit and improving the display quality.

[0183] This disclosure provides further structural schematic diagrams of shift register units, as shown in Figures 10 and 11, which are modifications of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0184] In some embodiments of this disclosure, as shown in Figures 10 and 11, a second leakage protection circuit 210 is further included, coupled to the first node N1 and the first control circuit 120, and configured to provide a signal of the fifth reference voltage signal terminal VDDI5 to the first control circuit 120 in response to a signal on the first node N1.

[0185] In some embodiments of this disclosure, as shown in Figures 10 and 11, the second leakage protection circuit includes: a fifth transistor T5; wherein the gate of the fifth transistor T5 is coupled to the first node N1, the first terminal of the fifth transistor T5 is coupled to the fifth reference voltage signal terminal VDDI5, and the second terminal of the fifth transistor T5 is coupled to the first control circuit 120.

[0186] For example, as shown in Figures 10 and 11, the second terminal of the fifth transistor T5 is coupled to the second terminals of the fourth control transistor M4, the sixth control transistor M6, and the eighth control transistor M8.

[0187] For example, the fifth transistor T5 can be turned on under the control of the effective level of the signal transmitted on the first node N1, and can be turned off under the control of the ineffective level of the signal transmitted on the first node N1. For example, if the fifth transistor T5 is set as an N-type transistor, then the effective level of the signal transmitted on the first node N1 is a high level, and the ineffective level of the signal transmitted on the first node N1 is a low level. Alternatively, if the fifth transistor T5 is set as a P-type transistor, then the effective level of the signal transmitted on the first node N1 is a low level, and the ineffective level of the signal transmitted on the first node N1 is a high level.

[0188] For example, in this embodiment of the present disclosure, by setting a second leakage protection circuit to respond to the signal on the first node and provide the signal of the fifth reference voltage signal terminal to the first control circuit, it is possible to further prevent the first node from forming a leakage path through the transistor in the first control circuit, thereby avoiding leakage problems of the first node in the shift register unit, thus improving the stability of the shift register unit and improving the display effect. Furthermore, by setting the second leakage protection circuit not to provide the fifth reference voltage signal to the second control circuit, the probability of the transistor in the second control circuit being forward biased can be reduced, preventing the forward bias of the transistor in the second control circuit from affecting the signal output of the shift register unit.

[0189] This disclosure provides further structural schematic diagrams of shift register units, as shown in Figures 12 and 13, which are modifications of the implementation methods described in the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0190] In some embodiments of this disclosure, as shown in Figures 12 and 13, a first leakage protection circuit is omitted. This arrangement reduces the number of components used, lowers production costs, and facilitates the achievement of a narrow bezel. Furthermore, a second leakage protection circuit is provided in response to a signal at the first node, supplying the signal from the fifth reference voltage terminal to the first control circuit. This arrangement reduces the risk of leakage through the transistor in the first control circuit, thereby avoiding leakage problems in the first node of the shift register unit, improving the stability of the shift register unit, and ultimately enhancing the display effect. Additionally, the second leakage protection circuit does not provide the fifth reference voltage signal to the second control circuit, reducing the number of connection lines between the second leakage protection circuit and the second control circuit, further facilitating the formation of a narrow bezel. In short, while reducing the risk of leakage, a narrow bezel can be achieved.

[0191] It should be noted that, as shown in Figures 12 and 13, the first cascaded input terminal Out_C(n-4) in the nth stage shift register unit SRn is coupled to the cascaded output terminal Out_C(n) in the (n-4)th stage shift register unit SRn-4. The second drive input terminal G(n+4) and the second cascaded input terminal Out_C(n+4) in the nth stage shift register unit SRn are coupled to the drive output terminal G(n) and the cascaded output terminal Out_C(n) in the (n+4)th stage shift register unit SRn+4, respectively. The drive output terminal G(n) and the cascaded output terminal Out_C(n) in the nth stage shift register unit SRn are coupled to the gate line GA(n). The first cascaded input terminal Out_C(n-4) in the first four stages of shift register units is coupled to the frame start signal line STV. The second drive input terminal G(n+4) and the second cascaded input terminal Out_C(n+4) in the last four stages are coupled to the reset signal terminal TRST.

[0192] This disclosure also provides a display device including the shift register unit described above. The principle by which this display device solves the problem is similar to that of the aforementioned shift register unit; therefore, the implementation of this display device can refer to the implementation of the aforementioned shift register unit, and the repetitions will not be repeated here.

[0193] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0194] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0195] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A shift register unit, wherein, The application relates to a circuit for controlling a first node, comprising: a first leakage prevention circuit coupled to the first node and configured to control a signal on the first node in response to signals on a first driving input terminal and a clock signal terminal; a first control circuit coupled to the first node and configured to provide a signal on the first node from a first cascade input terminal in response to a signal on the first cascade input terminal, and to provide a signal on the first node from a first reference voltage signal terminal in response to signals on a reset signal terminal and a second cascade input terminal; a second control circuit coupled to the first node and a second node and configured to provide a signal on the first node from the first reference voltage signal terminal in response to a signal on the second node; a third control circuit coupled to the first node and the second node and configured to control a signal on the second node in response to signals on the first cascade input terminal, a first power supply terminal and the first node; a fourth control circuit coupled to the second node and configured to provide a signal on a cascade output terminal from the first reference voltage signal terminal and to provide a signal on a driving output terminal from a second reference voltage signal terminal in response to a signal on the second node; an output control circuit coupled to the first node and configured to provide a signal on the clock signal terminal to the cascade output terminal and the driving output terminal in response to a signal on the first node.

2. The shift register cell of claim 1, wherein, The first leakage prevention circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a first capacitor; a gate of the first transistor is coupled to the first driving input terminal, a first pole of the first transistor is coupled to a third reference voltage signal terminal, and a second pole of the first transistor is coupled to a second pole of the second transistor; a gate of the second transistor is coupled to the clock signal terminal, and a first pole of the second transistor is coupled to an initialization signal terminal; a gate of the third transistor is coupled to the second pole of the first transistor, a first pole of the third transistor is coupled to a fourth reference voltage signal terminal, and a second pole of the third transistor is coupled to a first pole of the fourth transistor; a gate of the fourth transistor is coupled to the first pole of the fourth transistor, and a second pole of the fourth transistor is coupled to the first node; a first pole plate of the first capacitor is coupled to the gate of the third transistor, and a second pole plate of the first capacitor is coupled to the second pole of the third transistor.

3. The shift register cell of claim 1, wherein, The first control circuit comprises a first control transistor, a second control transistor and a third control transistor; a gate of the first control transistor is coupled to the first cascade input terminal, a first pole of the first control transistor is coupled to the first cascade input terminal, and a second pole of the first control transistor is coupled to the first node; a gate of the second control transistor is coupled to the second cascade input terminal, a first pole of the second control transistor is coupled to the first node, and a second pole of the second control transistor is coupled to the first reference voltage signal terminal; A gate of the third control transistor is coupled with the reset signal end, a first pole of the third control transistor is coupled with the first node, and a second pole of the third control transistor is coupled with the first reference voltage signal end.

4. The shift register cell of claim 1, wherein, The first control circuit comprises a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, an eighth control transistor and a ninth control transistor. A gate of the fourth control transistor is coupled with the first cascade input end, a first pole of the fourth control transistor is coupled with the first cascade input end, and a second pole of the fourth control transistor is coupled with a first pole of the fifth control transistor. A gate of the fifth control transistor is coupled with the first cascade input end, and a second pole of the fifth control transistor is coupled with the first node. A gate of the sixth control transistor is coupled with the second cascade input end, a first pole of the sixth control transistor is coupled with the first node, and a second pole of the sixth control transistor is coupled with a first pole of the seventh control transistor. A gate of the seventh control transistor is coupled with the second cascade input end, and a second pole of the seventh control transistor is coupled with the first reference voltage signal end. A gate of the eighth control transistor is coupled with the reset signal end, a first pole of the eighth control transistor is coupled with the first node, and a second pole of the eighth control transistor is coupled with a first pole of the ninth control transistor. A gate of the ninth control transistor is coupled with the reset signal end, and a second pole of the ninth control transistor is coupled with the first reference voltage signal end.

5. The shift register cell of claim 1, wherein, The second control circuit comprises a tenth control transistor. A gate of the tenth control transistor is coupled with the second node, a first pole of the tenth control transistor is coupled with the first node, and a second pole of the tenth control transistor is coupled with the first reference voltage signal end.

6. The shift register cell of claim 1, wherein, The second control circuit comprises an eleventh control transistor and a twelfth control transistor. A gate of the eleventh control transistor is coupled with the second node, a first pole of the eleventh control transistor is coupled with the first node, and a second pole of the eleventh control transistor is coupled with a first pole of the twelfth control transistor. A gate of the twelfth control transistor is coupled with the second node, and a second pole of the twelfth control transistor is coupled with the first reference voltage signal end.

7. The shift register cell of claim 1, wherein, The third control circuit comprises a thirteenth control transistor, a fourteenth control transistor and a fifteenth control transistor. A gate of the thirteenth control transistor is coupled with the first power supply end, a first pole of the thirteenth control transistor is coupled with the first power supply end, and a second pole of the thirteenth control transistor is coupled with the second node. A gate of the fourteenth control transistor is coupled with the first cascade input end, a first pole of the fourteenth control transistor is coupled with the second node, and a second pole of the fourteenth control transistor is coupled with the first reference voltage signal end. A gate of the fifteenth control transistor is coupled with the first node, a first electrode of the fifteenth control transistor is coupled with the second node, and a second electrode of the fifteenth control transistor is coupled with the first reference voltage signal terminal.

8. The shift register cell of claim 1, wherein, The fourth control circuit includes a sixteenth control transistor and a seventeenth control transistor. A gate of the sixteenth control transistor is coupled with the second node, a first electrode of the sixteenth control transistor is coupled with the cascade output terminal, and a second electrode of the sixteenth control transistor is coupled with the first reference voltage signal terminal. A gate of the seventeenth control transistor is coupled with the second node, a first electrode of the seventeenth control transistor is coupled with the drive output terminal, and a second electrode of the seventeenth control transistor is coupled with the second reference voltage signal terminal.

9. The shift register cell of claim 1, wherein, The output control circuit includes a first output transistor, a second output transistor, and a second capacitor. A gate of the first output transistor is coupled with the first node, a first electrode of the first output transistor is coupled with the clock signal terminal, and a second electrode of the first output transistor is coupled with the cascade output terminal. A gate of the second output transistor is coupled with the first node, a first electrode of the second output transistor is coupled with the clock signal terminal, and a second electrode of the second output transistor is coupled with the drive output terminal. A first electrode of the second capacitor is coupled with the gate of the second output transistor, and a second electrode of the second capacitor is coupled with the drive output terminal.

10. The shift register cell of any of claims 1-9, wherein, Further comprising: A second leakage prevention circuit is coupled with the first node and the first control circuit, and is configured to provide a signal of a fifth reference voltage signal terminal to the first control circuit in response to a signal on the first node.

11. The shift register cell of claim 10, wherein, The second leakage prevention circuit includes a fifth transistor. A gate of the fifth transistor is coupled with the first node, a first electrode of the fifth transistor is coupled with the fifth reference voltage signal terminal, and a second electrode of the fifth transistor is coupled with the first control circuit.

12. The shift register cell of any of claims 1-11, wherein, Further comprising: A fifth control circuit is configured to provide a signal of the second reference voltage signal terminal to the drive output terminal in response to a signal of a second drive input terminal.

13. The shift register cell of claim 12, wherein, The fifth control circuit includes an eighteenth control transistor. A gate of the eighteenth control transistor is coupled with the second drive input terminal, a first electrode of the eighteenth control transistor is coupled with the drive output terminal, and a second electrode of the eighteenth control transistor is coupled with the second reference voltage signal terminal.

14. The shift register cell of any of claims 1-12, wherein, Further comprising: A sixth control circuit is coupled with the first node and a third node, and is configured to provide a signal of the first reference voltage signal terminal to the first node in response to a signal on the third node. A seventh control circuit is coupled with the first node and the third node, and is configured to control a signal on the third node in response to signals of the first cascade input terminal, a second power supply terminal, and the first node. The eighth control circuit, coupled to the third node, is configured to, in response to a signal on the third node, provide the signal from the first reference voltage signal terminal to the cascaded output terminal and the signal from the second reference voltage signal terminal to the drive output terminal.

15. The shift register cell of claim 14, wherein, The sixth control circuit includes: a nineteenth control transistor; The gate of the nineteenth control transistor is coupled to the third node, the first terminal of the nineteenth control transistor is coupled to the first node, and the second terminal of the nineteenth control transistor is coupled to the first reference voltage signal terminal.

16. The shift register cell of claim 14, wherein, The sixth control circuit includes: a twentieth control transistor and a twenty-first control transistor; The gate of the twentieth control transistor is coupled to the third node, the first terminal of the twentieth control transistor is coupled to the first node, and the second terminal of the twentieth control transistor is coupled to the first terminal of the twentieth eleventh transistor. The gate of the 21st control transistor is coupled to the third node, and the second terminal of the 21st control transistor is coupled to the first reference voltage signal terminal.

17. The shift register cell of claim 14, wherein, The seventh control circuit includes: a twenty-second control transistor, a twenty-third control transistor, and a twenty-fourth control transistor; The gate of the twelfth control transistor is coupled to the second power supply terminal, the first terminal of the twelfth control transistor is coupled to the second power supply terminal, and the second terminal of the twelfth control transistor is coupled to the third node. The gate of the 23rd control transistor is coupled to the first cascaded input terminal, the first terminal of the 23rd control transistor is coupled to the third node, and the second terminal of the 23rd control transistor is coupled to the first reference voltage signal terminal. The gate of the 24th control transistor is coupled to the first node, the first terminal of the 24th control transistor is coupled to the third node, and the second terminal of the 24th control transistor is coupled to the first reference voltage signal terminal.

18. The shift register cell of claim 14, wherein, The eighth control circuit includes: a twenty-fifth control transistor and a twenty-sixth control transistor; The gate of the 25th control transistor is coupled to the third node, the first terminal of the 25th control transistor is coupled to the cascaded output terminal, and the second terminal of the 25th control transistor is coupled to the first reference voltage signal terminal. The gate of the 26th control transistor is coupled to the third node, the first terminal of the 26th control transistor is coupled to the drive output terminal, and the second terminal of the 26th control transistor is coupled to the second reference voltage signal terminal.

19. A display device comprising a shift register unit as described in any one of claims 1-18.

20. A driving method of a shift register unit as claimed in any one of claims 1 to 18, wherein, include: In the first stage, the first leakage protection circuit responds to the signal at the first drive input terminal and controls the signal on the first node; The first control circuit responds to the signal at the first cascade input terminal and provides the signal at the first cascade input terminal to the first node; The third control circuit responds to the signals at the first cascaded input terminal, the first power supply terminal, and the first node, and controls the signals at the second node. The output control circuit provides the signal of the clock signal terminal to the cascade output terminal and the driving output terminal in response to the signal on the first node; In the second stage, the first control circuit provides the signal of the first reference voltage signal terminal to the first node in response to the signal on the reset signal terminal; The third control circuit controls the signal on the second node in response to the signals on the first power supply terminal and the first node; The output control circuit provides the signal of the clock signal terminal to the cascade output terminal and the driving output terminal in response to the signal on the first node; In the third stage, the third control circuit controls the signal on the second node in response to the signals on the first power supply terminal and the first node; The output control circuit provides the signal of the clock signal terminal to the cascade output terminal and the driving output terminal in response to the signal on the first node; In the fourth stage, the first leakage prevention circuit controls the signal on the first node in response to the signal on the clock signal terminal; the third control circuit controls the signal on the second node in response to the signals on the first power supply terminal and the first node; and the output control circuit provides the signal of the clock signal terminal to the cascade output terminal and the driving output terminal in response to the signal on the first node; In the fifth stage, the first control circuit provides the signal of the first reference voltage signal terminal to the first node in response to the signal on the second cascade input terminal; The second control circuit provides the signal of the first reference voltage signal terminal to the first node in response to the signal on the second node; The third control circuit controls the signal on the second node in response to the signal on the first power supply terminal; and the fourth control circuit provides the signal of the first reference voltage signal terminal to the cascade output terminal and the signal of the second reference voltage signal terminal to the driving output terminal in response to the signal on the second node; In the sixth stage, the first leakage prevention circuit controls the signal on the first node in response to the signal on the clock signal terminal; The second control circuit provides the signal of the first reference voltage signal terminal to the first node in response to the signal on the second node; The third control circuit controls the signal on the second node in response to the signal on the first power supply terminal; and the fourth control circuit provides the signal of the first reference voltage signal terminal to the cascade output terminal and the signal of the second reference voltage signal terminal to the driving output terminal in response to the signal on the second node.

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