Array substrate, display apparatus and pixel driving method
Patent Information
- Application Number
- PCT/CN2025/085925
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2026-10-01
Smart Images
Figure CN2025085925_01102026_PF_FP_ABST
Abstract
Description
Array substrate, display device and pixel driving method Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display device, and a pixel driving method. Background Technology
[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention
[0003] The array substrate, display device, and pixel driving method disclosed herein are specifically as follows:
[0004] On one hand, embodiments of this disclosure provide an array substrate, including:
[0005] Multiple sub-pixels are arranged in an array. The sub-pixels include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are arranged cyclically in the row direction, and the sub-pixels in the same column have the same color.
[0006] Multiple data lines extend along the column direction and are arranged along the row direction. Every three data lines are sequentially designated as a first data line, a second data line, and a third data line. The first data line is electrically connected to the first color sub-pixel, the second data line is electrically connected to the second color sub-pixel, and the third data line is electrically connected to the third color sub-pixel. Furthermore, the first data line, the second data line, and the third data line are connected together.
[0007] Multiple gate lines extend along the row direction and are arranged along the column direction. Every three gate lines are sequentially designated as a first gate line, a second gate line, and a third gate line. The first gate line, the second gate line, and the third gate line are electrically connected to a sub-pixel of one of the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels in the same row.
[0008] In some embodiments, in the array substrate provided in the present disclosure, the first gate line is electrically connected to the first color sub-pixel in the same row.
[0009] In some embodiments, in the array substrate provided in the present disclosure, the second gate line and the third gate line are sequentially electrically connected to the second color sub-pixel and the third color sub-pixel in the same row.
[0010] In some embodiments, in the array substrate provided in the present disclosure, the second gate line and the third gate line are sequentially electrically connected to the third color sub-pixel and the second color sub-pixel in the same row.
[0011] In some embodiments, in the array substrate provided in the present disclosure, the first gate line is electrically connected to the third color sub-pixel described in the same row.
[0012] In some embodiments, in the array substrate provided in the present disclosure, the second gate line and the third gate line are sequentially electrically connected to the second color sub-pixel and the first color sub-pixel in the same row.
[0013] In some embodiments, in the array substrate provided in the present disclosure, the second gate line and the third gate line are sequentially electrically connected to the first color sub-pixel and the second color sub-pixel in the same row.
[0014] In some embodiments, in the array substrate provided in the present disclosure, the first gate line, the second gate line, and the third gate line are located on the same side of the row where the sub-pixel to which they are electrically connected is located.
[0015] In some embodiments, in the array substrate provided in the present disclosure, the first gate line and the second gate line are located on opposite sides of the row where the sub-pixel is electrically connected, and the third gate line is located on the side of the row where the second gate line is electrically connected away from the row where the sub-pixel is connected.
[0016] In some embodiments, in the array substrate provided in the present disclosure, three gate lines are provided between two adjacent rows of sub-pixels.
[0017] In some embodiments, in the array substrate provided in the present disclosure, the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.
[0018] In some embodiments, in the array substrate provided in the present disclosure, the size of the sub-pixel in the column direction is larger than its size in the row direction.
[0019] In some embodiments, the array substrate provided in this disclosure further includes a transistor, the first electrode of which is electrically connected to the data line, and the active layer of the transistor includes a first edge and a second edge arranged along the row direction, wherein the first edge is located on the side of the second edge closer to the data line, and there is a certain distance between the first edge and the edge of the data line away from the second edge.
[0020] In some embodiments, in the array substrate provided in the present disclosure, the sub-pixel includes a pixel electrode, the first electrode of the transistor is electrically connected to the data line, and the second electrode of the transistor is electrically connected to the pixel electrode;
[0021] The active layer of the transistor further includes a third edge and a fourth edge arranged side by side along the column direction, wherein the third edge is located on the side of the fourth edge close to the pixel electrode to which the transistor is connected, and the distance between the third edge and the pixel electrode to which the transistor is connected is greater than the distance between the edge of the gate line close to the pixel electrode to which it is connected and the pixel electrode to which it is connected.
[0022] On the other hand, this disclosure provides a display device including the array substrate provided in this disclosure, a counter substrate disposed opposite to the array substrate, and a backlight module located on the side of the array substrate away from the counter substrate.
[0023] On the other hand, embodiments of this disclosure provide a pixel driving method, including:
[0024] Within one frame, the first to the last gate line are turned on sequentially, and data signals are loaded for each column of sub-pixels through each data line. The turn-on times of two adjacent gate lines overlap. In every three columns of sub-pixels, one column of sub-pixels is not pre-charged, and two columns of sub-pixels are pre-charged. The sub-pixels in the columns without pre-charge have the same color.
[0025] On the other hand, embodiments of this disclosure provide a pixel driving method, including:
[0026] Within one frame, each gate line is turned on sequentially, and data signals are loaded for each column of sub-pixels through each data line. The turn-on times of two adjacent gate lines do not overlap, and each column of sub-pixels is not pre-charged.
[0027] On the other hand, embodiments of this disclosure provide a pixel driving method, including:
[0028] During the time of each frame from frame 1 to N (N is a positive integer), the first to the last gate line is turned on sequentially, and data signals are loaded for each column of sub-pixels through each data line. The turn-on time of two adjacent gate lines partially overlaps. Among every 18 columns of sub-pixels, 6 columns of sub-pixels have no pre-fill and 12 columns of sub-pixels have pre-fill.
[0029] During each frame time of the N+1 to 2Nth frames, the second to the last gate line are opened sequentially, and data signals are loaded for each column of sub-pixels through each data line. Among every 18 columns of sub-pixels, 6 columns of sub-pixels are not pre-charged, and 12 columns of sub-pixels are pre-charged. The 12 columns of sub-pixels with pre-charge include the 6 columns of sub-pixels that were not pre-charged in the 1st to Nth frames.
[0030] During each frame time of frames 2N+1 to 3N, the third to the last gate line are sequentially opened, and data signals are loaded for each column of sub-pixels through each data line. Among every 18 columns of sub-pixels, 6 columns of sub-pixels are not pre-charged, and 12 columns of sub-pixels are pre-charged. The 12 columns of sub-pixels with pre-charge include the 6 columns of sub-pixels that were not pre-charged in frames 1 to N, and the 6 columns of sub-pixels that were not pre-charged in frames N+1 to 2N.
[0031] In some embodiments, in the pixel driving method provided in the present disclosure, during each frame time of the 1st to Nth (N is a positive integer) frames, the sub-pixels in columns 1 to 6 of every 18 columns of sub-pixels have no pre-filling and the sub-pixels in columns 7 to 18 have pre-filling;
[0032] During each frame time of frames N+1 to 2N, sub-pixels in columns 1 to 6 and columns 13 to 18 of every 18 columns of sub-pixels are pre-charged, while sub-pixels in columns 7 to 12 are not pre-charged;
[0033] During each frame time of frames 2N+1 to 3N, sub-pixels in columns 1 to 12 of every 18 columns are pre-charged, while sub-pixels in columns 13 to 18 are not pre-charged.
[0034] In some embodiments, in the pixel driving method provided in the present disclosure, during each frame time of the first to N (N is a positive integer) frames, the sub-pixels in the (3n+1)th column of every 18 columns of sub-pixels have no pre-filling, while the sub-pixels in the (3n+2)th and (3n+3)th columns have pre-filling, where n is a natural number less than or equal to 5.
[0035] During each frame time of the N+1 to 2Nth frames, in every 18 columns of the sub-pixels, the (3n+2)th column sub-pixel has no pre-fill, while the (3n+1)th and (3n+3)th column sub-pixels have pre-fill;
[0036] During each frame time of frames 2N+1 to 3N, the sub-pixels in column (3n+3) of every 18 columns have no pre-filling, while the sub-pixels in columns (3n+1) and (3n+2) have pre-filling.
[0037] In some embodiments, in the pixel driving method provided in the present disclosure, during each frame time of the first to N (N is a positive integer) frames, the sub-pixels in the (3n+3)th column of every 18 columns of sub-pixels have no pre-filling, while the sub-pixels in the (3n+1)th and (3n+2)th columns have pre-filling, where n is a natural number less than or equal to 5.
[0038] During each frame time of the N+1 to 2Nth frames, in every 18 columns of the sub-pixels, the (3n+2)th column sub-pixel has no pre-fill, while the (3n+1)th and (3n+3)th column sub-pixels have pre-fill;
[0039] During each frame time of frames 2N+1 to 3N, the sub-pixels in column (3n+1) of every 18 columns have no pre-filling, while the sub-pixels in columns (3n+2) and (3n+3) have pre-filling. Attached Figure Description
[0040] Figure 1 is a schematic diagram of a three-gate pixel structure in a related technology;
[0041] Figure 2 is a schematic diagram of a three-gate pixel architecture provided in an embodiment of this disclosure;
[0042] Figure 3 shows the timing diagrams of Figure 2 with and without pre-filled sub-pixels;
[0043] Figure 4 shows the charging diagrams of Figure 2 with and without pre-charged sub-pixels;
[0044] Figure 5 is a schematic diagram of another three-gate pixel architecture provided in an embodiment of this disclosure;
[0045] Figure 6 is a schematic diagram of the structure of region Z1 in Figure 5;
[0046] Figure 7a shows the gate line driving timing of the three-gate pixel architecture shown in Figure 5;
[0047] Figure 7b shows the driving timing of each of the three gate lines and each of the three data lines in the three-gate pixel architecture shown in Figure 5;
[0048] Figure 8 is a schematic diagram of another three-gate pixel architecture provided in an embodiment of this disclosure;
[0049] Figure 9 is a schematic diagram of the structure of region Z2 in Figure 8;
[0050] Figure 10 is a schematic diagram of another three-gate pixel architecture provided in an embodiment of this disclosure;
[0051] Figure 11 is a schematic diagram of the structure of region Z3 in Figure 10;
[0052] Figure 12 is a schematic diagram of another three-gate pixel architecture provided in an embodiment of this disclosure;
[0053] Figure 13 is a schematic diagram of the structure of region Z4 in Figure 12;
[0054] Figure 14 is a schematic diagram of another three-gate pixel architecture provided in an embodiment of this disclosure;
[0055] Figure 15 is a schematic diagram of the structure of region Z5 in Figure 14;
[0056] Figure 16 is a timing diagram of a gate line drive provided in an embodiment of this disclosure;
[0057] Figure 17 is another gate line drive timing diagram provided in an embodiment of this disclosure;
[0058] Figure 18 is a charging diagram of the three-gate pixel architecture shown in Figure 2 when driven by the timing shown in Figure 17.
[0059] Figure 19 is another gate line driving timing diagram provided in an embodiment of this disclosure;
[0060] Figure 20 shows the charging diagram of the three-gate pixel architecture shown in Figure 2 when driven by the timing shown in Figure 19.
[0061] Figure 21 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure;
[0062] Figure 22 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure. Detailed Implementation
[0063] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.
[0064] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.
[0065] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.
[0066] As competition intensifies in the display market, cost control has become a crucial factor in enhancing product competitiveness. Dual-gate and triple-gate pixel architectures reduce the number of source driver chips (Source ICs) to half and one-third of those in single-gate pixel architectures, respectively, representing effective solutions for lowering panel costs. For example, a 1920*1200 resolution panel requires four source driver chips in a single-gate pixel structure, two in a dual-gate architecture, and only one in a triple-gate architecture, thus reducing the number of source driver chips and lowering costs.
[0067] Figure 1 shows the three-gate pixel structure of the related technology, in which the pixels are arranged horizontally. The applicant found that compared with vertically arranged pixels, the deflection of liquid crystal molecules in horizontally arranged pixels is changed from being affected by the upper and lower domain slits to being affected by the left and right domain slits. This causes the magnetic field disorder area at the corner of the slit in the middle of the pixel to become larger, which in turn causes the liquid crystal molecule deflection disorder area in the middle region to become larger. That is, the dark area in the middle region of the pixel increases, and the contrast ratio (CR value) of the display area (AA) decreases, which cannot meet the requirements of automotive customers.
[0068] In some embodiments, to improve the contrast of the display area, this disclosure proposes a three-gate pixel structure design as shown in Figure 2. In Figure 2, the pixels are arranged vertically, resulting in a significant improvement in transmittance; however, as shown in Figure 3, there is a difference between pre-charged and non-pre-charged pixels in Figure 2; the corresponding pixel charging rates also differ, as shown in Figure 4. Specifically, in every 18 columns of sub-pixels, the first 6 columns of RGB sub-pixels have no pre-charge, the next 6 columns of RGB sub-pixels have pre-charge, and then another 6 columns of RGB sub-pixels have pre-charge. Therefore, the white formed by the first 6 columns of RGB sub-pixels is slightly darker, while the white formed by the last 12 columns of RGB sub-pixels is slightly brighter, resulting in alternating vertical stripes of poor brightness.
[0069] To address the aforementioned technical problems, this disclosure provides an array substrate. Figure 5 is a schematic diagram of the connection of 3*6 sub-pixels in the array substrate provided in this disclosure, and Figure 6 is a schematic diagram of the structure of the Z1 region in Figure 5. As shown in Figures 5 and 6, the array substrate of this disclosure may include:
[0070] Multiple sub-pixels 101 are arranged in an array. Each sub-pixel 101 includes a first-color sub-pixel R, a second-color sub-pixel G, and a third-color sub-pixel B. The first-color sub-pixel R, the second-color sub-pixel G, and the third-color sub-pixel B are arranged cyclically in the row direction X, and the sub-pixels 101 in the same column have the same color. In some embodiments, the first-color sub-pixel R is a red sub-pixel, the second-color sub-pixel G is a green sub-pixel, and the third-color sub-pixel B is a blue sub-pixel. Optionally, to ensure transmittance, this disclosure sets the size of the sub-pixel 101 in the column direction Y to be larger than its size in the row direction X; in other words, the sub-pixels 101 of this disclosure are arranged vertically.
[0071] Multiple data lines 102 extend along the column direction Y and are arranged along the row direction X. Every three data lines 102 are sequentially designated as a first data line (e.g., DL1, DL4, etc.), a second data line (e.g., DL2, DL5, etc.), and a third data line (e.g., DL3, DL6, etc.). The first data line (e.g., DL1, DL4, etc.) is electrically connected to the first color sub-pixel R, the second data line (e.g., DL2, DL5, etc.) is electrically connected to the second color sub-pixel G, and the third data line (e.g., DL3, DL6, etc.) is electrically connected to the third color sub-pixel B. When using column inversion to reduce logic power consumption, the data polarity is flipped every three columns. For example, the data polarity of columns 1-3 is "+", and the data polarity of columns 4-6 is "-". In some embodiments, the material of the data line 102 may include metals such as copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The data line 102 may be a single-layer structure or a multilayer structure. For example, the data line 102 may be a single-layer structure made of aluminum.
[0072] Multiple gate lines 103 extend along the row direction X and are arranged along the column direction Y. Every three gate lines 103 are, in order, a first gate line (e.g., GL1, GL4, GL7, etc.), a second gate line (e.g., GL2, GL5, GL8, etc.), and a third gate line (e.g., GL3, GL6, GL9, etc.). The first gate line (e.g., GL1, GL4, GL7, etc.), the second gate line (e.g., GL2, GL5, GL8, etc.), and the third gate line (e.g., GL3, GL6, GL9, etc.) are electrically connected to a sub-pixel 101 of one of the three colors in the same row: the first color sub-pixel R, the second color sub-pixel G, and the third color sub-pixel B. In other words, the sub-pixels 101 connected to the first gate line (e.g., GL1, GL4, GL7, etc.) have the same color, the sub-pixels 101 connected to the second gate line (e.g., GL2, GL5, GL8, etc.) have the same color, and the sub-pixels 101 connected to the third gate line (e.g., GL3, GL6, GL9, etc.) have the same color, but the colors of the sub-pixels 101 connected to the first gate line (e.g., GL1, GL4, GL7, etc.), the sub-pixels 101 connected to the second gate line (e.g., GL2, GL5, GL8, etc.), and the sub-pixels 101 connected to the third gate line (e.g., GL3, GL6, GL9, etc.) are different. In some embodiments, the material of the gate line 103 may include metals such as copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The gate line 103 may be a single-layer structure or a multilayer structure; for example, the gate line 103 may be a single-layer structure made of copper.
[0073] In the array substrate provided in the embodiments of this disclosure, the first gate line (e.g., GL1), the second gate line (e.g., GL2), and the third gate line (e.g., GL3) of every three gate lines 103 are sequentially turned on, and the first data line (e.g., DL1), the second data line (e.g., DL2), and the third data line (e.g., DL3) of every three data lines 102 are synchronously connected to data signals. The first data line (e.g., DL1, DL4, etc.) writes a high voltage of the data signal into the sub-pixel 101 connected to the first gate line (e.g., GL1). Since the data signal switches from low voltage to high voltage at this time, the sub-pixel 101 connected to the first gate line (e.g., GL1) has no pre-charge. The second data line (e.g., DL2) writes a high voltage of the data signal into the sub-pixel 101 connected to the second gate line (e.g., GL2). The data signal remains at a high voltage, and the sub-pixel 101 connected to the second gate line (e.g., GL2) has pre-charge. The third data line (e.g., DL3) writes a high voltage data signal into the sub-pixel 101 connected to the third gate line (e.g., GL3), maintaining the data signal at a high voltage. The sub-pixel 101 connected to the third gate line (e.g., GL3) is pre-charged. Based on this, the sub-pixels 101 of the same color connected to the first gate line (e.g., GL1, GL4, GL7, etc.) are not pre-charged, while the sub-pixels 101 of the same color connected to the second gate line (e.g., GL2, GL5, GL8, etc.) and the sub-pixels 101 of the same color connected to the third gate line (e.g., GL3, GL6, GL9, etc.) are pre-charged. This ensures that the white brightness of the three columns of sub-pixels 101 connected by the first data line (e.g., DL1, DL4, etc.), the second data line (e.g., DL2, DL5, etc.), and the third data line (e.g., DL3, DL6, etc.) is uniform, preventing vertical stripe defects caused by a darker white due to a 6-column RGB sub-pixel mixture or a brighter white due to a 12-column RGB sub-pixel mixture.
[0074] Taking the pixel architecture shown in Figures 5 and 6 as an example, Figure 7a shows the gate line driving timing, and Figure 7b shows the driving timing for every three gate lines and every three data lines. Combining Figures 5, 6, 7a, and 7b, it can be seen that the gate lines 103 (Figure 7a specifically shows the first gate line G1 to the sixteenth gate line G16) are turned on sequentially, with a gate pulse high-level time of 4H. The overlap time between adjacent gate lines 103 (e.g., Gn+1 and Gn, Gn+2 and Gn+1) is 3H. During the gate pulse high-level time corresponding to the first color sub-pixel R, the data signal D switches from low to high, therefore the first color sub-pixel R has no pre-charge. During the gate pulse high-level time corresponding to the second color sub-pixel G, the high-level time of the data signal D is twice that of the first color sub-pixel R, meaning the second color sub-pixel G has 1H of pre-charge time and then 1H of positive charge time. During the high-level period of the gate pulse corresponding to the third color sub-pixel B, the high-level period of the data signal D is three times that of the first color sub-pixel R. That is, the third color sub-pixel B has 2H of pre-charge time and then 1H of positive charge time. Based on this, the first color sub-pixel R has no pre-charge, while the second color sub-pixel G and the third color sub-pixel B have pre-charge. The white brightness formed by the mixing of every three columns of the first color sub-pixel R, the second color sub-pixel G, and the third color sub-pixel B is uniform, thus solving the problem of vertical stripe defects.
[0075] In some embodiments, Figures 8 and 9, and Figures 10 and 11 respectively illustrate another three-gate pixel architecture. As can be seen from Figures 5, 6, 8 to 11, in the array substrate provided in the embodiments of this disclosure, the first gate line (e.g., G1, G4, G7, etc.) can be electrically connected to the first color sub-pixel R in the same row. Optionally, in Figures 5, 6, 8, and 9, the second gate line (e.g., G2, G5, G8, etc.) can be electrically connected to the second color sub-pixel G in the same row, and the third gate line (e.g., G3, G6, G9, etc.) can be electrically connected to the third color sub-pixel B in the same row; in Figures 10 and 11, the second gate line (e.g., G2, G5, G8, etc.) can be electrically connected to the third color sub-pixel B in the same row, and the third gate line (e.g., G3, G6, G9, etc.) can be electrically connected to the second color sub-pixel G in the same row. In Figures 5, 6, 8 to 11, the driving methods shown in Figures 7a and 7b can be used to achieve the following: the first color sub-pixel R has no pre-fill, while the second color sub-pixel G and the third color sub-pixel B have pre-fill. This ensures that the white brightness of the mixture formed by the first color sub-pixel R, the second color sub-pixel G, and the third color sub-pixel B in every three columns is uniform, thus solving the problem of poor vertical stripe quality.
[0076] In some embodiments, Figures 12 and 13, and Figures 14 and 15 respectively illustrate another three-gate pixel architecture. As can be seen from Figures 12 to 15, in the array substrate provided in the embodiments of this disclosure, a first gate line (e.g., G1, G4, G7, etc.) may be electrically connected to the third color sub-pixel B in the same row. Optionally, in Figures 12 and 13, a second gate line (e.g., G2, G5, G8, etc.) may be electrically connected to the second color sub-pixel G in the same row, and a third gate line (e.g., G3, G6, G9, etc.) may be electrically connected to the first color sub-pixel R in the same row. Alternatively, in some embodiments, a second gate line (e.g., G2, G5, G8, etc.) may be electrically connected to the first color sub-pixel R in the same row, and a third gate line (e.g., G3, G6, G9, etc.) may be electrically connected to the second color sub-pixel G in the same row. This allows the driving methods shown in Figures 7a and 7b to achieve a situation where the third color sub-pixel B has no pre-filling, while the first color sub-pixel R and the second color sub-pixel G have pre-filling. This ensures that the white brightness formed by the mixing of the first color sub-pixel R, the second color sub-pixel G, and the third color sub-pixel B in every three columns is uniform, thus solving the problem of poor vertical stripe quality.
[0077] As can be seen from the above, this disclosure illustrates the following examples: the first color sub-pixel R has no pre-charge, while the second color sub-pixel G and the third color sub-pixel B have pre-charge; or the third color sub-pixel B has no pre-charge, while the first color sub-pixel R and the second color sub-pixel G have pre-charge. When the first color sub-pixel R is a red sub-pixel, the second color sub-pixel G is a green sub-pixel, and the third color sub-pixel B is a blue sub-pixel, this is equivalent to this disclosure showing that the red sub-pixel has no pre-charge, while the blue and green sub-pixels have pre-charge; or, the blue sub-pixel has no pre-charge, while the red and green sub-pixels have pre-charge. Since the human eye is sensitive to green, when the green sub-pixel has pre-charge, it can ensure that the green sub-pixel is fully charged and has normal brightness, with minimal impact on the display effect. In addition, the blue sub-pixel contributes the least to the overall brightness and is less likely to cause other optical problems. Therefore, this disclosure can set the blue sub-pixel to have no pre-charge to solve the vertical stripe problem.
[0078] In some embodiments, in the array substrate provided in the present disclosure, for ease of connection, as shown in FIG5, FIG6, FIG14 and FIG15, the first gate line (e.g. G1), the second gate line (e.g. G2) and the third gate line (e.g. G3) can be disposed on the same side of the row sub-pixels 101 (e.g., the first row sub-pixels 101) to which they are electrically connected; or, as shown in FIG8 to FIG13, the first gate line (e.g. G1) and the second gate line (e.g. G2) can be disposed on opposite sides of the row sub-pixels 101 (e.g., the first row sub-pixels 101) to which they are electrically connected, and the third gate line (e.g. G3) is located on the side of the second gate line (e.g. G2) away from the row sub-pixels 101 (e.g., the first row sub-pixels 101) to which they are electrically connected. Referring to Figures 5, 6, 8 to 15, it can be seen that three gate lines 103 can be provided between two adjacent rows of sub-pixels 101 in this disclosure. This allows the gate lines 103 to be evenly distributed in the gaps between the rows of sub-pixels 101, which helps to improve the etching uniformity of the gate lines 103.
[0079] In some embodiments of the array substrate provided in this disclosure, as shown in Figures 5, 6, and 8 to 15, the data line 102 and gate line 103 can be electrically connected to the sub-pixel 101 via a transistor 104. Optionally, the transistor 104 is a P-type transistor or an N-type transistor, and the gate of the transistor 104 can be located above and / or below the active layer. The active layer material of the transistor 104 includes, but is not limited to, amorphous silicon, polycrystalline silicon, and indium gallium zinc oxide. The sub-pixel 101 can include a pixel electrode 105 and a common electrode (com); wherein the pixel electrode and the common electrode can be disposed in different layers, and one of them is a slit electrode and the other is a block electrode; or the pixel electrode and the common electrode can be disposed in the same layer, and both can be comb-shaped electrodes, with the comb teeth of the comb-shaped electrodes alternately arranged. In some embodiments, the pixel electrode 105 can also be disposed on the array substrate, and the common electrode can be disposed on the opposing substrate (also called the color filter substrate), in which case the common electrode can be a planar electrode covering the display area AA. The materials for pixel electrodes and common electrodes can be transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), and zinc gallium oxide (GZO).
[0080] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG6, the active layer ACT of transistor 104 includes a first edge A1 and a second edge A2 arranged along the row direction X, wherein the first edge A1 is located on the side of the second edge A2 near the data line 102, and there is a certain distance d1 between the first edge A1 and the edge of the data line 102 away from the second edge A2. In other words, the first edge A1 extends a certain distance d1 away from the data line 102 relative to the second edge A2. In some embodiments, the active layer ACT of transistor 104 may further include a third edge A3 and a fourth edge A4 arranged side by side along the column direction Y, wherein the third edge A3 is located on the side of the fourth edge A4 near the pixel electrode 105 connected to transistor 104, and the distance d2 between the third edge A3 and the pixel electrode 105 connected to transistor 104 is greater than the distance d3 between the edge of the gate line 103 near the pixel electrode 105 connected to it and the pixel electrode 105 connected to it.
[0081] On the other hand, this disclosure provides a pixel driving method, as shown in FIG7a, which may include the following steps:
[0082] Within one frame, the first to the last gate line (e.g., G1 to G14) are turned on sequentially, and data signals are loaded for each column of sub-pixels through each data line. The turn-on times of two adjacent gate lines overlap. In every three columns of sub-pixels, one column of sub-pixels is not pre-charged and two columns of sub-pixels are pre-charged. The sub-pixels in the columns without pre-charge have the same color.
[0083] For example, when driving using the method shown in Figure 7a, the first color sub-pixel R in Figures 5, 6, 8 to 11 has no pre-fill, while the second color sub-pixel G and the third color sub-pixel B have pre-fill; in Figures 12 to 15, the third color sub-pixel B has no pre-fill, while the first color sub-pixel R and the second color sub-pixel G have pre-fill. This ensures that the mixed white brightness of each of the three columns of RGB sub-pixels is as consistent as possible, avoiding vertical stripe defects.
[0084] On the other hand, this disclosure provides a pixel driving method, as shown in FIG16, which may include the following steps:
[0085] Within one frame, each gate line (e.g., G1 to G14) is turned on sequentially, and data signals are loaded for each column of sub-pixels through each data line. The turn-on times of two adjacent gate lines do not overlap, and each column of sub-pixels is not pre-charged.
[0086] In this pixel driving method, none of the RGB subpixels are pre-charged, thus avoiding vertical stripe defects caused by charging differences between pre-charged and non-pre-charged pixels. This pixel driving method is applicable to both the three-gate pixel architecture shown in Figure 2 and the three-gate pixel architectures shown in Figures 5, 6, 8 to 15.
[0087] On the other hand, embodiments of this disclosure provide a pixel driving method, which may include the following steps:
[0088] During the time of each frame from frame 1 to N (N is a positive integer), the first to the last gate line is turned on sequentially, and data signals are loaded for each column of sub-pixels through each data line. The turn-on time of two adjacent gate lines overlaps. In every 18 columns of sub-pixels, 6 columns of sub-pixels are not pre-charged and 12 columns of sub-pixels are pre-charged, as shown in Figure 7a and Figure 4.
[0089] During each frame time from frame N+1 to frame 2N, the second to the last gate line are opened sequentially, and data signals are loaded for each column of sub-pixels through each data line. Among them, 6 columns of sub-pixels in every 18 columns of sub-pixels are not pre-filled and 12 columns of sub-pixels are pre-filled. The 12 columns of sub-pixels with pre-filling include the 6 columns of sub-pixels without pre-filling in frames 1 to N, as shown in Figures 17 and 18.
[0090] During each frame time from frame 2N+1 to frame 3N, the third to the last gate line are opened sequentially, and data signals are loaded for each column of sub-pixels through each data line. Among the 18 columns of sub-pixels, 6 columns of sub-pixels are not pre-charged and 12 columns of sub-pixels are pre-charged. The 12 columns of sub-pixels with pre-charge include the 6 columns of sub-pixels without pre-charge in frames 1 to N and the 6 columns of sub-pixels without pre-charge in frames N+1 to 2N, as shown in Figures 19 and 20.
[0091] In this pixel driving method, different gate driving sequences are combined to make the pre-charged and non-pre-charged sub-pixels not fixed. Each sub-pixel has a macroscopic superposition effect of pre-charged and non-pre-charged, and the vertical stripes are significantly improved.
[0092] In some embodiments, as shown in Table 1, for a 120Hz panel, within a certain time period (taking 15 consecutive frames as an example), the first gate line G1 to the last gate line can be driven sequentially in the first 5 frames according to the sequence CK1→CK2→CK3→CK4→CK5→CK6→CK7→CK8 shown in Figure 7a. In the second 5 frames, the second gate line G2 to the last gate line can be driven sequentially in the sequence CK2→CK3→CK4→CK5→CK6→CK7→CK8→CK1 shown in Figure 17. In the third 5 frames, the third gate line G3 to the last gate line can be driven sequentially in the sequence CK3→CK4→CK5→CK6→CK7→CK8→CK1→CK2 shown in Figure 19. Gate lines are driven one by one. For a 165Hz panel, within a certain time (taking 18 consecutive frames as an example), the first gate line G1 to the last gate line can be driven one by one in the first 6 frames according to the sequence CK1→CK2→CK3→CK4→CK5→CK6→CK7→CK8 as shown in Figure 7a. In the second 6 frames, the second gate line G2 to the last gate line can be driven one by one in the sequence CK2→CK3→CK4→CK5→CK6→CK7→CK8→CK1 as shown in Figure 17. In the third 6 frames, the third gate line G3 to the last gate line can be driven one by one in the sequence CK3→CK4→CK5→CK6→CK7→CK8→CK1→CK2 as shown in Figure 19. Here, different gate driving methods are switched every 5 or 6 frames as an example. In some embodiments, switching can also be done one frame at a time. This disclosure does not make specific limitations.
[0093] Table 1
[0094] In some embodiments, when the pixel driving method with different gate driving order combinations provided in this disclosure is applied to FIG2, in each frame time of the first to N (N is a positive integer) frames, the first to sixth RGB sub-pixels in every 18 columns of RGB sub-pixels are not pre-charged, and the seventh to 18th RGB sub-pixels are pre-charged, as shown in FIG4; in each frame time of the N+1 to 2N frames, the first to sixth RGB sub-pixels and the 13th to 18th RGB sub-pixels in every 18 columns of RGB sub-pixels are pre-charged, and the 7th to 12th RGB sub-pixels are not pre-charged, as shown in FIG18; in each frame time of the 2N+1 to 3N frames, the first to 12th RGB sub-pixels in every 18 columns of RGB sub-pixels are pre-charged, and the 13th to 18th RGB sub-pixels are not pre-charged, as shown in FIG20.
[0095] In some embodiments, when the pixel driving method with different gate driving order combinations provided in this disclosure is applied to Figures 5, 6, 8 to 11, in each frame time of the first to N (N is a positive integer) frames, the first color sub-pixel in the (3n+1)th column of every 18 columns of sub-pixels has no pre-charge, the second color sub-pixel in the (3n+2)th column and the third color sub-pixel in the (3n+3)th column have pre-charge, where n is a natural number less than or equal to 5; in each frame time of the N+1 to 2N frames, the second color sub-pixel in the (3n+2)th column of every 18 columns of sub-pixels has no pre-charge, the first color sub-pixel in the (3n+1)th column and the third color sub-pixel in the (3n+3)th column have pre-charge; in each frame time of the 2N+1 to 3N frames, the third color sub-pixel in the (3n+3)th column of every 18 columns of sub-pixels has no pre-charge, the first color sub-pixel in the (3n+1)th column and the second color sub-pixel in the (3n+2)th column have pre-charge.
[0096] In some embodiments, when the pixel driving method with different gate driving order combinations provided in this disclosure is applied to Figures 12 to 15, in each frame time of the first to N (N is a positive integer) frames, the third color sub-pixel in the (3n+3)th column of every 18 columns of sub-pixels has no pre-charge, while the first color sub-pixel in the (3n+1)th column and the second color sub-pixel in the (3n+2)th column have pre-charge, where n is a natural number less than or equal to 5; in each frame time of the N+1 to 2N frames, the second color sub-pixel in the (3n+2)th column of every 18 columns of sub-pixels has no pre-charge, while the first color sub-pixel in the (3n+1)th column and the third color sub-pixel in the (3n+3)th column have pre-charge; in each frame time of the 2N+1 to 3N frames, the first color sub-pixel in the (3n+1)th column of every 18 columns of sub-pixels has no pre-charge, while the second color sub-pixel in the (3n+2)th column and the third color sub-pixel in the (3n+3)th column have pre-charge.
[0097] As can be seen from the above, this disclosure overcomes the limitation of insufficient side-view contrast in a horizontally arranged three-gate pixel architecture, proposing a vertically arranged three-gate pixel and its driving mechanism. This achieves single-chip display (One Chip), significantly reducing panel costs, while simultaneously meeting automotive-grade contrast requirements. Therefore, this disclosure is highly suitable for automotive displays. Furthermore, it employs a method of alternating pre-charged and non-pre-charged R / G / B sub-pixels to avoid vertical stripe issues caused by charging. Additionally, this disclosure adjusts the gate driving method so that all RGB sub-pixels are without pre-charge, thus avoiding charging differences caused by pre-charge and non-pre-charge, effectively improving vertical stripe defects. Moreover, this disclosure can use different combinations of gate driving methods to make the pre-charged and non-pre-charged sub-pixels variable, ensuring that each sub-pixel macroscopically exhibits a superposition effect of pre-charged and non-pre-charged pixels, thereby reducing the overall macroscopic grayscale differences caused by charging differences due to pre-charge and non-pre-charge, resulting in significant improvement in vertical stripes.
[0098] Based on the same inventive concept, this disclosure provides a display panel, as shown in FIG21, including an array substrate 001 and a counter substrate 002 placed opposite each other. The array substrate 001 is the array substrate 001 described above in this disclosure, and the counter substrate 002 may include a black matrix, red color resist, green color resist, blue color resist, and spacers. Since the principle by which this display panel solves the problem is similar to that of the array substrate described above, the implementation of this display panel can refer to the embodiments of the array substrate described above, and repeated details will not be elaborated further. In some embodiments, the black matrix, red color resist, green color resist, blue color resist, and spacers may also be disposed on the array substrate 001; this disclosure does not specifically limit this.
[0099] In some embodiments, as shown in FIG21, the display panel provided in this disclosure may further include a liquid crystal layer 003 between an array substrate 001 and a counter substrate 002, a first polarizer 004 on the side of the array substrate 001 away from the counter substrate 002, and a second polarizer 005 on the side of the counter substrate 002 away from the array substrate 001, wherein the polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0100] Based on the same inventive concept, this disclosure provides a display device, as shown in FIG22, including the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature light-emitting diodes (Mini LEDs, Micro LEDs, etc.).
[0101] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.
[0102] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.
[0103] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0104] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.
Claims
1. An array substrate, wherein, include: Multiple sub-pixels are arranged in an array. The sub-pixels include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are arranged cyclically in the row direction, and the sub-pixels in the same column have the same color. Multiple data lines extend along the column direction and are arranged along the row direction. Every three data lines are sequentially designated as a first data line, a second data line, and a third data line. The first data line is electrically connected to the first color sub-pixel, the second data line is electrically connected to the second color sub-pixel, and the third data line is electrically connected to the third color sub-pixel. Furthermore, the first data line, the second data line, and the third data line are connected together. Multiple gate lines extend along the row direction and are arranged along the column direction. Every three gate lines are sequentially designated as a first gate line, a second gate line, and a third gate line. The first gate line, the second gate line, and the third gate line are electrically connected to a sub-pixel of one of the first color sub-pixels, the second color sub-pixels, and the third color sub-pixels in the same row.
2. The array substrate as claimed in claim 1, wherein, The first gate line is electrically connected to the first color sub-pixel in the same row.
3. The array substrate as described in claim 2, wherein, The second gate line and the third gate line are electrically connected to the second color sub-pixel and the third color sub-pixel in the same row, respectively.
4. The array substrate as claimed in claim 2, wherein, The second gate line and the third gate line are electrically connected to the third color sub-pixel and the second color sub-pixel in the same row, respectively.
5. The array substrate as claimed in claim 1, wherein, The first gate line is electrically connected to the third color sub-pixel described in the same row.
6. The array substrate as claimed in claim 5, wherein, The second gate line and the third gate line are electrically connected to the second color sub-pixel and the first color sub-pixel in the same row, respectively.
7. The array substrate as claimed in claim 5, wherein, The second gate line and the third gate line are electrically connected to the first color sub-pixel and the second color sub-pixel in the same row, respectively.
8. The array substrate according to any one of claims 1 to 7, wherein, The first gate line, the second gate line, and the third gate line are located on the same side of the row where the sub-pixel to which they are electrically connected is located.
9. The array substrate according to any one of claims 1 to 7, wherein, The first gate line and the second gate line are located on opposite sides of the row containing the sub-pixel to which they are electrically connected, and the third gate line is located on the side of the row containing the sub-pixel away from the second gate line.
10. The array substrate as claimed in claim 8 or 9, wherein, Three gate lines are provided between two adjacent rows of sub-pixels.
11. The array substrate according to any one of claims 1 to 10, wherein, The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.
12. The array substrate according to any one of claims 1 to 11, wherein, The sub-pixel has a larger dimension in the column direction than in the row direction.
13. The array substrate according to any one of claims 1 to 12, wherein, It also includes a transistor, the first electrode of which is electrically connected to the data line. The active layer of the transistor includes a first edge and a second edge arranged along the row direction, wherein the first edge is located on the side of the second edge closer to the data line, and there is a certain distance between the first edge and the edge of the data line on the side away from the second edge.
14. The array substrate as claimed in claim 13, wherein, The sub-pixel includes a pixel electrode, the first electrode of the transistor is electrically connected to the data line, and the second electrode of the transistor is electrically connected to the pixel electrode; The active layer of the transistor further includes a third edge and a fourth edge arranged side by side along the column direction, wherein the third edge is located on the side of the fourth edge close to the pixel electrode to which the transistor is connected, and the distance between the third edge and the pixel electrode to which the transistor is connected is greater than the distance between the edge of the gate line close to the pixel electrode to which it is connected and the pixel electrode to which it is connected.
15. A display device, wherein, It includes an array substrate as described in any one of claims 1 to 14, a counter substrate opposite to the array substrate, and a backlight module located on the side of the array substrate away from the counter substrate.
16. A pixel driving method, wherein, include: Within one frame, the first to the last gate line are turned on sequentially, and data signals are loaded for each column of sub-pixels through each data line. The turn-on times of two adjacent gate lines overlap. In every three columns of sub-pixels, one column of sub-pixels is not pre-charged, and two columns of sub-pixels are pre-charged. The sub-pixels in the columns without pre-charge have the same color.
17. A pixel driving method, wherein, include: Within one frame, each gate line is turned on sequentially, and data signals are loaded for each column of sub-pixels through each data line. The turn-on times of two adjacent gate lines do not overlap, and each column of sub-pixels is not pre-charged.
18. A pixel driving method, wherein, include: During the time of each frame from frame 1 to N (N is a positive integer), the first to the last gate line is turned on sequentially, and data signals are loaded for each column of sub-pixels through each data line. The turn-on time of two adjacent gate lines partially overlaps. Among every 18 columns of sub-pixels, 6 columns of sub-pixels have no pre-fill and 12 columns of sub-pixels have pre-fill. During each frame time of the N+1 to 2Nth frames, the second to the last gate line are opened sequentially, and data signals are loaded for each column of sub-pixels through each data line. Among every 18 columns of sub-pixels, 6 columns of sub-pixels are not pre-charged, and 12 columns of sub-pixels are pre-charged. The 12 columns of sub-pixels with pre-charge include the 6 columns of sub-pixels that were not pre-charged in the 1st to Nth frames. During each frame time of frames 2N+1 to 3N, the third to the last gate line are sequentially opened, and data signals are loaded for each column of sub-pixels through each data line. Among every 18 columns of sub-pixels, 6 columns of sub-pixels are not pre-charged, and 12 columns of sub-pixels are pre-charged. The 12 columns of sub-pixels with pre-charge include the 6 columns of sub-pixels that were not pre-charged in frames 1 to N, and the 6 columns of sub-pixels that were not pre-charged in frames N+1 to 2N.
19. The pixel driving method as described in claim 18, wherein, During each frame time of frames 1 to N (N is a positive integer), sub-pixels in columns 1 to 6 of every 18 columns of sub-pixels are not pre-filled, and sub-pixels in columns 7 to 18 are pre-filled; During each frame time of frames N+1 to 2N, sub-pixels in columns 1 to 6 and columns 13 to 18 of every 18 columns of sub-pixels are pre-charged, while sub-pixels in columns 7 to 12 are not pre-charged; During each frame time of frames 2N+1 to 3N, sub-pixels in columns 1 to 12 of every 18 columns are pre-charged, while sub-pixels in columns 13 to 18 are not pre-charged.
20. The pixel driving method as described in claim 18, wherein, During each frame time of frames 1 to N (N is a positive integer), in every 18 columns of the sub-pixels, the sub-pixels in column (3n+1) have no pre-filling, while the sub-pixels in columns (3n+2) and (3n+3) have pre-filling, where n is a natural number less than or equal to 5; During each frame time of the N+1 to 2Nth frames, in every 18 columns of the sub-pixels, the (3n+2)th column sub-pixel has no pre-fill, while the (3n+1)th and (3n+3)th column sub-pixels have pre-fill; During each frame time of frames 2N+1 to 3N, in every 18 columns of the sub-pixels, the sub-pixels in column (3n+3) have no pre-fill, while the sub-pixels in columns (3n+1) and (3n+2) have pre-fill.
21. The pixel driving method as described in claim 18, wherein, During the time intervals of each frame from frame 1 to N (N is a positive integer), in every 18 columns of the sub-pixels, the sub-pixels in column (3n+3) have no pre-filling, while the sub-pixels in columns (3n+1) and (3n+2) have pre-filling, where n is a natural number less than or equal to 5; During each frame time of the N+1 to 2Nth frames, in every 18 columns of the sub-pixels, the (3n+2)th column sub-pixel has no pre-fill, while the (3n+1)th and (3n+3)th column sub-pixels have pre-fill; During each frame time of frames 2N+1 to 3N, the sub-pixels in column (3n+1) of every 18 columns have no pre-filling, while the sub-pixels in columns (3n+2) and (3n+3) have pre-filling.