Semiconductor device and manufacturing method therefor
Patent Information
- Application Number
- PCT/CN2025/086266
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-28
- Filing Date
- 2025-03-31
- Publication Date
- 2026-10-01
Smart Images
Figure CN2025086266_01102026_PF_FP_ABST
Abstract
Description
Semiconductor devices and their manufacturing methods Technical Field
[0001] This disclosure generally relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device and a method for manufacturing the same having a channel portion including a shell portion and a core portion. Background Technology
[0002] Fully depleted (FD) SOI semiconductor devices, especially oxide semiconductor field-effect transistors (MOS field-effect transistors), can effectively control short-channel effects and enable further miniaturization of devices. However, the fabrication process for FDSOI MOS field-effect transistors is complex and costly, and their performance needs further improvement. Summary of the Invention
[0003] In view of this, the purpose of this disclosure is at least in part to provide a semiconductor device having a channel portion including a metal sulfide layer and a method for manufacturing the same.
[0004] According to one aspect of this disclosure, a semiconductor device is provided, comprising:
[0005] Substrate;
[0006] The buried oxide layer on the substrate;
[0007] The channel portion includes a semiconductor layer stacked above the substrate, the semiconductor layer having a planar semiconductor layer surface;
[0008] Source / drain sections are arranged above the buried oxygen layer and connected to opposite ends of the channel section; and
[0009] A grid stack between the source and drain portions is arranged on the channel portion;
[0010] The semiconductor layer includes a shell and a core stacked in the projection direction. The shell has a doping type opposite to that of the source / drain, and the core has the same doping type as the source / drain.
[0011] The shell and the core are portions of the semiconductor layer and have opposite doping types, respectively.
[0012] The semiconductor layer of the channel portion is formed to include a protruding semiconductor portion, such that at least a portion of the interface between the channel portion and the gate stack protrudes away from the surface of the semiconductor layer and toward the gate stack.
[0013] According to one embodiment, the interface between the channel portion and the gate stack includes a first surface portion protruding from the semiconductor portion and a tilted second surface portion, the second surface portion extending from the first surface portion to the surface of the semiconductor layer.
[0014] According to one embodiment, the second surface portion of the protruding semiconductor portion and the source / drain portion define a gate stack bottom corner with increased sharpness.
[0015] According to one embodiment, the inner angle between the second surface portion and the source / drain portion is between 25 and 45 degrees.
[0016] According to one embodiment, the semiconductor layer is a silicon layer or a germanium-silicon layer, the first surface portion is oriented along the (100) crystal plane, and the second surface portion is oriented along the (111) crystal plane.
[0017] According to one embodiment, the doping concentration of the shell is greater than the doping concentration of the core.
[0018] According to one embodiment, the shell portion is located on the core portion, or the core portion is located on the shell portion; and
[0019] The shell and the core are either adjacent to each other or spaced apart.
[0020] According to one embodiment, the shell and the core are obtained by performing an ion implantation process and an annealing process on the semiconductor layer.
[0021] According to one embodiment, the gate stack includes gate metal.
[0022] According to one embodiment, the semiconductor device is configured as a plurality of semiconductor devices, the plurality of semiconductor devices including n-type semiconductor devices and / or p-type semiconductor devices.
[0023] Wherein, the channel portion of the n-type semiconductor device includes a p-type doped shell portion and an n-type doped core portion, and / or the channel portion of the p-type semiconductor device includes an n-type doped shell portion and a p-type doped core portion.
[0024] According to one embodiment, the semiconductor device is an n-type semiconductor device.
[0025] When the absolute value of the gate voltage is less than the absolute value of the threshold voltage, the space charge in the core is balanced by the space charge in the shell, resulting in total depletion; and
[0026] When the absolute value of the gate voltage gradually exceeds the absolute value of the threshold voltage, the core first forms a charge accumulation mode and begins to conduct electricity. Then, a larger gate voltage value causes the shell to form an inversion mode and join in conducting electricity.
[0027] According to one embodiment, the semiconductor device is a p-type semiconductor device.
[0028] When the absolute value of the gate voltage is less than the absolute value of the threshold voltage, the space charge in the core is balanced by the space charge in the shell, resulting in total depletion; and
[0029] When the gate voltage value gradually exceeds the absolute value of the threshold voltage, the core first forms a hole accumulation mode and begins to conduct electricity. Then, a larger absolute value of the gate voltage causes the shell to form an inversion mode and join in conducting electricity.
[0030] According to one embodiment, the semiconductor device further includes a buried oxide layer located on the substrate, and the semiconductor layer of the channel portion is stacked on top of the buried oxide layer.
[0031] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising:
[0032] A buried oxide layer is formed on the substrate;
[0033] A semiconductor layer is formed on the buried oxide layer;
[0034] A sacrificial gate is formed on the semiconductor layer, and a sacrificial gate sidewall is formed on the sidewall of the sacrificial gate;
[0035] Source / drain portions are formed on opposite sides of the sacrificial gate sidewall, and the source / drain portions overlap with the sacrificial gate in the channel extension direction;
[0036] Remove the sacrificial gate and optionally remove the sidewalls of the sacrificial gate to free up space between the source and drain;
[0037] A recess is etched in the semiconductor layer within the space, and a semiconductor portion protruding beyond the surface of the semiconductor layer is formed in the recess by epitaxy. Core and shell portions overlapping in the projection direction are formed in the semiconductor layer, wherein the doping type in the shell portion is opposite to the doping type in the semiconductor layer; and
[0038] A gate stack is formed in the space on the semiconductor layer, including a semiconductor portion protruding beyond the surface of the semiconductor layer.
[0039] According to one embodiment, at least one core and a shell are formed in the semiconductor layer by ion implantation.
[0040] According to one embodiment, the semiconductor portion protruding beyond the surface of the semiconductor layer includes a planar first surface portion and an inclined second surface portion, the second surface portion extending from the first surface portion to the surface of the semiconductor layer.
[0041] According to one embodiment, the second surface portion of the protruding semiconductor portion and the source / drain portion define a gate stack bottom corner with increased sharpness, wherein the inner angle between the second surface portion and the source / drain portion is between 25 and 45 degrees.
[0042] According to one embodiment, the method includes forming a p-type doped shell and an n-type doped core for an n-type semiconductor device; and / or
[0043] For p-type semiconductor devices, an n-type doped shell and a p-type doped core are formed.
[0044] According to one embodiment, the doping concentration of the shell is greater than the doping concentration of the core.
[0045] According to one embodiment, the semiconductor layer is selectively etched in the space such that the surface of the etched recess is along the (100) plane, and the first surface portion of the epitaxial growth is along the (100) plane, and the second surface portion is along the (111) plane.
[0046] According to embodiments of this disclosure, the channel portion may include a shell portion and a core portion. By changing the absolute value of the gate voltage, the charge of the shell portion and the core portion changes, allowing them to jointly contribute to conductivity, thereby improving the electrical characteristics of the semiconductor device. The increased sharpness of the gate stack bottom corners of the present invention can increase the driving voltage of the semiconductor device and reduce leakage current. Furthermore, the method for manufacturing the semiconductor device according to embodiments of this disclosure is simpler and has lower cost. Attached Figure Description
[0047] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:
[0048] Figures 1 to 9 schematically illustrate some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure, wherein Figure 9 schematically illustrates a portion of a semiconductor device having a shell, corners, and protruding semiconductor portions and a gate stack bottom corner with increased sharpness. Detailed Implementation
[0049] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0050] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0051] This disclosure may be presented in various forms, some of which are described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.
[0052] FDSOI technology has greatly improved device performance, and the application of field-effect transistors on FDSOI has been greatly developed. In the prior art, junctionless field-effect transistors on FDSOI have shown excellent advantages. Furthermore, the inventors have discovered that devices using FDSOI, which include a shell and a core, have further improved performance, surpassing the performance of devices in the prior art. Moreover, they can be integrated with current 10nm node and below process flows, which is expected to enable the integration and innovation of device structure, materials and processes, and has great development potential.
[0053] The inventors have discovered that the semiconductor layer of the channel portion can be fabricated using epitaxial growth technology. This semiconductor layer can include a shell and a core. For example, in an n-channel field-effect transistor, the shell in the channel semiconductor layer is restricted to p-type doping, while the core can be an n-type doped layer; or, in a p-channel field-effect transistor, the shell in the channel semiconductor layer is restricted to n-type doping, while the core can be a p-type doped layer. The thickness of the shell is comparable to (e.g., of the same order of magnitude) to the thickness of the core, but the doping concentration of the shell is higher than that of the core. The shell and core can be stacked on top of each other, either with the shell on top of the core or vice versa; they can be adjacent or spaced apart. There can be one or two cores. The fabrication methods for the shell and core are highly reliable, for example, they can be achieved through ion implantation after the semiconductor layer is formed. FDSOI planar technology has the potential to achieve or surpass the performance of Fin field-effect transistors at the same node, making it competitive in the market.
[0054] The inventors have also discovered that by forming a protruding semiconductor portion in the semiconductor layer of the channel portion in a semiconductor device, a gate stack bottom corner with improved sharpness can be obtained in the gate stack, thereby increasing the driving voltage of the semiconductor device and reducing leakage current.
[0055] According to embodiments of this disclosure, a semiconductor device is provided. Specifically, the semiconductor device may include a channel portion, a gate stack disposed on the channel portion, and source / drain portions 1011 disposed on opposite sides of the gate stack. The channel portion may extend in a first direction, and its opposite ends in the first direction may be connected to the source / drain portions 1011. In one implementation, there may be no gate sidewall between the gate stack and the source / drain portions 1011.
[0056] The channel portion may include a semiconductor layer, such as Si; in one implementation, the channel portion may also include a semiconductor layer 1005 with high mobility, such as SiGe; in other implementations, the semiconductor layer 1005 may be partially Si and partially SiGe. The semiconductor layer 1005 includes a shell portion 1005-1 and a core portion 1005-2. The shell portion 1005-1 is a partially doped region within the semiconductor layer 1005, and the core portion 1005-2 is a partially doped region within the semiconductor layer 1005, with the doping concentration of the shell portion being higher than that of the core portion.
[0057] The doping concentrations of the shell and core can be set according to the required performance, as can the arrangement between the shell and core. For example, in one implementation, the shell is on top of the core. In another implementation, the core is arranged on top of the shell (not shown). In one implementation, the shell and core are substantially adjacent; in another implementation, the shell and core are spaced apart.
[0058] A core-shell structure or morphology in the channel portion can be used to adjust the Vt value, achieving multiple Vt values. This invention, by setting a core-shell method, advantageously enables multi-Vt fine-tuning in FDSOI devices. This is extremely advantageous for FDSOI devices because conventional / existing multi-Vt FDSOI devices achieve this through back-side wells and biasing methods, which are extremely complex in terms of fabrication and circuit design. The design of this invention allows planar transistors to have a core-shell structure to fully utilize charge balance effects, while simultaneously enabling both the core and shell to conduct under conduction conditions. Additional doping in the shell determines the Vt of the FDSOI transistor, i.e., ΔVT = ΔQ / Cox.
[0059] In this invention, due to the presence of the shell, the additional doping concentration of the shell can be selectively adjusted by adjusting the doping of the shell, thereby enabling fine-tuning of Vt.
[0060] In this invention, since the doping of the shell-core portion can affect the thickness of the channel layer, the thickness of the channel layer can be proportionally reduced or increased. Under high doping levels, carrier mobility is reduced, and therefore, by optimizing the doping level, the final leakage current can be optimized to the greatest extent.
[0061] In the implementation shown in Figure 9, by way of example only, the semiconductor device includes a source / drain portion 1011 and a channel portion between the source / drain portion 1011, wherein the channel portion includes a semiconductor layer 1005, which includes a shell portion 1005-1 and a core portion 1005-2. In other implementations, the semiconductor layer 1005 may include one shell portion and two core portions. Compared to a single core portion, the configuration of one shell portion 1005-1 and two core portions 1005-2 provides better uniformity and greater current under the same conditions. In this implementation, a gate stack is formed between the source and drain portions and above the channel portion. The dashed lines in Figure 9 represent the shell portion 1005-1 and the core portion 1005-2, but these dashed lines do not actually exist.
[0062] In this invention, the semiconductor layer 1005 of the channel portion includes a shell portion 1005-1 and a core portion 1005-2. In one projection direction (e.g., a direction perpendicular to the semiconductor layer), a shell portion 1005-1 is substantially stacked on top of a core portion 1005-2. In the horizontal direction shown in the figure, the span of the shell portion 1005-1 and the core portion 1005-2 is substantially similar to the span of the channel portion. However, it should be understood that the characteristics of ion implantation determine that the ion distribution pattern of the shell portion 1005-1 and the core portion 1005-2 is not necessarily rectangular, but rather generally elliptical. Other shapes can be achieved by changing the implantation process.
[0063] In this embodiment of the invention, the semiconductor layer of the channel portion includes a protruding semiconductor portion that protrudes from the interface between the channel portion and the gate stack, away from the surface of the semiconductor layer, toward the gate stack. Here, the semiconductor layer surface refers to the surface portion of the semiconductor surface shown in the figures excluding the protruding semiconductor portion, as shown in Figures 7-9.
[0064] As shown in Figure 6-9, the semiconductor layer is first selectively etched to form recesses, and then epitaxially formed within these recesses to create protruding semiconductor portions extending beyond the surface of the semiconductor layer. The shell and core can be portions of the semiconductor layer. The core is formed by doping ions in the portion of the semiconductor layer that forms it, and the shell is formed by doping ions in the portion that forms it. The doping type in the shell is opposite to the doping type in the semiconductor layer. The doping type of the shell is opposite to the source / drain type of the semiconductor device.
[0065] Selective etching of the semiconductor layer forms a recess, the bottom surface of which can be a (100) plane; an epitaxial semiconductor, such as silicon or germanium, is formed on the recess to form a protruding semiconductor portion, which has a first surface portion, the top surface shown in the figure, and a second surface portion, the second surface portion being inclined relative to the top surface. Since the epitaxially grown semiconductor grows along the slowest growth direction on one side of the edge, the first surface portion can be a (100) plane, and the second surface portion can be a (111) plane, the included angle between the two crystal planes being shown as α in Figure 9. In this way, the protruding semiconductor portion can be formed in a self-assembly manner, with additional masks and other additional etching processes used to control the shape of the epitaxial semiconductor portion.
[0066] As shown in Figure 9, the core is located in the portion of the semiconductor layer below the recess shown in the figure, and the shell is located in the protruding semiconductor portion above the recess.
[0067] In this invention, it should be understood that after the epitaxially formed protruding semiconductor portion has been grown and formed, as part of the semiconductor layer, the shell and core portions can be the previously formed semiconductor layer and the protruding semiconductor portion subsequently epitaxially formed inside and outside the recess. In implementations of this invention, the core portion can be partially disposed in the previously formed semiconductor layer, or at least partially disposed in the protruding semiconductor portion as shown in the figure; in other implementations of this invention, the shell portion can be partially located below the protruding semiconductor portion, or disposed in the protruding semiconductor portion as shown in the figure, depending on the performance requirements of the semiconductor device and the dimensions of the recessed and protruding semiconductor layers.
[0068] As shown in Figure 9, since the semiconductor layer has a protruding semiconductor portion at this time, the gate subsequently formed is defined as a gate stack bottom corner with increased sharpness. Specifically, the second surface portion of the protruding semiconductor portion along the (111) plane and the source / drain portion together define the gate stack bottom corner with increased sharpness. In the implementation of the present invention, the gate stack bottom corner can have an internal angle β between 25 and 45 degrees. Ideally, the angle α between the face (100) and the face (111) is about 54 degrees, and the angle β of the gate stack bottom corner is the complementary angle between the face (100) and the face (111). However, in actual formation, due to the influence of many other factors, the face formed during epitaxy is not strictly face (111), and the angle α between the formed face and the face (100) is not 54 degrees, but an angle range, approximately between 40 and 70 degrees. Furthermore, there are more factors affecting the formation of the gate stack bottom corner, and the angle β of the gate stack bottom corner is in the range of 25 to 45 degrees.
[0069] This invention utilizes a selective etching-epitaxy process to obtain protruding semiconductor portions in the semiconductor layer of the channel region, taking advantage of the characteristics of the lattice structure of silicon and / or germanium or germanium-silicon semiconductors. This results in a gate stack bottom corner with improved sharpness, eliminating the need for additional masks or other etching processes, simplifying the process, and improving reliability and compatibility.
[0070] The semiconductor device of the present invention has an advantage in having a gate stack bottom corner with enhanced sharpness. Specifically, when the gate turn-on voltage (positive for n-type semiconductor devices and negative for p-type semiconductor devices) turns the channel on, the enhanced sharpness of the gate stack bottom corner can lead to an increase in the electric field around it, resulting in more attracted charge carriers at the channel edge, and thus an increase in the transistor's drive current. When the gate turn-on voltage (negative for n-type semiconductor devices and positive for p-type semiconductor devices) turns the channel off, the enhanced sharpness of the gate stack bottom corner can lead to an increase in the electric field around it, thereby enhancing the depletion charge of the doped material around the corner and along the channel, and thus reducing the transistor's leakage current. In other words, due to the inclusion of the enhanced sharpness of the gate stack bottom corner, the turn-on and turn-off performance of the semiconductor device is greatly improved, the drive current is increased, and the leakage current is reduced.
[0071] The improved sharpness of the gate stack bottom corner of the semiconductor device of the present invention can be formed by epitaxially growing a protruding semiconductor portion from the semiconductor layer without adding additional complex processes, resulting in high reliability and no increase in process complexity.
[0072] This invention utilizes existing injection technology to create a shell-core configuration in the channel section in a very simple way, which can advantageously realize a multi-Vt scheme for FDSOI devices. Compared with conventional / existing methods for manufacturing FDSOI devices with multiple Vt, the process is extremely simple, requiring no additional circuit design and corresponding process settings, thus greatly reducing complexity.
[0073] Those skilled in the art know that the energy of ion implantation can determine the depth of the implanted ions, and the dose of ion implantation can determine the concentration of the implanted ions. The combination of the energy and dose of ion implantation can be used to calculate the depth and amplitude of ion distribution in the semiconductor. Therefore, the formation of the protruding semiconductor portion in the manufacturing process of this invention and the subsequent doping process are fully compatible with conventional planar FDSOI, thus exhibiting strong adaptability.
[0074] By employing the shell-core junctionless channel technology of p-channels, carrier mobility is greatly enhanced, for example, by a factor of 5, thus enabling the formation of silicon-germanium p-channels for FDSOI without further or additional process simplification.
[0075] It should be noted that the technique for forming protruding semiconductor portions and shell-core portions in the channel provided by this invention is not limited to FDSOI, but can be applied to field-effect transistors in a general sense, such as field-effect transistors in conventional bulk silicon wafer integrated circuits (non-FDSOI). Of course, it has better effects in FDSOI with buried oxide layer and thin channel layer.
[0076] According to an embodiment, the above-described semiconductor device can be configured as a plurality of semiconductor devices, which may include n-type semiconductor devices and p-type semiconductor devices. Specifically, in the n-type semiconductor device, the shell portion 1005-1 of the semiconductor layer 1005 in the channel portion is a partially p-type doped region, and the core portion 1005-2 is a partially n-type doped region within the semiconductor layer 1005; in the p-type semiconductor device, the shell portion 1005-1 of the semiconductor layer 1005 in the channel portion is a partially n-type doped region, and the core portion 1005-2 is a partially p-type doped region within the semiconductor layer 1005. The doping concentration of the shell portion is higher than that of the core portion.
[0077] For example, in one implementation of the invention, such as an n-type semiconductor device, the doping concentration of the p-type shell is higher than that of the n-type core, which results in the core being completely depleted in the cutoff state. The core doping concentration can have a wide range, for example, in the range of 10. 17 Up to 10 19 cm -3 Between orders of magnitude.
[0078] According to the embodiment, the contact resistance between the channel portion and the source / drain portion 1011 of the semiconductor device can be lower in the on state of the semiconductor device than in the off state of the semiconductor device.
[0079] According to the embodiment, the above-mentioned semiconductor device can be an n-type semiconductor device. In this case, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage (positive voltage), the space charge in the core 1005-2 is balanced by the space charge in the shell 1005-1, becoming completely depleted. When the absolute value of the gate voltage gradually exceeds the absolute value of the threshold voltage, the core 1005-2 first forms an electron accumulation mode and begins to conduct electricity. Then, a larger gate voltage value causes the shell 1005-1 to form an inversion mode and jointly join in conducting electricity.
[0080] According to the embodiment, the above-described semiconductor device can be a p-type semiconductor device. In this case, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage (negative voltage), the space charge in the core 1005-2 is balanced by the space charge in the shell 1005-1, becoming completely depleted. As the absolute value of the gate voltage gradually increases and exceeds the absolute value of the threshold voltage, the core 1005-2 first forms a hole accumulation mode and begins to conduct electricity. Then, a larger gate voltage value causes the shell 1005-1 to form an inversion mode and jointly participate in conduction.
[0081] The following describes a method for manufacturing a transistor device according to one embodiment of the present invention.
[0082] Figures 1 to 7 schematically illustrate some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure.
[0083] As shown in Figure 1, a buried oxide layer 1003 can be formed on a substrate 1001 (e.g., Si), or a finished silicon-on-insulator (SOI) substrate can be used directly. A semiconductor layer 1005 is formed on the buried oxide layer 1003. In this embodiment, the SOI substrate can be formed using, for example, an SOI fabrication process such as a smart dicing process. The substrate 1001 may include elemental semiconductor materials such as Si or Ge, or compound semiconductor materials such as SiGe. Here, a silicon wafer is used as an example to describe the substrate 1001. The buried oxide layer 1003 may include oxides (e.g., silicon oxide). The semiconductor layer 1005 may include elemental semiconductor materials such as Si or Ge, or compound semiconductor materials such as SiGe. The thickness of the semiconductor layer 1005 can be set as needed, and the semiconductor layer 1005 can be grown directly by epitaxy. It is noted here that the upper surface of the semiconductor layer 1005 shown in the figure is planar, and the semiconductor layer surface mentioned in this application refers to this upper surface; however, in subsequent processes, a portion of the planar semiconductor layer surface can be formed into a protruding semiconductor portion.
[0084] Next, as shown in FIG2, a sacrificial gate 1007 can be formed on the semiconductor layer 1005. Here, the channel extension direction is designated as the first direction (e.g., the horizontal direction within the plane of the paper in FIG2), and the direction intersecting (e.g., perpendicular to) the first direction is designated as the second direction (e.g., the direction perpendicular to the plane of the paper in FIG2). The sacrificial gate 1007 extends along the second direction. The sacrificial gate 1007 may comprise polysilicon. For convenience, a hard mask that may exist on the sacrificial gate 1007 is not shown. On the sidewalls of the sacrificial gate 1007, sidewalls 1009 of the sacrificial gate 1007 can be formed by a sidewall forming process. For example, sidewalls 1009 may comprise a nitride (e.g., silicon nitride). As shown in FIG2, in the third direction (the vertical direction within the plane of the paper in FIG2), the portion of the upper surface of the semiconductor layer 1005 not covered by the sacrificial gate 1007 and sidewalls 1009 is exposed.
[0085] As shown in Figure 3, a source / drain portion 1011 extending upward in a third direction can be formed by using the exposed portion of the upper surface of the semiconductor layer 1005 as a seed, for example, through selective epitaxial growth. The source / drain portion 1011 can be formed on opposite sides of the sidewalls 1009 of the sacrificial gate 1007 and can be formed to overlap with the sacrificial gate 1007 in a first direction. The source / drain portion 1011 can comprise various suitable semiconductor materials, for example, Si for an n-type field-effect transistor and SiGe for a p-type field-effect transistor. The source / drain portion 1011 can be doped to the desired conductivity type (n-type doping for an n-type field-effect transistor and p-type doping for a p-type field-effect transistor) by, for example, in-situ doping or ion implantation. Advantageously, the height of the source / drain portion 1011 can be less than the height of the sacrificial gate 1007.
[0086] Next, an alternative gate process can be implemented.
[0087] For example, as shown in FIG4, an interlayer dielectric layer 1013 can be formed on the semiconductor layer 1005. The interlayer dielectric layer can be an oxide layer. For example, the interlayer dielectric layer 1013 can be formed by depositing an oxide and then planarizing the oxide deposited by CMP. CMP can be performed to expose the sacrificial gate 1007 inside the sacrificial gate sidewall 1009.
[0088] As shown in Figure 5, the sacrificial gate 1007 and the sacrificial gate sidewall 1009 can be selectively etched away to release the space 1015 between the source / drain portions 1011, forming an opening pattern that exposes the surface of the semiconductor layer 1005. Since the sacrificial gate sidewall 1009 is removed in addition to the sacrificial gate 1007, there may be no gate sidewall between the gate stack subsequently formed in the released space 1015 and the source / drain portions 1011. In another embodiment, the gate sidewall may be retained.
[0089] It should be noted that, for convenience, space 1015 in Figure 5 is shown as having a substantially uniform width in the vertical direction. However, considering the shape of the sacrificial fence sidewall 1009, space 1015 may have a shape where the lower width is greater than the upper width.
[0090] Subsequently, as shown in FIG6, the surface of the semiconductor layer 1005 exposed by the opening pattern (space 1015) is selectively etched. A trapezoidal recess, as schematically shown, is formed on the surface of the semiconductor layer 1005 exposed by the opening pattern (space 1015), wherein the surface of the semiconductor layer 1005, such as a silicon layer, in the horizontal direction of the paper is a (100) surface, and the inclined surface of the semiconductor layer 1005 at an angle to the horizontal surface can be a (111) surface (the actual inclined surface formed may not be an ideally flat inclined surface, for example, having a curvature or other irregular shape).
[0091] Silicon is then epitaxially grown in the trapezoidal recesses on the surface of the exposed semiconductor layer 1005. The epitaxial silicon fills the recesses as shown in FIG. 6 and forms protruding semiconductor portions, such as silicon, so that the planar semiconductor layer surface has protruding semiconductor portions. In this paper, the planar semiconductor layer surface is not excluded from having protruding semiconductor portions.
[0092] The protruding semiconductor portion here refers to the portion that protrudes from the upper surface of the plane or the outside of the semiconductor surface relative to the planar semiconductor surface (the upper surface mentioned above).
[0093] As shown in Figure 7, the protruding semiconductor portion on the surface of the semiconductor layer has a planar (upper surface) first surface portion and an inclined second surface portion, the second surface portion extending from the first surface portion to the surface of the semiconductor layer. Figure 7 schematically shows the protruding semiconductor portion as trapezoidal.
[0094] In one implementation, the angle between the first surface portion and the inclined second surface portion, as shown in Figure 7, is the angle between the (100) and (111) planes, ideally approximately 54 degrees. The actual angle between the first surface portion and the inclined second surface portion is between 40 and 70 degrees.
[0095] According to the present invention, a shell portion 1005-1 and a core portion 1005-2 can be formed by implanting ions toward the semiconductor layer 1005 using an opening pattern and a subsequent annealing process. Multiple ion implantation process parameters can be set according to the number, depth, and concentration of the shell portions 1005-1 and the core portions 1005-2, so as to form ion implantation regions of different depths and concentrations in the semiconductor layer 1005, thereby providing a shell portion 1005-1 and at least one core portion 1005-2 (e.g., one core portion, or two core portions). The distribution of doped ions in the shell portions 1005-1 and the core portions 1005-2 formed by this process can be as shown in FIG. 8, which is schematic.
[0096] The use of ion implantation is advantageous because it allows for precise control over the distribution range of the shell 1005-1 and core 1005-2, including depth and distribution amplitude. For example, the shell can be adjacent to the core or spaced apart. It also allows for precise control over the ion concentration, i.e., the doping concentration, of the shell 1005-1 and core 1005-2. Ion implantation is a mature semiconductor manufacturing process, thus it can be implemented using existing semiconductor process flows at a low cost. Since ion implantation can penetrate multiple layers and the implantation depth can be controlled by the implantation energy, it allows for the direct implantation of ions into different depth regions within the semiconductor layer 1005 to form the shell 1005-1 and core 1005-2 on the surface of the semiconductor layer 1005. Ion implantation can also be performed after other dielectric layers have been formed on top of the semiconductor layer 1005. For example, ions can be implanted through an opening (before epitaxial growth) as shown in Figure 6, or through an opening and a dielectric layer within the opening (after epitaxial growth of the semiconductor portion) as shown in Figure 8. The annealing process of this invention can be achieved through laser nanosecond annealing, which has low thermal costs and is fast.
[0097] For example, for an n-type field-effect transistor, n-type ions are first injected with a predetermined energy to provide the ion distribution for the core 1005-2, and then the injection energy is adjusted to inject p-type ions to provide the ion distribution for the shell 1005-1. In another implementation, for an n-type field-effect transistor, n-type ions are first injected with a predetermined energy to provide the ion distribution for the core 1005-2, then the injection energy is reduced to inject n-type ions to provide the ion distribution for a second core 1005-2, and then the injection energy is adjusted to inject p-type ions to provide the ion distribution for the shell 1005-1. In this implementation, the ion doping concentration of the shell 1005-1 can be higher than the ion doping concentration of the core 1005-2, that is, the ion dose injected into the shell 1005-1 is slightly higher than the ion dose injected into the core 1005-2.
[0098] For a p-type field-effect transistor, p-type ions are first injected at a predetermined energy to provide the ion distribution in the core 1005-2, and then the injection energy is adjusted to inject n-type ions to provide the ion distribution in the shell 1005-1. The dose of n-type ions injected into the shell 1005-1 is slightly higher than the dose of p-type ions injected into the core 1005-2.
[0099] In this invention, during ion implantation, the presence of the opening pattern allows ions to be implanted into the exposed portion of the semiconductor layer 1005 within the openings. Since the entire SOI substrate is covered by an interlayer dielectric layer 1013, the implanted ions are blocked within this layer. Therefore, a separate hard mask and alignment process are not required for ion implantation, simplifying the manufacturing process and ensuring accurate implantation.
[0100] Subsequently, as shown in Figure 9, a gate stack can be formed in space 1015, for example, by deposition. The gate stack may include metal.
[0101] Due to the protruding semiconductor portion, the deposited gate stack forms a sharper bottom corner under the influence of the protruding semiconductor portion. Since the sidewalls of the space between the source / drain portions may be imperfect and not vertical, the internal angle between the second surface portion and the source / drain portions is between 25 and 45 degrees. However, compared to the case without the protruding semiconductor portion, the bottom corner of the gate stack becomes sharper. This angle is schematically shown as β in Figure 9.
[0102] For n-type and p-type field-effect transistors, as described above, corresponding shell portions 1005-1 and core portions 1005-2 can be formed respectively, and n-type and p-type work function layers can be formed respectively. In one implementation, the threshold voltages of the n-type and p-type field-effect transistors can be set to be substantially symmetrical. In this case, the manufacturing process of the semiconductor device can be simplified and the manufacturing cost can be reduced.
[0103] The semiconductor devices according to embodiments of this disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such semiconductor devices, and electronic devices can be constructed therefrom. Such electronic devices may also include components such as display screens that cooperate with the integrated circuits and wireless transceivers that cooperate with the integrated circuits. Examples of such electronic devices include smartphones, computers, tablet computers, wearable smart devices, artificial intelligence devices, and power banks.
[0104] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0105] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A semiconductor device, comprising: Substrate; The buried oxide layer on the substrate; The channel portion includes a semiconductor layer stacked above the substrate, the semiconductor layer having a planar semiconductor layer surface; Source / drain sections are arranged above the buried oxygen layer and connected to opposite ends of the channel section; and A grid stack between the source and drain portions is arranged on the channel portion; The semiconductor layer includes a shell and a core stacked in the projection direction. The shell has a doping type opposite to that of the source / drain, and the core has the same doping type as the source / drain. The shell and the core are portions of the semiconductor layer and have opposite doping types, respectively. The semiconductor layer of the channel portion is formed to include a protruding semiconductor portion, such that at least a portion of the interface between the channel portion and the gate stack protrudes away from the surface of the semiconductor layer and toward the gate stack.
2. The semiconductor device of claim 1, wherein the interface between the channel portion and the gate stack includes a first surface portion protruding from the semiconductor portion as a plane and a second surface portion inclined to extend from the first surface portion to the surface of the semiconductor layer.
3. The semiconductor device of claim 2, wherein the second surface portion of the protruding semiconductor portion and the source / drain portion define a gate stack bottom corner with increased sharpness of the gate stack.
4. The semiconductor device of claim 3, wherein the inner angle between the second surface portion and the source / drain portion is between 25 and 45 degrees.
5. The semiconductor device according to claim 1, wherein the semiconductor layer is a silicon layer or a germanium-silicon layer, the first surface portion is oriented along the (100) crystal plane, and the second surface portion is oriented along the (111) crystal plane.
6. The semiconductor device according to claim 1, wherein the doping concentration of the shell portion is greater than the doping concentration of the core portion.
7. The semiconductor device of claim 1, wherein the housing is located on the core, or the core is located on the housing; and The shell and the core are either adjacent to each other or spaced apart.
8. The semiconductor device of claim 1, wherein the shell and the core are obtained by performing an ion implantation process and an annealing process on the semiconductor layer.
9. The semiconductor device of claim 1, wherein the gate stack comprises gate metal.
10. The semiconductor device of claim 1, wherein, The semiconductor device is configured as a plurality of semiconductor devices, including n-type semiconductor devices and / or p-type semiconductor devices. Wherein, the channel portion of the n-type semiconductor device includes a p-type doped shell portion and an n-type doped core portion, and / or the channel portion of the p-type semiconductor device includes an n-type doped shell portion and a p-type doped core portion.
11. The semiconductor device of claim 10, wherein the semiconductor device is an n-type semiconductor device. When the absolute value of the gate voltage is less than the absolute value of the threshold voltage, the space charge in the core is balanced by the space charge in the shell, resulting in total depletion; and When the absolute value of the gate voltage gradually exceeds the absolute value of the threshold voltage, the core first forms a charge accumulation mode and begins to conduct electricity. Then, a larger gate voltage value causes the shell to form an inversion mode and join in conducting electricity.
12. The semiconductor device of claim 10, wherein the semiconductor device is a p-type semiconductor device. When the absolute value of the gate voltage is less than the absolute value of the threshold voltage, the space charge in the core is balanced by the space charge in the shell, resulting in total depletion; and When the gate voltage value gradually exceeds the absolute value of the threshold voltage, the core first forms a hole accumulation mode and begins to conduct electricity. Then, a larger absolute value of the gate voltage causes the shell to form an inversion mode and join in conducting electricity.
13. The semiconductor device of claim 1, further comprising a buried oxide layer located on the substrate, wherein the semiconductor layer of the channel portion is stacked on top of the buried oxide layer.
14. A method for manufacturing a semiconductor device, comprising: A buried oxide layer is formed on the substrate; A semiconductor layer is formed on the buried oxide layer; A sacrificial gate is formed on the semiconductor layer, and a sacrificial gate sidewall is formed on the sidewall of the sacrificial gate; Source / drain portions are formed on opposite sides of the sacrificial gate sidewall, and the source / drain portions overlap with the sacrificial gate in the channel extension direction; Remove the sacrificial gate and optionally remove the sidewalls of the sacrificial gate to free up space between the source and drain; A recess is etched in the semiconductor layer in the space, and a semiconductor portion protruding to the surface of the semiconductor layer is formed in the recess by an epitaxial method. Core and shell portions are formed in the semiconductor layer that overlap in the projection direction, wherein the doping type in the shell portion is opposite to the doping type in the semiconductor layer. as well as A gate stack is formed in the space on the semiconductor layer, including a semiconductor portion protruding beyond the surface of the semiconductor layer.
15. The method of claim 14, wherein, At least one core and a shell are formed in the semiconductor layer by ion implantation.
16. The method of claim 14, wherein, The semiconductor portion protruding beyond the surface of the semiconductor layer includes a planar first surface portion and an inclined second surface portion, the second surface portion extending from the first surface portion to the surface of the semiconductor layer.
17. The method of claim 16, wherein, The second surface portion of the protruding semiconductor portion and the source / drain portion define a gate stack bottom corner with increased sharpness, wherein the inner angle between the second surface portion and the source / drain portion is between 25 and 45 degrees.
18. The method of claim 14, comprising: For n-type semiconductor devices, a p-type doped shell and an n-type doped core are formed; and / or For p-type semiconductor devices, an n-type doped shell and a p-type doped core are formed.
19. The method of claim 18, wherein the doping concentration of the shell portion is greater than the doping concentration of the core portion.
20. The method of claim 14, wherein the semiconductor layer is selectively etched in the space such that the surface of the etched recess is along the (100) plane, and the first surface portion of the epitaxial growth is along the (100) plane, and the second surface portion is along the (111) plane.