Semiconductor device and manufacturing method therefor
Patent Information
- Application Number
- PCT/CN2025/086290
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-28
- Filing Date
- 2025-03-31
- Publication Date
- 2026-10-01
Smart Images
Figure CN2025086290_01102026_PF_FP_ABST
Abstract
Description
Semiconductor devices and their manufacturing methods Technical Field
[0001] This disclosure generally relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device and a method for manufacturing the same having a channel portion including a shell portion and a core portion. Background Technology
[0002] Fully depleted (FD)SOI semiconductor devices, especially oxide semiconductor field-effect transistors (MOS field-effect transistors), can effectively control short-channel effects and enable further miniaturization. However, the fabrication process for FDSOI MOS field-effect transistors is complex and costly, and their performance requires further improvement. Furthermore, these FDSOI devices are used in lower-voltage logic applications. FDSOIs capable of operating at higher voltages (e.g., >10V) require a drift region to support the voltage; such high-voltage devices are called latent diffusion FDSOIs (or LDMOS). Summary of the Invention
[0003] In view of this, the purpose of this disclosure is at least in part to provide a semiconductor device and a method for manufacturing the same.
[0004] According to one aspect of this disclosure, a semiconductor device is provided, comprising:
[0005] Substrate;
[0006] Buried oxide layer on substrate; and
[0007] A semiconductor layer stacked on top of the buried oxide layer;
[0008] The semiconductor device includes a first type of semiconductor device and a second type of semiconductor device, wherein the first semiconductor device includes:
[0009] The first channel portion includes a first portion of the semiconductor layer;
[0010] A first source / drain of a first doped type is disposed above the buried oxide layer and connected to opposite ends of the first channel portion; and
[0011] A first gate stack between the first source and drain portions is disposed on the first channel portion; and
[0012] The second semiconductor device includes:
[0013] The second channel portion includes a second portion of the semiconductor layer;
[0014] A second source / drain of the second doped type is disposed above the buried oxide layer and connected to the opposite ends of the second channel portion; and
[0015] A second gate stack between the second source / drain is arranged on the second channel portion;
[0016] The first channel portion and the second channel portion each include at least one shell portion and at least one core portion that are spaced apart from each other and overlap in the projection direction, wherein the at least one shell portion and the at least one core portion have opposite doping types;
[0017] The drain portion of the first semiconductor device and the drain portion of the second semiconductor device are electrically connected, and the first gate stack of the first semiconductor device and the second gate stack of the second semiconductor device are electrically connected.
[0018] This invention provides a semiconductor device comprising:
[0019] Substrate;
[0020] The buried oxide layer on the substrate; and
[0021] A semiconductor layer stacked on top of the buried oxide layer;
[0022] The semiconductor device includes a third semiconductor device section and a drift section, wherein the third semiconductor device section includes:
[0023] The third channel portion includes the third part of the semiconductor layer;
[0024] A third source / leakage section is disposed above the buried oxygen layer and connected to the opposite ends of the third channel section; and
[0025] A third gate stack between the third source / drain is arranged on the third channel portion; and
[0026] The drift section includes:
[0027] The drift channel includes a fourth portion of the semiconductor layer, wherein the length of the drift channel in the extending direction of the semiconductor layer is greater than that of the third channel portion;
[0028] A fourth source / drain is disposed above the buried oxide layer and connected to the opposite ends of the drift channel. The doping type of the fourth source / drain is the same as that of the third source / drain.
[0029] An oxide layer between the fourth source and drain is disposed on the drift channel;
[0030] The third channel portion and the drift channel portion each include at least one shell portion and at least one core portion that are spaced apart from each other and overlap in the projection direction, wherein the at least one shell portion and the at least one core portion have opposite doping types; and
[0031] The drain portion of the third semiconductor device portion is the source portion of the drift portion.
[0032] In one embodiment, the thickness of one shell portion of at least one shell portion is 5 nm to 10 nm, and / or the thickness of one core portion of at least one core portion is 10 nm to 50 nm.
[0033] In one embodiment, at least one core comprises one or two cores, and / or wherein the at least one shell comprises one or two shells.
[0034] In one embodiment, the shell and the core are obtained by performing an ion implantation process and an annealing process on the semiconductor layer.
[0035] In one embodiment, the gate stack includes a work function layer and a gate metal conductive layer.
[0036] In one embodiment, the gate stack includes a first gate dielectric layer.
[0037] In one embodiment, the first semiconductor device includes a first doped source / drain and a first gate dielectric layer, wherein the work function on the first gate dielectric layer is of the first type; the second semiconductor device includes a second doped source / drain and a second gate dielectric layer, wherein the work function layer on the second gate dielectric layer is of the second type.
[0038] One aspect of the present invention provides a method for manufacturing a semiconductor device, comprising:
[0039] A buried oxide layer is formed on the substrate;
[0040] A semiconductor layer is formed on the buried oxide layer;
[0041] A first sacrificial gate and a second sacrificial gate are formed on the semiconductor layer, and a first sacrificial gate sidewall and a second sacrificial gate sidewall are formed on the sidewalls of the first sacrificial gate and the second sacrificial gate, respectively.
[0042] Using a mask, a first source / drain of a first doped type is formed on opposite sides of the first sacrificial gate sidewall, and a second source / drain of a second doped type is formed on opposite sides of the second sacrificial gate. The first source / drain of the first doped type and the second source / drain of the second type overlap with the first sacrificial gate and the second sacrificial gate in the extension direction of the channel.
[0043] Remove the first sacrificial gate, the second sacrificial gate, and optionally remove the sidewalls of the first sacrificial gate and the second sacrificial gate sidewalls to free up space between the first source / drain and the second source / drain;
[0044] At least one core and at least one shell are formed in the semiconductor layer within the space;
[0045] A gate stack is formed on the semiconductor layer in the space; and
[0046] The drain portion of the first doped type source / drain is electrically connected to the drain portion of the second type source / drain, and the gate stack between the first doped type source / drain and the gate stack between the second type source / drain are electrically connected;
[0047] The semiconductor layer of the channel portion between the first doped source / drain and the second doped source / drain includes at least one shell portion of the second doped type and at least one core portion of the first doped type, wherein the first doping type and the second doping type are opposite doping types.
[0048] One aspect of the present invention provides a method for manufacturing a semiconductor device, comprising:
[0049] A buried oxide layer is formed on the substrate;
[0050] A semiconductor layer is formed on the buried oxide layer;
[0051] A third sacrificial gate and a fourth sacrificial gate are formed on the semiconductor layer, and optionally a third sacrificial gate sidewall is formed on the sidewall of the third sacrificial gate, wherein the width of the fourth sacrificial gate is greater than that of the third sacrificial gate;
[0052] Sources / drains of the same doping type are formed on the opposite outer sides of the third and fourth sacrificial gate sidewalls and between the third and fourth sacrificial gate sidewalls, and the source / drains overlap with the third and fourth sacrificial gates in the channel extension direction;
[0053] Remove the third and fourth sacrificial gates and optionally remove the sidewalls of the third sacrificial gate to release the third and fourth spaces between the source and drain;
[0054] At least one core and at least one shell are formed in the semiconductor layer in the third and fourth spaces, the at least one shell being located above the at least one core; and
[0055] A gate stack is formed on the semiconductor layer in the third space, and an oxide layer is formed on the semiconductor layer in the fourth space, wherein the third space corresponds to a third sacrificial gate and the fourth space corresponds to a fourth sacrificial gate;
[0056] The doping type of the source / drain portion is opposite to that of at least one shell portion, but the same as that of at least one core portion.
[0057] In one embodiment, at least one core and at least one shell are formed in the semiconductor layer by ion implantation.
[0058] In one embodiment, the thickness of one shell portion of at least one shell portion is 5 nm to 10 nm, and / or the thickness of one core portion of at least one core portion is 10 nm to 50 nm.
[0059] In one embodiment, forming the gate stack includes:
[0060] A first gate dielectric layer, a work function layer, and a gate conductive layer are sequentially formed on the exposed surface of the semiconductor layer.
[0061] According to embodiments of this disclosure, the channel portion may include a shell portion and a core portion. By changing the absolute value of the gate voltage, the charge of the shell portion and the core portion changes, allowing them to jointly contribute to conductivity, thereby improving the electrical characteristics of the semiconductor device. Furthermore, the method for manufacturing the semiconductor device according to embodiments of this disclosure is simpler and has lower cost. Attached Figure Description
[0062] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:
[0063] Figures 1 to 7 schematically illustrate some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure.
[0064] Figure 8 schematically illustrates the structure of a semiconductor device (inverter) according to an embodiment of the present disclosure.
[0065] Figure 9 schematically illustrates the structure of a semiconductor device (with a drift section) according to an embodiment of the present disclosure. Detailed Implementation
[0066] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0067] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0068] This disclosure may be presented in various forms, some of which are described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.
[0069] FDSOI technology has greatly improved device performance, and the application of field-effect transistors on FDSOI has been greatly developed. In the prior art, junctionless field-effect transistors on FDSOI have shown excellent advantages. Furthermore, the inventors have discovered that devices using FDSOI, which include a shell and a core, have further improved performance, surpassing the performance of devices in the prior art. Moreover, they can be integrated with current 10nm node and below process flows, which is expected to enable the integration and innovation of device structure, materials and processes, and has great development potential.
[0070] The inventors have discovered that a channel layer can be fabricated using epitaxial growth techniques. This channel layer can include a shell and a core. For example, in an n-channel field-effect transistor, the shell in the semiconductor layer of the channel is limited to undoped or lightly p-type doped material, while the core can be a heavily n-type doped layer. The thickness of the shell is comparable to (e.g., on the same order of magnitude) as the thickness of the core, but the thickness of both can be adjusted as needed. The fabrication methods for the shell and core are highly reliable; for example, they can be achieved through direct epitaxy or by ion implantation after the semiconductor layer has been formed. FDSOI planar technology has the potential to achieve or surpass the performance of Fin field-effect transistors at the same node, making it competitive in the market.
[0071] According to embodiments of this disclosure, a semiconductor device is provided. Specifically, the semiconductor device may include: a substrate; a buried oxide layer on the substrate; and a semiconductor layer stacked on top of the buried oxide layer; wherein the semiconductor device includes a first semiconductor device of a first type (e.g., n-type or p-type) and a second semiconductor device of a second type (correspondingly, e.g., p-type or n-type). In this invention, the first semiconductor device and the second semiconductor device are both located on the buried oxide layer on the substrate, and their channel portions are formed by the same semiconductor layer.
[0072] In one embodiment, a first semiconductor device includes: a first channel portion including a first portion of a semiconductor layer; first source / drain portions disposed over a buried oxide layer and connected to opposite ends of the first channel portion; and a first gate stack between the first source / drain portions disposed on the first channel portion. A second semiconductor device includes a second channel portion including a second portion of a semiconductor layer; second source / drain portions disposed over a buried oxide layer and connected to opposite ends of the second channel portion; and a second gate stack between the second source / drain portions disposed on the second channel portion. The first channel portion and the second channel portion each include at least one shell portion and at least one core portion that are spaced apart from each other and overlap in a projected direction, the at least one shell portion and the at least one core portion having opposite doping types.
[0073] In an embodiment of the present invention, as shown in FIG8, a first semiconductor device and a second semiconductor device together constitute an inverter, wherein the drain portion (Vss) of the first semiconductor device and the drain portion (Vcc) of the second semiconductor device are electrically connected, and the first gate stack of the first semiconductor device and the second gate stack of the second semiconductor device are electrically connected (VG).
[0074] The first semiconductor device and the second semiconductor device can have the same structure, such as similar channel portions, gate stacks, and core and shell portions within the channel portions. The difference between the first semiconductor device and the second semiconductor device lies in having source / drain portions with opposite doping types.
[0075] In this invention, the first and second channel portions may include portions of a semiconductor layer, such as Si; in one embodiment, the first and second channel portions may also include portions of a semiconductor layer 1005 with high mobility, such as SiGe; in other embodiments, the semiconductor layer 1005 may be partially Si and partially SiGe. The semiconductor layer 1005 includes at least one shell portion 1005-1 and at least one core portion 1005-2. The shell portion 1005-1 is a partially doped region within the semiconductor layer 1005, and the core portion 1005-2 is a partially doped region within the semiconductor layer 1005. The first and second channel portions may have the same core and shell structure; however, it should be understood that the first and second channel portions may have different core and shell structures. For example, the first channel portion may have two shell portions and one core, and the second channel portion may have one shell portion and one core. Those skilled in the art can specifically configure these configurations according to the principles and significance disclosed in this invention.
[0076] At least one shell portion 1005-1 and at least one core portion 1005-2 means, for example, combinations such as one shell portion 1005-1 and one core portion 1005-2, two shell portions 1005-1 and one core portion 1005-2, two shell portions 1005-1 and two core portions 1005-2, one shell portion 1005-1 and two core portions 1005-2, etc. It should be understood that there can also be configurations such as three or four shell portions and / or three or four core portions. The number of shell portions and core portions, the doping concentration of shell portions and core portions, and the arrangement between shell portions and core portions can be set according to the required performance. For example, in one embodiment, one shell portion and one core portion are arranged alternately. In one embodiment, one core portion is arranged on top of one shell portion (not shown).
[0077] In the embodiment shown in Figure 7, by way of example only, the first semiconductor device includes a first source / drain portion 1011 and a first channel portion between the first source / drain portion 1011, wherein the first channel portion includes a portion of a semiconductor layer 1005, the portion of which includes two shell portions 1005-1 and a core portion 1005-2. Compared to a single shell portion, the configuration using two shell portions 1005-1 superimposed with a core portion 1005-2 has better uniformity and greater current under the same conditions. In this embodiment, a first gate stack is formed between the first source / drain portions 1011 and above the first channel portion; the first gate stack may include a first gate dielectric layer and / or a first work function layer 1019. In one embodiment, the first gate stack may include the first work function layer 1019, such as a metal work function layer, particularly, for example, a titanium nitride layer. In one embodiment, the first gate stack includes a first gate dielectric layer 1017, such as a hafnium oxide layer. The hafnium oxide layer may have a thickness of approximately 2 nm. The first gate stack may also include a gate conductive layer 1021.
[0078] In one embodiment, a sidewall 1009 is formed on the sidewall of the first gate stack, located between the first gate stack and the first source / drain portion 1011. In the embodiment of FIG. 7, no sidewall is provided. Furthermore, in the embodiment of FIG. 7, the semiconductor device shown includes an interlayer dielectric layer 1013; however, in other embodiments, the semiconductor device may not include the interlayer dielectric layer 1013. It should be understood that in this embodiment, the semiconductor device also includes a second semiconductor device, not shown in FIG. 7, which has a similar structure to the first semiconductor device and is formed on the buried oxide layer 1003. The second channel portion of the second semiconductor device includes a portion of the semiconductor layer 1005, including a similar core and shell structure, which will not be described in detail here. Since the second semiconductor device and the second semiconductor device have similar structures, and the core and shell can be completely identical, the fabrication process does not require distinguishing between the first and second semiconductor devices, thereby reducing the number of masks and implantation cycles.
[0079] In an embodiment of the present invention, the semiconductor layer 1005 of the first channel portion includes at least one shell portion 1005-1 and at least one core portion 1005-2. As an example, in an embodiment of an n-type semiconductor device, n-type ion implantation (forming a core portion) is performed toward the channel portion using predetermined energy and dose, followed by p-type implantation (forming a shell portion) toward the channel portion of the n-type semiconductor device using different predetermined energy and dose. In this embodiment, two different energies can be used for p-type implantation to form ion doping distributions at different depths of the semiconductor layer 1005, wherein the doses can be the same or different; after ion implantation is completed, rapid laser annealing, such as nanosecond laser annealing, can be performed. Through this process, two shell layers 1005-1 and one core layer 1005-2 are formed within the semiconductor layer 1005 of the first and second channels. The depth of the core layer 1005-2 is greater than that of the shell layers 1005-1. Thus, in one projection direction, the two shell layers 1005-1 are substantially stacked on top of the core layer 1005-2, and the two shell layers 1005-1 and the core layer 1005-2 are arranged to be spaced apart from each other. The amplitude or range of the shell layer 1005-1 (thickness in the vertical direction as shown in the figure) is, for example, about 5-10 nm, and the amplitude or range of the core layer 1005-2 (thickness in the vertical direction as shown in the figure) is, for example, about 10-50 nm. In the horizontal direction of the figure, the span of the shell layer 1005-1 and the core layer 1005-2 is substantially similar to the span of the channel. However, it should be understood that the characteristics of ion implantation determine that the ion distribution pattern of the shell 1005-1 and the core 1005-2 is not necessarily rectangular, but rather roughly elliptical. Other shapes can be achieved by changing the implantation process.
[0080] This invention utilizes existing implantation techniques to advantageously realize a multi-Vt scheme for FDSOI devices by setting one or more shells in the channel portion in a very simple manner. Compared with conventional / existing methods for manufacturing FDSOI devices with multiple Vt, the process is extremely simple. In particular, when the first semiconductor device and the second semiconductor device have the same shell-core structure, the channel portion structure of the first semiconductor device and the second semiconductor device can be formed simultaneously by the same implantation method, without the need for additional circuit design and corresponding process settings, greatly reducing complexity. Furthermore, the channel portion with the same structure in the first and second (i.e., n and p) semiconductor devices has the characteristic of charge balance, realizing a fully depleted channel and symmetrical Vt.
[0081] In another embodiment of the present invention, the shell portion 1005-1 may be an undoped portion of the semiconductor layer 1005, or the shell portion 1005-1 may be an undoped region of the semiconductor layer 1005.
[0082] In one embodiment, the threshold voltage of the n-type semiconductor device and the threshold voltage of the p-type semiconductor device can be set to be substantially symmetrical, which can be determined, for example, by the doping dose and work function layer of the shell and the core. According to an embodiment, the contact resistance between the channel portion and the source / drain portion 1011 of the semiconductor device can be lower in the on-state of the semiconductor device than in the off-state.
[0083] According to the embodiment, the first semiconductor device described above can be an n-type semiconductor device. In this case, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage (positive voltage), the space charge in the core 1005-2 of the n-type semiconductor device is balanced by the space charge in the shell 1005-1, becoming completely depleted. When the absolute value of the gate voltage gradually exceeds the absolute value of the threshold voltage, the core 1005-2 of the n-type semiconductor device first forms an electron accumulation mode and begins to conduct electricity. Then, a larger gate voltage value causes the shell 1005-1 to form an inversion mode and jointly join in conducting electricity.
[0084] According to the embodiment, the second semiconductor device described above can be a p-type semiconductor device. In this case, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage (negative voltage), the space charge in the core 1005-2' is balanced by the space charge in the shell 1005-1', becoming completely depleted. As the absolute value of the gate voltage gradually increases and exceeds the absolute value of the threshold voltage, the core 1005-2' first forms a hole accumulation mode and begins to conduct electricity. Then, a larger gate voltage value causes the shell 1005-1' to form an inversion mode and jointly participate in conduction.
[0085] In this invention, the inverter is formed by connecting a first semiconductor device and a second semiconductor device, that is, electrically connecting the drain of the first semiconductor device and the drain of the second semiconductor device, and electrically connecting the gate stack (actually the gate conductor layer) of the first semiconductor device and the gate stack (actually the gate conductor layer) of the second semiconductor device. Due to the arrangement of the shell and the core, a higher quality inverting voltage can be achieved, and the noise margin can be improved.
[0086] The following describes a method for manufacturing a transistor device according to an embodiment of the present invention.
[0087] Figures 1 to 7 schematically illustrate some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure. For simplicity, only the manufacturing process of a first semiconductor device is shown. The second semiconductor device is formed by the same or similar process, especially when the first and second semiconductor devices have the same channel structure. Except for the source / drain portions, the formation processes of other components are exactly the same, which is also an advantage of the simplicity of the process of the present invention.
[0088] As shown in Figure 1, a buried oxide layer 1003 can be formed on a substrate 1001 (e.g., Si), or a finished silicon-on-insulator (SOI) substrate can be used directly. A semiconductor layer 1005 is formed on the buried oxide layer 1003. In this embodiment, the SOI substrate can be formed using, for example, an SOI fabrication process such as a smart dicing process. The substrate 1001 may include elemental semiconductor materials such as Si or Ge, or compound semiconductor materials such as SiGe. Here, a silicon wafer is used as an example to describe the substrate 1001. The buried oxide layer 1003 may include oxides (e.g., silicon oxide). The semiconductor layer 1005 may include elemental semiconductor materials such as Si or Ge, or compound semiconductor materials such as SiGe. The thickness of the semiconductor layer 1005 can be set as needed, and the semiconductor layer 1005 can be grown directly by epitaxy.
[0089] Next, as shown in FIG2, a sacrificial gate 1007 can be formed on the semiconductor layer 1005. Here, the channel extension direction is designated as the first direction (e.g., the horizontal direction within the plane of the paper in FIG2), and the direction intersecting (e.g., perpendicular to) the first direction is designated as the second direction (e.g., the direction perpendicular to the plane of the paper in FIG2). The sacrificial gate 1007 extends along the second direction. The sacrificial gate 1007 may comprise polysilicon. For convenience, a hard mask that may exist on the sacrificial gate 1007 is not shown. On the sidewalls of the sacrificial gate 1007, sidewalls 1009 of the sacrificial gate 1007 can be formed by a sidewall forming process. For example, sidewalls 1009 may comprise a nitride (e.g., silicon nitride). As shown in FIG2, in the third direction (the vertical direction within the plane of the paper in FIG2), the portion of the upper surface of the semiconductor layer 1005 not covered by the sacrificial gate 1007 and sidewalls 1009 is exposed. In this invention, a first sacrificial gate and a second sacrificial gate can be formed. Optionally, a first sacrificial gate sidewall and a second sacrificial gate sidewall can be formed on the sidewalls of the first sacrificial gate and the second sacrificial gate, respectively.
[0090] As shown in Figure 3, a source / drain portion 1011 extending upward in a third direction can be formed by using the exposed portion of the upper surface of the semiconductor layer 1005 as a seed, for example, through selective epitaxial growth. The source / drain portion 1011 can be formed on opposite sides of the sidewalls 1009 of the sacrificial gate 1007 and can be formed to overlap with the sacrificial gate 1007 in a first direction. The source / drain portion 1011 can comprise various suitable semiconductor materials, for example, Si for n-type field-effect transistors and SiGe for p-type field-effect transistors. The source / drain portion 1011 can be doped to the desired conductivity type (n-type doping for n-type field-effect transistors and p-type doping for p-type field-effect transistors) by, for example, in-situ doping or ion implantation. Advantageously, the height of the source / drain portion 1011 can be less than the height of the sacrificial gate 1007. For both the first and second sacrificial gates, the formation process is the same: the first source / drain portion 1011 is formed first through the first sacrificial gate, and then the second source / drain portion is formed through the second sacrificial gate.
[0091] Next, an alternative gate process can be implemented.
[0092] For example, as shown in FIG4, an interlayer dielectric layer 1013 can be formed on the semiconductor layer 1005. The interlayer dielectric layer can be an oxide layer. For example, the interlayer dielectric layer 1013 can be formed by depositing an oxide and then planarizing the oxide deposited by CMP. CMP can be performed to expose the sacrificial gate 1007 inside the sacrificial gate sidewall 1009. In this step, the first sacrificial gate and the second sacrificial gate can be exposed simultaneously by CMP.
[0093] As shown in Figure 5, the sacrificial gate 1007 and the sacrificial gate sidewall 1009 can be selectively etched away to release the space 1015 between the source / drain portions 1011, forming an opening pattern that exposes the surface of the semiconductor layer 1005. Since the sacrificial gate sidewall 1009 is removed in addition to the sacrificial gate 1007, there may be no gate sidewall between the gate stack subsequently formed in the released space 1015 and the source / drain portions 1011. In another embodiment, the gate sidewall may be retained.
[0094] It should be noted that, for convenience, space 1015 in Figure 5 is shown as having a substantially uniform width in the vertical direction. However, considering the shape of the sacrificial fence sidewall 1009, space 1015 may have a shape where the lower width is greater than the upper width.
[0095] Subsequently, as shown in Figure 6, ions can be implanted into the semiconductor layer 1005 using the opening pattern. Multiple ion implantation process parameters can be set according to the number, depth, and concentration of the shell 1005-1 and core 1005-2, so as to form ion implantation regions of different depths and concentrations in the semiconductor layer 1005, thereby providing at least one shell 1005-1 and at least one core 1005-2. For example, for an n-type field-effect transistor, n-type ions are first implanted at a predetermined energy to provide the ion distribution of the core 1005-2, then the implantation energy is adjusted to implant p-type ions to provide the ion distribution of the shell 1005-1, and subsequently, the implantation energy can be further reduced to implant p-type ions to provide the ion distribution of the second shell 1005-1.
[0096] For a p-type field-effect transistor, p-type ions are first injected with a predetermined energy to provide the ion distribution in the core 1005-2. Then, the injection energy is adjusted to inject n-type ions to provide the ion distribution in the shell 1005-1. Subsequently, the injection energy can be further reduced to inject n-type ions to provide the ion distribution in the second shell 1005-1.
[0097] It should be noted that Figure 6 only schematically illustrates the ion distribution of the shell portion 1005-1 and the core portion 1005-2. In this invention, especially in cases where the same channel structure is present, the first and second semiconductor devices can be selectively etched without a mask to remove the first and second sacrificial gates simultaneously. Furthermore, the core-shell structure can be formed without a mask using ion implantation and annealing to create the space between the first and second source / drain portions obtained after removal.
[0098] In this invention, during ion implantation, the presence of the opening pattern allows ions to be implanted into the exposed portion of the semiconductor layer 1005 within the openings. Since the entire SOI substrate is covered by an interlayer dielectric layer 1013, the implanted ions are blocked within this layer. Therefore, a separate hard mask and alignment process are not required for ion implantation, simplifying the manufacturing process and ensuring accurate implantation.
[0099] Subsequently, as shown in FIG7, a gate stack can be formed in space 1015, for example, by deposition. For example, a first gate dielectric layer 1017, a work function layer 1019, and a gate conductor layer 1021 can be sequentially formed directly on the surface of semiconductor layer 1005 to obtain the final gate stack. The first gate dielectric layer 1017 can be a high-k gate dielectric, such as a hafnium oxide layer, and the hafnium oxide layer can have a thickness of approximately 2 nm. The work function layer 1019 can be TiN. In one embodiment, the gate stack may include a gate conductor layer 1021, which may include a gate electrode metal such as tungsten (W).
[0100] For n-type field-effect transistors (which can correspond to the first semiconductor device) and p-type field-effect transistors (which can correspond to the second semiconductor device), corresponding shell portions 1005-1 and core portions 1005-2 or shell portions 1005-1' and core portions 1005-2' can be formed respectively, and n-type and p-type work function layers can be formed respectively (see Figure 8). In one embodiment, the threshold voltage of the n-type field-effect transistor and the threshold voltage of the p-type field-effect transistor can be set to be substantially symmetrical, which can simplify the manufacturing process of semiconductor devices and reduce manufacturing costs.
[0101] As shown in FIG7, the semiconductor device according to the embodiment may include a gate stack, and the gate stack may be located between the source / drain portions 1011.
[0102] In addition, the work function layer includes metallic materials such as titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum nitride (TiAl), zirconium aluminum nitride (ZrAl), tungsten aluminum nitride (WAl), tantalum aluminum nitride (TaAl), hafnium aluminum nitride (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto.
[0103] Subsequently, as shown in Figure 8, the drain portion 1011-1 of the first semiconductor device and the drain portion 1011-2 of the second semiconductor device are electrically connected, and the gate stacks of the first and second semiconductor devices are electrically connected (in fact, the gate conductor layer 1021-1 of the gate stack of the first semiconductor device is electrically connected to the gate conductor layer 1021-2 of the gate stack of the second semiconductor device), thus forming an inverter. It should be understood that the core and shell portions in Figure 7 are different from the actual core and shell portions in Figure 8; they are only used to illustrate that there are multiple configurations or implementations of the shell-core configuration.
[0104] One aspect of the present invention discloses a semiconductor device, comprising: a substrate 1001; a buried oxide layer 1003 on the substrate; and a semiconductor layer 1005 stacked above the buried oxide layer. The semiconductor device includes a third semiconductor device portion 300 and a drift portion 400.
[0105] In this embodiment, the third semiconductor device portion 300 includes: a third channel portion, including a third portion of a semiconductor layer; third source / drain portions 1011-3, disposed above the buried oxide layer 1005 and connected to opposite ends of the third channel portion; and a third gate stack between the third source / drain portions 1011-3, disposed on the third channel portion.
[0106] The drift section 400 includes: a drift section channel, including a fourth portion of a semiconductor layer, the length of the drift section channel in the extending direction of the semiconductor layer being greater than that of the third channel portion; fourth source / drain portions 1011-4, disposed above the buried oxide layer and connected to opposite ends of the drift section channel; and an oxide layer 1030 disposed on the drift section channel between the fourth source / drain portions 1011-4. In projection, the third portion of the semiconductor layer of the third channel portion is located between the source / drain portions 1011-3, and the fourth portion of the semiconductor layer of the drift section channel portion is located between the source / drain portions 1011-4. These locations are not shown using reference numerals in the accompanying drawings, however, should be understood.
[0107] The third channel portion includes at least one shell portion 1005-1” and at least one core portion 1005-2”, which are spaced apart from each other and overlap in the projection direction. The drift channel portion includes at least one shell portion 1005-1”’ and at least one core portion 1005-2”’, which are spaced apart from each other and overlap in the projection direction. The shell portions 1005-1”, 1005-1”’ and the core portions 1005-2”, 1005-2”’ have opposite doping types. The drain portion 1011-3 of the third semiconductor device portion is the source portion 1011-4 of the drift portion, which is shown as 1011-3 / 4 in FIG9.
[0108] In the above embodiments, the semiconductor device according to the present invention shown in FIG9 is described as including a third semiconductor device portion and a drift portion; however, in another embodiment of the present invention, the semiconductor device shown in FIG9 is described as including source / drain portions 1011-3, 1011-4 and transition semiconductor portions 1011-3 / 4 (intermediate components between the two source / drain portions shown in FIG9), all three having the same doping type. Those skilled in the art will understand that although the description has changed, the arrangement of the components in its structure and their corresponding functions form the basis for realizing the overall function of the semiconductor device of the present invention.
[0109] Here, it should be understood that the third and fourth are follow-up statements to the first and second. For the sake of distinction and differentiation, it is not stipulated that the third semiconductor device section is different from the aforementioned example first semiconductor device; on the contrary, they can have the same structure. The structure and manufacturing process of the third semiconductor device section can refer to the aforementioned first semiconductor device.
[0110] In this invention, the third semiconductor device section 300 and the drift section 400 constitute a semiconductor device that can withstand high voltage applications (e.g., 10V). For example, the third semiconductor device section 300 is an n-type semiconductor device, and the drift section 400 has a p-type shell. The drift section 400 can be used as a charge balance region, which improves the breakdown voltage, and the shell-core structure reduces the operating resistance.
[0111] In this example, unlike the inverter described above, the drift section 400 has an oxide layer 1040 between the fourth source and drain portions, without gate stacking. Furthermore, unlike the inverter described above, the fourth channel portion of the drift section 400 has a different size than the third channel portion of the third semiconductor device; the longer fourth channel portion of the drift section 400 enables the semiconductor device to operate at high voltage.
[0112] Furthermore, in the embodiment shown in FIG9, it may include a configuration with two shells and one core as in the previous embodiments, or a configuration with other numbers of shells and cores.
[0113] A method for manufacturing a semiconductor device is provided in this invention. The method includes: forming a buried oxide layer 1003 on a substrate 1001; forming a semiconductor layer 1005 on the buried oxide layer 1003; forming a third sacrificial gate and a fourth sacrificial gate on the semiconductor layer 1005; in some embodiments, forming a third sacrificial gate sidewall on the sidewall of the third sacrificial gate, wherein the width or length (in the extension direction of the channel) of the fourth sacrificial gate is greater than that of the third sacrificial gate;
[0114] Source / drain portions 1011-3 and 1011-4 are formed on the opposite outer sides of the third sacrificial gate sidewall and the fourth sacrificial gate, and source / drain portions 1011-3 / 4 of the same doping type are formed between the third sacrificial gate sidewall and the fourth sacrificial gate. The third and fourth source / drain portions overlap with the third and fourth sacrificial gates in the channel extension direction.
[0115] Remove the third and fourth sacrificial gates and optionally remove the sidewalls of the third sacrificial gate to release the third and fourth spaces between the source and drain;
[0116] At least one core and at least one shell 1005-1”, 1005-1”' are formed in the semiconductor layer by ion implantation (and annealing) in the third and fourth spaces, wherein at least one shell is located above at least one core 1005-2”, 1005-2”'; and
[0117] A gate stack is formed on the semiconductor layer 1005 in the third space, and an oxide layer is formed on the semiconductor layer in the fourth space, wherein the third space corresponds to the third sacrificial gate and the fourth space corresponds to the fourth sacrificial gate.
[0118] The doping type of the source / drain is opposite to that of at least one shell portion 1005-1”, 1005-1”', and the same as that of at least one core portion 1005-2”, 1005-2”'.
[0119] In this embodiment, since the drift section 400 is longer, a third sacrificial gate and a fourth sacrificial gate of different sizes are formed; based on the third and fourth sacrificial gates, source / drain sections with the same doping type are formed, for example, three source / drain sections that are all n-type doped. The term source / drain is used here only for convention, and it should be understood that they are semiconductor components with the same doping type.
[0120] The shell-core structure is formed in semiconductor layer 1005 by removing the third and fourth sacrificial gates to form the third and fourth spaces, and by doping through ion implantation and annealing of the third and fourth spaces. This can be referred to the description of the aforementioned example, and will not be repeated here.
[0121] The semiconductor devices according to embodiments of this disclosure can be applied to electronic devices in various voltage ranges. For example, integrated circuits (ICs) (e.g., less than 2V) can be formed based on such semiconductor devices, and electronic devices can be constructed therefrom. Such electronic devices may also include higher voltage display screens (e.g., greater than 5V) that cooperate with the integrated circuits, as well as components such as wireless transceivers that cooperate with the integrated circuits. Examples of such electronic devices include smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks.
[0122] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.
[0123] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A semiconductor device, comprising: Substrate; The buried oxide layer on the substrate; as well as A semiconductor layer stacked on top of the buried oxide layer; The semiconductor device includes a first type of semiconductor device and a second type of semiconductor device, wherein the first semiconductor device includes: The first channel portion includes a first portion of the semiconductor layer; A first source / drain of a first doped type is disposed above the buried oxide layer and connected to opposite ends of the first channel portion; and A first gate stack between the first source and drain portions is disposed on the first channel portion; and The second semiconductor device includes: The second channel portion includes a second portion of the semiconductor layer; A second source / drain of the second doped type is disposed above the buried oxide layer and connected to the opposite ends of the second channel portion; and A second gate stack between the second source / drain is arranged on the second channel portion; The first channel portion and the second channel portion each include at least one shell portion and at least one core portion that are spaced apart from each other and overlap in the projection direction, wherein the at least one shell portion and the at least one core portion have opposite doping types; The drain portion of the first semiconductor device and the drain portion of the second semiconductor device are electrically connected, and the first gate stack of the first semiconductor device and the second gate stack of the second semiconductor device are electrically connected.
2. A semiconductor device, comprising: Substrate; The buried oxide layer on the substrate; as well as A semiconductor layer stacked on top of the buried oxide layer; The semiconductor device includes a third semiconductor device section and a drift section, wherein the third semiconductor device section includes: The third channel portion includes the third part of the semiconductor layer; A third source / leakage section is disposed above the buried oxygen layer and connected to the opposite ends of the third channel section; and A third gate stack between the third source / drain is arranged on the third channel portion; and The drift section includes: The drift channel includes a fourth portion of the semiconductor layer, wherein the length of the drift channel in the extending direction of the semiconductor layer is greater than that of the third channel portion; A fourth source / drain is disposed above the buried oxide layer and connected to the opposite ends of the drift channel. The doping type of the fourth source / drain is the same as that of the third source / drain. An oxide layer between the fourth source and drain is disposed on the drift channel; The third channel portion and the drift channel portion each include at least one shell portion and at least one core portion that are spaced apart from each other and overlap in the projection direction, wherein the at least one shell portion and the at least one core portion have opposite doping types; and The drain portion of the third semiconductor device portion is the source portion of the drift portion.
3. The semiconductor device according to claim 1 or 2, wherein the thickness of one of the at least one housing portion is 5 nm to 10 nm, and / or the thickness of one of the at least one core portion is 10 nm to 50 nm.
4. The semiconductor device according to claim 1 or 2, wherein the at least one core comprises one or two cores, and / or wherein the at least one housing comprises one or two housings.
5. The semiconductor device of claim 4, wherein the shell and the core are obtained by performing an ion implantation process and an annealing process on the semiconductor layer.
6. The semiconductor device according to claim 1 or 2, wherein the gate stack comprises a work function layer and a gate metal conductive layer.
7. The semiconductor device of claim 6, wherein the gate stack includes a first gate dielectric layer.
8. The semiconductor device of claim 1, wherein, The first semiconductor device includes a source / drain of a first doping type and a first gate dielectric layer, wherein the work function on the first gate dielectric layer is of a first type; the second semiconductor device includes a source / drain of a second doping type and a second gate dielectric layer, wherein the work function layer on the second gate dielectric layer is of a second type.
9. A method for manufacturing a semiconductor device, comprising: A buried oxide layer is formed on the substrate; A semiconductor layer is formed on the buried oxide layer; A first sacrificial gate and a second sacrificial gate are formed on the semiconductor layer, and a first sacrificial gate sidewall and a second sacrificial gate sidewall are formed on the sidewalls of the first sacrificial gate and the second sacrificial gate, respectively. Using a mask, a first source / drain of a first doped type is formed on opposite sides of the first sacrificial gate sidewall, and a second source / drain of a second doped type is formed on opposite sides of the second sacrificial gate. The first source / drain of the first doped type and the second source / drain of the second type overlap with the first sacrificial gate and the second sacrificial gate in the extension direction of the channel. Remove the first sacrificial gate, the second sacrificial gate, and optionally remove the sidewalls of the first sacrificial gate and the second sacrificial gate sidewalls to free up space between the first source / drain and the second source / drain; At least one core and at least one shell are formed in the semiconductor layer within the space; A gate stack is formed on the semiconductor layer in the space; as well as The drain portion of the first doped type source / drain is electrically connected to the drain portion of the second type source / drain, and the gate stack between the first doped type source / drain and the gate stack between the second type source / drain are electrically connected; The semiconductor layer of the channel portion between the first doped source / drain and the second doped source / drain includes at least one shell portion of the second doped type and at least one core portion of the first doped type, wherein the doping of the first doped type and the second doped type are opposite doping types.
10. A method for manufacturing a semiconductor device, comprising: A buried oxide layer is formed on the substrate; A semiconductor layer is formed on the buried oxide layer; A third sacrificial gate and a fourth sacrificial gate are formed on the semiconductor layer, and optionally a third sacrificial gate sidewall is formed on the sidewall of the third sacrificial gate, wherein the width of the fourth sacrificial gate is greater than that of the third sacrificial gate; Sources / drains of the same doping type are formed on the opposite outer sides of the third and fourth sacrificial gate sidewalls and between the third and fourth sacrificial gate sidewalls, and the source / drains overlap with the third and fourth sacrificial gates in the channel extension direction; Remove the third and fourth sacrificial gates and optionally remove the sidewalls of the third sacrificial gate to release the third and fourth spaces between the source and drain; At least one core and at least one shell are formed in the semiconductor layer in the third and fourth spaces, with the at least one shell located above the at least one core; as well as A gate stack is formed on the semiconductor layer in the third space, and an oxide layer is formed on the semiconductor layer in the fourth space, wherein the third space corresponds to a third sacrificial gate and the fourth space corresponds to a fourth sacrificial gate; The doping type of the source / drain portion is opposite to that of at least one shell portion, but the same as that of at least one core portion.
11. The method of claim 9 or 10, wherein, At least one core and at least one shell are formed in the semiconductor layer by ion implantation.
12. The method of claim 9 or 10, wherein, The thickness of one shell portion of the at least one shell portion is 5 nm to 10 nm, and / or the thickness of one core portion of the at least one core portion is 10 nm to 50 nm.
13. The method of claim 9, wherein, Forming the gate stack includes: A first gate dielectric layer, a work function layer, and a gate conductive layer are sequentially formed on the exposed surface of the semiconductor layer.