Semiconductor device and manufacturing method therefor

Abstract

Disclosed are a semiconductor device and a manufacturing method therefor. On the basis of the embodiments, the semiconductor device may comprise: a base, which comprises a substrate base and a buried oxide layer on the substrate base; a channel layer on the buried oxide layer, wherein the channel layer has a stress; an isolation layer between the channel layer and the buried oxide layer; a gate stack on the channel layer; and source / drain layers at two opposite sides of the channel layer.

Description

Semiconductor devices and their manufacturing methods Technical Field

[0001] This disclosure relates generally to semiconductor technology, and more specifically to a semiconductor device with improved performance and a method for manufacturing the same. Background Technology

[0002] Planar semiconductor-on-insulator (SOI) devices lag behind other device architectures such as FinFETs and multi-nanosheet or nanowire devices in terms of area miniaturization. Therefore, it is desirable for SOI devices to improve other device performance aspects, such as increased carrier mobility and stress applications. Summary of the Invention

[0003] The purpose of this disclosure is at least in part to provide a semiconductor device with improved performance and a method for manufacturing the same.

[0004] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a substrate including a base substrate and a buried oxide layer on the base substrate; a channel layer on the buried oxide layer, wherein the channel layer has stress; an isolation layer between the channel layer and the buried oxide layer; a gate stack on the channel layer; and source / drain layers on opposite sides of the channel layer.

[0005] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: sequentially disposing a sacrificial layer and a pre-channel layer on a substrate, wherein the substrate includes a base substrate and a buried oxide layer on the base substrate, the sacrificial layer causing stress in the pre-channel layer; patterning the sacrificial layer and the pre-channel layer into a fin structure extending along a first direction; forming a sacrificial gate extending along a second direction intersecting the first direction and thus intersecting the fin structure, and forming a sidewall on the sidewall of the sacrificial gate; patterning the fin structure using the sacrificial gate and the sidewall as a mask; forming a source / drain layer on the sidewall of the patterned fin structure; removing the sacrificial gate to expose the sidewall of the sacrificial layer inside the sidewall; removing the sacrificial layer via the exposed sidewall of the sacrificial layer, and forming an isolation layer in the space released due to the removal of the sacrificial layer; and forming a gate stack on the pre-channel layer inside the sidewall.

[0006] According to embodiments of this disclosure, by providing a sacrificial layer, stress can be introduced into the channel layer to improve device performance. Furthermore, the sacrificial layer is ultimately replaced by an isolation layer, thereby maintaining the semiconductor-on-insulator (SOI) structure and retaining the advantages of SOI devices. Attached Figure Description

[0007] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figures 1(a) and 1(b) schematically illustrate cross-sectional views of a semiconductor device according to an embodiment of the present disclosure;

[0009] Figures 2 to 15(b) schematically illustrate some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0010] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0011] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0012] Figures 1(a) and 1(b) schematically illustrate cross-sectional views of a semiconductor device according to an embodiment of the present disclosure.

[0013] As shown in FIG1(a), a semiconductor device according to one embodiment may include a substrate, which may include a base substrate 101 and a buried oxide layer 103 on the base substrate 101. Such a substrate may be provided, for example, as a semiconductor-on-insulator (SOI) substrate, as described in further detail below. The semiconductor device may also include a channel layer 107 on the buried oxide layer 103 and an isolation layer 121 between the channel layer 107 and the buried oxide layer 103. The channel layer 107 may include a suitable semiconductor material such as silicon (Si) and may be in the form of nanosheets. The isolation layer 121 may include a suitable dielectric material such as an oxide (e.g., silicon oxide). The lower surface of the isolation layer 121 may be adjacent to the buried oxide layer 103, and the upper surface may be adjacent to the channel layer 107.

[0014] As described in further detail below, the isolation layer 121 can be formed by replacing the sacrificial layer beneath the channel layer 107 and can be self-aligned with the channel layer 107. For example, in a top view, the isolation layer 121 and the channel layer 107 can substantially completely overlap. Furthermore, this sacrificial layer can cause stress in the channel layer 107, for example, due to differences in lattice constants. For n-type semiconductor devices, the channel layer 107 can have tensile stress to improve the mobility of charge carriers (electrons); while for p-type semiconductor devices, the channel layer 107 can have compressive stress to improve the mobility of charge carriers (holes). For example, for n-type semiconductor devices, the sacrificial layer can include SiGe and the channel layer can include Si, thus causing tensile stress in the Si channel layer. On the other hand, for p-type semiconductor devices, the sacrificial layer can include Si and the channel layer can include SiGe, thus causing compressive stress in the SiGe channel layer.

[0015] The semiconductor device may also include a gate stack on the channel layer 107. The gate stack may include a gate dielectric layer 123 and a gate electrode layer 125 on the gate dielectric layer 123. The gate stack may include a metal gate stack. For example, the gate dielectric layer 123 may include a high-K gate dielectric such as hafnium oxide (HfO2), and the gate electrode layer 125 may include a work function layer such as a conductive metal nitride such as titanium nitride (TiN) and a gate conductor layer such as a metal such as tungsten (W) on the work function layer.

[0016] The semiconductor device may further include source / drain layers 117 on opposite sides of the channel layer 107. The source / drain layers 117 may be disposed on the buried oxide layer 103 and extend on the sidewalls of the isolation layer 121. The source / drain layers 117 may include a suitably doped semiconductor material. For example, for an n-type semiconductor device, the source / drain layer 117 may be doped to n-type; or for a p-type semiconductor device, the source / drain layer 117 may be doped to p-type. The source / drain layers 117 may include the same semiconductor material as the channel layer 107, such as Si, or may include a different semiconductor material. When including different materials, the source / drain layers 117 may also apply stress to the channel layer 107 to further improve device performance.

[0017] Figure 1(b) illustrates a semiconductor device according to another embodiment. The semiconductor device shown in Figure 1(b) may have substantially the same structure as the semiconductor device shown in Figure 1(a), except for the channel layer. The channel layer of the semiconductor device according to this embodiment may include a multilayer structure. The differences between the two embodiments are described below.

[0018] As shown in Figure 1(b), the channel layer may include a first semiconductor layer 107′ and a second semiconductor layer 127 on the first semiconductor layer 107′. The first semiconductor layer 107′ may be adjacent to the isolation layer 121 and may include a portion extending on the bottom surface of the second semiconductor layer 127 and a portion extending on the sidewalls of the second semiconductor layer. As described above, the first semiconductor layer 107′ may have stress due to the sacrificial layer (replaced by the isolation layer 121). Typically, the first semiconductor layer 107′ has one type of stress, namely, tensile stress or compressive stress. This single type of stress may be suitable for optimizing one type of device (e.g., tensile stress is suitable for optimizing n-type semiconductor devices while compressive stress is suitable for optimizing p-type semiconductor devices). If another type of device is to be formed, then a different stress needs to be generated in the channel layer. This can be achieved by providing the second semiconductor layer 127 on the first semiconductor layer 107′. For example, due to the difference in lattice constant between the first semiconductor layer 107′ and the second semiconductor layer 127, another type of stress can be caused in the second semiconductor layer 127. In one example, the first semiconductor layer 107′ may include Si (e.g., with tensile stress due to the SiGe sacrificial layer), and the second semiconductor layer 127 may include SiGe (with compressive stress due to the Si first semiconductor layer 107′), thus favoring p-type semiconductor devices. In this example, the channel layer may also include a third semiconductor layer 129, such as Si, on the second semiconductor layer 127 to improve interface quality. In another example, the first semiconductor layer 107′ may include SiGe (e.g., with compressive stress due to the Si sacrificial layer), and the second semiconductor layer 127 may include Si (with compressive stress due to the SiGe first semiconductor layer 107′), thus favoring n-type semiconductor devices.

[0019] Although Figures 1(a) and 1(b) show semiconductor devices with different configurations, both configurations can be integrated on a substrate, with some devices having the configuration shown in Figure 1(a) and others having the configuration shown in Figure 1(b). For example, in devices integrated on a substrate, an n-type semiconductor device can have the configuration shown in Figure 1(a), while a p-type semiconductor device can have the configuration shown in Figure 1(b); and vice versa. In this case, the channel layer 107 in the configuration shown in Figure 1(a) and the first semiconductor layer 107′ in the configuration shown in Figure 1(b) can comprise the same semiconductor material, for example, they can be obtained from the same pre-channel layer as described below.

[0020] This semiconductor device can be manufactured as follows.

[0021] For example, a sacrificial layer and a pre-channel layer can be sequentially disposed on a substrate. As described above, the substrate may include a base substrate and a buried oxide layer on the base substrate. The sacrificial layer can cause stress in the pre-channel layer, for example, due to the difference in lattice constants between the two. In one example, an SOI substrate may be provided, comprising a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer. The SOI layer can be used as a sacrificial layer.

[0022] The sacrificial layer and the pre-channel layer can be patterned into a fin-like structure extending along a first direction. Additionally, a sacrificial gate can be formed extending along a second direction intersecting (e.g., perpendicular to) the first direction, thus intersecting the fin-like structure. Sidewalls can be formed on the sidewalls of the sacrificial gate. The fin-like structure can be patterned using the sacrificial gate and sidewalls as masks. This exposes the opposing sidewalls of the sacrificial layer and the pre-channel layer in the first direction. Source / drain layers can be formed on the sidewalls of the patterned sacrificial layer and the pre-channel layer. These processes are compatible with the fabrication processes of (SOI) nanosheet devices.

[0023] Subsequently, alternative gate processes can be performed. For example, the sacrificial gate can be removed to expose the sidewalls of the sacrificial layer inside the sidewalls. The sacrificial layer can be removed via the exposed sidewalls, and an isolation layer can be formed in the space freed up by the removal of the sacrificial layer. A gate stack can be formed on the prepared trench layer inside the sidewalls.

[0024] According to embodiments of this disclosure, stress can be introduced into the channel layer via a sacrificial layer. The sacrificial layer is replaced by an isolation layer in the final device, maintaining the SOI structure and eliminating the need to consider bottom isolation issues as in nanosheet devices. The semiconductor device according to embodiments of this disclosure can be a fully depleted (FD) SOI device.

[0025] This disclosure may be presented in various forms, some of which are described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.

[0026] Figures 2 to 15(b) schematically illustrate some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure.

[0027] As shown in Figure 2, an SOI substrate 100 can be provided. The SOI substrate 100 may include a base substrate 1001, a buried oxide layer 1003 on the base substrate 1001, and an SOI layer 1005 on the buried oxide layer 1003. The base substrate 1001 may include a semiconductor material such as silicon (Si), the buried oxide layer 1003 may include an oxide (such as silicon oxide), and the SOI layer 1005 may include a suitable semiconductor material such as SiGe. The SOI layer 1005 can be used as the sacrificial layer described above.

[0028] SOI substrates with SiGe SOI layers can be provided using different methods. For example, a SiGe layer can be bonded to a substrate using a smart-cut process to form a SiGe-on-insulator (SGOI) substrate. Alternatively, a conventional SOI substrate with Si SOI layers can be converted into a SiGe layer using a germanium enrichment process.

[0029] As shown in Figure 3, a pre-channel layer 1007 can be formed on the SOI substrate 100, specifically on the SOI layer 1005, by, for example, epitaxial growth. The pre-channel layer 1007 may include a semiconductor material different from that of the SOI layer 1005, to generate strain or stress relative to the SOI layer 1005 by having both etching selectivity and a difference in lattice constant. For example, the pre-channel layer 1007 may include Si.

[0030] In this example, the SOI layer 1005 comprises SiGe and the pre-channel layer 1007 comprises Si, thus tensile stress can be generated in the pre-channel layer 1007. However, this disclosure is not limited thereto. For example, the SOI layer 1005 may comprise Si and the pre-channel layer 1007 may comprise SiGe, thus compressive stress can be generated in the pre-channel layer 1007. Furthermore, a Si-based material is described herein as an example. However, this disclosure is not limited thereto, and other suitable semiconductor materials are equally applicable.

[0031] For example, as shown in Figures 4(a), 4(b), and 4(c) (the cut-off positions of sections AA' and BB' are shown in the top view of Figure 4(a)), the SOI layer 1005 and the pre-channel layer 1007 can be patterned as strips extending along a first direction (e.g., the horizontal direction within the plane of the paper in Figures 4(a) and 4(b), and the direction perpendicular to the plane of the paper in Figure 4(c)). As shown in Figure 4(c), the patterned SOI layer 1005 and the pre-channel layer 1007 protrude relative to each other, forming a fin structure. The patterning of the SOI layer 1005 and the pre-channel layer 1007 can be incorporated into the substrate 1001. Between the individual fin structures (only a single fin structure is shown in Figures 4(a), 4(b), and 4(c); however, those skilled in the art will understand that multiple fin structures can be formed), shallow trench isolation (STI) can be formed, see 1011 in Figure 5(c). STI may include oxides, and the top surface may be between the top and bottom surfaces of the buried oxide layer 1003.

[0032] As shown in Figures 5(a), 5(b), and 5(c), a sacrificial gate 1013 can be formed extending along a second direction (e.g., vertical in the plane of the paper in Figure 5(a), perpendicular to the plane of the paper in Figure 5(b), and horizontal in the plane of the paper in Figure 5(c)) to intersect the fin structure. Sidewalls 1015 can be formed on the sidewalls of the sacrificial gate 1013. For example, the sacrificial gate 1013 may comprise a stack of oxide and polysilicon (with a hard mask layer on top to aid in patterning), and the sidewalls 1015 may comprise nitrides (e.g., silicon nitride). Although a single-layer structure is shown for the sidewalls 1015 in this example, the disclosure is not limited thereto. The sidewalls 1015 may also have a multilayer structure.

[0033] Source / drain layers can be formed on opposite sides of the sacrificial gate.

[0034] For example, as shown in Figure 6, the gate 1013 and sidewall 1015 can be used as etching masks to perform anisotropic etching, such as vertical reactive ion etching (RIE), on the SOI layer 1005 and the pre-channel layer 1007. The sidewalls of the SOI layer 1005 and the pre-channel layer 1007 in the first direction can be exposed. Figure 6 shows an example where the etching stops at the buried oxide layer 1003. However, this disclosure is not limited thereto. For example, the etching can also stop at the SOI layer 1005, so that the SOI layer 1005 can also be used as a seed in subsequent source / drain epitaxial growth processes to improve the crystal quality of the source / drain layers.

[0035] As shown in Figure 7, the source / drain layer 1017 can be formed, for example, by selective epitaxial growth, using the exposed sidewalls as seeds. The source / drain layer 101 can be doped to the desired conductivity type, for example, by in-situ doping during growth or by ion implantation after growth. For details regarding the source / drain layer 1017, please refer to the detailed description of the source / drain layer above in conjunction with Figure 1.

[0036] Next, an alternative gate process can be implemented.

[0037] For example, as shown in Figure 8, an interlayer dielectric layer 1019 can be formed. For example, an oxide layer can be formed by deposition such as chemical vapor deposition (CVD) and planarized by chemical mechanical polishing (CMP), which can be performed until the sacrificial gate 1013 is exposed, thereby forming the interlayer dielectric layer 1019.

[0038] As shown in Figures 9(a) and 9(b), the sacrificial gate 1013 can be removed by selective etching, thereby freeing up space inside the gate stack on the sidewall 1015. In the freed space, the sidewalls of the SOI layer 1005 (in the second direction) can be exposed.

[0039] As shown in Figures 10(a) and 10(b), the SOI layer 1005 can be removed by selective etching through the exposed sidewalls of the SOI layer 1005. Due to the structures surrounding the pre-channel layer 1007 (e.g., source / drain layer 1017, interlayer dielectric layer 1019, etc.), the stress caused by the SOI layer 1005 in the pre-channel layer 1007 can be retained even after the SOI layer 1005 is removed. The process for removing the SOI layer 1005 is similar to the process for releasing the channel layer in nanosheet devices, and therefore is compatible with the processes used to fabricate nanosheet devices.

[0040] An isolation layer can be formed in the space freed up by the removal of the SOI layer 1005. For example, as shown in Figures 11(a) and 11(b), an oxide layer can be formed by deposition such as CVD, planarization of the deposited oxide layer such as CMP, and etching back the planarized oxide layer to form the isolation layer 1021. To facilitate control of the stop point of the etching back, the STI 1011 can include, for example, high-density plasma (HDP) oxide, and thus the etching back of the oxide can stop at the HDP oxide.

[0041] Subsequently, as shown in Figures 12(a) and 12(b), a gate stack can be formed on the pre-channel layer 1007 inside the sidewall 1015. The gate stack may include a gate dielectric layer 1023 and a gate electrode layer 1025. For a detailed description of the gate stack above in conjunction with Figure 1, please refer to the above description of the gate stack.

[0042] The portion of the pre-channel layer 1007 remaining in the final device can serve as the channel layer. As mentioned above, the channel layer can have a single type of stress. In the example where the SOI layer 1005 is SiGe and the pre-channel layer 1007 is Si, the final channel layer can have tensile stress. Alternatively, for example, if the SOI layer 1005 is Si and the pre-channel layer 1007 is SiGe, the final channel layer can have compressive stress.

[0043] Therefore, the direct formation of gate stacks on the pre-channel layer 1007 as described above in conjunction with Figures 12(a) and 12(b) is applicable to one type of device (e.g., n-type semiconductor devices when the pre-channel layer 1007 has tensile stress; p-type semiconductor devices when the pre-channel layer 1007 has compressive stress). If another type of device is to be formed on the substrate, the two types of devices can be processed separately. For example, when processing the area of ​​one type of device as described above in conjunction with Figures 12(a) and 12(b), the area of ​​the other type of device can be masked; after processing, the processed area can be masked, exposing the previously masked area of ​​the other type of device for further processing.

[0044] For example, as shown in Figures 13(a) and 13(b), after forming the isolation layer as described above, instead of directly forming the gate stack on the pre-channel layer 1007, selective etching can be used to etch back the pre-channel layer 1007, causing it to be recessed to a certain depth. As shown in Figures 14(a) and 14(b), the remaining pre-channel layer 1007 can serve as a seed, and a semiconductor layer 1027 can be formed on the pre-channel layer 1007 by, for example, selective epitaxial growth. The semiconductor layer 1027 may include a semiconductor material different from the pre-channel layer 1007 to generate strain or stress due to a difference in lattice constant relative to the pre-channel layer 1007. For example, in an example where the pre-channel layer 1007 includes Si, the semiconductor layer 1027 may include SiGe and therefore may have compressive stress. Alternatively, in an example where the pre-channel layer 1007 includes SiGe, the semiconductor layer 1027 may include Si and therefore may have tensile stress. In addition, in the example where the semiconductor layer 1027 includes SiGe, in order to improve the interface characteristics, a capping layer 1029 of, for example, Si can be further formed on the semiconductor layer 1027 by, for example, selective epitaxial growth.

[0045] Subsequently, as shown in Figures 15(a) and 15(b), a gate stack can be formed inside the sidewall 1015. The gate stack may include a gate dielectric layer 1023′ and a gate electrode layer 1025′. For a detailed description of the gate stack above in conjunction with Figure 1, please refer to the above description of the gate stack. The gate stacks of n-type semiconductor devices and p-type semiconductor devices can have different configurations, such as different equivalent work functions, to optimize the performance of n-type semiconductor devices and p-type semiconductor devices, respectively.

[0046] The semiconductor devices according to embodiments of this disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such semiconductor devices, and electronic devices can be constructed therefrom. Such electronic devices may also include components such as display screens that cooperate with the integrated circuits and wireless transceivers that cooperate with the integrated circuits. Examples of such electronic devices include smartphones, computers, tablet computers, wearable smart devices, artificial intelligence devices, and power banks.

[0047] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0048] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: The substrate includes a base substrate and a buried oxide layer on the base substrate; The trench layer on the buried oxide layer, wherein the trench layer is under stress; An isolation layer between the channel layer and the buried oxygen layer; The gate stack on the channel layer; and The channel layer consists of source / drain layers on opposite sides.

2. The semiconductor device according to claim 1, comprising an n-type semiconductor device and a p-type semiconductor device. in, The channel layer of one of the n-type semiconductor devices and the p-type semiconductor devices comprises a semiconductor layer of a first semiconductor material. The channel layer of the other of the n-type semiconductor device and the p-type semiconductor device includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes the first semiconductor material, and the second semiconductor layer includes a second semiconductor material different from the first semiconductor material.

3. The semiconductor device according to claim 2, wherein, The first semiconductor layer includes a portion extending on the bottom surface of the second semiconductor layer and a portion extending on the sidewall of the second semiconductor layer.

4. The semiconductor device according to claim 1, wherein, The isolation layer is self-aligned with the channel layer.

5. The semiconductor device according to claim 1, wherein, The lower surface of the isolation layer is adjacent to the buried oxygen layer, and the upper surface is adjacent to the channel layer.

6. The semiconductor device according to claim 1, wherein, The semiconductor device is an n-type semiconductor device, and the channel layer has tensile stress.

7. The semiconductor device according to claim 6, wherein, The channel layer of the n-type semiconductor device comprises Si with tensile stress, and the source / drain layer comprises Si.

8. The semiconductor device according to claim 1, wherein, The semiconductor device is a p-type semiconductor device, and the channel layer has compressive stress.

9. The semiconductor device according to claim 8, wherein, The channel layer of the p-type semiconductor device includes: The first Si layer on the isolation layer; The SiGe layer on the first Si layer; and The second Si layer on the SiGe layer.

10. The semiconductor device according to claim 1, wherein, The source / drain layer is disposed on the buried oxygen layer and extends on the sidewall of the isolation layer.

11. A method for manufacturing a semiconductor device, comprising: A sacrificial layer and a pre-trench layer are sequentially disposed on a substrate, wherein the substrate includes a base substrate and a buried oxide layer on the base substrate, and the sacrificial layer causes stress in the pre-trench layer; The sacrificial layer and the pre-ditch layer are patterned as fin-like structures extending along a first direction; A sacrificial gate is formed extending along a second direction intersecting the first direction, thereby intersecting the fin structure, and a sidewall is formed on the sidewall of the sacrificial gate; Using the sacrificial fence and the sidewall as masks, the fin-shaped structure is patterned. A source / drain layer is formed on the sidewall of the patterned fin structure; Remove the sacrificial grid to expose the sidewall of the sacrificial layer inside the sidewall; The sacrificial layer is removed via its exposed sidewalls, and an isolation layer is formed in the space freed up by the removal of the sacrificial layer; and A grid stack is formed on the prepared trench layer on the inner side of the sidewall.

12. The method according to claim 11, wherein, Forming a grid stack on the prepared channel layer further includes: The prepared trench layer is etched back; A semiconductor layer is grown on the prepared channel layer after etch-back, wherein the prepared channel layer causes stress in the semiconductor layer.

13. The method according to claim 12, wherein, Forming a grid stack on the prepared channel layer further includes: A capping layer is grown on the semiconductor layer.

14. The method according to claim 13, wherein, The pre-channel layer comprises Si, the semiconductor layer comprises SiGe, the capping layer comprises Si, and the pre-channel layer causes compressive stress in the semiconductor layer.

15. The method according to claim 11, wherein, The sacrificial layer comprises SiGe, the pre-channel layer comprises Si, and the sacrificial layer causes tensile stress in the pre-channel layer.

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