Method for measuring overlay error, and integrated circuit
Patent Information
- Application Number
- PCT/CN2025/086316
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-27
- Filing Date
- 2025-03-31
- Publication Date
- 2026-10-01
Smart Images
Figure CN2025086316_01102026_PF_FP_ABST
Abstract
Description
Methods for measuring overlay errors and integrated circuits Technical Field
[0001] This disclosure generally relates to the field of integrated circuit manufacturing, and more specifically, to a method for measuring overlay errors and integrated circuits. Background Technology
[0002] Currently, overlay error is measured using broadband light through box-in-box structures. Overlay error is one of the core issues determining chip yield and performance in semiconductor manufacturing. With the evolution of process miniaturization and 3D integration technologies, its control precision will directly affect the feasibility of advanced processes. Furthermore, as devices continue to shrink, the requirements for overlay become more stringent, and optical methods for measuring overlay error may reach their limits. Summary of the Invention
[0003] The purpose of this disclosure is to provide a method and integrated circuit for measuring overlay error by electrical means.
[0004] Specifically, according to one aspect of this disclosure, a method for measuring overlay error is proposed. The method includes: forming a first layer comprising a first region, a second region, and a third region having the same dimensions; forming a second layer, wherein the first region is not covered by the second layer, the second region is completely covered by the second layer, and the third region is partially covered by the second layer, wherein the third region is designed to be partially covered by the second layer at a nominal ratio; measuring a first resistance value of the first region, a second resistance value of the second region, and a third resistance value of the third region; and determining the overlay error between the first layer and the second layer based on the first resistance value, the second resistance value, the third resistance value, and the nominal ratio.
[0005] According to embodiments of this disclosure, the first layer may be an active layer or a gate layer, and the second layer may be an implantation layer.
[0006] According to embodiments of this disclosure, the first region, the second region, and the third region may have the same rectangular shape.
[0007] According to embodiments of this disclosure, determining the overlay error may include using the following equation:
[0008] Where R1 is the first resistance value, R2 is the second resistance value, R3 is the third resistance value, P is the nominal ratio, and ΔP is the deviation from the nominal ratio caused by overprinting error.
[0009] According to embodiments of this disclosure, each of the first, second, and third regions may have the same rectangular shape. The third region may be designed to be covered by the second layer across its entire width for a nominal 50% length. Determining the overprinting error may include using the following equation:
[0010] Where x is the overprinting error along the length of the third region, R3 is the third resistance value, R1 is the first resistance value, R2 is the second resistance value, and L is the length of the rectangle.
[0011] According to embodiments of this disclosure, the length direction of the third region may be in the first direction, and the first layer may further include a fourth region extending along a second direction intersecting the first direction. The fourth region may have the same rectangular shape and is designed to be covered by the second layer across its entire width for a nominal 50% length range.
[0012] According to embodiments of this disclosure, the measurement may further include measuring a fourth resistance value in the fourth region.
[0013] According to embodiments of this disclosure, determining the overlay error may include using the following equation:
[0014] Where y is the overlay error in the length direction of the fourth region, R4 is the fourth resistance value, R1 is the first resistance value, R2 is the second resistance value, and L is the length of the rectangle.
[0015] According to embodiments of this disclosure, the length direction of one of the first region and the second region may be in the first direction, and the length direction of the other region may be in the second direction.
[0016] According to embodiments of this disclosure, the measurement may include: forming pads electrically connected to the two ends of each of the first to fourth regions; and measuring the first to fourth resistance values through the pads.
[0017] According to embodiments of this disclosure, one end of each of the first to fourth regions can be electrically connected to a common common pad, and the other end can be electrically connected to their respective corresponding pads.
[0018] According to another aspect of this disclosure, an integrated circuit is proposed. The integrated circuit includes: a first layer including a first region, a second region, and a third region having the same dimensions; a second layer, wherein the first region is not covered by the second layer, the second region is completely covered by the second layer, and the third region is partially covered by the second layer, wherein the third region is designed to be partially covered by the second layer at a nominal scale; and circuit devices at least partially formed in the first and second layers. The first, second, and third regions are electrically isolated from the circuit devices. The first, second, and third regions have corresponding first, second, and third resistance values. The first to third resistance values and the nominal scale can be configured to determine the overlay error between the first and second layers.
[0019] According to embodiments of this disclosure, overlay error can be measured online or offline using electrical testing methods, thereby enabling monitoring of overlay performance. Attached Figure Description
[0020] To gain a more complete understanding of this disclosure and its advantages, reference will now be made to the following description taken in conjunction with the accompanying drawings, wherein:
[0021] Figure 1 shows a schematic diagram of an electrical structure for monitoring overlay performance according to an embodiment of the present disclosure.
[0022] Figure 2 shows a schematic diagram of an electrical structure for monitoring overlay performance according to another embodiment of the present disclosure.
[0023] Figure 3 shows a schematic cross-sectional view of a coverage example according to an embodiment of the present disclosure.
[0024] Figure 4 shows a schematic diagram of overlay error in the X direction according to an embodiment of the present disclosure.
[0025] Figure 5 shows a schematic flowchart of a method for determining overlay error according to an embodiment of the present disclosure.
[0026] Figure 6 is a schematic diagram illustrating an integrated circuit according to an embodiment of the present disclosure.
[0027] In the accompanying drawings, identical or similar structures are identified by the same or similar reference numerals. Detailed Implementation
[0028] Other aspects, advantages, and key features of this disclosure will become apparent to those skilled in the art from the following detailed description of exemplary embodiments of the disclosure taken in conjunction with the accompanying drawings.
[0029] In this disclosure, the terms “comprising” and “containing” and their derivatives are used to mean including rather than limiting; the term “or” is inclusive and means and / or.
[0030] In this specification, the various embodiments described below to illustrate the principles of this disclosure are merely illustrative and should not be construed as limiting the scope of the disclosure in any way. The following description, with reference to the accompanying drawings, is intended to aid in a comprehensive understanding of exemplary embodiments of this disclosure as defined by the claims and their equivalents. The following description includes various specific details to aid understanding, but these details should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Furthermore, for clarity and brevity, descriptions of well-known functions and structures have been omitted. Additionally, throughout the drawings, the same reference numerals are used for similar functions and operations.
[0031] Figure 1 shows a schematic diagram of an electrical structure 100 for monitoring overlay performance according to an embodiment of the present disclosure.
[0032] As shown in Figure 1, the electrical structure 100 may include a first pattern or first region 101, a second pattern or second region 103, and a third pattern or third region 105 (shown by the dashed box in Figure 1) formed in layer A. For example, layer A may be a layer in an integrated circuit that forms an active region or a polysilicon gate. Here, the first region 101, the second region 103, and the third region 105 may have the same dimensions to facilitate subsequent calculations. Furthermore, the electrical structure 100 may also include a pattern formed in layer B (shown by the shaded box in Figure 1). For example, layer B may be a layer in an integrated circuit that forms an implantation layer (e.g., a boron or phosphorus-doped implantation layer). However, this disclosure is not limited thereto; layers A and B may be other layers that need to be aligned with each other in integrated circuit manufacturing.
[0033] As shown in Figure 1, the pattern in layer B can be formed such that the first region 101 is not covered by layer B (that is, no pattern is formed in layer B at the location of the first region 101), the second region 103 can be completely covered by layer B (that is, a pattern that completely covers the second region 103 can be formed in layer B at the location of the second region 103; considering process margin, the pattern can be (slightly) larger than the second region 103), and the third region 105 can be partially covered by layer B (that is, a pattern that partially covers the third region 105 can be formed in layer B at the location of the third region 105).
[0034] Layer A and Layer B can be formed on the substrate based on a mask. For example, the mask for Layer A may include patterns corresponding to the first region 101, the second region 103, and the third region 105, and the mask for Layer B may include patterns corresponding to the aforementioned patterns. When Layer A and Layer B are formed based on masks respectively, overlay errors may occur.
[0035] For example, suppose the third region 105 is designed to be partially covered by layer B at a nominal scale P. That is, when the two layers are ideally perfectly aligned as designed, the third region 105 should be partially covered by layer B at a scale P. However, in reality, there is an overlay error, meaning the alignment between layer A and layer B will deviate from the theoretical design value. For example, the third region 105, which is designed to be partially covered by layer B at a nominal scale P, may actually be partially covered by layer B at a scale P + ΔP after layers A and B are actually formed. In other words, due to the overlay error, there is a deviation ΔP relative to the nominal scale P.
[0036] According to embodiments of this disclosure, the overlay error between two layers (layer A and layer B) can be electrically measured using the electrical structure 100 described above. For example, the electrical characteristics, such as resistance, of a pattern / region in layer A may be altered due to being (fully or partially) covered by a pattern / region in layer B, and the degree of change in electrical characteristics may be related to the proportion of coverage. Specifically, the first region 101, being not covered by layer B, can maintain its electrical characteristics, such as resistance, substantially unchanged; the second region 103, being completely covered by layer B, may have its electrical characteristics significantly altered; and the third region 105, being partially covered by layer B, may have its electrical characteristics slightly altered. The overlay error (characterized by ΔP as described above) can be determined based on this change in electrical characteristics.
[0037] For ease of subsequent calculations, the first region 101, the second region 103, and the third region 105 can have the same dimensions, thus (without forming a B layer) having substantially the same initial electrical characteristics, such as resistance values. In the example shown in Figure 1, the first region 101, the second region 103, and the third region 105 can be formed into the same rectangular shape. Although these three regions are shown as extending parallel to each other in Figure 1, this disclosure is not limited thereto. Their respective orientations can be arbitrarily chosen in the absence of anisotropy. Of course, extending substantially parallel or orthogonal to each other is advantageous for manufacturing processes.
[0038] In one embodiment, the overlay error between layer A and layer B can be determined based on the resistance values of the first region 101 to the third region 105 and the nominal ratio P, for example, according to the following formula:
[0039] Wherein, R1 is the first resistance value of the first region 101, R2 is the second resistance value of the second region 103, R3 is the third resistance value of the third region 105, P is the nominal ratio, and ΔP is the deviation from the nominal ratio caused by overlay error.
[0040] According to embodiments of this disclosure, the resistance values of each of the first region 101 to the third region 105 can be measured by the pads electrically connected to both ends of each of the first region 101 to the third region 105.
[0041] In the example shown in Figure 1, the third region 105 is shown as being covered by layer B over its entire width within a certain range along the length direction. In this case, the nominal proportion P can represent the proportion of the covered area to the length L of the rectangular shape, and ΔP can represent the offset between the two layers in the length direction, i.e., the overlay error.
[0042] Figure 2 shows a schematic diagram of an electrical structure 200 for monitoring overlay performance according to another embodiment of the present disclosure.
[0043] As shown in Figure 2, the electrical structure 200 can also include layers A and B, as described above in conjunction with Figure 1, and will not be repeated here. As shown in Figure 2, in layer A, four rectangular regions with the same dimensions (length L and width W) can be formed, two of which are in the X direction and the other two in the Y direction. For example, the first region 101 and the third region 105 are in the X direction, and the second region 103 and the fourth region 107 are in the Y direction. Here, the X direction can intersect the Y direction (e.g., perpendicularly). Furthermore, the length L of the first region 101 and the third region 105 is measured in the X direction, and the length L of the second region 103 and the fourth region 107 is measured in the Y direction.
[0044] In the first region 101 to the fourth region 107, one region is completely covered by layer B, and another region is completely open; for the remaining two regions, they may be partially covered by layer B, for example, with a nominal coverage ratio of 50% (i.e., 1 / 2). For example, in an embodiment, the first region 101 may not be covered by layer B, the second region 103 may be completely covered by layer B, and the third region 105 and the fourth region 107 may be partially covered by layer B (nominal ratio P is 50%). However, this disclosure is not limited thereto, and the third region 105 and the fourth region 107 may be partially covered by layer B with any nominal ratio as designed.
[0045] In this example, partial coverage areas extending along the X and Y directions, respectively, are formed, namely, the third region 105 and the fourth region 107. This is to more effectively measure the overprinting error in the X and Y directions (as described above with reference to FIG. 1, the overprinting error in the length direction of the rectangular shape can be obtained). However, this disclosure is not limited thereto. For example, partial coverage areas extending along the direction between the X and Y directions can be formed to obtain the overprinting error in its length direction, and the overprinting error in the X and Y directions can be obtained through vector decomposition.
[0046] Furthermore, in this example, two regions extend in the X direction and two other regions extend in the Y direction, resulting in a substantially symmetrical structure. This is advantageous for electrical measurements. However, this disclosure is not limited thereto. As mentioned above, the extension directions of the individual regions can be changed. For example, the first region 101 and the second region 103 can be interchanged.
[0047] As mentioned above, when a pattern or area in layer A is covered by layer B, its electrical properties, such as resistance, may change. An example of a change in resistance due to layer B being covered by layer A will be described below with reference to Figure 3.
[0048] Figure 3 shows a schematic cross-sectional view of a coverage example according to an embodiment of the present disclosure. As shown in Figure 3, layer B can be an implanted region formed in layer A by, for example, ion implantation, where the implanted impurities can alter the conductivity of layer A (e.g., an active layer or polysilicon). Therefore, when a region in layer A is covered by layer B, the resistance value of that region can change.
[0049] Referring back to Figure 2, in the electrical structure 200, a common pad Pc can be provided to be electrically connected to one end of each of the first region 101, the second region 103, the third region 105, and the fourth region 107. Furthermore, first pads P1, second pads P2, third pads P3, and fourth pads P4 can be provided to be electrically connected to the other end of each of the first region 101, the second region 103, the third region 105, and the fourth region 107, respectively. That is, one end of each of the first region 101 to the fourth region 107 is electrically connected to the common pad Pc, and the other end is electrically connected to their respective pads, such as first pad P1, second pad P2, third pad P3, and fourth pad P4.
[0050] In this embodiment, the resistance values of the first region 101, the second region 103, the third region 105, and the fourth region 107 can be measured using the common pad Pc, and the first pad P1, the second pad P2, the third pad P3, and the fourth pad P4, respectively. Here, the resistance value of the first region 101 can be R1, the resistance value of the second region 103 can be R2, the resistance value of the third region 105 can be R3, and the resistance value of the fourth region 107 can be R4. For example, a specific voltage can be applied to the pads, and the resistance value of each region can be calculated by measuring the current flowing through each region.
[0051] However, the embodiments are not limited thereto. In other embodiments, pads can be formed that are electrically connected to the two ends of each of the first region 101 to the fourth region 107, and the first resistance value R1 to the fourth resistance value R4 can be measured through these pads.
[0052] As described above, the third region 105 can be designed to be covered by layer B across the entire width for a nominal 50% length range, and the fourth region 107 can be designed to be covered by layer B across the entire width for a nominal 50% length range. However, in practice, overprinting errors can exist between layer B and layer A. For example, it can be assumed that the overprinting error between layer B and layer A in the X direction is x, and the overprinting error between layer B and layer A in the Y direction is y. Therefore, it can be considered that, in practice, the third region 105 is not covered by layer B at the nominal 50% ratio, but rather there is a deviation of overprinting error x in the X direction, that is, the third region 105 can be covered by layer B across the entire width for a length range (50%Lx) in the length direction. Similarly, the fourth region 107 may not be covered by layer B at the nominal 50% ratio, but rather there is a deviation of overprinting error y in the Y direction, that is, the fourth region 107 can be covered by layer B across the entire width for a length range (50%Ly) in the length direction.
[0053] Figure 4 shows a schematic diagram of overlay error in the X direction according to an embodiment of the present disclosure.
[0054] Here, the third region 105 is used as an example for description. As mentioned above, the overlay error between layer B and layer A in the X direction can be x. For ease of description, the positive (+) direction in the X direction can be defined as the direction from the uncovered portion of the third region 105 to the covered portion (this definition only affects the sign of the value and does not affect the working principle of the inventive concept). The overlay error x in the X direction can be positive or negative.
[0055] Figure 4(a) illustrates a schematic diagram of the overlay error of layer B and layer A in the X direction shifting to the left (i.e., x is negative). Therefore, a region (e.g., the third region 105) can be covered by layer B within a length of (50%L + |x|), i.e., (50%Lx). In other words, the overlay error occurs in the X direction along the direction in which layer A is covered by layer B.
[0056] Furthermore, Figure 4(b) shows a schematic diagram of the overlay error between layer B and layer A in the X direction shifting to the right (i.e., x is a positive value). Therefore, a region (e.g., the third region 105) can be covered by layer B within a length of (50% L - |x|), i.e., (50% Lx). In other words, the overlay error occurs in the X direction along the direction in which layer A is covered by layer B, thus decreasing the overlay.
[0057] The resistance values R1 of the first region 101, R2 of the second region 103, and R3 of the third region 105 can have the following relationship with the actual length (50% Lx) of the third region 105 covered by layer B:
[0058] Based on the above relationships, the overlay error x in the X direction can be determined as follows:
[0059] In the same way, the overlay error y between layer A and layer B in the Y direction can also be determined:
[0060] I will not go into details here.
[0061] Figure 5 shows a schematic flowchart of a method for determining overlay error according to an embodiment of the present disclosure.
[0062] As shown in FIG. 5, the method 500 according to this embodiment may include: forming a first layer in S502. The first layer includes a first region (e.g., 101 in FIG. 1 or FIG. 2), a second region (e.g., 103 in FIG. 1 or FIG. 2), and a third region (e.g., 105 in FIG. 1 or FIG. 2) having the same dimensions. As mentioned above, these regions may have the same rectangular shape, and more specifically, may have the same length and width. Additionally, a fourth region (e.g., 107 in FIG. 2) extending in a different direction than the third region may also be formed. The fourth region may have the same rectangular shape as the first to third regions.
[0063] Method 500 may further include: forming a second layer in S504. The first region may not be covered by the second layer, the second region may be completely covered by the second layer, and the third region may be partially covered by the second layer. For example, the third region is designed to be partially covered by the second layer at a nominal ratio. Additionally, the fourth region is designed to be partially covered by the second layer at a nominal ratio. The nominal coverage ratios of the third and fourth regions may be the same (e.g., 50%) or different. For information regarding the first and second layers and their coverage relationship, please refer to layers A and B described above with reference to Figures 1 to 4.
[0064] Method 500 may further include measuring, in S506, a first resistance value of the first region, a second resistance value of the second region, and a third resistance value of the third region. Additionally, if a fourth region is formed, a fourth resistance value of the fourth region may also be measured. For example, each resistance value may be measured by means of pads electrically connected to both ends of each region.
[0065] Method 500 may further include: in S508 determining the overlay error between the first layer and the second layer based on the first resistance value, the second resistance value, the third resistance value, and the nominal ratio.
[0066] For example, the following equation can be used to determine overlay error:
[0067] Where R1 is the first resistance value, R2 is the second resistance value, R3 is the third resistance value, P is the nominal ratio, and ΔP is the deviation from the nominal ratio caused by overprinting error.
[0068] In an embodiment, the third region can be designed to be covered by the second layer across its entire width for 50% of the nominal length. In this case, the overlay error can be determined using the following equation:
[0069] Where x is the overprinting error in the length direction of the third region, R3 is the third resistance value, R1 is the first resistance value, R2 is the second resistance value, and L is the length of the rectangular shape.
[0070] In an embodiment, the fourth region can be designed to be covered by the second layer across its entire width for 50% of its nominal length. In this case, the overlay error can be determined using the following equation:
[0071] Where y is the overlay error in the length direction of the fourth region, R4 is the fourth resistance value, R1 is the first resistance value, R2 is the second resistance value, and L is the length of the rectangular shape.
[0072] Figure 6 is a schematic diagram illustrating an integrated circuit according to an embodiment of the present disclosure.
[0073] As shown in Figure 6, the integrated circuit 600 according to this embodiment may include a first layer and a second layer. For example, the integrated circuit 600 can be fabricated by forming multiple layers, including the first layer and the second layer, on a substrate and processing each layer (e.g., etching, implantation, etc.).
[0074] Integrated circuit 600 may include a device region and a test region. In the device region, electronic components that implement the desired function of integrated circuit 600 can be formed, such as various active devices like transistors and passive devices like capacitors. These electronic components can be formed at least partially in the first and second layers. For example, the active region or polysilicon gate of a transistor device can be formed in the first layer, and the implantation region of the transistor device can be formed in the second layer. In the test region, components for testing whether integrated circuit 600 can properly perform its desired function can be formed, such as the electrical structure for testing overlay errors described above with reference to Figures 1 to 4. The electrical structure and the method for measuring overlay errors are described above and will not be repeated here.
[0075] Note that the device area and the test area are only logically separated, not physically separated. For example, the device area and the test area can be separated from each other, or the test area can be embedded in the device area. The test area can be electrically isolated from the device area.
[0076] As described above, embodiments of this disclosure have been described in detail with reference to the accompanying drawings. However, the specific structure is not limited to the above embodiments, and this disclosure also includes any design modifications that do not depart from the spirit of this disclosure. Furthermore, various modifications can be made to this disclosure within the scope of the claims, and embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included within the technical scope of this disclosure. In addition, components with the same effects described in the above embodiments can be substituted for each other.
Claims
1. A method for measuring overlay error, comprising: A first layer is formed, the first layer comprising a first region, a second region, and a third region having the same size; A second layer is formed, wherein the first region is not covered by the second layer, the second region is completely covered by the second layer, and the third region is partially covered by the second layer, wherein the third region is designed to be partially covered by the second layer in a nominal proportion; Measure the first resistance value of the first region, the second resistance value of the second region, and the third resistance value of the third region; and Based on the first resistance value, the second resistance value, the third resistance value, and the nominal ratio, the overlay error between the first layer and the second layer is determined.
2. The method according to claim 1, wherein, The first layer is an active layer or a gate layer, and the second layer is an implantation layer.
3. The method according to claim 1, wherein, The first region, the second region, and the third region have the same rectangular shape.
4. The method according to claim 1, wherein, Determining the overprinting error includes using the following equation: Wherein, R1 is the first resistance value, R2 is the second resistance value, R3 is the third resistance value, P is the nominal ratio, and ΔP is the deviation from the nominal ratio caused by the overlay error.
5. The method according to claim 4, wherein, Each of the first, second, and third regions has the same rectangular shape. The third region is designed to be covered by the second layer across its entire width for 50% of its nominal length. Determining the overprinting error includes using the following equation: Where x is the overprinting error in the length direction of the third region, R3 is the third resistance value, R1 is the first resistance value, R2 is the second resistance value, and L is the length of the rectangular shape.
6. The method according to claim 5, wherein, The length direction of the third region is in the first direction. The first layer also includes a fourth region extending along a second direction intersecting the first direction, the fourth region having the same rectangular shape and designed to be covered by the second layer across its entire width for a nominal 50% length. The measurement also includes measuring the fourth resistance value of the fourth region. Determining the overprinting error includes using the following equation: Where y is the overprinting error in the length direction of the fourth region, R4 is the fourth resistance value, R1 is the first resistance value, R2 is the second resistance value, and L is the length of the rectangular shape.
7. The method according to claim 6, wherein, The length direction of one of the first region and the second region is in the first direction, and the length direction of the other region is in the second direction.
8. The method according to claim 6, wherein, The measurements include: Forming pads electrically connected to both ends of each of the first to fourth regions; and The first resistance value to the fourth resistance value are measured through the pads.
9. The method according to claim 6, wherein, One end of each of the first to fourth regions is electrically connected to a common pad, and the other end is electrically connected to its respective pad.
10. An integrated circuit, comprising: The first layer includes a first area, a second area, and a third area of the same size; The second layer, wherein the first region is not covered by the second layer, the second region is completely covered by the second layer, and the third region is partially covered by the second layer, wherein the third region is designed to be partially covered by the second layer in a nominal proportion; and Circuitry devices that are at least partially formed in the first and second layers. The first region, the second region, and the third region are electrically isolated from the circuit device. The first region, the second region, and the third region each have a corresponding first resistance value, a second resistance value, and a third resistance value. The first resistance value to the third resistance value and the nominal ratio are configured to determine the overlay error between the first layer and the second layer.