Semiconductor device and manufacturing method therefor

Abstract

Disclosed are a semiconductor device and a manufacturing method therefor. According to embodiments, the semiconductor device may comprise: a channel portion comprising a core layer and a shell layer that are stacked, wherein the core layer has a first doping type, and the shell layer has a second doping type opposite to the first doping type; a source / drain portion on opposite sides of the channel portion, wherein the source / drain portion has the first doping type; and a gate stack on the channel portion, wherein the channel portion has a shape protruding toward the gate stack.

Description

Semiconductor devices and their manufacturing methods Technical Field

[0001] This disclosure relates generally to semiconductor technology, and more specifically to a semiconductor device with improved performance and a method for manufacturing the same. Background Technology

[0002] To address the continuous miniaturization of semiconductor devices, various performance optimization schemes have been proposed.

[0003] In addition, (fully depleted (FD)) semiconductor-on-insulator (SOI) is a promising technology route. (FD)SOI technology has the potential to achieve or even surpass the performance of FinFETs at the same node, making it competitive in the market. Summary of the Invention

[0004] The purpose of this disclosure is at least in part to provide a semiconductor device with improved performance and a method for manufacturing the same.

[0005] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a channel portion including a core layer and a shell layer stacked on top of each other, wherein the core layer has a first doping type and the shell layer has a second doping type opposite to the first doping type; source / drain portions on opposite sides of the channel portion, wherein the source / drain portions have the first doping type; and a gate stack on the channel portion, wherein the channel portion has a shape protruding toward the gate stack.

[0006] According to another aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a first semiconductor layer having a first doping type on a substrate; forming a sacrificial gate on the first semiconductor layer; forming a sidewall on a sidewall of the sacrificial gate; forming source / drain portions on opposite sides of the sacrificial gate; removing the sacrificial gate inside the sidewall to expose a surface of the first semiconductor layer; forming a second semiconductor layer having a second doping type on the exposed surface of the first semiconductor layer, wherein the second doping type is opposite to the first doping type, and the second semiconductor layer is formed to have an upwardly convex shape; and forming a gate stack on the second semiconductor layer inside the sidewall.

[0007] According to embodiments of this disclosure, the semiconductor device can have a core-shell (CS) junctionless structure. This CS structure can be formed in an alternative gate process, and therefore its doping level can be easily tuned. This allows for relatively easy achievement of the threshold voltage (V0). t Adjustments to ) and thus enable multi-V tThe solution involves adjusting the doping level to optimize the channel thickness. Furthermore, the channel can have a convex shape, and correspondingly, the bottom of the gate stack can have sharp corners, such as acute angles (e.g., acute angles in the range of 50° to 70°). These sharp corners can improve the drive current and leakage current characteristics of the device. Attached Figure Description

[0008] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figures 1 to 6 schematically illustrate some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure;

[0010] Figure 7 schematically illustrates a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure;

[0011] Figure 8 schematically illustrates a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure;

[0012] Figure 9 schematically illustrates the current-voltage characteristic curve of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0013] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0014] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0015] According to embodiments of this disclosure, a semiconductor device, particularly a fully depleted (FD) semiconductor-on-insulator (SOI) field-effect transistor (FET), is provided. The channel portion of this semiconductor device may have a core-shell (CS) structure, comprising a core layer and a shell layer stacked on top of each other and having opposite doping types. Source / drain portions may be located on opposite sides of the channel portion and may have the same doping type as the core layers. Therefore, a junctionless (JL) device based on a CS structure can be obtained.

[0016] The gate stack can be disposed on the channel portion, and the channel portion can have a shape that protrudes towards the gate stack. Thus, the gate stack can have sharp corners formed at the bottom, such as corners with acute interior angles (e.g., acute angles in the range of 50° to 70°). Such sharp corners can improve device performance, such as improving the drive current and leakage current characteristics of the device.

[0017] According to an embodiment, the semiconductor device may include a first semiconductor layer disposed on a substrate. The first semiconductor layer may have a first doping type and includes a first portion (e.g., a portion overlapping a gate stack in the vertical direction) and second and third portions (e.g., portions on opposite sides of the gate stack) located on opposite sides of the first portion. A second semiconductor layer having a second doping type opposite to the first doping type may be disposed on the first portion of the first semiconductor layer. The gate stack may be disposed on the second semiconductor layer. Thus, the first semiconductor layer (the first portion) and the second semiconductor layer can form a CS structure. For example, the first semiconductor layer (the first portion) may serve as a core layer, and the second semiconductor layer may serve as a shell layer; or vice versa. Source / drain portions may be formed in and / or on the second and third portions of the first semiconductor layer.

[0018] According to an embodiment, the above-described semiconductor device can be an n-type semiconductor device. In this case, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage (e.g., a positive voltage), the space charge in the core layer is balanced by the space charge in the shell layer, resulting in complete depletion; when the absolute value of the gate voltage gradually increases to be greater than the absolute value of the threshold voltage, the core layer first forms an electron accumulation mode and begins to conduct electricity, and then a larger gate voltage value causes the shell layer to form an inversion mode and jointly join in conducting electricity.

[0019] According to an embodiment, the above-described semiconductor device can be a p-type semiconductor device. In this case, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage (e.g., a negative voltage), the space charge in the core layer is balanced by the space charge in the shell layer, becoming completely depleted; when the absolute value of the gate voltage gradually increases to be greater than the absolute value of the threshold voltage, the core layer first forms a hole accumulation mode and begins to conduct electricity, and then a larger gate voltage value causes the shell layer to form an inversion mode and jointly join in conducting electricity.

[0020] The doping level of at least one of the first semiconductor layer and the second semiconductor layer (or, the doping level of at least one of the core layer and the shell layer) can be controlled or adjusted to achieve control over the device threshold voltage (V). t Adjustments to V. As described in further detail below. t V can be determined at least in part by the amount of additional dopant charge in the shell relative to the core. The amount of additional dopant charge can be adjusted by adjusting the doping level, thereby adjusting V. t Compared to adjusting V through methods such as back-gate wells. t The relevant technical solutions can simplify the process and circuit design.

[0021] Because V can be adjusted relatively easily t Therefore, multi-V can be implemented relatively easily. t Solutions, for example, devices for different regions and / or different applications can have different V values. t For example, the first device among a plurality of devices formed on the substrate may have a first doping level (resulting in a first additional dopant charge) and thus a first V. t The second device can have a second doping level different from the first doping level (resulting in a second additional dopant charge) and therefore have a second V. t Furthermore, different dopant levels can lead to different carrier mobilities. Device performance can be optimized by adjusting carrier mobility.

[0022] The protruding shape of the channel portion can originate from the second semiconductor layer. For example, the second semiconductor can have an upwardly convex shape, where the thickness of the middle portion can be greater than the thickness of the edge portions. The thickness of the channel portion can be adjusted to accommodate changes in the doping level. For example, the thickness of the channel portion can be adjusted by thinning the thickness of the first portion of the first semiconductor (as described below, this can be done in an alternative gate process). At relatively high doping levels, the channel portion thickness can be relatively thin.

[0023] This semiconductor device can be manufactured as follows: A first semiconductor layer having a first doping type can be formed on a substrate, a sacrificial gate can be formed on the first semiconductor layer, and sidewalls can be formed on the sidewalls of the sacrificial gate. Source / drain portions can be formed on opposite sides of the sacrificial gate. The source / drain portions can have a first doping type (when the first semiconductor layer is the core layer) or a second doping type opposite to the first doping type (when the first semiconductor layer is the shell layer). The first semiconductor layer can be a semiconductor layer separately disposed on the substrate, or it can be a part of the substrate, such as the SOI layer of a semiconductor on insulator (SOI) substrate or a doped region in a bulk semiconductor substrate. The source / drain portions can be (at least partially) formed in the first semiconductor layer (e.g., when both the source / drain portions and the first semiconductor layer have the first doping type; or, by ion implantation into the first semiconductor layer), or (at least partially) formed on the first semiconductor layer (e.g., by epitaxial growth).

[0024] Alternative gate processes can be performed. For example, the sacrificial gate can be removed inside the gate sidewall to expose the surface of the first semiconductor layer. A second semiconductor layer with a second doping type opposite to the first doping type can be formed on the surface of the first semiconductor layer. Here, the doping level of the second semiconductor layer (and optionally the first semiconductor layer) can be adjusted by means of the opening formed due to the removal of the sacrificial gate, for example by ion implantation, to adjust V as described above. t This also optimizes carrier mobility. Additionally, the thickness of the first semiconductor layer can be adjusted by thinning the exposed surface of the first semiconductor layer, as described above. Alternatively, the growth thickness of the second semiconductor layer can be controlled to adjust the thickness of the channel portion.

[0025] The second semiconductor layer can be formed on the exposed surface of the first semiconductor layer, for example, by epitaxial growth, and can have an upwardly convex shape. For example, when grown within a limited space defined by sidewalls, the growth rate in the middle portion can be greater than the growth rate in the edge portion, so that the second semiconductor layer can be thicker in the middle portion and thinner in the edge portion.

[0026] On the inside of the sidewall, on the second semiconductor layer, a gate stack can be formed.

[0027] The manufacturing process according to the embodiments of this disclosure is fully compatible with the processes of related technologies, and can save additional development costs.

[0028] This disclosure may be presented in various forms, some of which are described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.

[0029] Figures 1 to 6 schematically illustrate some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure.

[0030] As shown in Figure 1, an SOI substrate 100 can be provided. The SOI substrate 100 may include a base substrate 1001, a buried oxide layer 1003 on the base substrate 1001, and an SOI layer 1005 on the buried oxide layer 1003.

[0031] The substrate 1001 may include a semiconductor material such as silicon (Si), the buried oxide layer 1003 may include an oxide (such as silicon oxide), and the SOI layer 1005 may include a suitable semiconductor material, such as elemental semiconductor materials such as Si and Ge, compound semiconductor materials such as group IV compound semiconductor materials such as SiGe and SiC, and group III-V compound semiconductor materials such as GaN. The SOI layer 1005 may be doped to a first doping type, such as n-type or p-type, by means of, for example, ion implantation.

[0032] Shallow trench isolation (STI) can be formed in SOI substrate 100 to define the active region.

[0033] According to embodiments of this disclosure, a back-gate process can be performed. Various methods exist in the art for implementing a back-gate process; only one example is described below.

[0034] For example, as shown in FIG2, a sacrificial gate 1007 may be formed on the SOI substrate 100, and sidewalls 1009 may be formed on the sidewalls of the sacrificial gate 1007. For example, the sacrificial gate 1007 may comprise a stack of oxide and polysilicon, and the sidewalls 1009 may comprise nitrides (e.g., silicon nitride). Although the sidewalls 1011 are shown as a single-layer structure in FIG2, this disclosure is not limited thereto. The sidewalls 1009 may also have a multilayer structure.

[0035] According to some embodiments, an additional source / drain layer can be formed on the outer side of the sidewall 1009, on the surface of the SOI layer 1005, by means of, for example, epitaxial growth, as shown by the dashed line in Figure 2. The source / drain layer can be doped in situ during growth or doped by ion implantation after growth to have a specific doping type (e.g., n-type doping for NMOS; p-type doping for PMOS).

[0036] Next, an alternative gate process can be implemented.

[0037] For example, as shown in FIG3, an interlayer dielectric layer 1011 can be formed on an SOI substrate 100. For example, the interlayer dielectric layer 1011 can be formed by depositing an oxide and planarizing the deposited oxide such as by chemical mechanical polishing (CMP) to expose the sacrificial gate 1007.

[0038] As shown in Figure 4, the sacrificial gate 1007 can be removed by etching, for example, using a re-etching process (RIE), on the inner side of the sidewall 1009 to free up space for gate stacking. This space allows for selective etching of the exposed SOI layer 1005 to reduce its thickness. As further described below, this thickness adjustment can be used to optimize device performance.

[0039] As shown in Figure 5, a semiconductor layer 1013 can be formed on the SOI layer 1005, for example, through epitaxial growth. The semiconductor layer 1013 may include the same semiconductor material as the SOI layer 1005, or it may include a different semiconductor material. The semiconductor layer 1013 can be doped with a second doping type opposite to the first doping type by ion implantation or in-situ doping. Considering the effect of doping level on device performance, ion implantation can be used to easily adjust the doping level.

[0040] Due to at least one of various factors such as limited space within the sidewalls and crystal growth characteristics, the grown semiconductor layer 1013 may have an upwardly convex shape, with a relatively thicker thickness in the middle and a relatively thinner thickness at the edges. For example, when the upper surface of the SOI layer 1005 is a (100) crystal plane, considering the difference in growth rate between the (100) and (111) crystal planes (the (111) crystal plane grows slower than the (100) crystal plane), the semiconductor layer 1013 may have an upper surface along the (100) crystal plane and a side surface along the (111) crystal plane.

[0041] As shown in Figure 6, a gate stack can be formed inside the sidewall 1009. For example, a gate dielectric layer 1015 and a gate electrode layer 1017 can be formed sequentially. For example, the gate dielectric layer 1015 may include a high-k gate dielectric such as hafnium oxide (HfO2). An interface oxide layer may exist between the gate dielectric layer 1015 and the semiconductor layer 1013. The gate electrode layer 1017 may include a metal gate electrode, for example, including a work function layer and a gate conductor layer. The work function layer may include a metal nitride such as TiN and have a suitable work function, for example, an n-type work function for NMOS and a p-type work function for PMOS. The gate conductor layer may include a conductive material, such as a metal such as tungsten (W).

[0042] As shown in Figure 6, the channel portion of the semiconductor device according to this embodiment may include a structure in which an SOI layer 1005 (the portion overlapping the gate stack in the vertical direction) and a semiconductor layer 1013 are stacked on top of each other. These two layers have opposite doping types and can form a CS structure. For example, the SOI layer 1005 (which can serve as the "first semiconductor layer" as described above) can form a core layer, while the semiconductor layer 1013 on the SOI layer 1005 (which can serve as the "second semiconductor layer" as described above) can form a shell layer; and vice versa.

[0043] The source / drain portions are located on opposite sides of the channel portion. For example, the source / drain portions can be portions of SOI layer 1005 (on opposite sides of the gate stack), and optionally may also include additional source / drain layers grown on SOI layer 1005 (as shown by dashed lines in Figure 6). The source / drain portions can have the same doping type as the core layer and the opposite doping type to the shell layer. The source / drain portions can be connected to the core layer.

[0044] The doping type of the shell (e.g., semiconductor layer 1013) is opposite to that of the core layer (e.g., SOI layer 1005) to establish a total depletion condition in the core layer. The total dopant charge in the shell can be (slightly) greater than the total dopant charge in the core layer. This additional dopant charge in the shell can modulate the device's threshold voltage V. t More specifically, the change in threshold voltage can be determined as follows: ΔV t =ΔQ / C OX Where ΔQ represents the amount of additional dopant charge in the shell, and C OX ΔVt represents the gate oxide capacitance, and it represents the change in threshold voltage relative to when the dopant charges in the core and shell are balanced (equal in quantity). The greater the amount of additional dopant charge in the shell, the greater the change in threshold voltage.

[0045] Here, the core and shell layers have opposite doping types, and therefore one has a positive charge (e.g., holes) while the other has a negative charge (e.g., electrons). Here, ΔQ represents the difference in the amount of charge, regardless of the polarity of the charge itself. For example, 1 unit of positive charge (e.g., hole) is balanced by 1 unit of negative charge (e.g., electron). On the other hand, for m units of charge (e.g., positive or negative) in the shell layer relative to n units of charge (e.g., negative or positive, opposite in polarity to the charge in the shell layer), ΔQ is (mn) units.

[0046] Similarly, the threshold voltage change ΔV corresponding to ΔQ t This can refer to the magnitude of the threshold voltage variation. For NMOS and PMOS, the threshold voltage can vary in different directions. For example, for NMOS, the additional dopant charge in the shell (ΔQ>0) can cause the threshold voltage V to change. t The voltage increases towards the positive direction; however, for PMOS, the additional dopant charge in the shell (ΔQ>0) can lead to a threshold voltage V. t Increase in the direction of negative voltage (note that the sign of voltage only indicates direction, and its absolute value indicates voltage amplitude).

[0047] Figure 9 schematically illustrates the (drain) current-(gate) voltage characteristic curve of a semiconductor device according to an embodiment of the present disclosure.

[0048] Figure 9 shows the drain current (I) when the dopant charges in the shell and core are balanced. D - Gate voltage (V) G The curve ① and I when there is an additional dopant charge in the shell. D -V G Curve ②. Additionally, the figure also shows the conduction current I corresponding to the threshold voltage. ON When the dopant charges in the shell and core are balanced (ΔQ = 0), the threshold voltage V is... t1 It can be approximated as 0V. When there is additional dopant charge in the shell (ΔQ>0), the threshold voltage V is... t2 V t2 =V t1 +ΔV t =ΔQ / C OX (A value greater than 0V). For NMOS, a positive threshold voltage can be achieved. Similarly, for PMOS, a negative threshold voltage can be achieved.

[0049] Therefore, the additional dopant charge ΔQ can be adjusted by regulating the doping level of at least one of the shell and core layers, thereby regulating the device's threshold voltage. The doping level can be adjusted by modifying the ion implantation parameters. Furthermore, multiple threshold voltage schemes can be formed. For example, when forming multiple semiconductor devices, they can be implemented as devices with different threshold voltages by adjusting ΔQ differently in different devices. For example, while the SOI layer 1005 is doped in the same way, the semiconductor layer 1013 can be doped differently. For example, more doping can be applied to the semiconductor layer 1013 in some regions (while the semiconductor layer 1003 in other regions can be masked). Compared to related techniques that adjust the threshold voltage using methods such as back gate wells, this simplifies the process and circuit design.

[0050] Furthermore, the doping levels in the core and shell layers can be adjusted to optimize carrier mobility. Additionally, the channel thickness can be adjusted proportionally to the doping level adjustment. Higher doping levels allow for a smaller thickness (e.g., while maintaining the same threshold voltage). Ultimately, it is possible to optimize, for example, maximizing Ik when the device is on. D Figure 7 schematically illustrates a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. The semiconductor device shown in Figure 7 is substantially the same as that described in Figure 6, except that the SOI layer 1005a is not thinned.

[0051] Since carrier mobility can be improved by varying the doping level, for example, by up to 5 times, some techniques used in related technologies to improve carrier mobility, such as using SiGe channels for p-type devices (which is more complex in FDSOI technology) and strain / stress design, can be eliminated. This simplifies the process and enhances device reliability.

[0052] A gate stack (including a gate dielectric layer 1015 and a gate electrode layer 1017) may be disposed on a semiconductor layer 1013. Corresponding to the convex shape of the semiconductor layer 1013, the bottom of the gate stack may have an concave shape, and thus may form a sharp corner. The interior angle of this corner may be an acute angle, for example, an angle in the range of 50° to 70°.

[0053] These sharp corners can help enhance the electric field strength along the channel around the corners, thus improving drive current and leakage current characteristics. Specifically, when the device is turned on, the enhanced electric field can attract more charge carriers along the channel around the corners, thus increasing the drive current. This is as if the channel length were shortened. On the other hand, when the device is turned off, the enhanced reverse electric field can increase the depletion region into the source / drain region, thus reducing the leakage current. This is as if the channel length were lengthened.

[0054] Although the above embodiments are described using an SOI FET as an example, this disclosure is not limited thereto. For example, the inventive concept of this disclosure can also be applied to a bulk FET.

[0055] Figure 8 schematically illustrates a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure.

[0056] As shown in FIG8, the semiconductor device according to this embodiment may include a substrate 1001b. Unlike the SOI substrate in the above example, the substrate 1001b may be a bulk substrate, such as a bulk Si substrate. A first semiconductor layer 1005 and a second semiconductor layer 1013 as described above may be formed on the substrate 1001b. The first semiconductor layer 1005 may be another semiconductor layer epitaxially grown on the substrate 1001b, or it may be a region in the upper part of the substrate 1001b that has been doped by, for example, ion implantation. For a detailed description of the first semiconductor layer 1005 and the second semiconductor layer 1013, please refer to the above embodiments. Similarly, the semiconductor device includes a gate stack (including a gate dielectric layer 1015 and a gate electrode layer 1017) on the second semiconductor layer 1013.

[0057] The semiconductor devices according to embodiments of this disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such semiconductor devices, and electronic devices can be constructed therefrom. Such electronic devices may also include components such as display screens that cooperate with the integrated circuits and wireless transceivers that cooperate with the integrated circuits. Examples of such electronic devices include smartphones, computers, tablet computers, wearable smart devices, artificial intelligence devices, and power banks.

[0058] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0059] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: The channel portion includes a core layer and a shell layer stacked on top of each other, wherein the core layer has a first doping type and the shell layer has a second doping type opposite to the first doping type; The source / drain portions on opposite sides of the channel portion, wherein the source / drain portions have the first doping type; and The grid stack on the channel section The channel portion has a shape that protrudes toward the gate stack.

2. The semiconductor device according to claim 1, comprising: A first semiconductor layer on a substrate includes a first portion and second and third portions located on opposite sides of the first portion, wherein one of the core layer and the shell layer includes the first portion of the first semiconductor layer, and the source / drain portions are formed in and / or on the second and third portions of the first semiconductor layer; and A second semiconductor layer on a first portion of the first semiconductor layer, wherein the other of the core layer and the shell layer includes the second semiconductor layer.

3. The semiconductor device according to claim 2, wherein, The first portion of the first semiconductor layer has a reduced thickness compared to the second and third portions.

4. The semiconductor device according to claim 2, wherein, The thickness of the second semiconductor layer in the middle portion is greater than that in the edge portion.

5. The semiconductor device according to claim 2, wherein, The second semiconductor layer has an upper surface of a (100) crystal plane and a side surface of a (111) crystal plane.

6. The semiconductor device according to claim 1, wherein, Compared to the core layer, the shell layer has additional dopant charge.

7. The semiconductor device according to claim 6, wherein, The semiconductor devices are configured as a plurality of devices, including a first semiconductor device and a second semiconductor device. The first semiconductor device has a shell layer with a first additional dopant charge, and the second semiconductor device has a shell layer with a second additional dopant charge that is different in number from the first additional dopant charge. The threshold voltage of the first semiconductor device is different from the threshold voltage of the second semiconductor device.

8. The semiconductor device according to claim 1, wherein, The semiconductor devices are configured as a plurality of devices, including a first semiconductor device and a second semiconductor device. Compared to the second semiconductor device, the channel portion of the first semiconductor device has a relatively high doping level and a relatively thin thickness.

9. The semiconductor device according to claim 1, wherein, The grid stack has a corner with an acute interior angle at its bottom.

10. The semiconductor device according to claim 9, wherein, The acute angle is in the range of 50° to 70°.

11. A method for manufacturing a semiconductor device, comprising: A first semiconductor layer having a first doping type is disposed on a substrate; A sacrificial gate is formed on the first semiconductor layer; A sidewall is formed on the sidewall of the sacrificial gate; Source / drain portions are formed on opposite sides of the sacrificial gate; On the inside of the sidewall, the sacrificial gate is removed to expose the surface of the first semiconductor layer; On the exposed surface of the first semiconductor layer, a second semiconductor layer having a second doping type is formed, wherein the second doping type is opposite to the first doping type, and the second semiconductor layer is formed to have an upward convex shape; as well as On the inner side of the sidewall, a gate stack is formed on the second semiconductor layer.

12. The method according to claim 11, wherein, The second semiconductor layer is epitaxially grown on the exposed surface of the first semiconductor layer, wherein the growth rate in the middle portion of the space inside the sidewall is greater than the growth rate in the edge portion.

13. The method according to claim 11, wherein, The second semiconductor layer has an upper surface of a (100) crystal plane and a side surface of a (111) crystal plane.

14. The method of claim 11, further comprising: By reducing the thickness of the first semiconductor layer through its exposed surface. The second semiconductor layer is formed on the first semiconductor layer, which has been thinned.

15. The method of claim 11, further comprising: The amount of dopant in the first semiconductor layer and the second semiconductor layer is controlled such that the second semiconductor layer has an additional dopant charge compared to the first semiconductor layer.

16. The method of claim 15, further comprising: By injecting different doses, the amount of additional dopant charge is adjusted to regulate the threshold voltage of the semiconductor device.

17. The method of claim 11, further comprising: The thickness of the channel portion is reduced by increasing the doping levels in the first and second semiconductor layers.

18. The method according to claim 11, wherein, The grid stack has a corner at its bottom with an acute angle ranging from 50° to 70°.

19. The method according to claim 11, wherein, The source / drain is formed in and / or on the first semiconductor layer.

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