Semiconductor device and manufacturing method therefor

Abstract

Disclosed are a semiconductor device and a manufacturing method therefor. The method according to an embodiment may comprise: disposing a lower film layer on a substrate, which lower film layer comprises a first semiconductor layer and a first oxide layer alternately stacked on each other; on the basis of the lower film layer, forming a lower-layer device, wherein the lower-layer device comprises one or more first channel patterns spaced apart from each other in a vertical direction, first source / drain portions on two opposite sides of each first channel pattern, and a first gate stack at least partially surrounding the first channel pattern, the first channel pattern being formed on the basis of a first semiconductor layer in the lower film layer; disposing an upper film layer on the lower-layer device by means of bonding, wherein the upper film layer comprises a second semiconductor layer; and on the basis of the upper film layer, forming an upper-layer device, wherein the upper-layer device comprises one or more second channel patterns spaced apart from each other in a vertical direction, second source / drain portions on two opposite sides of the second channel pattern, and a second gate stack at least partially surrounding the second channel pattern, the second channel pattern being formed on the basis of the second semiconductor layer in the upper film layer.

Description

Semiconductor devices and their manufacturing methods Technical Field

[0001] This disclosure generally relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a three-dimensional (3D) stacked semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the continuous miniaturization of semiconductor devices, the field has now entered the three-dimensional (3D) structure technology route, such as vertically stacked complementary field-effect transistors (CFETs). Among related technologies, CFETs can be divided into monolithic CFETs (m-CFETs) and sequential CFETs (s-CFETs). The m-CFET process is relatively complex, while the s-CFET process can be relatively simple. Summary of the Invention

[0003] In view of this, the purpose of this disclosure is at least in part to provide a 3D stacked semiconductor device and a method for manufacturing the same.

[0004] According to one aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a lower film layer on a substrate, the lower film layer including a first semiconductor layer and a first oxide layer alternately stacked on top of each other; forming a lower device based on the lower film layer, the lower device including one or more first channel patterns spaced apart from each other in a vertical direction, first source / drain portions on opposite sides of the first channel patterns, and a first gate stack at least partially surrounding the first channel patterns, wherein the first channel patterns are formed based on the first semiconductor layers in the lower film layer; forming an upper film layer on the lower device by bonding, the upper film layer including a second semiconductor layer and a sacrificial layer alternately stacked on top of each other; and forming an upper device based on the upper film layer, the upper device including one or more second channel patterns spaced apart from each other in a vertical direction, second source / drain portions on opposite sides of the second channel patterns, and a second gate stack at least partially surrounding the second channel patterns, wherein the second channel patterns are formed based on the second semiconductor layers in the upper film layer.

[0005] According to another aspect of this disclosure, a semiconductor device is provided, which is manufactured according to the method described above.

[0006] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a lower device on a substrate, the lower device including one or more first channel patterns spaced apart from each other in a vertical direction, first source / drain portions on opposite sides of the first channel patterns, and a first gate stack at least partially surrounding the first channel patterns; an upper device on the lower device, the upper device including one or more second channel patterns spaced apart from each other in a vertical direction, second source / drain portions on opposite sides of the second channel patterns, and a second gate stack at least partially surrounding the second channel patterns; and a shallow trench isolation (STI) around the periphery of the lower device, wherein the STI includes an oxide in direct contact with the substrate.

[0007] According to embodiments of this disclosure, lower-layer devices and optional upper-layer devices can be formed based on a film layer comprising alternating semiconductor and oxide layers (also referred to as a semiconductor / oxide superlattice, such as a Si / SiOx superlattice). This alternating stacking of semiconductor / oxide layers can be provided using (multiple) smart-cut techniques. Smart-cut techniques offer lower costs and easier control over inter-channel spacing (the spacing between adjacent semiconductor layers). Furthermore, compared to epitaxial processes, smart-cut techniques provide greater flexibility in material selection and avoid low-temperature silicon processes; process complexity can be reduced, for example, by simplifying superlattice epitaxy, channel release, and selective etching of inner sidewalls; and there are no issues such as Ge contamination, for example, when the sacrificial layer includes SiGe, resulting in fewer defects at the semiconductor / oxide layer interface (e.g., the Si / SiOx interface). Attached Figure Description

[0008] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 schematically illustrates a flowchart of the manufacture of a semiconductor device according to an embodiment of the present disclosure;

[0010] Figure 2 schematically illustrates the flow of the smart-cut loop according to an embodiment of the present disclosure;

[0011] Figure 3 schematically illustrates the SOI structure obtained through a series of smart-cut loops according to an embodiment of the present disclosure;

[0012] Figures 4 to 29(b) schematically illustrate some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure;

[0013] Figures 30 to 32 schematically illustrate some stages in the process of manufacturing a semiconductor device according to other embodiments of the present disclosure. Detailed Implementation

[0014] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0015] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0016] According to embodiments of this disclosure, three-dimensional (3D) stacked semiconductor devices can be fabricated based on sequential processes. For example, lower-layer devices can be fabricated first, and then upper-layer devices can be stacked on top of the lower-layer devices. Using sequential processes, the upper and lower layers can independently support heterogeneous integration, and the design is flexible with simple mid-processing.

[0017] According to embodiments of this disclosure, lower-layer devices and optional upper-layer devices can be fabricated based on a film layer comprising alternating semiconductor layers and oxide layers (or, as may be called, a “semiconductor / oxide superlattice”). Such a film layer can be provided via (multiple) smart-cut processes. In the process of fabricating (lower or upper) devices based on such a film layer, the semiconductor layers can be used to define the channel pattern, and the oxide layers can be used as sacrificial layers. Unlike related technologies that form a film layer comprising alternating semiconductor layers and sacrificial layers (of semiconductor material) via epitaxial growth (or, as may be called, a “semiconductor / semiconductor superlattice,” such as a Si / SiGe superlattice), the smart-cut process is less costly and allows for easier control of the inter-channel spacing (the spacing between adjacent semiconductor layers). Moreover, the use of smart-cut technology allows for more flexible selection of channel materials compared to epitaxial processes and avoids low-temperature silicon processes; process complexity can be reduced, for example, the difficulty of superlattice epitaxy, channel release, and inner sidewall selection etching can be reduced; and there are no problems such as Ge contamination when the sacrificial layer includes SiGe, and fewer defects at the semiconductor layer / oxide layer interface (e.g., Si / SiOx interface).

[0018] When fabricating a device (lower or upper layer) based on this film layer, for example, the film layer can be patterned as a fin extending along a first direction. A sacrificial gate extending along a second direction intersecting (e.g., perpendicular to) the first direction can be formed on the fin, and gate sidewalls can be formed on the sidewalls of the sacrificial gate. Additionally, inner sidewalls can be formed. For example, the sacrificial gate and gate sidewalls can be used as an etching mask to anisotropically etch the fin to expose the sidewalls of the semiconductor layer and the oxide layer. Through the exposed sidewalls of the oxide layer, the oxide layer can be selectively etched to free up space for the inner sidewalls. The inner sidewalls can be formed in the thus freed space. Subsequently, source / drain portions can be formed on opposite sides of the gate sidewalls in the first direction.

[0019] To form a gate stack, the sacrificial gate can be removed to expose an alternating stack of semiconductor and oxide layers in the space between the gate sidewalls (and inner sidewalls). Subsequently, the oxide layers can be selectively etched away to expose the surface of the semiconductor layers. After removing the oxide layers, a gate dielectric layer and a work function layer can be sequentially stacked in the space between the gate sidewalls to form the gate stack.

[0020] In the smart-cut process for setting such a film layer, alternating stacked semiconductor and oxide layers can be formed on a carrier substrate through several (one or more) smart-cut cycles. During the smart-cut cycle, a carrier substrate and a donor substrate can be provided. A bonded oxide layer can be formed on the carrier substrate by, for example, thermal oxidation or deposition. On the other hand, a semiconductor layer (which can also be part of the donor substrate; for example, a dicing line can be defined in the donor substrate by hydrogen ion implantation, and the portion of the donor substrate above the dicing line can serve as the semiconductor layer) can be formed on the donor substrate, and an oxide (e.g., an intrinsic oxide) can also be present on the first surface of the semiconductor layer. The donor substrate can be bonded to the carrier substrate with the oxide on the first surface of the semiconductor layer facing the bonded oxide layer on the carrier substrate. The donor substrate can be removed (e.g., along the dicing line), exposing a second surface of the semiconductor layer opposite to the first surface. In this way, the semiconductor layer remains on the bonded oxide layer of the carrier substrate, resulting in a semiconductor-on-insulator (SOI) structure, namely carrier substrate - buried oxide layer (e.g., bonded oxide layer + intrinsic oxide) - semiconductor layer.

[0021] If multiple semiconductor layers are desired, more smart-cut cycles can be performed. Specifically, a bonding oxide layer can be formed on the SOI structure obtained in the previous smart-cut cycle, on the second surface of the exposed semiconductor layer. Additionally, a donor substrate and a semiconductor layer on the donor substrate are also provided. Following the smart-cut process described above, the semiconductor layer on the donor substrate can be further bonded to the semiconductor layer of the SOI structure obtained in the previous smart-cut cycle, with a bonding oxide layer positioned between the two semiconductor layers.

[0022] This disclosure may be presented in various forms, some of which are described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.

[0023] Figure 1 schematically illustrates a flowchart of manufacturing a semiconductor device according to an embodiment of the present disclosure, Figure 2 schematically illustrates a smart-cut cycle according to an embodiment of the present disclosure, Figure 3 schematically illustrates an SOI structure obtained through several smart-cut cycles according to an embodiment of the present disclosure, and Figures 4 to 29(b) schematically illustrate some stages in the process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0024] As shown in FIG1, the semiconductor device manufacturing method 100 according to this embodiment may include forming a lower film layer on a substrate in operation S110. The lower film layer includes semiconductor layers and oxide layers stacked alternately on top of each other. Referring to FIG4 (which shows a cross-sectional view along the channel extension direction, i.e., a first direction), a lower film layer may be formed on a substrate 4001. This lower film layer includes semiconductor layers 4005-1, 4005-2, 4005-3 and oxide layers 4003, 4007-1, 4007-2 stacked alternately on top of each other. This is an SOI structure, wherein the oxide layer 4003 can serve as a buried oxide layer. The substrate 4001 may include a semiconductor material such as silicon, the semiconductor layers 4005-1, 4005-2, 4005-3 may include a semiconductor material suitable for the channel, such as the same or different semiconductor material as the substrate 4001, and the oxide layers 4003, 4007-1, 4007-2 may include oxides (such as silicon oxide).

[0025] This SOI structure can be formed through multiple smart-cut processes.

[0026] Figure 2 schematically illustrates the flow of a smart-cut loop according to an embodiment of the present disclosure.

[0027] As shown in Figure 2, a carrier substrate 2011, such as a silicon wafer, can be provided. A bonded oxide layer 2013 can be formed on the carrier substrate 2011 by thermal oxidation or deposition, such as chemical vapor deposition (CVD). Alternatively, a donor substrate 2021, such as a silicon wafer, can be provided. Cutting positions can be defined in the carrier substrate 2011 by hydrogen ion implantation, as shown by the dashed lines in the figure. A buffer layer 2023 and a semiconductor layer 2025 can be sequentially formed on the donor substrate 2021 by epitaxial growth. The semiconductor layer 2025 is then retained as a semiconductor layer in the SOI structure (e.g., semiconductor layers 4005-1, 4005-2, and 4005-3 mentioned above) and can be used to define channel patterns. Therefore, it can include various suitable semiconductor materials, such as elemental semiconductor materials like Si or Ge, compound semiconductor materials like SiGe, transition metal dichalcogenides (TMD), etc. The buffer layer 2023 can have etch selectivity relative to the semiconductor layer 2025. The buffer layer 2023 can be used as a stress relaxation buffer layer so that the semiconductor layer 2025 formed thereon can have appropriate stress such as tensile stress (which can improve the performance of devices such as NMOS devices).

[0028] In one example, the buffer layer 2023 may include SiGe, and the semiconductor layer 2025 may include Si. In the absence of strain or stress, the lattice constant of SiGe is greater than that of Si. Therefore, the SiGe buffer layer 2023 may have compressive stress near the interface with the Si donor substrate 2021, and this stress can relax as it moves away from the donor substrate 2021, thus resulting in reduced stress or no stress on the upper part of the buffer layer 2023. The Si semiconductor layer 2025 grown on the stress-relaxed SiGe buffer layer 2023 may have tensile stress.

[0029] For bonding, oxide 2027, such as intrinsic oxide or thermal oxide, can also be formed on the first surface (upper surface in the figure) of semiconductor layer 2025.

[0030] The donor substrate can be bonded to the carrier substrate with the oxide 2027 on the first surface of the semiconductor layer 2025 facing the bonding oxide layer 2013. After bonding, the donor substrate 2021 can be cut according to the cutting position defined by hydrogen ion implantation, thereby removing most of the donor substrate 2021 and leaving a portion 2021'. The remaining portion 2021' of the donor substrate and the buffer layer 2023 can be removed sequentially by selective etching, thereby obtaining an SOI structure in which the semiconductor layer 2025 (with stress such as tensile stress) is disposed on the carrier substrate 2011 and an oxide layer (bonding oxide layer 2013 + oxide 2027) is buried between them.

[0031] In this example, a buffer layer 2023 and a semiconductor layer 2025 are sequentially formed on the donor substrate 2021 to achieve stress in the semiconductor layer 2025 to improve device performance. However, this disclosure is not limited thereto.

[0032] For example, in the above example, instead of forming the buffer layer 2023 and the semiconductor layer 2025, an oxide can be formed directly on the surface of the donor substrate 2021, and the donor substrate 2021 can be bonded to the carrier substrate 2011. The donor carrier 2021 can be cut based on the cutting position, and the remaining part 2021′ of the donor carrier can serve as the semiconductor layer on the buried oxide layer in the final SOI structure.

[0033] According to embodiments of this disclosure, a semiconductor layer on a donor substrate is bonded to a carrier substrate (bonded oxide layer on the substrate) by means of bonding. The semiconductor layer may be a semiconductor layer additionally grown on the donor substrate (e.g., the semiconductor layer 2025 mentioned above) or a part of the donor substrate itself (e.g., part 2021' mentioned above).

[0034] Through the aforementioned smart-cut cycle, a semiconductor layer 2025 (with embedded oxide between them) is stacked on the carrier substrate 2011. According to other embodiments, low-temperature repair can also be performed to improve the crystal quality of the semiconductor layer 2025.

[0035] If more semiconductor layers are to be formed on the carrier substrate, more smart-cut cycles can be performed. For example, a bonding oxide layer can be formed on the surface of the resulting SOI structure, more specifically, on the second surface of the second semiconductor layer 2025 opposite to the first surface, and a donor substrate can be provided in the same smart-cut cycle, through which additional semiconductor layers are stacked on the structure. According to embodiments of this disclosure, for example, 1 to 5 smart-cut cycles can be performed.

[0036] Thus, the SOI structure 300 shown in Figure 3 can be obtained. The SOI structure 300 may include a carrier substrate SUB, a buried oxide layer of the carrier substrate SUB (e.g., the aforementioned bonding oxide layer + intrinsic oxide layer), and alternatingly stacked semiconductor layers SE1, SE2, SE3 and oxide layers OX1, OX2 on the buried oxide layer. Depending on the number of smart-cut cycles, the number of alternatingly stacked semiconductor layers SE1, SE2, SE3 and oxide layers OX1, OX2 may be fewer or more. The thickness of semiconductor layers SE1, SE2, SE3 can be determined by epitaxial growth (e.g., epitaxial growth of semiconductor layer 2025 on buffer layer 2023) or the cutting position (e.g., cutting the remaining portion 2021' from donor substrate 2021); the thickness of oxide layers OX1, OX2 (i.e., the spacing between semiconductor layers SE1, SE2, SE3) can be determined according to the oxidation process.

[0037] The smart-cut process allows for easier control of the spacing between channel patterns (e.g., semiconductor layers SE1, SE2, SE3) (essentially determined by the thicknesses of oxide layers OX1, OX2). Furthermore, compared to a Si / SiGe superlattice-based lower film, it avoids the epitaxial growth process required to realize the Si / SiGe superlattice, thus reducing costs. It also allows for increased spacing between channel patterns (e.g., from approximately 10 nm in the Si / SiGe superlattice to approximately 15 nm in the Si / SiOx superlattice), providing more space for alternative gate processes.

[0038] The structure described above with reference to FIG4 can be provided based on the SOI structure 300 shown in FIG3.

[0039] Referring back to Figure 1, method 100 may also include, in operation S120, forming a lower-layer device based on the lower film layer. Various methods can exist to form a lower-layer device, such as a field-effect transistor (FET), based on such a lower film layer; only one example is described below.

[0040] For example, as shown in Figures 5(a) and 5(b) (Figure 5(a) shows a cross-sectional view along the channel extension direction, i.e., the first direction, and Figure 5(b) shows a cross-sectional view along the gate extension direction, i.e., the second direction), an etching mask such as photoresist (not shown) can be formed, and the photoresist can be patterned into a form corresponding to the channel portion to be formed by photolithography. For example, in the examples shown in Figures 5(a) and 5(b), the photoresist can be in the form of a strip extending along the first direction (the horizontal direction within the plane of the paper in Figure 5(a), and the direction perpendicular to the plane of the paper in Figure 5(b)).

[0041] For convenience, hard mask structures that may be used in patterning processes, such as hard masks in the form of stacked oxide / nitride layers, are not shown here. Furthermore, instead of being limited to examples using photoresist, spacer image transfer (SIT) processes can also be used. For example, sidewalls of, for example, nitride (e.g., silicon nitride) extending along a first direction can be formed by a sidewall formation process, and these sidewalls can be used as etching masks.

[0042] Using the etching mask thus formed, semiconductor layers 4005-1, 4005-2, 4005-3 and oxide layers 4003, 4007-1, 4007-2 are sequentially etched by anisotropic etching, such as vertical reactive ion etching (RIE). According to an embodiment, the etching can penetrate into the substrate 4001. This forms protruding structures (which may be referred to as "fins") extending along a first direction on the substrate 4001. The etching mask can then be removed.

[0043] For electrical isolation purposes, as shown in FIG6, an isolation portion 4009, such as shallow trench isolation (STI), can be formed on the outer periphery of the fin. For example, an oxide can be deposited on a substrate 4001, the deposited oxide can be planarized, for example, by chemical mechanical polishing (CMP), and the planarized oxide can be etched back to form the isolation portion 4009. The isolation portion 4009 fills the bottom of the trench T between the fins on the substrate 4001. More specifically, its top surface may not be higher than, for example, lower than, the top surface of the lowest semiconductor layer 4005-1 (so that at least the top surface of the lowest semiconductor layer 4005-1 and optionally at least part of the side surface can also be used as the channel portion), and not lower than the bottom surface of the buried oxide layer 4003 (so that it can extend continuously with the buried oxide layer 4003 so as to still maintain the SOI structure). The bottom of the fin can be surrounded by the isolation portion 4009. Considering the etching selectivity of the corresponding other oxides in subsequent processes, the isolation portion 4009 may include high-density plasma (HDP) oxide.

[0044] According to embodiments of this disclosure, since SiGe can be omitted, when forming the isolation portion 4009, it is not necessary to form a nitride liner (for preventing Ge diffusion), so that the oxide material of the isolation portion 4009 can directly contact the underlying material layers such as the substrate 4001 and the oxide layer 4003.

[0045] Subsequently, as shown in Figures 7(a) and 7(b), a sacrificial gate 4011 can be formed on the substrate extending along a second direction (e.g., a direction perpendicular to the plane of the paper in Figure 7(a), or a horizontal direction within the plane of the paper in Figure 7(b)) to intersect the aforementioned fins. For example, the sacrificial gate 4011 may comprise an oxide layer and polysilicon on the oxide layer. Similarly, for convenience, a hard mask that may be present on the sacrificial gate 4011 is not shown. On the sidewalls of the sacrificial gate 4011, gate sidewalls 4013 can be formed by a sidewall forming process. For example, gate sidewalls 4013 may comprise nitrides.

[0046] As shown in Figure 8, the sacrificial gate 4011 and gate sidewall 4013 can be used as etching masks to perform anisotropic etching, such as vertical RIE, on the semiconductor layers 4005-1, 4005-2, 4005-3 and oxide layers 4007-1, 4007-2. The RIE can stop at the buried oxide layer 4003. Thus, the semiconductor layers 4005-1, 4005-2, and 4005-3 can form a first channel pattern self-aligned to the sacrificial gate 4011. Here, the first channel pattern can be in the form of a nanosheet.

[0047] According to embodiments of this disclosure, an inner sidewall can also be formed.

[0048] For example, as shown in FIG9, oxide layers 4007-1 and 4007-2 can be selectively etched relative to semiconductor layers 4005-1, 4005-2, and 4005-3, such that their sidewalls are recessed inward to a certain depth relative to the sidewall of gate sidewall 4013 or the sidewalls of semiconductor layers 4005-1, 4005-2, and 4005-3. Preferably, the recess depths of oxide layers 4007-1 and 4007-2 are substantially the same and can be substantially equal to the thickness (in the first direction) of gate sidewall 4013, so that the subsequently formed inner sidewall can have substantially the same thickness as gate sidewall 4013.

[0049] In the recess thus formed, an inner sidewall can be formed. As shown in FIG10, a dielectric material layer of a certain thickness can be formed on the substrate, for example, by deposition. The thickness of the deposited dielectric material layer is sufficient to fill the recess. For example, the dielectric material layer may include SiC, etc. Subsequently, the deposited dielectric material layer can be etched back by, for example, a vertical RIE, thereby forming the inner sidewall 4015. The inner sidewall 4015 may also include the same material as the gate sidewall 4013.

[0050] As shown in Figure 10, in the first direction (the horizontal direction within the plane of the paper in Figure 10), the sidewalls of semiconductor layers 4005-1, 4005-2, and 4005-3 can be exposed. As shown in Figure 11, the exposed sidewalls of semiconductor layers 4005-1, 4005-2, and 4005-3 can be used as seeds to form a source / drain layer 4017 by, for example, selective epitaxial growth. The source / drain layer 4017 can be formed in contact with the exposed sidewalls of semiconductor layers 4005-1, 4005-2, and 4005-3. The bottom surface of the source / drain layer 4017 can be no lower than the bottom surface of the lowest semiconductor layer 4005-1, and therefore can be referred to as a "lifted" source / drain. The source / drain layer 4017 can include various suitable semiconductor materials, for example, Si for n-type FETs (NFETs) and SiGe for p-type FETs (PFETs). The source / drain layer 4017 can be doped to the desired conductivity type (n-type doping for n-type FETs and p-type doping for p-type FETs) by, for example, in-situ doping or ion implantation.

[0051] Next, an alternative gate process can be implemented.

[0052] For example, as shown in FIG12, an interlayer dielectric layer 4019 can be formed on the substrate. For example, the interlayer dielectric layer 4019 can be formed by depositing an oxide and then planarizing the oxide deposited by CMP. CMP can be performed up to expose the sacrificial gate 4011 inside the gate sidewall 4013.

[0053] As shown in Figures 13(a) and 13(b), the sacrificial gate 4011 can be selectively etched away to expose the semiconductor layers 4005-1, 4005-2, 4005-3, the isolation portion 4009, and the oxide layers 4007-1, 4007-2 within the space between the gate sidewalls 4013. It can be seen that, in the second direction, the sidewalls of the oxide layers 4007-1, 4007-2 are exposed (see Figure 13(b)).

[0054] Subsequently, as shown in Figures 14(a) and 14(b), the oxide layers 4007-1 and 4007-2 can be selectively etched away, for example, to expose the surfaces of the semiconductor layers 4005-1, 4005-2 and 4005-3.

[0055] In this example, since the lower film is based on a Si / SiOx superlattice, the etching selectivity between semiconductor layers 4005-1, 4005-2, 4005-3 and oxide layers 4007-1, 4007-2 can be higher compared to a lower film based on a Si / SiGe superlattice. Therefore, after selectively removing oxide layers 4007-1, 4007-2, the edges of semiconductor layers 4005-1, 4005-2, 4005-3, especially the edges in the second direction, can have a sharper morphology (more like a rectangle in cross-sectional view).

[0056] Next, as shown in Figures 15(a) and 15(b), a gate stack can be formed within the space between the gate sidewalls 4013. For example, a gate dielectric layer 4021 and a gate electrode 4023 can be formed sequentially to obtain the final gate stack. For example, the gate dielectric layer 4021 may include a high-k gate dielectric such as hafnium oxide (HfO2). An interface oxide layer may exist between the gate dielectric layer 4021 and the semiconductor layers 4005-1, 4005-2, and 4005-3. The gate electrode 4023 may include a work function layer and a gate conductor layer on the work function layer. The work function layer may include a metal nitride such as TiN and have a suitable work function, for example, an n-type work function for an n-type FET and a p-type work function for a p-type FET. The gate conductor layer may include a conductive material, such as a metal such as tungsten (W).

[0057] As shown in Figures 15(a) and 15(b), the lower-layer device may include one or more first channel patterns (semiconductor layers 4005-1, 4005-2, 4005-3) spaced apart from each other in a vertical direction (e.g., perpendicular to the upper surface of substrate 4001), source / drain layers 4017 on opposite sides of the first channel patterns, and a first gate stack (including gate dielectric layer 4021 and gate electrode 4023) at least partially surrounding the first channel patterns. The first channel patterns (semiconductor layers 4005-1, 4005-2, 4005-3) may be formed as nanosheets substantially aligned with each other in the vertical direction.

[0058] According to embodiments of this disclosure, the gate stack may surround semiconductor layers 4005-2 and 4005-3 and may extend on at least the top surface (in this example, the top surface and side surface) of semiconductor layer 4005-1. Therefore, in addition to semiconductor layers 4005-2 and 4005-3 above the substrate, at least the top surface (and side surface) of semiconductor layer 4005-1 can also serve as a channel portion, thus providing an additional (half) channel compared to conventional bulk nanosheet devices, thereby enhancing the device drive current. To enhance device performance, semiconductor layer 4005-1 may be doped with the opposite type of doping to the source / drain layers; for example, for an n-type FET, p-type doping (e.g., boron doping) may be performed, while for a p-type FET, n-type doping (e.g., phosphorus doping) may be performed. The doping concentration may be on the order of approximately 1E18.

[0059] In this example, the lowest first channel pattern (lowest semiconductor layer 4005-1) is adjacent to the buried oxide layer 4003. However, this disclosure is not limited thereto. According to other embodiments, the buried oxide layer 4003 may include a lower portion and an upper portion, which may include different oxides (e.g., phosphorus-doped oxide and non-phosphorus-doped oxide) with etch selectivity relative to each other. In the process of patterning the first channel pattern as described above in conjunction with FIG8, etching may proceed to the upper portion of the buried oxide layer 4003 and stop at the lower portion of the buried oxide layer 4003, and in subsequent processes, the upper portion of the buried oxide layer 4003 may be treated in the same way as the oxide layers 4007-1, 4007-2. Thus, in the resulting lower device, the gate stack may surround the lowest semiconductor layer 4005-1.

[0060] In the process of fabricating the underlying devices, problems such as Ge contamination, insufficient etching selectivity, and poor interface caused by using a Si / SiGe superlattice-based underlying film can be avoided.

[0061] Referring back to Figure 1, the method 100 may further include, in operation S130, setting an upper film layer for forming an upper device on a lower device by bonding.

[0062] Referring to Figure 16, on a substrate on which the underlying device is formed, an oxide layer can be formed by depositing an oxide layer, for example, by CVD, and then planarizing the deposited oxide layer, such as by CMP. In this example, the oxide layer is shown integrally with the previous interlayer dielectric layer 4019 (e.g., oxide) as interlayer dielectric layer 4025.

[0063] Additionally, an upper film layer for an upper device can be provided, which may include semiconductor layers and sacrificial layers stacked alternately on top of each other. The semiconductor layers in the upper film layer can be used to define a second channel pattern for the upper device. Furthermore, as described below, the sacrificial layer in the upper film layer may include a semiconductor material (e.g., having etch selectivity relative to the semiconductor layer used to define the second channel pattern; in this case, a semiconductor / semiconductor superlattice, such as a Si / SiGe superlattice, can be formed) or an insulating material (e.g., an oxide; in this case, like the lower film layer, a semiconductor / oxide superlattice, such as a Si / SiOx superlattice, can be formed).

[0064] For example, as shown in Figure 17, a film layer consisting of alternating stacked semiconductor layers SE1, SE2, SE3 and sacrificial layers SC1, SC2, SC3 of semiconductor material with etch selectivity relative to semiconductor layers SE1, SE2, SE3 can be formed on a carrier substrate SUB by, for example, epitaxial growth. For example, semiconductor layers SE1, SE2, SE3 may include Si, and sacrificial layers SC1, SC2, SC3 may include SiGe. The thickness of semiconductor layers SE1, SE2, SE3 can be the same as or similar to the thickness of semiconductor layers 4005-1, 4005-2, 4005-3 in the underlying device, and the spacing between semiconductor layers SE1, SE2, SE3 (e.g., about 10 nm) can be smaller than the spacing between semiconductor layers 4005-1, 4005-2, 4005-3 in the underlying device (e.g., about 15 nm). Additionally, an oxide layer OX can be formed on the uppermost semiconductor layer SE3 by, for example, deposition or thermal oxidation. In the substrate SUB, the cutting location can be defined by hydrogen ion implantation (as shown by the dashed line in the figure).

[0065] As shown in Figure 18, the aforementioned film layer is bonded to the interlayer dielectric layer 4025 with the outermost oxide layer OX facing the interlayer dielectric layer 4025 (including the oxide layer). Then, as shown in Figure 19, the carrier substrate SUB can be cut based on the cutting position, thereby removing most of the carrier substrate SUB. Additionally, the remaining portion of the carrier substrate SUB and the sacrificial layer SC1 can be removed by selective etching. Thus, an upper film layer comprising alternately stacked semiconductor layers SE1, SE2, SE3 and sacrificial layers SC2, SC3 is formed on the lower device (specifically, the interlayer dielectric layer 4025).

[0066] In this example, the semiconductor layers SE1, SE2, and SE3 in the upper film layer may not include the portion of the carrier substrate SUB.

[0067] As described above in conjunction with Figure 2, the bonding process is not limited to this. For example, after dicing the carrier substrate SUB, the remaining portion of the carrier substrate SUB may not be removed, but instead used as the uppermost semiconductor layer in the upper film layer, with the sacrificial layer SC1 remaining between this semiconductor layer and the underlying semiconductor layer SE1. In this case, the semiconductor layer in the upper film layer may include a portion of the carrier substrate SUB.

[0068] According to embodiments of this disclosure, the upper film layer is bonded to the lower device. Therefore, the semiconductor layers SE1, SE2, and SE3 in the upper film layer can have different configurations from the semiconductor layers 4005-1, 4005-2, and 4005-3 in the lower film layer. For example, they can differ in at least one of the following aspects: material, crystal structure, and lattice orientation. For instance, one of the semiconductor layers in the lower and upper films may include Si, while the other semiconductor layer may include at least one of SiGe, Ge, III-V compound semiconductors, and transition metal dichalcogenide (TMD). In one example, the lower layer can form an n-type device, and the corresponding semiconductor layers 4005-1, 4005-2, and 4005-3 may include Si and / or may have… <100> Orientation; the upper layer can form a p-type device, and the corresponding semiconductor layers SE1, SE2, SE3 can include SiGe, and / or can have <110> Orientation. The channel patterns can be configured separately according to the different performance requirements of the upper and lower layer devices.

[0069] Referring back to Figure 1, method 100 may further include forming an upper device based on the upper film layer in operation S140. The process of forming an upper device based on the upper film layer can be substantially the same as the process of forming a lower device based on the lower film layer as described above; the main differences will be described below.

[0070] For example, as shown in Figures 20(a) and 20(b), the upper film layer can be patterned as protruding fins. Regarding the patterning process of the fins, please refer to the description above in conjunction with Figures 5(a) and 5(b). In this example, the fins patterned by the upper film layer can extend in the same direction (first direction) as the fins patterned in the process of forming the lower device described above, and can be substantially aligned in the vertical direction (the widths can be the same or different; in the case of different widths, they can be center-aligned). However, this disclosure is not limited thereto.

[0071] Subsequently, as shown in Figures 21(a) and 21(b), a sacrificial gate 4027 intersecting with the fin can be formed. For the process of forming the sacrificial gate, please refer to the description above in conjunction with Figures 7(a) and 7(b). In this example, the formed sacrificial gate can extend in the same direction (second direction) as the sacrificial gate formed in the process of forming the lower-layer device described above, and can be substantially aligned in the vertical direction (the widths can be the same or different; in the case of different widths, they can be center-aligned). However, this disclosure is not limited thereto. A gate sidewall 4029 can be formed on the sidewall of the sacrificial gate 4027.

[0072] As shown in Figure 22, the sacrificial gate 4027 and gate sidewall 4029 can be used as etching masks to connect semiconductor layers SE1, SE2, and SE3 into a second channel pattern self-aligned to the sacrificial gate 4027. For details on the patterning process, please refer to the description above in conjunction with Figure 8. Similarly, the second channel pattern can be in the form of nanosheets.

[0073] Similarly, inner sidewalls can also be formed. For example, as shown in Figure 23, sacrificial layers SC2 and SC3 can be selectively etched relative to semiconductor layers SE1, SE2, and SE3 to define a space for forming the inner sidewalls. As shown in Figure 24, inner sidewall 4031 can be formed within the defined space. For the formation process of the inner sidewalls, please refer to the description above in conjunction with Figures 9 and 10.

[0074] As shown in Figure 25, the exposed sidewalls of semiconductor layers SE1, SE2, and SE3 can be used as seeds to form source / drain layers 4033 through selective epitaxial growth, for example. The specific configuration of the source / drain layers 4033 can be found in the description above in conjunction with Figure 10.

[0075] According to some embodiments, the lower-layer device and the upper-layer device may have different conductivity types, such as the lower-layer device being a PFET and the upper-layer device being an NFET, or vice versa. However, this disclosure is not limited thereto. The upper and lower-layer devices may also have the same conductivity type. In addition, the upper and lower-layer devices may have different configurations (especially when they have different conductivity types), for example, at least one aspect such as the material and lattice orientation of the channel pattern, the material of the source / drain layer, etc., may be different to optimize the respective performance of the upper and lower-layer devices.

[0076] A similar alternative gate process can be performed.

[0077] For example, as shown in FIG26, an interlayer dielectric layer 4035 can be formed. Then, as shown in FIG27(a) and 27(b), the sacrificial gate 4027 can be removed by selective etching. Subsequently, as shown in FIG28(a) and 28(b), the sacrificial layers SC2 and SC3 can be removed by, for example, selective etching to expose the surfaces of semiconductor layers SE1, SE2, and SE3 in the space inside the gate sidewall 4029. Here, as mentioned above, the edges of semiconductor layers SE1, SE2, and SE3, especially the edges in the second direction, can be less sharp than the edges of semiconductor layers 4005-1, 4005-2, and 4005-3 in the underlying device. Next, as shown in FIG29(a) and 29(b), a gate stack can be formed in the space inside the gate sidewall 4029. For example, the gate dielectric layer 4037 and the gate electrode 4039 can be formed sequentially to obtain the final gate stack. For alternative gate processes, please refer to the above description in conjunction with FIGS. 12 to 15(b). Upper and lower layer devices can include the same gate stack configuration or different gate stack configurations to optimize their respective performance.

[0078] Similar to the lower-layer device, the upper-layer device may include one or more second channel patterns (semiconductor layers SE1, SE2, SE3) spaced apart from each other in the vertical direction, source / drain layers 4033 on opposite sides of the second channel patterns, and a second gate stack (including gate dielectric layer 4037 and gate electrode 4039) at least partially surrounding the second channel patterns. The second channel patterns (semiconductor layers SE1, SE2, SE3) may be formed as nanosheets substantially aligned with each other in the vertical direction.

[0079] According to embodiments of this disclosure, the gate stack may surround semiconductor layers SE2 and SE3, and may extend on at least the top surface (and side surface in this example) of semiconductor layer SE1. Therefore, in addition to semiconductor layers SE2 and SE3 above the substrate, at least the top surface (and side surface) of semiconductor layer SE1 may also serve as a channel. To enhance device performance, semiconductor layer SE1 may be doped with the opposite type of doping to the source / drain layers; for example, for an n-type FET, p-type doping (e.g., boron doping) may be performed, while for a p-type FET, n-type doping (e.g., phosphorus doping) may be performed. The doping concentration may be on the order of approximately 1E18.

[0080] In this example, the lowest second channel pattern (the lowest semiconductor layer SE1) is adjacent to the oxide layer OX. However, this disclosure is not limited thereto. According to other embodiments, the upper film layer may include another sacrificial layer (e.g., of the same material and having the same thickness as sacrificial layers SC2 and SC3) between the oxide layer OX and the semiconductor layer SE3. In the process of patterning the second channel pattern as described above in conjunction with FIG22, etching may be performed up to this other sacrificial layer, and this other sacrificial layer may be treated in the same way as sacrificial layers SC2 and SC3 in subsequent processes. Thus, in the resulting lower device, the gate stack may surround the lowest semiconductor layer SE1.

[0081] In this example, a top film based on a Si / SiGe superlattice is used to fabricate the upper-layer device. This is feasible because the upper-layer device can have a lower thermal budget, thereby suppressing Ge diffusion issues.

[0082] In the above example, the sacrificial layer may include a semiconductor material. According to other embodiments, the sacrificial layer may include a dielectric material such as an oxide, and therefore, similar to the lower film layer, the upper film layer can be provided by an SOI structure.

[0083] For example, as shown in Figure 30, an alternating stack of oxide layers OX1 and OX2 and semiconductor layers SE2 and SE3 can be formed on a carrier substrate SUB through, for example, multiple smart-cut processes. On the uppermost semiconductor layer SE3, an oxide layer OX3 can be formed, for example, by deposition or thermal oxidation.

[0084] This film layer can be bonded to the underlying device. For example, as shown in FIG31, the film layer can be bonded to the interlayer dielectric layer 4025 with the outermost oxide layer OX3 facing the interlayer dielectric layer 4025. Then, as shown in FIG32, the carrier substrate SUB can be cut according to the cutting position, thereby removing most of the carrier substrate SUB, and the remaining portion of the carrier substrate SUB can serve as another semiconductor layer SE1. Thus, an upper film layer including alternately stacked semiconductor layers SE1, SE2, SE3 and oxide layers OX1, OX2 is disposed on the underlying device.

[0085] Next, the upper-layer device can be fabricated based on the upper film layer. In this case, the process for fabricating the upper-layer device based on the upper film layer is essentially the same as the process for fabricating the lower-layer device based on the lower film layer, and will not be described in detail here.

[0086] The semiconductor devices according to embodiments of this disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such semiconductor devices, and electronic devices can be constructed therefrom. Such electronic devices may also include components such as display screens that cooperate with the integrated circuits and wireless transceivers that cooperate with the integrated circuits. Examples of such electronic devices include smartphones, computers, tablet computers, wearable smart devices, artificial intelligence devices, and power banks.

[0087] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0088] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: A lower film layer is disposed on a substrate, the lower film layer comprising a first semiconductor layer and a first oxide layer stacked alternately on each other; Based on the lower film layer, a lower device is formed, the lower device including one or more first channel patterns spaced apart from each other in a vertical direction, first source / drain portions on opposite sides of the first channel patterns, and a first gate stack at least partially surrounding the first channel patterns, wherein the first channel patterns are made based on a first semiconductor layer in the lower film layer. An upper film layer is formed on the lower device by bonding, the upper film layer comprising alternating second semiconductor layers and sacrificial layers; and Based on the upper film layer, an upper device is formed, the upper device including one or more second channel patterns spaced apart from each other in a vertical direction, second source / drain portions on opposite sides of the second channel patterns, and a second gate stack at least partially surrounding the second channel patterns, wherein the second channel patterns are made based on a second semiconductor layer in the upper film layer.

2. The method according to claim 1, wherein, The lower film layer is formed by multiple smart-cut processes.

3. The method according to claim 1, wherein, Forming the lower-layer device based on the lower film layer includes: The lower membrane layer is patterned as a fin extending along a first direction; A sacrificial gate is formed on the fin, extending along a second direction intersecting the first direction, and a gate sidewall is formed on the sidewall of the sacrificial gate; Using the sacrificial gate and the gate sidewall as an etching mask, anisotropic etching is performed on the fin to expose the sidewalls of the first semiconductor layer and the first oxide layer; The first source / drain portion is formed on the exposed sidewall of the first semiconductor layer; Remove the sacrificial gate to expose the first semiconductor layer and the first oxide layer in the space between the gate sidewalls; The first oxide layer is removed by selective etching to expose the surface of the first semiconductor layer; and The first grid stack is formed within the space between the grid sidewalls. The first semiconductor layer forms the first channel pattern.

4. The method according to claim 3, wherein, After anisotropic etching of the fin and before forming the first source / drain portion, the method further includes: Through the exposed sidewalls of the first oxide layer, the first oxide layer is selectively etched to free up space for the inner sidewalls; and The inner wall is formed in the space.

5. The method according to claim 1, wherein, The sacrificial layer comprises a semiconductor material having etch selectivity relative to the second semiconductor layer or comprises a second oxide layer.

6. The method according to claim 5, wherein, The upper film layer is formed on the carrier substrate by epitaxial growth or multiple smart-cut processes.

7. The method according to claim 5, wherein, Forming the upper device based on the upper film layer includes: The upper membrane layer is patterned as a fin extending along a first direction; A sacrificial gate is formed on the fin, extending along a second direction intersecting the first direction, and a gate sidewall is formed on the sidewall of the sacrificial gate; Using the sacrificial gate and the gate sidewall as an etching mask, anisotropic etching is performed on the fin to expose the sidewalls of the second semiconductor layer and the sacrificial layer; The second source / drain portion is formed on the exposed sidewall of the second semiconductor layer; Remove the sacrificial gate to expose the second semiconductor layer and the sacrificial layer in the space between the gate sidewalls; The sacrificial layer is removed by selective etching to expose the surface of the second semiconductor layer; and A second grid stack is formed within the space between the grid sidewalls. The second semiconductor layer forms the second channel pattern.

8. The method according to claim 7, wherein, After anisotropic etching of the fin and before forming the second source / drain portion, the method further includes: Through the exposed sidewalls of the sacrificial layer, the sacrificial layer is selectively etched to free up space for the inner sidewall; and The inner wall is formed in the space.

9. The method according to claim 6, wherein, The bonding includes: The carrier substrate on which the upper film layer is formed is bonded to the lower device with the upper film layer facing the lower device; and Remove the carrier substrate.

10. The method of claim 9, further comprising: An interlayer oxide layer is formed on the lower device. The upper film layer is bonded to the interlayer oxide layer.

11. A semiconductor device, comprising: A lower layer device on a substrate, the lower layer device comprising one or more first channel patterns spaced apart from each other in a vertical direction, first source / drain portions on opposite sides of the first channel patterns, and a first gate stack at least partially surrounding the first channel patterns. The upper-layer device on the lower-layer device includes one or more second channel patterns spaced apart from each other in a vertical direction, second source / drain portions on opposite sides of the second channel patterns, and a second gate stack at least partially surrounding the second channel patterns; and Shallow trench isolation (STI) on the outer periphery of the underlying device. The STI includes an oxide that is in direct contact with the substrate.

12. The semiconductor device according to claim 11, wherein, There is no nitride liner between the STI and the substrate.

13. The semiconductor device according to claim 11, wherein, The first channel pattern and the second channel pattern have semiconductor materials that are different from each other, and / or The first channel pattern and the second channel pattern have different lattice orientations.

14. The semiconductor device according to claim 13, wherein, One of the first channel pattern and the second channel pattern has <100> Orientation, another with <110> orientation.

15. The semiconductor device according to claim 13, wherein, One of the first channel pattern and the second channel pattern includes Si, and the other includes at least one of SiGe, Ge, III-V compound semiconductor, and transition metal dichalcogenide (TMD).

16. The semiconductor device according to claim 11, wherein, The edge of the first channel pattern in the extension direction of the first gate stack has a sharper shape than the edge of the second channel pattern in the extension direction of the second gate stack.

17. The semiconductor device according to claim 11, wherein, At least one of the edges of the first channel pattern in the extension direction of the first gate stack and the edges of the second communication pattern in the extension direction of the second gate stack has a sharper morphology than the edges of Si obtained by selectively etching away SiGe from an alternating stack of Si and SiGe.

18. The semiconductor device according to claim 11, wherein, The spacing between the first channel patterns is greater than the spacing between the second channel patterns.

19. The semiconductor device according to claim 11, wherein, At least one of the spacing between the first channel patterns and the spacing between the second channel patterns is 15 nm.

20. The semiconductor device according to claim 11, wherein, The lowest first channel pattern in the first channel pattern is disposed on the buried oxide layer, and the first gate stack covers the top and side surfaces of the lowest first channel pattern, and / or The lowest second channel pattern of the second channel pattern is disposed on the oxide layer, and the second gate stack covers the top and side surfaces of the lowest second channel pattern.

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